F203/Debug/ETC/JFlash/Flash.csv

1	Manufacturer	Name	Id16	Id8	Internal	Algo	AlgoVar	BusWidth	SupportsSectorErase	SupportsChipErase	ZeroProgram	SupportsSoftLock	SoftLockAreaType(0:Sector,1:Chip)	SoftUnlockAreaType	SupportsHardLock	HardLockAreaType	SupportsHardUnlock	HardUnlockAreaType	SoftLockResetState(0:Remember,1:ON,2:OFF)	SupportsSecure	SupportsUnsecure	Sectors
2	Atmel	AC33M8128 internal	0	0	1	82	0	32	1	1	0	0	0	0	0	0	0	0	0	1	0	80[1024];
3	Actel	A2FxxxM3E internal	0	0	1	76	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	80[1024];
4	Actel	A2FxxxM3F internal	0	0	1	76	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	80[2048];
5	Actel	A2FxxxM3G internal	0	0	1	76	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	80[4096];
6	active-semi	PAC52xx internal	0	0	1	98	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	400[32];
7	AmbiqMicro	APOLLO512 internal	0	0	1	94	0	32	1	1	0	0	0	0	0	0	0	0	0	0	0	800[256];
8	AmbiqMicro	APOLLO256 internal	0	0	1	94	0	32	1	1	0	0	0	0	0	0	0	0	0	0	0	800[128];
9	AmbiqMicro	APOLLO128 internal	0	0	1	94	0	32	1	1	0	0	0	0	0	0	0	0	0	0	0	800[64];
10	AmbiqMicro	APOLLO064 internal	0	0	1	94	0	32	1	1	0	0	0	0	0	0	0	0	0	0	0	800[32];
11	AMD	Am29DL161DB	12239	10039	0	1	0	16	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[8]; 10000[31];
12	AMD	Am29DL161DT	12236	10036	0	1	0	16	1	0	0	0	0	0	0	0	0	0	0	0	0	10000[31]; 2000[8];
13	AMD	Am29DL162DB	01222E	01002E	0	1	0	16	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[8]; 10000[3]; 10000[28];
14	AMD	Am29DL162DT	01222D	01002D	0	1	0	16	1	0	0	0	0	0	0	0	0	0	0	0	0	10000[28]; 10000[3]; 2000[8];
15	AMD	Am29DL163DB	01222B	01002B	0	1	0	16	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[8]; 10000[7]; 10000[24];
16	AMD	Am29DL163DT	12228	10028	0	1	0	16	1	0	0	0	0	0	0	0	0	0	0	0	0	10000[24]; 10000[7]; 2000[8];
17	AMD	Am29DL164DB	12235	10035	0	1	0	16	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[8]; 10000[15]; 10000[16];
18	AMD	Am29DL164DT	12233	10033	0	1	0	16	1	0	0	0	0	0	0	0	0	0	0	0	0	10000[16]; 10000[15]; 2000[8];
19	AMD	Am29DL322DB/GB	12256	10056	0	1	0	16	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[8]; 10000[7]; 10000[56];
20	AMD	Am29DL322DT/GT	12255	10055	0	1	0	16	1	0	0	0	0	0	0	0	0	0	0	0	0	10000[56]; 10000[7]; 2000[8];
21	AMD	Am29DL323DB/GB	12253	10053	0	1	0	16	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[8]; 10000[15]; 10000[48];
22	AMD	Am29DL323DT/GT	12250	10050	0	1	0	16	1	0	0	0	0	0	0	0	0	0	0	0	0	10000[48]; 10000[15]; 2000[8];
23	AMD	Am29DL324DB/GB	01225F	01005F	0	1	0	16	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[8]; 10000[31]; 10000[32];
24	AMD	Am29DL324DT/GT	01225C	01005C	0	1	0	16	1	0	0	0	0	0	0	0	0	0	0	0	0	10000[32]; 10000[31]; 2000[8];
25	AMD	Am29DL400BB	01220F	01000F	0	1	0	16	1	0	0	0	0	0	0	0	0	0	0	0	0	4000; 8000; 2000[4]; 8000; 4000; 10000[6];
26	AMD	Am29DL400BT	01220C	01000C	0	1	0	16	1	0	0	0	0	0	0	0	0	0	0	0	0	10000[6]; 4000; 8000; 2000[4]; 8000; 4000;
27	AMD	Am29DL800BB	0122CB	0100CB	0	1	0	16	1	0	0	0	0	0	0	0	0	0	0	0	0	4000; 8000; 2000[4]; 8000; 4000; 10000[14];
28	AMD	Am29DL800BT	01224A	01004A	0	1	0	16	1	0	0	0	0	0	0	0	0	0	0	0	0	10000[14]; 4000; 8000; 2000[4]; 8000; 4000;
29	AMD	Am29DS323DB	0122B8	0100B8	0	1	0	16	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[8]; 10000[15]; 10000[48];
30	AMD	Am29DS323DT	0122B7	0100B7	0	1	0	16	1	0	0	0	0	0	0	0	0	0	0	0	0	10000[48]; 10000[15]; 2000[8];
31	AMD	Am29F100B	0122DF	0100DF	0	1	0	16	1	0	0	0	0	0	0	0	0	0	0	0	0	4000; 2000[2]; 8000; 10000;
32	AMD	Am29F100T	0122D9	0100D9	0	1	0	16	1	0	0	0	0	0	0	0	0	0	0	0	0	10000; 8000; 2000[2]; 4000;
33	AMD	Am29F400BB	0122AB	0100AB	0	1	0	16	1	0	0	0	0	0	0	0	0	0	0	0	0	4000; 2000[2]; 8000; 10000[7];
34	AMD	Am29F400BT	12223	10023	0	1	0	16	1	0	0	0	0	0	0	0	0	0	0	0	0	10000[7]; 8000; 2000[2]; 4000;
35	AMD	Am29F800BB	12258	10058	0	1	0	16	1	0	0	0	0	0	0	0	0	0	0	0	0	4000; 2000[2]; 8000; 10000[15];
36	AMD	Am29F800BT	0122D6	0100D6	0	1	0	16	1	0	0	0	0	0	0	0	0	0	0	0	0	10000[15]; 8000; 2000[2]; 4000;
37	AMD	Am29LV001BB	01006D	01006D	0	1	0	8	1	0	0	0	0	0	0	0	0	0	0	0	0	2000; 1000[2]; 4000[7];
38	AMD	Am29LV001BT	0100ED	0100ED	0	1	0	8	1	0	0	0	0	0	0	0	0	0	0	0	0	4000[7]; 1000[2]; 2000;
39	AMD	Am29LV002BB	0100C2	0100C2	0	1	0	8	1	0	0	0	0	0	0	0	0	0	0	0	0	4000; 2000[2]; 8000; 10000[3];
40	AMD	Am29LV002BT	10040	10040	0	1	0	8	1	0	0	0	0	0	0	0	0	0	0	0	0	10000[3]; 8000; 2000[2]; 4000;
41	AMD	Am29LV004BB	0100B6	0100B6	0	1	0	8	1	0	0	0	0	0	0	0	0	0	0	0	0	4000; 2000[2]; 8000; 10000[7];
42	AMD	Am29LV004BT	0100B5	0100B5	0	1	0	8	1	0	0	0	0	0	0	0	0	0	0	0	0	10000[7]; 8000; 2000[2]; 4000;
43	AMD	Am29LV033C	0100A3	0100A3	0	1	0	8	1	0	0	0	0	0	0	0	0	0	0	0	0	10000[64];
44	AMD	Am29LV033MU	01007E	01007E	0	1	0	8	1	0	0	0	0	0	0	0	0	0	0	0	0	10000[64];
45	AMD	Am29LV065D	010093	010093	0	1	0	8	1	0	0	0	0	0	0	0	0	0	0	0	0	10000[128];
46	AMD	Am29LV116DB	01004C	01004C	0	1	0	8	1	0	0	0	0	0	0	0	0	0	0	0	0	4000; 2000[2]; 8000; 10000[31];
47	AMD	Am29LV116DT	0100C7	0100C7	0	1	0	8	1	0	0	0	0	0	0	0	0	0	0	0	0	10000[31]; 8000; 2000[2]; 4000;
48	AMD	Am29LV160BB	12249	10049	0	1	0	16	1	0	0	0	0	0	0	0	0	0	0	0	0	4000; 2000[2]; 8000; 10000[31];
49	AMD	Am29LV160BT	0122C4	0100C4	0	1	0	16	1	0	0	0	0	0	0	0	0	0	0	0	0	10000[31]; 8000; 2000[2]; 4000;
50	AMD	Am29LV160DB	12249	10049	0	1	0	16	1	0	0	0	0	0	0	0	0	0	0	0	0	4000; 2000[2]; 8000; 10000[31];
51	AMD	Am29LV160DT	0122C4	0100C4	0	1	0	16	1	0	0	0	0	0	0	0	0	0	0	0	0	10000[31]; 8000; 2000[2]; 4000;
52	AMD	Am29LV200BB	0122BF	0100BF	0	1	0	16	1	0	0	0	0	0	0	0	0	0	0	0	0	4000; 2000[2]; 8000; 10000[3];
53	AMD	Am29LV200BT	01223B	01003B	0	1	0	16	1	0	0	0	0	0	0	0	0	0	0	0	0	10000[3]; 8000; 2000[2]; 4000;
54	AMD	Am29LV320DB	0122F9	0100F9	0	1	0	16	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[8]; 10000[63];
55	AMD	Am29LV320DT	0122F6	0100F6	0	1	0	16	1	0	0	0	0	0	0	0	0	0	0	0	0	10000[63]; 2000[8];
56	AMD	Am29LV400BB	0122BA	0100BA	0	1	0	16	1	0	0	0	0	0	0	0	0	0	0	0	0	4000; 2000[2]; 8000; 10000[7];
57	AMD	Am29LV400BT	0122B9	0100B9	0	1	0	16	1	0	0	0	0	0	0	0	0	0	0	0	0	10000[7]; 8000; 2000[2]; 4000;
58	AMD	Am29LV640D	0122D7	0100D7	0	1	0	16	1	0	0	0	0	0	0	0	0	0	0	0	0	10000[128];
59	AMD	Am29LV641D	0122D7	0100D7	0	1	0	16	1	0	0	0	0	0	0	0	0	0	0	0	0	10000[128];
60	AMD	Am29LV800BB	01225B	01005B	0	1	0	16	1	0	0	0	0	0	0	0	0	0	0	0	0	4000; 2000[2]; 8000; 10000[15];
61	AMD	Am29LV800BT	0122DA	0100DA	0	1	0	16	1	0	0	0	0	0	0	0	0	0	0	0	0	10000[15]; 8000; 2000[2]; 4000;
62	AMD	Am29SL800DB	01226B	01006B	0	1	0	16	1	0	0	0	0	0	0	0	0	0	0	0	0	4000; 2000[2]; 8000; 10000[15];
63	AMD	Am29SL800DT	0122EA	0100EA	0	1	0	16	1	0	0	0	0	0	0	0	0	0	0	0	0	10000[15]; 8000; 2000[2]; 4000;
64	AMIC	A29L400B	37B3B5	3700B5	0	1	0	16	1	0	0	0	0	0	0	0	0	0	0	0	0	4000; 2000[2]; 8000; 10000[7];
65	AMIC	A29L400T	37B334	370034	0	1	0	16	1	0	0	0	0	0	0	0	0	0	0	0	0	10000[7]; 8000; 2000[2]; 4000;
66	AMS	AS7000 internal	0	0	1	86	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	1000[8];
67	Analog Devices	AD7160 internal	0	0	1	36	0	32	1	1	0	0	0	0	0	0	0	0	0	0	0	200[64];
68	Analog Devices	ADuC702xx32 internal	0	0	1	6	1	16	1	1	0	0	0	0	0	0	0	0	0	1	0	200[64];
69	Analog Devices	ADuC702xx62 internal	0	0	1	6	1	16	1	1	0	0	0	0	0	0	0	0	0	1	0	200[124];
70	Analog Devices	ADuC7023 internal	0	0	1	6	7	16	1	1	0	0	0	0	0	0	0	0	0	1	0	200[124];
71	Analog Devices	ADuC7028x62 internal	0	0	1	6	1	16	1	1	0	0	0	0	0	0	0	0	0	1	0	200[124];
72	Analog Devices	ADuC7030 internal	0	0	1	6	3	16	1	1	0	0	0	0	0	0	0	0	0	1	0	200[60];
73	Analog Devices	ADuC7031 internal	0	0	1	6	3	16	1	1	0	0	0	0	0	0	0	0	0	1	0	200[60];
74	Analog Devices	ADuC7032 internal	0	0	1	6	4	16	1	1	0	0	0	0	0	0	0	0	0	1	0	200[188];
75	Analog Devices	ADuC7033 internal	0	0	1	6	4	16	1	1	0	0	0	0	0	0	0	0	0	1	0	200[188];
76	Analog Devices	ADuC7034 internal	0	0	1	6	3	16	1	1	0	0	0	0	0	0	0	0	0	1	0	200[60];
77	Analog Devices	ADuC7036 internal	0	0	1	6	4	16	1	1	0	0	0	0	0	0	0	0	0	1	0	200[188];
78	Analog Devices	ADuC7038 internal	0	0	1	6	5	16	1	1	0	0	0	0	0	0	0	0	0	1	0	200[124];
79	Analog Devices	ADuC7039 internal	0	0	1	6	5	16	1	1	0	0	0	0	0	0	0	0	0	1	0	200[124];
80	Analog Devices	ADuC7060 internal	0	0	1	6	3	16	1	1	0	0	0	0	0	0	0	0	0	1	0	200[60];
81	Analog Devices	ADuC7061 internal	0	0	1	6	3	16	1	1	0	0	0	0	0	0	0	0	0	1	0	200[60];
82	Analog Devices	ADuC7062 internal	0	0	1	6	3	16	1	1	0	0	0	0	0	0	0	0	0	1	0	200[60];
83	Analog Devices	ADuC7121 internal	0	0	1	6	2	16	1	1	0	0	0	0	0	0	0	0	0	1	0	200[252];
84	Analog Devices	ADuC7122 internal	0	0	1	6	2	16	1	1	0	0	0	0	0	0	0	0	0	1	0	200[252];
85	Analog Devices	ADuC7124 internal	0	0	1	6	6	16	1	1	0	0	0	0	0	0	0	0	0	1	0	200[252];
86	Analog Devices	ADuC7128 internal	0	0	1	6	2	16	1	1	0	0	0	0	0	0	0	0	0	1	0	200[252];
87	Analog Devices	ADuC7129 internal	0	0	1	6	2	16	1	1	0	0	0	0	0	0	0	0	0	1	0	200[252];
88	Analog Devices	ADuC722xx126 internal	0	0	1	6	2	16	1	1	0	0	0	0	0	0	0	0	0	1	0	200[252];
89	Analog Devices	ADuCM301 internal	0	0	1	36	0	32	1	1	0	0	0	0	0	0	0	0	0	0	0	200[128];
90	Analog Devices	ADuCM310 internal	0	0	1	36	3	32	1	1	0	0	0	0	0	0	0	0	0	0	0	800[128];
91	Analog Devices	ADuCM320 internal	0	0	1	36	3	32	1	1	0	0	0	0	0	0	0	0	0	0	0	800[128];
92	Analog Devices	ADuCM330 internal	0	0	1	36	1	32	1	1	0	0	0	0	0	0	0	0	0	0	0	800[48]; 200[8], 400000;
93	Analog Devices	ADuCM331 internal	0	0	1	36	1	32	1	1	0	0	0	0	0	0	0	0	0	0	0	800[64]; 200[8], 400000;
94	Analog Devices	ADuCM332 internal	0	0	1	36	1	32	1	1	0	0	0	0	0	0	0	0	0	0	0	800[32]; 200[8], 400000;
95	Analog Devices	ADuCM350 internal	0	0	1	36	2	32	1	1	0	0	0	0	0	0	0	0	0	0	0	800[192];
96	Analog Devices	ADuCM360 internal	0	0	1	36	0	32	1	1	0	0	0	0	0	0	0	0	0	0	0	200[256];
97	Analog Devices	ADuCM361 internal	0	0	1	36	0	32	1	1	0	0	0	0	0	0	0	0	0	0	0	200[256];
98	Analog Devices	ADuCM362 internal	0	0	1	36	5	32	1	1	0	0	0	0	0	0	0	0	0	0	0	800[128];
99	Analog Devices	ADuCRF02 internal	0	0	1	36	0	32	1	1	0	0	0	0	0	0	0	0	0	0	0	200[256];
100	Analog Devices	ADuCRF101 internal	0	0	1	36	0	32	1	1	0	0	0	0	0	0	0	0	0	0	0	200[256];
101	Analog Devices	ADSP-CM402BSWZ-EF internal	0	0	1	68	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	10000[8];
102	Analog Devices	ADSP-CM402BSWZ-FF internal	0	0	1	68	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	10000[4];
103	Analog Devices	ADSP-CM403BSWZ-CF internal	0	0	1	68	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	10000[32];
104	Analog Devices	ADSP-CM403BSWZ-EF internal	0	0	1	68	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	10000[8];
105	Analog Devices	ADSP-CM403BSWZ-FF internal	0	0	1	68	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	10000[4];
106	Analog Devices	ADSP-CM407BSWZ-AF internal	0	0	1	68	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	10000[32];
107	Analog Devices	ADSP-CM407BSWZ-BF internal	0	0	1	68	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	10000[32];
108	Analog Devices	ADSP-CM407BSWZ-DF internal	0	0	1	68	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	10000[16];
109	Analog Devices	ADSP-CM408BSWZ-AF internal	0	0	1	68	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	10000[32];
110	Analog Devices	ADSP-CM408BSWZ-BF internal	0	0	1	68	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	10000[32];
111	Analog Devices	ADSP-CM409BSWZ-AF internal	0	0	1	68	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	10000[32];
112	Analog Devices	ADSP-CM409BSWZ-BF internal	0	0	1	68	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	10000[32];
113	Atmel	AT29BV010A	1F0035	1F0035	0	1	0	8	1	0	0	0	0	0	0	0	0	0	0	0	0	80[1024];
114	Atmel	AT29BV020	1F00BA	1F00BA	0	1	0	8	1	0	0	0	0	0	0	0	0	0	0	0	0	100[1024];
115	Atmel	AT29BV040	1F003B	1F003B	0	1	0	8	1	0	0	0	0	0	0	0	0	0	0	0	0	200[1024];
116	Atmel	AT29BV040A	1F00C4	1F00C4	0	1	0	8	1	0	0	0	0	0	0	0	0	0	0	0	0	100[2048];
117	Atmel	AT29C010A	1F00D5	1F00D5	0	1	0	8	1	0	0	0	0	0	0	0	0	0	0	0	0	80[1024];
118	Atmel	AT29C020	1F00DA	1F00DA	0	1	0	8	1	0	0	0	0	0	0	0	0	0	0	0	0	100[1024];
119	Atmel	AT29C040	1F005B	1F005B	0	1	0	8	1	0	0	0	0	0	0	0	0	0	0	0	0	200[1024];
120	Atmel	AT29C040A	1F00A4	1F00A4	0	1	0	8	1	0	0	0	0	0	0	0	0	0	0	0	0	100[2048];
121	Atmel	AT29C1024	1F0025	1F0025	0	1	0	16	1	0	0	0	0	0	0	0	0	0	0	0	0	100[512];
122	Atmel	AT29C256	1F00DC	1F00DC	0	1	0	8	1	0	0	0	0	0	0	0	0	0	0	0	0	40[512];
123	Atmel	AT29C257	1F00DC	1F00DC	0	1	0	8	1	0	0	0	0	0	0	0	0	0	0	0	0	40[512];
124	Atmel	AT29C512	1F005D	1F005D	0	1	0	8	1	0	0	0	0	0	0	0	0	0	0	0	0	80[512];
125	Atmel	AT29LV010A	1F0035	1F0035	0	1	0	8	1	0	0	0	0	0	0	0	0	0	0	0	0	80[1024];
126	Atmel	AT29LV020	1F00BA	1F00BA	0	1	0	8	1	0	0	0	0	0	0	0	0	0	0	0	0	100[1024];
127	Atmel	AT29LV040	1F003B	1F003B	0	1	0	8	1	0	0	0	0	0	0	0	0	0	0	0	0	200[1024];
128	Atmel	AT29LV040A	1F00C4	1F00C4	0	1	0	8	1	0	0	0	0	0	0	0	0	0	0	0	0	100[2048];
129	Atmel	AT29LV1024	1F0026	1F0026	0	1	0	16	1	0	0	0	0	0	0	0	0	0	0	0	0	100[512];
130	Atmel	AT29LV256	1F00BC	1F00BC	0	1	0	8	1	0	0	0	0	0	0	0	0	0	0	0	0	40[512];
131	Atmel	AT29LV512	1F003D	1F003D	0	1	0	8	1	0	0	0	0	0	0	0	0	0	0	0	0	80[512];
132	Atmel	AT49BN6416	1F00D6	1F00D6	0	1	0	16	1	0	0	1	0	0	0	0	0	0	1	0	0	2000[8]; 10000[127];
133	Atmel	AT49BN6416T	1F00D2	1F00D2	0	1	0	16	1	0	0	1	0	0	0	0	0	0	1	0	0	10000[127]; 2000[8];
134	Atmel	AT49BV001A	1F0005	1F0005	0	1	0	8	1	0	0	0	0	0	0	0	0	0	0	0	0	4000; 2000[2]; 8000; 10000;
135	Atmel	AT49BV001AN	1F0005	1F0005	0	1	0	8	1	0	0	0	0	0	0	0	0	0	0	0	0	4000; 2000[2]; 8000; 10000;
136	Atmel	AT49BV001ANT	1F0004	1F0004	0	1	0	8	1	0	0	0	0	0	0	0	0	0	0	0	0	10000; 8000; 2000[2]; 4000;
137	Atmel	AT49BV001AT	1F0004	1F0004	0	1	0	8	1	0	0	0	0	0	0	0	0	0	0	0	0	10000; 8000; 2000[2]; 4000;
138	Atmel	AT49BV002	1F0007	1F0007	0	1	0	8	1	0	0	0	0	0	0	0	0	0	0	0	0	4000; 2000[2]; 18000; 20000;
139	Atmel	AT49BV002A	1F0007	1F0007	0	1	0	8	1	0	0	0	0	0	0	0	0	0	0	0	0	4000; 2000[2]; 8000; 10000[3];
140	Atmel	AT49BV002AN	1F0007	1F0007	0	1	0	8	1	0	0	0	0	0	0	0	0	0	0	0	0	4000; 2000[2]; 8000; 10000[3];
141	Atmel	AT49BV002ANT	1F0008	1F0008	0	1	0	8	1	0	0	0	0	0	0	0	0	0	0	0	0	10000[3]; 8000; 2000[2]; 4000;
142	Atmel	AT49BV002AT	1F0008	1F0008	0	1	0	8	1	0	0	0	0	0	0	0	0	0	0	0	0	10000[3]; 8000; 2000[2]; 4000;
143	Atmel	AT49BV002N	1F0007	1F0007	0	1	0	8	1	0	0	0	0	0	0	0	0	0	0	0	0	4000; 2000[2]; 18000; 20000;
144	Atmel	AT49BV002NT	1F0008	1F0008	0	1	0	8	1	0	0	0	0	0	0	0	0	0	0	0	0	20000; 18000; 2000[2]; 4000;
145	Atmel	AT49BV002T	1F0008	1F0008	0	1	0	8	1	0	0	0	0	0	0	0	0	0	0	0	0	20000; 18000; 2000[2]; 4000;
146	Atmel	AT49BV040	1F0013	1F0013	0	1	0	8	0	1	0	0	0	0	0	0	0	0	0	0	0	80000[1];
147	Atmel	AT49BV040A	1F0013	1F0013	0	1	0	8	1	0	0	0	0	0	0	0	0	0	0	0	0	4000; 2000[2]; 8000; 10000[7];
148	Atmel	AT49BV1024A	1F0087	1F0087	0	1	0	16	0	1	0	0	0	0	0	0	0	0	0	0	0	4000; 1C000;
149	Atmel	AT49BV1604	1F00C0	1F00C0	0	1	0	16	1	0	1	0	0	0	0	0	0	0	0	0	0	2000[8]; 8000[2]; 10000[30];
150	Atmel	AT49BV1604A	1F00C0	1F00C0	0	1	0	16	1	0	1	0	0	0	0	0	0	0	0	0	0	2000[8]; 10000[31];
151	Atmel	AT49BV1604AT	1F00C2	1F00C2	0	1	0	16	1	0	1	0	0	0	0	0	0	0	0	0	0	10000[31]; 2000[8];
152	Atmel	AT49BV1604T	1F00C2	1F00C2	0	1	0	16	1	0	1	0	0	0	0	0	0	0	0	0	0	10000[30]; 8000[2]; 2000[8];
153	Atmel	AT49BV160C	1F88C3	1F00C3	0	2	0	16	1	0	0	1	0	0	0	0	0	0	1	0	0	2000[8]; 10000[31];
154	Atmel	AT49BV160CT	1F88C2	1F00C2	0	2	0	16	1	0	0	1	0	0	0	0	0	0	1	0	0	10000[31]; 2000[8];
155	Atmel	AT49BV160D	1F90C3	1F00C3	0	2	0	16	1	0	0	1	0	0	0	0	0	0	1	0	0	2000[8]; 10000[31];
156	Atmel	AT49BV160DT	1F90C2	1F00C2	0	2	0	16	1	0	0	1	0	0	0	0	0	0	1	0	0	10000[31]; 2000[8];
157	Atmel	AT49BV1614	1F00C0	1F00C0	0	1	0	16	1	0	1	0	0	0	0	0	0	0	0	0	0	2000[8]; 8000[2]; 10000[30];
158	Atmel	AT49BV1614A	1F00C0	1F00C0	0	1	0	16	1	0	1	0	0	0	0	0	0	0	0	0	0	2000[8]; 10000[31];
159	Atmel	AT49BV1614AT	1F00C2	1F00C2	0	1	0	16	1	0	1	0	0	0	0	0	0	0	0	0	0	10000[31]; 2000[8];
160	Atmel	AT49BV1614T	1F00C2	1F00C2	0	1	0	16	1	0	1	0	0	0	0	0	0	0	0	0	0	10000[30]; 8000[2]; 2000[8];
161	Atmel	AT49BV162A	1F00C0	1F00C0	0	1	0	16	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[8]; 10000[31];
162	Atmel	AT49BV162AT	1F00C2	1F00C2	0	1	0	16	1	0	0	0	0	0	0	0	0	0	0	0	0	10000[31]; 2000[8];
163	Atmel	AT49BV163D	1F01C0	1F00C0	0	1	0	16	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[8]; 10000[31];
164	Atmel	AT49BV163DT	1F01C2	1F00C2	0	1	0	16	1	0	0	0	0	0	0	0	0	0	0	0	0	10000[31]; 2000[8];
165	Atmel	AT49BV2048A	1F0082	1F0082	0	1	0	16	1	0	0	0	0	0	0	0	0	0	0	0	0	4000; 2000[2]; 38000;
166	Atmel	AT49BV320C	1F88C5	1F00C5	0	2	0	16	1	0	0	1	0	0	0	0	0	0	1	0	0	2000[8]; 10000[63];
167	Atmel	AT49BV320CT	1F88C4	1F00C4	0	2	0	16	1	0	0	1	0	0	0	0	0	0	1	0	0	10000[63]; 2000[8];
168	Atmel	AT49BV320D	1F90C5	1F00C5	0	2	0	16	1	0	0	1	0	0	0	0	0	0	1	0	0	2000[8]; 10000[63];
169	Atmel	AT49BV320DT	1F90C4	1F00C4	0	2	0	16	1	0	0	1	0	0	0	0	0	0	1	0	0	10000[63]; 2000[8];
170	Atmel	AT49BV322A	1F00C8	1F00C8	0	1	0	16	1	0	0	0	0	0	1	0	0	0	2	0	0	2000[8]; 10000[63];
171	Atmel	AT49BV322AT	1F00C9	1F00C9	0	1	0	16	1	0	0	0	0	0	1	0	0	0	2	0	0	10000[63]; 2000[8];
172	Atmel	AT49BV322D	1F01C8	1F00C8	0	1	0	16	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[8]; 10000[63];
173	Atmel	AT49BV322DT	1F01C9	1F00C9	0	1	0	16	1	0	0	0	0	0	0	0	0	0	0	0	0	10000[63]; 2000[8];
174	Atmel	AT49BV4096A	161F1692	1F0092	0	1	0	16	1	0	0	0	0	0	0	0	0	0	0	0	0	4000; 2000[2]; 78000;
175	Atmel	AT49BV512	1F0003	1F0003	0	1	0	8	0	1	0	0	0	0	0	0	0	0	0	0	0	10000[1];
176	Atmel	AT49BV640	1F00D6	1F00D6	0	1	0	16	1	0	0	1	0	0	0	0	0	0	1	0	0	2000[8]; 10000[127];
177	Atmel	AT49BV640D	1F02DE	1F00DE	0	2	0	16	1	0	0	1	0	0	0	0	0	0	1	0	0	2000[8]; 10000[127];
178	Atmel	AT49BV640DT	1F02DB	1F00DB	0	2	0	16	1	0	0	1	0	0	0	0	0	0	1	0	0	10000[127]; 2000[8];
179	Atmel	AT49BV640T	1F00D2	1F00D2	0	1	0	16	1	0	0	1	0	0	0	0	0	0	1	0	0	10000[127]; 2000[8];
180	Atmel	AT49BV6416	1F00D6	1F00D6	0	1	0	16	1	0	0	1	0	0	0	0	0	0	1	0	0	2000[8]; 10000[127];
181	Atmel	AT49BV6416T	1F00D2	1F00D2	0	1	0	16	1	0	0	1	0	0	0	0	0	0	1	0	0	10000[127]; 2000[8];
182	Atmel	AT49BV642D	1F01D6	1F00D6	0	1	0	16	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[8]; 10000[127];
183	Atmel	AT49BV642DT	1F01D2	1F00D2	0	1	0	16	1	0	0	0	0	0	0	0	0	0	0	0	0	10000[127]; 2000[8];
184	Atmel	AT49BV802A	1F00C1	1F00C1	0	1	0	16	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[8]; 10000[15];
185	Atmel	AT49BV802AT	1F00C3	1F00C3	0	1	0	16	1	0	0	0	0	0	0	0	0	0	0	0	0	10000[15]; 2000[8];
186	Atmel	AT49F001A	1F0005	1F0005	0	1	0	8	1	0	0	0	0	0	0	0	0	0	0	0	0	4000; 2000[2]; 8000; 10000;
187	Atmel	AT49F001AN	1F0005	1F0005	0	1	0	8	1	0	0	0	0	0	0	0	0	0	0	0	0	4000; 2000[2]; 8000; 10000;
188	Atmel	AT49F001ANT	1F0004	1F0004	0	1	0	8	1	0	0	0	0	0	0	0	0	0	0	0	0	10000; 8000; 2000[2]; 4000;
189	Atmel	AT49F001AT	1F0004	1F0004	0	1	0	8	1	0	0	0	0	0	0	0	0	0	0	0	0	10000; 8000; 2000[2]; 4000;
190	Atmel	AT49F002A	1F0007	1F0007	0	1	0	8	1	0	0	0	0	0	0	0	0	0	0	0	0	4000; 2000[2]; 8000; 10000[3];
191	Atmel	AT49F002AN	1F0007	1F0007	0	1	0	8	1	0	0	0	0	0	0	0	0	0	0	0	0	4000; 2000[2]; 8000; 10000[3];
192	Atmel	AT49F002ANT	1F0008	1F0008	0	1	0	8	1	0	0	0	0	0	0	0	0	0	0	0	0	10000[3]; 8000; 2000[2]; 4000;
193	Atmel	AT49F002AT	1F0008	1F0008	0	1	0	8	1	0	0	0	0	0	0	0	0	0	0	0	0	10000[3]; 8000; 2000[2]; 4000;
194	Atmel	AT49F040A	1F0013	1F0013	0	1	0	8	1	0	0	0	0	0	0	0	0	0	0	0	0	4000; 2000[2]; 8000; 10000[7];
195	Atmel	AT49F1024	1F0087	1F0087	0	1	0	16	0	1	0	0	0	0	0	0	0	0	0	0	0	4000; 1C000;
196	Atmel	AT49F1024A	1F0087	1F0087	0	1	0	16	0	1	0	0	0	0	0	0	0	0	0	0	0	4000; 1C000;
197	Atmel	AT49F1025	1F0087	1F0087	0	1	0	16	0	1	0	0	0	0	0	0	0	0	0	0	0	4000; 1C000;
198	Atmel	AT49F2048A	1F0082	1F0082	0	1	0	16	1	0	0	0	0	0	0	0	0	0	0	0	0	4000; 2000[2]; 38000;
199	Atmel	AT49F4096A	161F1692	1F0092	0	1	0	16	1	0	0	0	0	0	0	0	0	0	0	0	0	4000; 2000[2]; 78000;
200	Atmel	AT49F512	1F0003	1F0003	0	1	0	8	0	1	0	0	0	0	0	0	0	0	0	0	0	2000; E000;
201	Atmel	AT49LV002	1F0007	1F0007	0	1	0	8	1	0	0	0	0	0	0	0	0	0	0	0	0	4000; 2000[2]; 18000; 20000;
202	Atmel	AT49LV002N	1F0007	1F0007	0	1	0	8	1	0	0	0	0	0	0	0	0	0	0	0	0	4000; 2000[2]; 18000; 20000;
203	Atmel	AT49LV002NT	1F0008	1F0008	0	1	0	8	1	0	0	0	0	0	0	0	0	0	0	0	0	20000; 18000; 2000[2]; 4000;
204	Atmel	AT49LV002T	1F0008	1F0008	0	1	0	8	1	0	0	0	0	0	0	0	0	0	0	0	0	20000; 18000; 2000[2]; 4000;
205	Atmel	AT49LV040	1F0013	1F0013	0	1	0	8	0	1	0	0	0	0	0	0	0	0	0	0	0	80000[1];
206	Atmel	AT49LV1024	1F0087	1F0087	0	1	0	16	0	1	0	0	0	0	0	0	0	0	0	0	0	4000; 1C000;
207	Atmel	AT49LV1024A	1F0087	1F0087	0	1	0	16	0	1	0	0	0	0	0	0	0	0	0	0	0	4000; 1C000;
208	Atmel	AT49LV1614A	1F00C0	1F00C0	0	1	0	16	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[8]; 10000[31];
209	Atmel	AT49LV1614AT	1F00C2	1F00C2	0	1	0	16	1	0	0	0	0	0	0	0	0	0	0	0	0	10000[31]; 2000[8];
210	Atmel	AT49LV2048A	1F0082	1F0082	0	1	0	16	1	0	0	0	0	0	0	0	0	0	0	0	0	4000; 2000[2]; 38000;
211	Atmel	AT49LV4096A	161F1692	1F0092	0	1	0	16	1	0	0	0	0	0	0	0	0	0	0	0	0	4000; 2000[2]; 78000;
212	Atmel	AT49SN3208	1F00DB	1F00DB	0	1	0	16	1	0	0	1	0	0	1	0	0	0	2	0	0	2000[8]; 10000[63];
213	Atmel	AT49SN3208T	1F00D1	1F00D1	0	1	0	16	1	0	0	1	0	0	1	0	0	0	2	0	0	10000[63]; 2000[8];
214	Atmel	AT49SN6416	1F00DC	1F00DC	0	1	0	16	1	0	0	1	0	0	1	0	0	0	2	0	0	2000[8]; 10000[127];
215	Atmel	AT49SN6416T	1F00D8	1F00D8	0	1	0	16	1	0	0	1	0	0	1	0	0	0	2	0	0	10000[127]; 2000[8];
216	Atmel	AT49SV322A	1F00DB	1F00DB	0	1	0	16	1	0	0	0	0	0	1	0	0	0	2	0	0	2000[8]; 10000[63];
217	Atmel	AT49SV322AT	1F00D1	1F00D1	0	1	0	16	1	0	0	0	0	0	1	0	0	0	2	0	0	10000[63]; 2000[8];
218	Atmel	AT49SV802A	1F00C4	1F00C4	0	1	0	16	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[8]; 10000[15];
219	Atmel	AT49SV802AT	1F00C6	1F00C4	0	1	0	16	1	0	0	0	0	0	0	0	0	0	0	0	0	10000[15]; 2000[8];
220	Atmel	AT91SAM3A2 internal	0	0	1	26	2	32	1	1	0	0	0	0	0	0	0	0	0	1	0	100[512];
221	Atmel	AT91SAM3A4 internal	0	0	1	26	2	32	1	1	0	0	0	0	0	0	0	0	0	1	0	100[1024];
222	Atmel	AT91SAM3A8 internal	0	0	1	26	2	32	1	1	0	0	0	0	0	0	0	0	0	1	0	100[2048];
223	Atmel	AT91SAM3N00 internal	0	0	1	26	1	32	1	1	0	0	0	0	0	0	0	0	0	1	0	100[64];
224	Atmel	AT91SAM3N0 internal	0	0	1	26	1	32	1	1	0	0	0	0	0	0	0	0	0	1	0	100[128];
225	Atmel	AT91SAM3N1 internal	0	0	1	26	1	32	1	1	0	0	0	0	0	0	0	0	0	1	0	100[256];
226	Atmel	AT91SAM3N2 internal	0	0	1	26	1	32	1	1	0	0	0	0	0	0	0	0	0	1	0	100[512];
227	Atmel	AT91SAM3N4 internal	0	0	1	26	1	32	1	1	0	0	0	0	0	0	0	0	0	1	0	100[1024];
228	Atmel	AT91SAM3S1 internal	0	0	1	26	1	32	1	1	0	0	0	0	0	0	0	0	0	1	0	100[256];
229	Atmel	AT91SAM3S2 internal	0	0	1	26	1	32	1	1	0	0	0	0	0	0	0	0	0	1	0	100[512];
230	Atmel	AT91SAM3S4 internal	0	0	1	26	1	32	1	1	0	0	0	0	0	0	0	0	0	1	0	100[1024];
231	Atmel	AT91SAM3S8 internal	0	0	1	26	1	32	1	1	0	0	0	0	0	0	0	0	0	1	0	100[2048];
232	Atmel	AT91SAM3U1 internal	0	0	1	26	0	32	1	1	0	0	0	0	0	0	0	0	0	1	0	100[256];
233	Atmel	AT91SAM3U2 internal	0	0	1	26	0	32	1	1	0	0	0	0	0	0	0	0	0	1	0	100[512];
234	Atmel	AT91SAM3U4 internal	0	0	1	26	0	32	1	1	0	0	0	0	0	0	0	0	0	1	0	100[512];100[512],80000;
235	Atmel	AT91SAM3X2 internal	0	0	1	26	2	32	1	1	0	0	0	0	0	0	0	0	0	1	0	100[512];
236	Atmel	AT91SAM3X4 internal	0	0	1	26	2	32	1	1	0	0	0	0	0	0	0	0	0	1	0	100[1024];
237	Atmel	AT91SAM3X8 internal	0	0	1	26	2	32	1	1	0	0	0	0	0	0	0	0	0	1	0	100[2048];
238	Atmel	AT91SAM4N8 internal	0	0	1	47	2	32	1	1	0	0	0	0	0	0	0	0	0	1	0	200[32]; 1000[124];
239	Atmel	AT91SAM4N16 internal	0	0	1	47	2	32	1	1	0	0	0	0	0	0	0	0	0	1	0	200[32]; 1000[252];
240	Atmel	AT91SAM4S2 internal	0	0	1	47	2	32	1	1	0	0	0	0	0	0	0	0	0	1	0	200[32]; 1000[28];
241	Atmel	AT91SAM4S4 internal	0	0	1	47	2	32	1	1	0	0	0	0	0	0	0	0	0	1	0	200[32]; 1000[60];
242	Atmel	AT91SAM4S8 internal	0	0	1	47	2	32	1	1	0	0	0	0	0	0	0	0	0	1	0	200[32]; 1000[124];
243	Atmel	AT91SAM4S16 internal	0	0	1	47	2	32	1	1	0	0	0	0	0	0	0	0	0	1	0	200[32]; 1000[252];
244	Atmel	AT91SAM4SA16 internal	0	0	1	47	2	32	1	1	0	0	0	0	0	0	0	0	0	1	0	200[32]; 1000[252];
245	Atmel	AT91SAM4SD16 internal	0	0	1	47	3	32	1	1	0	0	0	0	0	0	0	0	0	1	0	200[32]; 1000[124]; 200[32]; 1000[124];
246	Atmel	AT91SAM4SD32 internal	0	0	1	47	3	32	1	1	0	0	0	0	0	0	0	0	0	1	0	200[32]; 1000[252]; 200[32]; 1000[252];
247	Atmel	AT91SAM4SP16 internal	0	0	1	47	2	32	1	1	0	0	0	0	0	0	0	0	0	1	0	200[32]; 1000[252];
248	Atmel	AT91SAM4SP32 internal	0	0	1	47	2	32	1	1	0	0	0	0	0	0	0	0	0	1	0	200[32]; 1000[508];
249	Atmel	AT91SAM7A3 internal	0	0	1	8	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	100[1024];
250	Atmel	AT91SAM7L64 internal	0	0	1	22	0	32	1	1	0	0	0	0	0	0	0	0	0	1	0	100[256];
251	Atmel	AT91SAM7L128 internal	0	0	1	22	0	32	1	1	0	0	0	0	0	0	0	0	0	1	0	100[512];
252	Atmel	AT91SAM7S128 internal	0	0	1	8	0	32	1	0	0	0	0	0	0	0	0	0	0	1	0	100[512];
253	Atmel	AT91SAM7S16 internal	0	0	1	33	0	32	1	0	0	0	0	0	0	0	0	0	0	1	0	40[256];
254	Atmel	AT91SAM7S161 internal	0	0	1	33	0	32	1	0	0	0	0	0	0	0	0	0	0	1	0	40[256];
255	Atmel	AT91SAM7S256 internal	0	0	1	8	0	32	1	0	0	0	0	0	0	0	0	0	0	1	0	100[1024];
256	Atmel	AT91SAM7S32 internal	0	0	1	5	0	32	1	0	0	0	0	0	0	0	0	0	0	1	0	80[256];
257	Atmel	AT91SAM7S321 internal	0	0	1	5	0	32	1	0	0	0	0	0	0	0	0	0	0	1	0	80[256];
258	Atmel	AT91SAM7S512 internal	0	0	1	8	0	32	1	0	0	0	0	0	0	0	0	0	0	1	0	100[2048];
259	Atmel	AT91SAM7S64 internal	0	0	1	5	0	32	1	0	0	0	0	0	0	0	0	0	0	1	0	80[512];
260	Atmel	AT91SAM7SE256 internal	0	0	1	8	0	32	1	0	0	0	0	0	0	0	0	0	0	1	0	100[1024];
261	Atmel	AT91SAM7SE32 internal	0	0	1	5	0	32	1	0	0	0	0	0	0	0	0	0	0	1	0	80[256];
262	Atmel	AT91SAM7SE512 internal	0	0	1	8	0	32	1	0	0	0	0	0	0	0	0	0	0	1	0	100[2048];
263	Atmel	AT91SAM7X128 internal	0	0	1	8	0	32	1	0	0	0	0	0	0	0	0	0	0	1	0	100[512];
264	Atmel	AT91SAM7X256 internal	0	0	1	8	0	32	1	0	0	0	0	0	0	0	0	0	0	1	0	100[1024];
265	Atmel	AT91SAM7X512 internal	0	0	1	8	0	32	1	0	0	0	0	0	0	0	0	0	0	1	0	100[2048];
266	Atmel	AT91SAM7XC128 internal	0	0	1	8	0	32	1	0	0	0	0	0	0	0	0	0	0	1	0	100[512];
267	Atmel	AT91SAM7XC256 internal	0	0	1	8	0	32	1	0	0	0	0	0	0	0	0	0	0	1	0	100[1024];
268	Atmel	AT91SAM7XC512 internal	0	0	1	8	0	32	1	0	0	0	0	0	0	0	0	0	0	1	0	100[2048];
269	Atmel	AT91SAM9XE128 internal	0	0	1	23	0	32	1	1	0	0	0	0	0	0	0	0	0	1	0	200[256];
270	Atmel	AT91SAM9XE256 internal	0	0	1	23	0	32	1	1	0	0	0	0	0	0	0	0	0	1	0	200[512];
271	Atmel	AT91SAM9XE512 internal	0	0	1	23	0	32	1	1	0	0	0	0	0	0	0	0	0	1	0	200[1024];
272	Atmel	ATSAM4C4x internal	0	0	1	47	0	32	1	1	0	0	0	0	0	0	0	0	0	1	0	1000[64];
273	Atmel	ATSAM4C8x internal	0	0	1	47	0	32	1	1	0	0	0	0	0	0	0	0	0	1	0	1000[128];
274	Atmel	ATSAM4C16x internal	0	0	1	47	0	32	1	1	0	0	0	0	0	0	0	0	0	1	0	1000[256];
275	Atmel	ATSAM4C32x internal	0	0	1	47	0	32	1	1	0	0	0	0	0	0	0	0	0	1	0	1000[512];
276	Atmel	ATSAM4E8x internal	0	0	1	47	1	32	1	1	0	0	0	0	0	0	0	0	0	1	0	1000[128];
277	Atmel	ATSAM4E16x internal	0	0	1	47	1	32	1	1	0	0	0	0	0	0	0	0	0	1	0	1000[256];
278	Atmel	ATSAM4Lx1xx internal	0	0	1	50	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	200[128];
279	Atmel	ATSAM4Lx2xx internal	0	0	1	50	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	200[256];
280	Atmel	ATSAM4Lx4xx internal	0	0	1	50	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	200[512];
281	Atmel	ATSAM4Lx8xx internal	0	0	1	50	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	200[1024];
282	Atmel	ATSAMC20x14 internal	0	0	1	58	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	100[64];10[1],804000;
283	Atmel	ATSAMC20x15 internal	0	0	1	58	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	100[128];10[1],804000;
284	Atmel	ATSAMC20x16 internal	0	0	1	58	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	100[256];10[1],804000;
285	Atmel	ATSAMC20x17 internal	0	0	1	58	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	100[512];10[1],804000;
286	Atmel	ATSAMC20x18 internal	0	0	1	58	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	100[1024];10[1],804000;
287	Atmel	ATSAMC21x15 internal	0	0	1	58	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	100[128];10[1],804000;
288	Atmel	ATSAMC21x16 internal	0	0	1	58	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	100[256];10[1],804000;
289	Atmel	ATSAMC21x17 internal	0	0	1	58	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	100[512];10[1],804000;
290	Atmel	ATSAMC21x18 internal	0	0	1	58	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	100[1024];10[1],804000;
291	Atmel	ATSAMD09x13 internal	0	0	1	58	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	100[32];10[1],804000;
292	Atmel	ATSAMD09x14 internal	0	0	1	58	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	100[64];10[1],804000;
293	Atmel	ATSAMD10x12 internal	0	0	1	58	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	100[16];10[1],804000;
294	Atmel	ATSAMD10x13 internal	0	0	1	58	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	100[32];10[1],804000;
295	Atmel	ATSAMD10x14 internal	0	0	1	58	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	100[64];10[1],804000;
296	Atmel	ATSAMD11x12 internal	0	0	1	58	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	100[16];10[1],804000;
297	Atmel	ATSAMD11x13 internal	0	0	1	58	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	100[32];10[1],804000;
298	Atmel	ATSAMD11x14 internal	0	0	1	58	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	100[64];10[1],804000;
299	Atmel	ATSAMD20x14 internal	0	0	1	58	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	100[64];10[1],804000;
300	Atmel	ATSAMD20x15 internal	0	0	1	58	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	100[128];10[1],804000;
301	Atmel	ATSAMD20x16 internal	0	0	1	58	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	100[256];10[1],804000;
302	Atmel	ATSAMD20x17 internal	0	0	1	58	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	100[512];10[1],804000;
303	Atmel	ATSAMD20x18 internal	0	0	1	58	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	100[1024];10[1],804000;
304	Atmel	ATSAMD21x15 internal	0	0	1	58	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	100[128];10[1],804000;
305	Atmel	ATSAMD21x16 internal	0	0	1	58	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	100[256];10[1],804000;
306	Atmel	ATSAMD21x17 internal	0	0	1	58	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	100[512];10[1],804000;
307	Atmel	ATSAMD21x18 internal	0	0	1	58	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	100[1024];10[1],804000;
308	Atmel	ATSAMDA1x14 internal	0	0	1	58	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	100[64];10[1],804000;
309	Atmel	ATSAMDA1x15 internal	0	0	1	58	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	100[128];10[1],804000;
310	Atmel	ATSAMDA1x16 internal	0	0	1	58	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	100[256];10[1],804000;
311	Atmel	ATSAME70x19 internal	0	0	1	83	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[2];1C000[1];20000[3];
312	Atmel	ATSAME70x20 internal	0	0	1	83	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[2];1C000[1];20000[7];
313	Atmel	ATSAME70x21 internal	0	0	1	83	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[2];1C000[1];20000[15];
314	Atmel	ATSAMG51G18 internal	0	0	1	47	2	32	1	1	0	0	0	0	0	0	0	0	0	1	0	200[32]; 1000[60];
315	Atmel	ATSAMG51N18 internal	0	0	1	47	2	32	1	1	0	0	0	0	0	0	0	0	0	1	0	200[32]; 1000[60];
316	Atmel	ATSAMG53G19 internal	0	0	1	47	2	32	1	1	0	0	0	0	0	0	0	0	0	1	0	200[32]; 1000[60];
317	Atmel	ATSAMG53N18 internal	0	0	1	47	2	32	1	1	0	0	0	0	0	0	0	0	0	1	0	200[32]; 1000[124];
318	Atmel	ATSAMG53N19 internal	0	0	1	47	2	32	1	1	0	0	0	0	0	0	0	0	0	1	0	200[32]; 1000[124];
319	Atmel	ATSAMG54G19 internal	0	0	1	47	2	32	1	1	0	0	0	0	0	0	0	0	0	1	0	200[32]; 1000[124];
320	Atmel	ATSAMG54J19 internal	0	0	1	47	2	32	1	1	0	0	0	0	0	0	0	0	0	1	0	200[32]; 1000[124];
321	Atmel	ATSAMG54N19 internal	0	0	1	47	2	32	1	1	0	0	0	0	0	0	0	0	0	1	0	200[32]; 1000[124];
322	Atmel	ATSAMG55G18 internal	0	0	1	47	4	32	1	1	0	0	0	0	0	0	0	0	0	1	0	200[32]; 2000[30];
323	Atmel	ATSAMG55G19 internal	0	0	1	47	4	32	1	1	0	0	0	0	0	0	0	0	0	1	0	200[32]; 2000[62];
324	Atmel	ATSAMG55J18 internal	0	0	1	47	4	32	1	1	0	0	0	0	0	0	0	0	0	1	0	200[32]; 2000[30];
325	Atmel	ATSAMG55J19 internal	0	0	1	47	4	32	1	1	0	0	0	0	0	0	0	0	0	1	0	200[32]; 2000[62];
326	Atmel	ATSAMG55N19 internal	0	0	1	47	4	32	1	1	0	0	0	0	0	0	0	0	0	1	0	200[32]; 2000[62];
327	Atmel	ATSAMR21x15 internal	0	0	1	58	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	100[128];10[1],804000;
328	Atmel	ATSAMH21x15 internal	0	0	1	58	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	100[128];10[1],804000;
329	Atmel	ATSAMH21x16 internal	0	0	1	58	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	100[256];10[1],804000;
330	Atmel	ATSAML21x15 internal	0	0	1	58	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	100[128];10[1],804000;
331	Atmel	ATSAML21x16 internal	0	0	1	58	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	100[256];10[1],804000;
332	Atmel	ATSAML21x17 internal	0	0	1	58	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	100[512];10[1],804000;
333	Atmel	ATSAML21x18 internal	0	0	1	58	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	100[1024];10[1],804000;
334	Atmel	ATSAML22x16 internal	0	0	1	58	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	100[256];10[1],804000;
335	Atmel	ATSAML22x17 internal	0	0	1	58	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	100[512];10[1],804000;
336	Atmel	ATSAML22x18 internal	0	0	1	58	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	100[1024];10[1],804000;
337	Atmel	ATSAMR21x16 internal	0	0	1	58	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	100[256];10[1],804000;
338	Atmel	ATSAMR21x17 internal	0	0	1	58	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	100[512];10[1],804000;
339	Atmel	ATSAMR21x18 internal	0	0	1	58	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	100[1024];10[1],804000;
340	Atmel	ATSAMR21x19 internal	0	0	1	58	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	100[2048];10[1],804000;
341	Atmel	ATSAMG51x18 internal	0	0	1	58	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	200[32]; 1000[60];
342	Atmel	ATSAMG53x19 internal	0	0	1	58	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	200[32]; 1000[60];
343	Atmel	ATSAMS7xx19 internal	0	0	1	83	0	32	1	1	0	0	0	0	0	0	0	0	0	1	0	2000[2]; 1C000[1]; 20000[3];
344	Atmel	ATSAMS7xx20 internal	0	0	1	83	0	32	1	1	0	0	0	0	0	0	0	0	0	1	0	2000[2]; 1C000[1]; 20000[7];
345	Atmel	ATSAMS7xx21 internal	0	0	1	83	0	32	1	1	0	0	0	0	0	0	0	0	0	1	0	2000[2]; 1C000[1]; 20000[15];
346	Atmel	ATSAMV21x14 internal	0	0	1	58	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	100[64];
347	Atmel	ATSAMV21x15 internal	0	0	1	58	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	100[128];
348	Atmel	ATSAMV21x16 internal	0	0	1	58	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	100[256];
349	Atmel	ATSAMV7xx19 internal	0	0	1	83	0	32	1	1	0	0	0	0	0	0	0	0	0	1	0	2000[2]; 1C000[1]; 20000[3];
350	Atmel	ATSAMV7xx20 internal	0	0	1	83	0	32	1	1	0	0	0	0	0	0	0	0	0	1	0	2000[2]; 1C000[1]; 20000[7];
351	Atmel	ATSAMV7xx21 internal	0	0	1	83	0	32	1	1	0	0	0	0	0	0	0	0	0	1	0	2000[2]; 1C000[1]; 20000[15];
352	AyDeeKay	Chaveiro internal	0	0	1	46	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	800[79];
353	AyDeeKay	Heimdall Slave internal	0	0	1	46	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	800[79];
354	AyDeeKay	KamCho internal	0	0	1	46	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	800[79];
355	AyDeeKay	uSesame internal	0	0	1	46	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	800[79];
356	AyDeeKay	uSobek internal	0	0	1	46	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	800[79];
357	Cutera	LH28F640BFHE-PBTL (x2)	B000B1	B000B1	0	10	0	16	1	0	0	1	0	0	0	0	0	0	1	0	0	2000[8]; 10000[127]; 2000[8],10000000; 10000[127];
358	Cutera	LH28F128BFHED	B000B0	B000B0	0	10	0	16	1	0	0	1	0	0	0	0	0	0	1	0	0	10000[127]; 2000[8]; 2000[8],4000000; 10000[127];
359	Cutera	LH28F128BFHED-473	B000B0	B000B0	0	10	0	16	1	0	0	1	0	0	0	0	0	0	1	0	0	10000[127]; 2000[8]; 2000[8]; 10000[127]; 10000[127]; 2000[8]; 2000[8]; 10000[127];
360	Cypress	CY8C4013xxx internal	0	0	1	62	1	32	0	0	0	0	0	0	0	0	0	0	0	0	0	2000[1];
361	Cypress	CY8C4014xxx internal	0	0	1	62	1	32	0	0	0	0	0	0	0	0	0	0	0	0	0	4000[1];
362	Cypress	CY8C4024xxx-Sxxx internal	0	0	1	62	3	32	0	0	0	0	0	0	0	0	0	0	0	0	0	4000[1];
363	Cypress	CY8C4025xxx-Sxxx internal	0	0	1	62	3	32	0	0	0	0	0	0	0	0	0	0	0	0	0	8000[1];
364	Cypress	CY8C4045xxx-Sxxx internal	0	0	1	62	3	32	0	0	0	0	0	0	0	0	0	0	0	0	0	8000[1];
365	Cypress	CY8C4124xxx internal	0	0	1	62	0	32	0	0	0	0	0	0	0	0	0	0	0	0	0	4000[1];
366	Cypress	CY8C4124xxx-Sxxx internal	0	0	1	62	2	32	0	0	0	0	0	0	0	0	0	0	0	0	0	4000[1];
367	Cypress	CY8C4125xxx internal	0	0	1	62	0	32	0	0	0	0	0	0	0	0	0	0	0	0	0	8000[1];
368	Cypress	CY8C4125xxx-Sxxx internal	0	0	1	62	2	32	0	0	0	0	0	0	0	0	0	0	0	0	0	8000[1];
369	Cypress	CY8C4127xxx internal	0	0	1	62	2	32	0	0	0	0	0	0	0	0	0	0	0	0	0	20000[1];
370	Cypress	CY8C4128xxx-BLxxx internal	0	0	1	62	5	32	0	0	0	0	0	0	0	0	0	0	0	0	0	40000[1];
371	Cypress	CY8C4146xxx-Sxxx internal	0	0	1	62	2	32	0	0	0	0	0	0	0	0	0	0	0	0	0	10000[1];
372	Cypress	CY8C41x5xxx-Mxxx internal	0	0	1	62	2	32	0	0	0	0	0	0	0	0	0	0	0	0	0	8000[1];
373	Cypress	CY8C41x6xxx-Mxxx internal	0	0	1	62	2	32	0	0	0	0	0	0	0	0	0	0	0	0	0	10000[1];
374	Cypress	CY8C41x7xxx-Mxxx internal	0	0	1	62	2	32	0	0	0	0	0	0	0	0	0	0	0	0	0	20000[1];
375	Cypress	CY8C4244xxx internal	0	0	1	62	0	32	0	0	0	0	0	0	0	0	0	0	0	0	0	4000[1];
376	Cypress	CY8C4245xxx internal	0	0	1	62	0	32	0	0	0	0	0	0	0	0	0	0	0	0	0	8000[1];
377	Cypress	CY8C4245xxx-Dxxx internal	0	0	1	62	2	32	0	0	0	0	0	0	0	0	0	0	0	0	0	8000[1];
378	Cypress	CY8C4246xxx-Dxxx internal	0	0	1	62	2	32	0	0	0	0	0	0	0	0	0	0	0	0	0	10000[1];
379	Cypress	CY8C4247xxx internal	0	0	1	62	2	32	0	0	0	0	0	0	0	0	0	0	0	0	0	20000[1];
380	Cypress	CY8C4247xxx-BLxxx internal	0	0	1	62	2	32	0	0	0	0	0	0	0	0	0	0	0	0	0	8000[1];
381	Cypress	CY8C4248xxx-BLxxx internal	0	0	1	62	5	32	0	0	0	0	0	0	0	0	0	0	0	0	0	40000[1];
382	Cypress	CY8C42x5xxx-Mxxx internal	0	0	1	62	2	32	0	0	0	0	0	0	0	0	0	0	0	0	0	8000[1];
383	Cypress	CY8C42x6xxx-Mxxx internal	0	0	1	62	2	32	0	0	0	0	0	0	0	0	0	0	0	0	0	10000[1];
384	Cypress	CY8C42x7xxx-Mxxx internal	0	0	1	62	2	32	0	0	0	0	0	0	0	0	0	0	0	0	0	20000[1];
385	Cypress	CY8C4A24xxx internal	0	0	1	62	3	32	0	0	0	0	0	0	0	0	0	0	0	0	0	4000[1];
386	Cypress	CY8C4A25xxx internal	0	0	1	62	3	32	0	0	0	0	0	0	0	0	0	0	0	0	0	4000[1];
387	Cypress	CY8C4A45xxx internal	0	0	1	62	3	32	0	0	0	0	0	0	0	0	0	0	0	0	0	8000[1];
388	Cypress	CY8C5266xxxLP internal	0	0	1	57	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	100[256];
389	Cypress	CY8C5267xxxLP internal	0	0	1	57	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	100[512];
390	Cypress	CY8C5268xxxLP internal	0	0	1	57	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	100[1024];
391	Cypress	CY8C5466xxxLP internal	0	0	1	57	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	100[256];
392	Cypress	CY8C5467xxxLP internal	0	0	1	57	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	100[512];
393	Cypress	CY8C5468xxxLP internal	0	0	1	57	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	100[1024];
394	Cypress	CY8C5666xxxLP internal	0	0	1	57	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	100[256];
395	Cypress	CY8C5667xxxLP internal	0	0	1	57	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	100[512];
396	Cypress	CY8C5668xxxLP internal	0	0	1	57	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	100[1024];
397	Cypress	CY8C5866xxxLP internal	0	0	1	57	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	100[256];
398	Cypress	CY8C5867xxxLP internal	0	0	1	57	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	100[512];
399	Cypress	CY8C5868xxxLP internal	0	0	1	57	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	100[1024];
400	Cypress	CYBL10xxx internal	0	0	1	62	2	32	0	0	0	0	0	0	0	0	0	0	0	0	0	20000[1];
401	Cypress	CYBL10xxx-256 internal	0	0	1	62	5	32	0	0	0	0	0	0	0	0	0	0	0	0	0	40000[1];
402	Cypress	CYPD21xxx internal	0	0	1	62	3	32	0	0	0	0	0	0	0	0	0	0	0	0	0	8000[1];
403	DSPGroup	DA56KLF internal	0	0	1	20	0	32	1	1	0	0	0	0	0	0	0	0	0	0	0	2000[64];
404	Ember	EM351 internal	0	0	1	29	0	32	1	1	0	0	0	0	0	0	0	0	0	0	0	800[64];
405	Ember	EM351 (allow CIB) internal	0	0	1	29	1	32	1	1	0	0	0	0	0	0	0	0	0	0	0	800[64]; 800[1], 40800;
406	Ember	EM357 internal	0	0	1	29	0	32	1	1	0	0	0	0	0	0	0	0	0	0	0	800[96];
407	Ember	EM357 (allow CIB) internal	0	0	1	29	1	32	1	1	0	0	0	0	0	0	0	0	0	0	0	800[96]; 800[1], 40800;
408	Ember	EM3581 internal	0	0	1	29	2	32	1	1	0	0	0	0	0	0	0	0	0	0	0	800[128];
409	Ember	EM3582 internal	0	0	1	29	2	32	1	1	0	0	0	0	0	0	0	0	0	0	0	800[128];
410	Ember	EM3585 internal	0	0	1	29	2	32	1	1	0	0	0	0	0	0	0	0	0	0	0	800[256];
411	Ember	EM3586 internal	0	0	1	29	2	32	1	1	0	0	0	0	0	0	0	0	0	0	0	800[256];
412	Ember	EM3587 internal	0	0	1	29	2	32	1	1	0	0	0	0	0	0	0	0	0	0	0	800[256];
413	Ember	EM3588 internal	0	0	1	29	2	32	1	1	0	0	0	0	0	0	0	0	0	0	0	800[256];
414	Energy Micro	EFM32GxxxF16 internal	0	0	1	28	0	32	1	0	0	0	0	0	0	0	0	0	0	1	1	200[32]; 200[1], FE00000; 200[1], FE04000;
415	Energy Micro	EFM32GxxxF32 internal	0	0	1	28	0	32	1	0	0	0	0	0	0	0	0	0	0	1	1	200[64]; 200[1], FE00000; 200[1], FE04000;
416	Energy Micro	EFM32GxxxF64 internal	0	0	1	28	0	32	1	0	0	0	0	0	0	0	0	0	0	1	1	200[128]; 200[1], FE00000; 200[1], FE04000;
417	Energy Micro	EFM32GxxxF128 internal	0	0	1	28	0	32	1	0	0	0	0	0	0	0	0	0	0	1	1	200[256]; 200[1], FE00000; 200[1], FE04000;
418	Energy Micro	EFM32GGxxxF512 internal	0	0	1	28	0	32	1	0	0	0	0	0	0	0	0	0	0	1	1	1000[128]; 800[1], FE00000; 800[1], FE04000;
419	Energy Micro	EFM32GGxxxF1024 internal	0	0	1	28	0	32	1	0	0	0	0	0	0	0	0	0	0	1	1	1000[256]; 800[1], FE00000; 800[1], FE04000;
420	Energy Micro	EFM32LGxxxF64 internal	0	0	1	28	0	32	1	0	0	0	0	0	0	0	0	0	0	1	1	800[32]; 800[1], FE00000; 800[1], FE04000;
421	Energy Micro	EFM32LGxxxF128 internal	0	0	1	28	0	32	1	0	0	0	0	0	0	0	0	0	0	1	1	800[64]; 800[1], FE00000; 800[1], FE04000;
422	Energy Micro	EFM32LGxxxF256 internal	0	0	1	28	0	32	1	0	0	0	0	0	0	0	0	0	0	1	1	800[128]; 800[1], FE00000; 800[1], FE04000;
423	Energy Micro	EFM32TGxxxF4 internal	0	0	1	28	0	32	1	0	0	0	0	0	0	0	0	0	0	1	1	200[8]; 200[1], FE00000; 200[1], FE04000;
424	Energy Micro	EFM32TGxxxF8 internal	0	0	1	28	0	32	1	0	0	0	0	0	0	0	0	0	0	1	1	200[16]; 200[1], FE00000; 200[1], FE04000;
425	Energy Micro	EFM32TGxxxF16 internal	0	0	1	28	0	32	1	0	0	0	0	0	0	0	0	0	0	1	1	200[32]; 200[1], FE00000; 200[1], FE04000;
426	Energy Micro	EFM32TGxxxF32 internal	0	0	1	28	0	32	1	0	0	0	0	0	0	0	0	0	0	1	1	200[64]; 200[1], FE00000; 200[1], FE04000;
427	Energy Micro	EFM32WGxxxF64 internal	0	0	1	28	0	32	1	0	0	0	0	0	0	0	0	0	0	1	1	800[32]; 800[1], FE00000; 800[1], FE04000;
428	Energy Micro	EFM32WGxxxF128 internal	0	0	1	28	0	32	1	0	0	0	0	0	0	0	0	0	0	1	1	800[64]; 800[1], FE00000; 800[1], FE04000;
429	Energy Micro	EFM32WGxxxF256 internal	0	0	1	28	0	32	1	0	0	0	0	0	0	0	0	0	0	1	1	800[128]; 800[1], FE00000; 800[1], FE04000;
430	Energy Micro	EFM32ZGxxxF4 internal	0	0	1	28	0	32	1	0	0	0	0	0	0	0	0	0	0	1	0	400[4]; 400[1], FE00000; 400[1], FE04000;
431	Energy Micro	EFM32ZGxxxF8 internal	0	0	1	28	0	32	1	0	0	0	0	0	0	0	0	0	0	1	0	400[8]; 400[1], FE00000; 400[1], FE04000;
432	Energy Micro	EFM32ZGxxxF16 internal	0	0	1	28	0	32	1	0	0	0	0	0	0	0	0	0	0	1	0	400[16]; 400[1], FE00000; 400[1], FE04000;
433	Energy Micro	EFM32ZGxxxF32 internal	0	0	1	28	0	32	1	0	0	0	0	0	0	0	0	0	0	1	0	400[32]; 400[1], FE00000; 400[1], FE04000;
434	Eon	EN29PL032	1C227E	1C007E	0	16	0	16	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[8]; 10000[62]; 2000[8];
435	Eon	EN29PL064	1C227E	1C007E	0	16	0	16	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[8]; 10000[126]; 2000[8];
436	Eon	EN29LV800BB	1C225B	1C005B	0	1	0	16	1	0	0	0	0	0	0	0	0	0	0	0	0	4000; 2000[2]; 8000; 10000[15];
437	Eon	EN29LV800BT	1C22DA	1C00DA	0	1	0	16	1	0	0	0	0	0	0	0	0	0	0	0	0	10000[15]; 8000; 2000[2]; 4000;
438	Eon	EN29LV800CB	1C225B	1C005B	0	1	0	16	1	0	0	0	0	0	0	0	0	0	0	0	0	4000; 2000[2]; 8000; 10000[15];
439	Eon	EN29LV800CT	1C22DA	1C00DA	0	1	0	16	1	0	0	0	0	0	0	0	0	0	0	0	0	10000[15]; 8000; 2000[2]; 4000;
440	Eon	EN29LV160BB	1C2249	1C0049	0	1	0	16	1	0	0	1	0	0	1	0	0	0	0	0	0	4000[1]; 2000[2]; 8000[1]; 10000[31];
441	Eon	EN29LV160BT	1C22C4	1C00C4	0	1	0	16	1	0	0	1	0	0	1	0	0	0	0	0	0	10000[31]; 8000[1]; 2000[2]; 4000[1];
442	Eon	EN71PL032	1C227E	1C007E	0	16	0	16	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[8]; 10000[62]; 2000[8];
443	Freescale	VF3xxR_A5 internal	0	0	1	79	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	10000[1024];
444	Freescale	VF3xxR_A5_ParallelMode internal	0	0	1	79	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	20000[1024];
445	Freescale	VF5xxR_A5 internal	0	0	1	79	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	10000[1024];
446	Freescale	VF5xxR_A5_ParallelMode internal	0	0	1	79	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	20000[1024];
447	Freescale	VF6xx_A5 internal	0	0	1	79	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	10000[1024];
448	Freescale	VF6xx_A5_ParallelMode internal	0	0	1	79	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	20000[1024];
449	Freescale	VF7xx_A5 internal	0	0	1	79	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	10000[1024];
450	Freescale	VF7xx_A5_ParallelMode internal	0	0	1	79	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	20000[1024];
451	Freescale	MAC71x1 internal	0	0	1	12	0	32	1	0	0	0	0	0	0	0	0	0	0	0	1	1000[128];
452	Freescale	MAC71x2 internal	0	0	1	12	0	32	1	0	0	0	0	0	0	0	0	0	0	0	1	1000[64];
453	Freescale	MAC71x6 internal	0	0	1	12	0	32	1	0	0	0	0	0	0	0	0	0	0	0	1	1000[256];
454	Freescale	MK02FN64xxx10 internal	0	0	1	35	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	800[32];
455	Freescale	MK02FN64xxx10 internal (allow security)	0	0	1	35	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	800[32];
456	Freescale	MK02FN128xxx10 internal	0	0	1	35	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	800[64];
457	Freescale	MK02FN128xxx10 internal (allow security)	0	0	1	35	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	800[64];
458	Freescale	MK10DN32xxx5 internal	0	0	1	35	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	400[32];
459	Freescale	MK10DN32xxx5 internal (allow security)	0	0	1	35	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	400[32];
460	Freescale	MK10DN64xxx5 internal	0	0	1	35	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	400[64];
461	Freescale	MK10DN64xxx5 internal (allow security)	0	0	1	35	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	400[64];
462	Freescale	MK10DN128xxx5 internal	0	0	1	35	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	400[128];
463	Freescale	MK10DN128xxx5 internal (allow security)	0	0	1	35	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	400[128];
464	Freescale	MK10DN512xxx10 internal	0	0	1	35	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	800[256];
465	Freescale	MK10DN512xxx10 internal (allow security)	0	0	1	35	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	800[256];
466	Freescale	MK10DX32xxx5 internal	0	0	1	35	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	400[32]; 400[32], 10000000;
467	Freescale	MK10DX32xxx5 internal (allow security)	0	0	1	35	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	400[32]; 400[32], 10000000;
468	Freescale	MK10DX64xxx5 internal	0	0	1	35	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	400[64]; 400[32], 10000000;
469	Freescale	MK10DX64xxx5 internal (allow security)	0	0	1	35	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	400[64]; 400[32], 10000000;
470	Freescale	MK10DX64xxx7 internal	0	0	1	35	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	800[32]; 400[32], 10000000;
471	Freescale	MK10DX64xxx7 internal (allow security)	0	0	1	35	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	800[32]; 400[32], 10000000;
472	Freescale	MK10DX128xxx5 internal	0	0	1	35	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	400[128]; 400[32], 10000000;
473	Freescale	MK10DX128xxx5 internal (allow security)	0	0	1	35	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	400[128]; 400[32], 10000000;
474	Freescale	MK10DX128xxx7 internal	0	0	1	35	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	800[64]; 400[32], 10000000;
475	Freescale	MK10DX128xxx7 internal (allow security)	0	0	1	35	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	800[64]; 400[32], 10000000;
476	Freescale	MK10DX128xxx10 internal	0	0	1	35	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	800[64]; 800[64], 10000000;
477	Freescale	MK10DX128xxx10 internal (allow security)	0	0	1	35	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	800[64]; 800[64], 10000000;
478	Freescale	MK10DX256xxx7 internal	0	0	1	35	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	800[128]; 400[32], 10000000;
479	Freescale	MK10DX256xxx7 internal (allow security)	0	0	1	35	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	800[128]; 400[32], 10000000;
480	Freescale	MK10DX256xxx10 internal	0	0	1	35	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	800[128]; 800[128], 10000000;
481	Freescale	MK10DX256xxx10 internal (allow security)	0	0	1	35	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	800[128]; 800[128], 10000000;
482	Freescale	MK10FN1M0xxx12 internal	0	0	1	35	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	1000[256];
483	Freescale	MK10FN1M0xxx12 internal (allow security)	0	0	1	35	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	1000[256];
484	Freescale	MK10FX512xxx12 internal	0	0	1	35	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	1000[128]; 1000[128], 10000000;
485	Freescale	MK10FX512xxx12 internal (allow security)	0	0	1	35	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	1000[128]; 1000[128], 10000000;
486	Freescale	MK11DN512xxx5 internal	0	0	1	35	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	800[256];
487	Freescale	MK11DN512xxx5 internal (allow security)	0	0	1	35	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	800[256];
488	Freescale	MK11DX128xxx5 internal	0	0	1	35	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	800[64]; 800[32], 10000000;
489	Freescale	MK11DX128xxx5 internal (allow security)	0	0	1	35	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	800[64]; 800[32], 10000000;
490	Freescale	MK11DX256xxx5 internal	0	0	1	35	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	800[128]; 800[32], 10000000;
491	Freescale	MK11DX256xxx5 internal (allow security)	0	0	1	35	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	800[128]; 800[32], 10000000;
492	Freescale	MK12DN512xxx5 internal	0	0	1	35	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	800[256];
493	Freescale	MK12DN512xxx5 internal (allow security)	0	0	1	35	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	800[256];
494	Freescale	MK12DX128xxx5 internal	0	0	1	35	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	800[64]; 800[32], 10000000;
495	Freescale	MK12DX128xxx5 internal (allow security)	0	0	1	35	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	800[64]; 800[32], 10000000;
496	Freescale	MK12DX256xxx5 internal	0	0	1	35	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	800[128]; 800[32], 10000000;
497	Freescale	MK12DX256xxx5 internal (allow security)	0	0	1	35	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	800[128]; 800[32], 10000000;
498	Freescale	MK20DN32xxx5 internal	0	0	1	35	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	400[32];
499	Freescale	MK20DN32xxx5 internal (allow security)	0	0	1	35	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	400[32];
500	Freescale	MK20DN64xxx5 internal	0	0	1	35	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	400[64];
501	Freescale	MK20DN64xxx5 internal (allow security)	0	0	1	35	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	400[64];
502	Freescale	MK20DN128xxx5 internal	0	0	1	35	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	400[128];
503	Freescale	MK20DN128xxx5 internal (allow security)	0	0	1	35	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	400[128];
504	Freescale	MK20DN512xxx10 internal	0	0	1	35	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	800[256];
505	Freescale	MK20DN512xxx10 internal (allow security)	0	0	1	35	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	800[256];
506	Freescale	MK20DX32xxx5 internal	0	0	1	35	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	400[32]; 400[32], 10000000;
507	Freescale	MK20DX32xxx5 internal (allow security)	0	0	1	35	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	400[32]; 400[32], 10000000;
508	Freescale	MK20DX64xxx5 internal	0	0	1	35	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	400[64]; 400[32], 10000000;
509	Freescale	MK20DX64xxx5 internal (allow security)	0	0	1	35	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	400[64]; 400[32], 10000000;
510	Freescale	MK20DX64xxx7 internal	0	0	1	35	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	800[32]; 400[32], 10000000;
511	Freescale	MK20DX64xxx7 internal (allow security)	0	0	1	35	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	800[32]; 400[32], 10000000;
512	Freescale	MK20DX128xxx5 internal	0	0	1	35	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	400[128]; 400[32], 10000000;
513	Freescale	MK20DX128xxx5 internal (allow security)	0	0	1	35	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	400[128]; 400[32], 10000000;
514	Freescale	MK20DX128xxx7 internal	0	0	1	35	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	800[64]; 400[32], 10000000;
515	Freescale	MK20DX128xxx7 internal (allow security)	0	0	1	35	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	800[64]; 400[32], 10000000;
516	Freescale	MK20DX128xxx10 internal	0	0	1	35	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	800[64]; 800[64], 10000000;
517	Freescale	MK20DX128xxx10 internal (allow security)	0	0	1	35	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	800[64]; 800[64], 10000000;
518	Freescale	MK20DX256xxx7 internal	0	0	1	35	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	800[128]; 400[32], 10000000;
519	Freescale	MK20DX256xxx7 internal (allow security)	0	0	1	35	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	800[128]; 400[32], 10000000;
520	Freescale	MK20DX256xxx10 internal	0	0	1	35	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	800[128]; 800[128], 10000000;
521	Freescale	MK20DX256xxx10 internal (allow security)	0	0	1	35	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	800[128]; 800[128], 10000000;
522	Freescale	MK20FN1M0xxx12 internal	0	0	1	35	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	1000[256];
523	Freescale	MK20FN1M0xxx12 internal (allow security)	0	0	1	35	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	1000[256];
524	Freescale	MK20FX512xxx12 internal	0	0	1	35	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	1000[128]; 1000[128], 10000000;
525	Freescale	MK20FX512xxx12 internal (allow security)	0	0	1	35	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	1000[128]; 1000[128], 10000000;
526	Freescale	MK21DN512xxx5 internal	0	0	1	35	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	800[256];
527	Freescale	MK21DN512xxx5 internal (allow security)	0	0	1	35	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	800[256];
528	Freescale	MK21DX128xxx5 internal	0	0	1	35	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	800[64]; 800[32], 10000000;
529	Freescale	MK21DX128xxx5 internal (allow security)	0	0	1	35	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	800[64]; 800[32], 10000000;
530	Freescale	MK21DX256xxx5 internal	0	0	1	35	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	800[128]; 800[32], 10000000;
531	Freescale	MK21DX256xxx5 internal (allow security)	0	0	1	35	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	800[128]; 800[32], 10000000;
532	Freescale	MK21FN1M0xxx12 internal	0	0	1	35	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	1000[256];
533	Freescale	MK21FN1M0xxx12 internal (allow security)	0	0	1	35	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	1000[256];
534	Freescale	MK21FX512xxx12 internal	0	0	1	35	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	1000[128]; 1000[32], 10000000;
535	Freescale	MK21FX512xxx12 internal (allow security)	0	0	1	35	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	1000[128]; 1000[32], 10000000;
536	Freescale	MK22DN512xxx5 internal	0	0	1	35	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	800[256];
537	Freescale	MK22DN512xxx5 internal (allow security)	0	0	1	35	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	800[256];
538	Freescale	MK22DX128xxx5 internal	0	0	1	35	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	800[64]; 800[32], 10000000;
539	Freescale	MK22DX128xxx5 internal (allow security)	0	0	1	35	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	800[64]; 800[32], 10000000;
540	Freescale	MK22DX256xxx5 internal	0	0	1	35	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	800[128]; 800[32], 10000000;
541	Freescale	MK22DX256xxx5 internal (allow security)	0	0	1	35	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	800[128]; 800[32], 10000000;
542	Freescale	MK22FN128xxx10 internal	0	0	1	35	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	800[64];
543	Freescale	MK22FN128xxx10 internal (allow security)	0	0	1	35	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	800[64];
544	Freescale	MK22FN256xxx12 internal	0	0	1	35	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	800[128];
545	Freescale	MK22FN256xxx12 internal (allow security)	0	0	1	35	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	800[128];
546	Freescale	MK22FN512xxx12 internal	0	0	1	35	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	800[256];
547	Freescale	MK22FN512xxx12 internal (allow security)	0	0	1	35	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	800[256];
548	Freescale	MK22FN1M0xxx12 internal	0	0	1	35	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	1000[256];
549	Freescale	MK22FN1M0xxx12 internal (allow security)	0	0	1	35	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	1000[256];
550	Freescale	MK22FX512xxx12 internal	0	0	1	35	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	1000[128]; 1000[32], 10000000;
551	Freescale	MK22FX512xxx12 internal (allow security)	0	0	1	35	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	1000[128]; 1000[32], 10000000;
552	Freescale	MK24FN256xxx12 internal	0	0	1	35	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	1000[64];
553	Freescale	MK24FN256xxx12 internal (allow security)	0	0	1	35	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	1000[64];
554	Freescale	MK24FN1M0xxx12 internal	0	0	1	35	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	1000[256];
555	Freescale	MK24FN1M0xxx12 internal (allow security)	0	0	1	35	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	1000[256];
556	Freescale	MK26FN2M0xxx18 internal	0	0	1	35	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	1000[512];
557	Freescale	MK26FN2M0xxx18 internal (allow security)	0	0	1	35	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	1000[512];
558	Freescale	MK30DN512xxx10 internal	0	0	1	35	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	800[256];
559	Freescale	MK30DN512xxx10 internal (allow security)	0	0	1	35	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	800[256];
560	Freescale	MK30DX64xxx7 internal	0	0	1	35	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	800[32]; 400[32], 10000000;
561	Freescale	MK30DX64xxx7 internal (allow security)	0	0	1	35	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	800[32]; 400[32], 10000000;
562	Freescale	MK30DX128xxx7 internal	0	0	1	35	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	800[64]; 400[32], 10000000;
563	Freescale	MK30DX128xxx7 internal (allow security)	0	0	1	35	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	800[64]; 400[32], 10000000;
564	Freescale	MK30DX128xxx10 internal	0	0	1	35	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	800[64]; 800[64], 10000000;
565	Freescale	MK30DX128xxx10 internal (allow security)	0	0	1	35	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	800[64]; 800[64], 10000000;
566	Freescale	MK30DX256xxx7 internal	0	0	1	35	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	800[128]; 400[32], 10000000;
567	Freescale	MK30DX256xxx7 internal (allow security)	0	0	1	35	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	800[128]; 400[32], 10000000;
568	Freescale	MK30DX256xxx10 internal	0	0	1	35	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	800[128]; 800[128], 10000000;
569	Freescale	MK30DX256xxx10 internal (allow security)	0	0	1	35	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	800[128]; 800[128], 10000000;
570	Freescale	MK40DN512xxx10 internal	0	0	1	35	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	800[256];
571	Freescale	MK40DN512xxx10 internal (allow security)	0	0	1	35	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	800[256];
572	Freescale	MK40DX64xxx7 internal	0	0	1	35	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	800[32]; 400[32], 10000000;
573	Freescale	MK40DX64xxx7 internal (allow security)	0	0	1	35	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	800[32]; 400[32], 10000000;
574	Freescale	MK40DX128xxx7 internal	0	0	1	35	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	800[64]; 400[32], 10000000;
575	Freescale	MK40DX128xxx7 internal (allow security)	0	0	1	35	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	800[64]; 400[32], 10000000;
576	Freescale	MK40DX128xxx10 internal	0	0	1	35	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	800[64]; 800[64], 10000000;
577	Freescale	MK40DX128xxx10 internal (allow security)	0	0	1	35	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	800[64]; 800[64], 10000000;
578	Freescale	MK40DX256xxx7 internal	0	0	1	35	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	800[128]; 400[32], 10000000;
579	Freescale	MK40DX256xxx7 internal (allow security)	0	0	1	35	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	800[128]; 400[32], 10000000;
580	Freescale	MK40DX256xxx10 internal	0	0	1	35	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	800[128]; 800[128], 10000000;
581	Freescale	MK40DX256xxx10 internal (allow security)	0	0	1	35	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	800[128]; 800[128], 10000000;
582	Freescale	MK50DN512xxx10 internal	0	0	1	35	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	800[256];
583	Freescale	MK50DN512xxx10 internal (allow security)	0	0	1	35	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	800[256];
584	Freescale	MK50DX128xxx7 internal	0	0	1	35	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	800[64]; 400[32], 10000000;
585	Freescale	MK50DX128xxx7 internal (allow security)	0	0	1	35	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	800[64]; 400[32], 10000000;
586	Freescale	MK50DX256xxx7 internal	0	0	1	35	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	800[128]; 400[32], 10000000;
587	Freescale	MK50DX256xxx7 internal (allow security)	0	0	1	35	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	800[128]; 400[32], 10000000;
588	Freescale	MK50DX256xxx10 internal	0	0	1	35	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	800[128]; 800[128], 10000000;
589	Freescale	MK50DX256xxx10 internal (allow security)	0	0	1	35	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	800[128]; 800[128], 10000000;
590	Freescale	MK51DN256xxx10 internal	0	0	1	35	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	800[128];
591	Freescale	MK51DN256xxx10 internal (allow security)	0	0	1	35	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	800[128];
592	Freescale	MK51DN512xxx10 internal	0	0	1	35	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	800[256];
593	Freescale	MK51DN512xxx10 internal (allow security)	0	0	1	35	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	800[256];
594	Freescale	MK51DX128xxx7 internal	0	0	1	35	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	800[64]; 400[32], 10000000;
595	Freescale	MK51DX128xxx7 internal (allow security)	0	0	1	35	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	800[64]; 400[32], 10000000;
596	Freescale	MK51DX256xxx7 internal	0	0	1	35	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	800[128]; 400[32], 10000000;
597	Freescale	MK51DX256xxx7 internal (allow security)	0	0	1	35	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	800[128]; 400[32], 10000000;
598	Freescale	MK51DX256xxx10 internal	0	0	1	35	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	800[128]; 800[128], 10000000;
599	Freescale	MK51DX256xxx10 internal (allow security)	0	0	1	35	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	800[128]; 800[128], 10000000;
600	Freescale	MK52DN512xxx10 internal	0	0	1	35	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	800[256];
601	Freescale	MK52DN512xxx10 internal (allow security)	0	0	1	35	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	800[256];
602	Freescale	MK53DN512xxx10 internal	0	0	1	35	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	800[256];
603	Freescale	MK53DN512xxx10 internal (allow security)	0	0	1	35	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	800[256];
604	Freescale	MK53DX256xxx10 internal	0	0	1	35	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	800[128]; 800[128], 10000000;
605	Freescale	MK53DX256xxx10 internal (allow security)	0	0	1	35	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	800[128]; 800[128], 10000000;
606	Freescale	MK60DN256xxx10 internal	0	0	1	35	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	800[128];
607	Freescale	MK60DN256xxx10 internal (allow security)	0	0	1	35	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	800[128];
608	Freescale	MK60DN512xxx10 internal	0	0	1	35	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	800[256];
609	Freescale	MK60DN512xxx10 internal (allow security)	0	0	1	35	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	800[256];
610	Freescale	MK60DX256xxx10 internal	0	0	1	35	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	800[128]; 800[128], 10000000;
611	Freescale	MK60DX256xxx10 internal (allow security)	0	0	1	35	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	800[128]; 800[128], 10000000;
612	Freescale	MK60FN1M0xxx12 internal	0	0	1	35	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	1000[256];
613	Freescale	MK60FN1M0xxx12 internal (allow security)	0	0	1	35	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	1000[256];
614	Freescale	MK60FN1M0xxx15 internal	0	0	1	35	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	1000[256];
615	Freescale	MK60FN1M0xxx15 internal (allow security)	0	0	1	35	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	1000[256];
616	Freescale	MK60FX512xxx12 internal	0	0	1	35	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	1000[128]; 1000[128], 10000000;
617	Freescale	MK60FX512xxx12 internal (allow security)	0	0	1	35	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	1000[128]; 1000[128], 10000000;
618	Freescale	MK60FX512xxx15 internal	0	0	1	35	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	1000[128]; 1000[128], 10000000;
619	Freescale	MK60FX512xxx15 internal (allow security)	0	0	1	35	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	1000[128]; 1000[128], 10000000;
620	Freescale	MK61FN1M0xxx12 internal	0	0	1	35	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	1000[256];
621	Freescale	MK61FN1M0xxx12 internal (allow security)	0	0	1	35	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	1000[256];
622	Freescale	MK61FN1M0xxx15 internal	0	0	1	35	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	1000[256];
623	Freescale	MK61FN1M0xxx15 internal (allow security)	0	0	1	35	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	1000[256];
624	Freescale	MK61FX512xxx12 internal	0	0	1	35	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	1000[128]; 1000[128], 10000000;
625	Freescale	MK61FX512xxx12 internal (allow security)	0	0	1	35	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	1000[128]; 1000[128], 10000000;
626	Freescale	MK61FX512xxx15 internal	0	0	1	35	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	1000[128]; 1000[128], 10000000;
627	Freescale	MK61FX512xxx15 internal (allow security)	0	0	1	35	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	1000[128]; 1000[128], 10000000;
628	Freescale	MK63FN1M0xxx12 internal	0	0	1	35	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	1000[256];
629	Freescale	MK63FN1M0xxx12 internal (allow security)	0	0	1	35	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	1000[256];
630	Freescale	MK64FN1M0xxx12 internal	0	0	1	35	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	1000[256];
631	Freescale	MK64FN1M0xxx12 internal (allow security)	0	0	1	35	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	1000[256];
632	Freescale	MK64FX512xxx12 internal	0	0	1	35	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	1000[128]; 1000[32], 10000000;
633	Freescale	MK64FX512xxx12 internal (allow security)	0	0	1	35	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	1000[128]; 1000[32], 10000000;
634	Freescale	MK65FN2M0xxx18 internal	0	0	1	35	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	1000[512];
635	Freescale	MK65FN2M0xxx18 internal (allow security)	0	0	1	35	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	1000[512];
636	Freescale	MK65FX1M0xxx18 internal	0	0	1	35	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	1000[256]; 1000[64], 10000000;
637	Freescale	MK65FX1M0xxx18 internal (allow security)	0	0	1	35	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	1000[256]; 1000[64], 10000000;
638	Freescale	MK66FN2M0xxx18 internal	0	0	1	35	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	1000[512];
639	Freescale	MK66FN2M0xxx18 internal (allow security)	0	0	1	35	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	1000[512];
640	Freescale	MK66FX1M0xxx18 internal	0	0	1	35	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	1000[5]; 1000[64], 10000000;
641	Freescale	MK66FX1M0xxx18 internal (allow security)	0	0	1	35	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	1000[256]; 1000[64], 10000000;
642	Freescale	MK70FN1M0xxx12 internal	0	0	1	35	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	1000[256];
643	Freescale	MK70FN1M0xxx12 internal (allow security)	0	0	1	35	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	1000[256];
644	Freescale	MK70FN1M0xxx15 internal	0	0	1	35	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	1000[256];
645	Freescale	MK70FN1M0xxx15 internal (allow security)	0	0	1	35	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	1000[256];
646	Freescale	MK70FX512xxx12 internal	0	0	1	35	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	1000[128]; 1000[128], 10000000;
647	Freescale	MK70FX512xxx12 internal (allow security)	0	0	1	35	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	1000[128]; 1000[128], 10000000;
648	Freescale	MK70FX512xxx15 internal	0	0	1	35	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	1000[128]; 1000[128], 10000000;
649	Freescale	MK70FX512xxx15 internal (allow security)	0	0	1	35	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	1000[128]; 1000[128], 10000000;
650	Freescale	MK80FN256xxx15 internal	0	0	1	35	2	32	1	0	0	0	0	0	0	0	0	0	0	0	0	1000[64];
651	Freescale	MK80FN256xxx15 internal (allow security)	0	0	1	35	3	32	1	0	0	0	0	0	0	0	0	0	0	0	0	1000[64];
652	Freescale	MK82FN256xxx15 internal	0	0	1	35	2	32	1	0	0	0	0	0	0	0	0	0	0	0	0	1000[64];
653	Freescale	MK82FN256xxx15 internal (allow security)	0	0	1	35	3	32	1	0	0	0	0	0	0	0	0	0	0	0	0	1000[64];
654	Freescale	MKE02Z16xxx2 internal	0	0	1	53	2	32	1	0	0	0	0	0	0	0	0	0	0	0	0	200[32];
655	Freescale	MKE02Z16xxx2 internal (allow security)	0	0	1	53	3	32	1	0	0	0	0	0	0	0	0	0	0	0	0	200[32];
656	Freescale	MKE02Z32xxx2 internal	0	0	1	53	2	32	1	0	0	0	0	0	0	0	0	0	0	0	0	200[64];
657	Freescale	MKE02Z32xxx2 internal (allow security)	0	0	1	53	3	32	1	0	0	0	0	0	0	0	0	0	0	0	0	200[64];
658	Freescale	MKE02Z64xxx2 internal	0	0	1	53	2	32	1	0	0	0	0	0	0	0	0	0	0	0	0	200[128];
659	Freescale	MKE02Z64xxx2 internal (allow security)	0	0	1	53	3	32	1	0	0	0	0	0	0	0	0	0	0	0	0	200[128];
660	Freescale	MKE02Z16xxx4 internal	0	0	1	53	2	32	1	0	0	0	0	0	0	0	0	0	0	0	0	200[32];
661	Freescale	MKE02Z16xxx4 internal (allow security)	0	0	1	53	3	32	1	0	0	0	0	0	0	0	0	0	0	0	0	200[32];
662	Freescale	MKE02Z32xxx4 internal	0	0	1	53	2	32	1	0	0	0	0	0	0	0	0	0	0	0	0	200[64];
663	Freescale	MKE02Z32xxx4 internal (allow security)	0	0	1	53	3	32	1	0	0	0	0	0	0	0	0	0	0	0	0	200[64];
664	Freescale	MKE02Z64xxx4 internal	0	0	1	53	2	32	1	0	0	0	0	0	0	0	0	0	0	0	0	200[128];
665	Freescale	MKE02Z64xxx4 internal (allow security)	0	0	1	53	3	32	1	0	0	0	0	0	0	0	0	0	0	0	0	200[128];
666	Freescale	MKE04Z8xxx4 internal	0	0	1	53	8	32	1	0	0	0	0	0	0	0	0	0	0	0	0	200[16];
667	Freescale	MKE04Z8xxx4 internal (allow security)	0	0	1	53	9	32	1	0	0	0	0	0	0	0	0	0	0	0	0	200[16];
668	Freescale	MKE04Z64xxx4 internal	0	0	1	53	8	32	1	0	0	0	0	0	0	0	0	0	0	0	0	200[128];
669	Freescale	MKE04Z64xxx4 internal (allow security)	0	0	1	53	9	32	1	0	0	0	0	0	0	0	0	0	0	0	0	200[128];
670	Freescale	MKE04Z128xxx4 internal	0	0	1	53	8	32	1	0	0	0	0	0	0	0	0	0	0	0	0	200[256];
671	Freescale	MKE04Z128xxx4 internal (allow security)	0	0	1	53	9	32	1	0	0	0	0	0	0	0	0	0	0	0	0	200[256];
672	Freescale	MKE06Z64xxx4 internal	0	0	1	53	6	32	1	0	0	0	0	0	0	0	0	0	0	0	0	200[128];
673	Freescale	MKE06Z64xxx4 internal (allow security)	0	0	1	53	7	32	1	0	0	0	0	0	0	0	0	0	0	0	0	200[128];
674	Freescale	MKE06Z128xxx4 internal	0	0	1	53	6	32	1	0	0	0	0	0	0	0	0	0	0	0	0	200[256];
675	Freescale	MKE06Z128xxx4 internal (allow security)	0	0	1	53	7	32	1	0	0	0	0	0	0	0	0	0	0	0	0	200[256];
676	Freescale	MKE14D128xxx3 internal	0	0	1	53	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	400[128];
677	Freescale	MKE14D128xxx3 internal (allow security)	0	0	1	53	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	400[128];
678	Freescale	MKE14D128xxx7 internal	0	0	1	53	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	400[128];
679	Freescale	MKE14D128xxx7 internal (allow security)	0	0	1	53	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	400[128];
680	Freescale	MKE14D256xxx3 internal	0	0	1	53	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	400[256];
681	Freescale	MKE14D256xxx3 internal (allow security)	0	0	1	53	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	400[256];
682	Freescale	MKE14D256xxx7 internal	0	0	1	53	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	400[256];
683	Freescale	MKE14D256xxx7 internal (allow security)	0	0	1	53	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	400[256];
684	Freescale	MKE14Z128xxx7 internal	0	0	1	91	8	32	1	0	0	0	0	0	0	0	0	0	0	0	0	400[128];
685	Freescale	MKE14Z128xxx7 internal (allow security)	0	0	1	91	9	32	1	0	0	0	0	0	0	0	0	0	0	0	0	400[128];
686	Freescale	MKE14Z256xxx7 internal	0	0	1	91	8	32	1	0	0	0	0	0	0	0	0	0	0	0	0	800[128];
687	Freescale	MKE14Z256xxx7 internal (allow security)	0	0	1	91	9	32	1	0	0	0	0	0	0	0	0	0	0	0	0	800[128];
688	Freescale	MKE15D128xxx3 internal	0	0	1	53	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	400[128];
689	Freescale	MKE15D128xxx3 internal (allow security)	0	0	1	53	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	400[128];
690	Freescale	MKE15D128xxx7 internal	0	0	1	53	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	400[128];
691	Freescale	MKE15D128xxx7 internal (allow security)	0	0	1	53	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	400[128];
692	Freescale	MKE15D256xxx3 internal	0	0	1	53	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	400[256];
693	Freescale	MKE15D256xxx3 internal (allow security)	0	0	1	53	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	400[256];
694	Freescale	MKE15D256xxx7 internal	0	0	1	53	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	400[256];
695	Freescale	MKE15D256xxx7 internal (allow security)	0	0	1	53	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	400[256];
696	Freescale	MKE15Z128xxx7 internal	0	0	1	91	8	32	1	0	0	0	0	0	0	0	0	0	0	0	0	400[128];
697	Freescale	MKE15Z128xxx7 internal (allow security)	0	0	1	91	9	32	1	0	0	0	0	0	0	0	0	0	0	0	0	400[128];
698	Freescale	MKE15Z256xxx7 internal	0	0	1	91	8	32	1	0	0	0	0	0	0	0	0	0	0	0	0	800[128];
699	Freescale	MKE15Z256xxx7 internal (allow security)	0	0	1	91	9	32	1	0	0	0	0	0	0	0	0	0	0	0	0	800[128];
700	Freescale	MKE18F512xxx15 internal	0	0	1	91	2	32	1	0	0	0	0	0	0	0	0	0	0	0	0	1000[128];
701	Freescale	MKE18F512xxx15 internal (allow security)	0	0	1	91	3	32	1	0	0	0	0	0	0	0	0	0	0	0	0	1000[128];
702	Freescale	MKL02Z8xxx4 internal	0	0	1	35	4	32	1	0	0	0	0	0	0	0	0	0	0	0	0	400[8];
703	Freescale	MKL02Z8xxx4 internal (allow security)	0	0	1	35	5	32	1	0	0	0	0	0	0	0	0	0	0	0	0	400[8];
704	Freescale	MKL02Z16xxx4 internal	0	0	1	35	4	32	1	0	0	0	0	0	0	0	0	0	0	0	0	400[16];
705	Freescale	MKL02Z16xxx4 internal (allow security)	0	0	1	35	5	32	1	0	0	0	0	0	0	0	0	0	0	0	0	400[16];
706	Freescale	MKL02Z32xxx4 internal	0	0	1	35	4	32	1	0	0	0	0	0	0	0	0	0	0	0	0	400[32];
707	Freescale	MKL02Z32xxx4 internal (allow security)	0	0	1	35	5	32	1	0	0	0	0	0	0	0	0	0	0	0	0	400[32];
708	Freescale	MKL03Z8xxx4 internal	0	0	1	35	4	32	1	0	0	0	0	0	0	0	0	0	0	0	0	400[8];
709	Freescale	MKL03Z8xxx4 internal (allow security)	0	0	1	35	5	32	1	0	0	0	0	0	0	0	0	0	0	0	0	400[8];
710	Freescale	MKL03Z16xxx4 internal	0	0	1	35	4	32	1	0	0	0	0	0	0	0	0	0	0	0	0	400[16];
711	Freescale	MKL03Z16xxx4 internal (allow security)	0	0	1	35	5	32	1	0	0	0	0	0	0	0	0	0	0	0	0	400[16];
712	Freescale	MKL03Z32xxx4 internal	0	0	1	35	4	32	1	0	0	0	0	0	0	0	0	0	0	0	0	400[32];
713	Freescale	MKL03Z32xxx4 internal (allow security)	0	0	1	35	5	32	1	0	0	0	0	0	0	0	0	0	0	0	0	400[32];
714	Freescale	MKL04Z8xxx4 internal	0	0	1	35	4	32	1	0	0	0	0	0	0	0	0	0	0	0	0	400[8];
715	Freescale	MKL04Z8xxx4 internal (allow security)	0	0	1	35	5	32	1	0	0	0	0	0	0	0	0	0	0	0	0	400[8];
716	Freescale	MKL04Z16xxx4 internal	0	0	1	35	4	32	1	0	0	0	0	0	0	0	0	0	0	0	0	400[16];
717	Freescale	MKL04Z16xxx4 internal (allow security)	0	0	1	35	5	32	1	0	0	0	0	0	0	0	0	0	0	0	0	400[16];
718	Freescale	MKL04Z32xxx4 internal	0	0	1	35	4	32	1	0	0	0	0	0	0	0	0	0	0	0	0	400[32];
719	Freescale	MKL04Z32xxx4 internal (allow security)	0	0	1	35	5	32	1	0	0	0	0	0	0	0	0	0	0	0	0	400[32];
720	Freescale	MKL05Z8xxx4 internal	0	0	1	35	4	32	1	0	0	0	0	0	0	0	0	0	0	0	0	400[8];
721	Freescale	MKL05Z8xxx4 internal (allow security)	0	0	1	35	5	32	1	0	0	0	0	0	0	0	0	0	0	0	0	400[8];
722	Freescale	MKL05Z16xxx4 internal	0	0	1	35	4	32	1	0	0	0	0	0	0	0	0	0	0	0	0	400[16];
723	Freescale	MKL05Z16xxx4 internal (allow security)	0	0	1	35	5	32	1	0	0	0	0	0	0	0	0	0	0	0	0	400[16];
724	Freescale	MKL05Z32xxx4 internal	0	0	1	35	4	32	1	0	0	0	0	0	0	0	0	0	0	0	0	400[32];
725	Freescale	MKL05Z32xxx4 internal (allow security)	0	0	1	35	5	32	1	0	0	0	0	0	0	0	0	0	0	0	0	400[32];
726	Freescale	MKL13Z32xxx4 internal	0	0	1	35	4	32	1	0	0	0	0	0	0	0	0	0	0	0	0	400[32];
727	Freescale	MKL13Z32xxx4 internal (allow security)	0	0	1	35	5	32	1	0	0	0	0	0	0	0	0	0	0	0	0	400[32];
728	Freescale	MKL13Z64xxx4 internal	0	0	1	35	4	32	1	0	0	0	0	0	0	0	0	0	0	0	0	400[64];
729	Freescale	MKL13Z64xxx4 internal (allow security)	0	0	1	35	5	32	1	0	0	0	0	0	0	0	0	0	0	0	0	400[64];
730	Freescale	MKL14Z32xxx4 internal	0	0	1	35	4	32	1	0	0	0	0	0	0	0	0	0	0	0	0	400[32];
731	Freescale	MKL14Z32xxx4 internal (allow security)	0	0	1	35	5	32	1	0	0	0	0	0	0	0	0	0	0	0	0	400[32];
732	Freescale	MKL14Z64xxx4 internal	0	0	1	35	4	32	1	0	0	0	0	0	0	0	0	0	0	0	0	400[64];
733	Freescale	MKL14Z64xxx4 internal (allow security)	0	0	1	35	5	32	1	0	0	0	0	0	0	0	0	0	0	0	0	400[64];
734	Freescale	MKL15Z32xxx4 internal	0	0	1	35	4	32	1	0	0	0	0	0	0	0	0	0	0	0	0	400[32];
735	Freescale	MKL15Z32xxx4 internal (allow security)	0	0	1	35	5	32	1	0	0	0	0	0	0	0	0	0	0	0	0	400[32];
736	Freescale	MKL15Z64xxx4 internal	0	0	1	35	4	32	1	0	0	0	0	0	0	0	0	0	0	0	0	400[64];
737	Freescale	MKL15Z64xxx4 internal (allow security)	0	0	1	35	5	32	1	0	0	0	0	0	0	0	0	0	0	0	0	400[64];
738	Freescale	MKL15Z128xxx4 internal	0	0	1	35	4	32	1	0	0	0	0	0	0	0	0	0	0	0	0	400[128];
739	Freescale	MKL15Z128xxx4 internal (allow security)	0	0	1	35	5	32	1	0	0	0	0	0	0	0	0	0	0	0	0	400[128];
740	Freescale	MKL16Z32xxx4 internal	0	0	1	35	4	32	1	0	0	0	0	0	0	0	0	0	0	0	0	400[32];
741	Freescale	MKL16Z32xxx4 internal (allow security)	0	0	1	35	5	32	1	0	0	0	0	0	0	0	0	0	0	0	0	400[32];
742	Freescale	MKL16Z64xxx4 internal	0	0	1	35	4	32	1	0	0	0	0	0	0	0	0	0	0	0	0	400[64];
743	Freescale	MKL16Z64xxx4 internal (allow security)	0	0	1	35	5	32	1	0	0	0	0	0	0	0	0	0	0	0	0	400[64];
744	Freescale	MKL16Z128xxx4 internal	0	0	1	35	4	32	1	0	0	0	0	0	0	0	0	0	0	0	0	400[128];
745	Freescale	MKL16Z128xxx4 internal (allow security)	0	0	1	35	5	32	1	0	0	0	0	0	0	0	0	0	0	0	0	400[128];
746	Freescale	MKL16Z256xxx4 internal	0	0	1	35	4	32	1	0	0	0	0	0	0	0	0	0	0	0	0	400[256];
747	Freescale	MKL16Z256xxx4 internal (allow security)	0	0	1	35	5	32	1	0	0	0	0	0	0	0	0	0	0	0	0	400[256];
748	Freescale	MKL17Z128xxx4 internal	0	0	1	35	4	32	1	0	0	0	0	0	0	0	0	0	0	0	0	400[128];
749	Freescale	MKL17Z128xxx4 internal (allow security)	0	0	1	35	5	32	1	0	0	0	0	0	0	0	0	0	0	0	0	400[128];
750	Freescale	MKL17Z256xxx4 internal	0	0	1	35	4	32	1	0	0	0	0	0	0	0	0	0	0	0	0	400[256];
751	Freescale	MKL17Z256xxx4 internal (allow security)	0	0	1	35	5	32	1	0	0	0	0	0	0	0	0	0	0	0	0	400[256];
752	Freescale	MKL17Z32xxx4 internal	0	0	1	35	4	32	1	0	0	0	0	0	0	0	0	0	0	0	0	400[32];
753	Freescale	MKL17Z32xxx4 internal (allow security)	0	0	1	35	5	32	1	0	0	0	0	0	0	0	0	0	0	0	0	400[32];
754	Freescale	MKL17Z64xxx4 internal	0	0	1	35	4	32	1	0	0	0	0	0	0	0	0	0	0	0	0	400[64];
755	Freescale	MKL17Z64xxx4 internal (allow security)	0	0	1	35	5	32	1	0	0	0	0	0	0	0	0	0	0	0	0	400[64];
756	Freescale	MKL24Z32xxx4 internal	0	0	1	35	4	32	1	0	0	0	0	0	0	0	0	0	0	0	0	400[32];
757	Freescale	MKL24Z32xxx4 internal (allow security)	0	0	1	35	5	32	1	0	0	0	0	0	0	0	0	0	0	0	0	400[32];
758	Freescale	MKL24Z64xxx4 internal	0	0	1	35	4	32	1	0	0	0	0	0	0	0	0	0	0	0	0	400[64];
759	Freescale	MKL24Z64xxx4 internal (allow security)	0	0	1	35	5	32	1	0	0	0	0	0	0	0	0	0	0	0	0	400[64];
760	Freescale	MKL25Z32xxx4 internal	0	0	1	35	4	32	1	0	0	0	0	0	0	0	0	0	0	0	0	400[32];
761	Freescale	MKL25Z32xxx4 internal (allow security)	0	0	1	35	5	32	1	0	0	0	0	0	0	0	0	0	0	0	0	400[32];
762	Freescale	MKL25Z64xxx4 internal	0	0	1	35	4	32	1	0	0	0	0	0	0	0	0	0	0	0	0	400[64];
763	Freescale	MKL25Z64xxx4 internal (allow security)	0	0	1	35	5	32	1	0	0	0	0	0	0	0	0	0	0	0	0	400[64];
764	Freescale	MKL25Z128xxx4 internal	0	0	1	35	4	32	1	0	0	0	0	0	0	0	0	0	0	0	0	400[128];
765	Freescale	MKL25Z128xxx4 internal (allow security)	0	0	1	35	5	32	1	0	0	0	0	0	0	0	0	0	0	0	0	400[128];
766	Freescale	MKL26Z32xxx4 internal	0	0	1	35	4	32	1	0	0	0	0	0	0	0	0	0	0	0	0	400[32];
767	Freescale	MKL26Z32xxx4 internal (allow security)	0	0	1	35	5	32	1	0	0	0	0	0	0	0	0	0	0	0	0	400[32];
768	Freescale	MKL26Z64xxx4 internal	0	0	1	35	4	32	1	0	0	0	0	0	0	0	0	0	0	0	0	400[64];
769	Freescale	MKL26Z64xxx4 internal (allow security)	0	0	1	35	5	32	1	0	0	0	0	0	0	0	0	0	0	0	0	400[64];
770	Freescale	MKL26Z128xxx4 internal	0	0	1	35	4	32	1	0	0	0	0	0	0	0	0	0	0	0	0	400[128];
771	Freescale	MKL26Z128xxx4 internal (allow security)	0	0	1	35	5	32	1	0	0	0	0	0	0	0	0	0	0	0	0	400[128];
772	Freescale	MKL26Z256xxx4 internal	0	0	1	35	4	32	1	0	0	0	0	0	0	0	0	0	0	0	0	400[256];
773	Freescale	MKL26Z256xxx4 internal (allow security)	0	0	1	35	5	32	1	0	0	0	0	0	0	0	0	0	0	0	0	400[256];
774	Freescale	MKL27Z128xxx4 internal	0	0	1	35	4	32	1	0	0	0	0	0	0	0	0	0	0	0	0	400[128];
775	Freescale	MKL27Z128xxx4 internal (allow security)	0	0	1	35	5	32	1	0	0	0	0	0	0	0	0	0	0	0	0	400[128];
776	Freescale	MKL27Z256xxx4 internal	0	0	1	35	4	32	1	0	0	0	0	0	0	0	0	0	0	0	0	400[256];
777	Freescale	MKL27Z256xxx4 internal (allow security)	0	0	1	35	5	32	1	0	0	0	0	0	0	0	0	0	0	0	0	400[256];
778	Freescale	MKL27Z32xxx4 internal	0	0	1	35	4	32	1	0	0	0	0	0	0	0	0	0	0	0	0	400[32];
779	Freescale	MKL27Z32xxx4 internal (allow security)	0	0	1	35	5	32	1	0	0	0	0	0	0	0	0	0	0	0	0	400[32];
780	Freescale	MKL27Z64xxx4 internal	0	0	1	35	4	32	1	0	0	0	0	0	0	0	0	0	0	0	0	400[64];
781	Freescale	MKL27Z64xxx4 internal (allow security)	0	0	1	35	5	32	1	0	0	0	0	0	0	0	0	0	0	0	0	400[64];
782	Freescale	MKL28Z512xxx7 internal	0	0	1	91	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	800[256];
783	Freescale	MKL28Z512xxx7 internal (allow security)	0	0	1	91	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	800[256];
784	Freescale	MKL33Z32xxx4 internal	0	0	1	35	4	32	1	0	0	0	0	0	0	0	0	0	0	0	0	400[32];
785	Freescale	MKL33Z32xxx4 internal (allow security)	0	0	1	35	5	32	1	0	0	0	0	0	0	0	0	0	0	0	0	400[32];
786	Freescale	MKL33Z64xxx4 internal	0	0	1	35	4	32	1	0	0	0	0	0	0	0	0	0	0	0	0	400[64];
787	Freescale	MKL33Z64xxx4 internal (allow security)	0	0	1	35	5	32	1	0	0	0	0	0	0	0	0	0	0	0	0	400[64];
788	Freescale	MKL33Z128xxx4 internal	0	0	1	35	4	32	1	0	0	0	0	0	0	0	0	0	0	0	0	400[128];
789	Freescale	MKL33Z128xxx4 internal (allow security)	0	0	1	35	5	32	1	0	0	0	0	0	0	0	0	0	0	0	0	400[128];
790	Freescale	MKL33Z256xxx4 internal	0	0	1	35	4	32	1	0	0	0	0	0	0	0	0	0	0	0	0	400[256];
791	Freescale	MKL33Z256xxx4 internal (allow security)	0	0	1	35	5	32	1	0	0	0	0	0	0	0	0	0	0	0	0	400[256];
792	Freescale	MKL34Z64xxx4 internal	0	0	1	35	4	32	1	0	0	0	0	0	0	0	0	0	0	0	0	400[64];
793	Freescale	MKL34Z64xxx4 internal (allow security)	0	0	1	35	5	32	1	0	0	0	0	0	0	0	0	0	0	0	0	400[64];
794	Freescale	MKL36Z64xxx4 internal	0	0	1	35	4	32	1	0	0	0	0	0	0	0	0	0	0	0	0	400[64];
795	Freescale	MKL36Z64xxx4 internal (allow security)	0	0	1	35	5	32	1	0	0	0	0	0	0	0	0	0	0	0	0	400[64];
796	Freescale	MKL36Z128xxx4 internal	0	0	1	35	4	32	1	0	0	0	0	0	0	0	0	0	0	0	0	400[128];
797	Freescale	MKL36Z128xxx4 internal (allow security)	0	0	1	35	5	32	1	0	0	0	0	0	0	0	0	0	0	0	0	400[128];
798	Freescale	MKL36Z256xxx4 internal	0	0	1	35	4	32	1	0	0	0	0	0	0	0	0	0	0	0	0	400[256];
799	Freescale	MKL36Z256xxx4 internal (allow security)	0	0	1	35	5	32	1	0	0	0	0	0	0	0	0	0	0	0	0	400[256];
800	Freescale	MKL43Z128xxx4 internal	0	0	1	35	4	32	1	0	0	0	0	0	0	0	0	0	0	0	0	400[128];
801	Freescale	MKL43Z128xxx4 internal (allow security)	0	0	1	35	5	32	1	0	0	0	0	0	0	0	0	0	0	0	0	400[128];
802	Freescale	MKL43Z256xxx4 internal	0	0	1	35	4	32	1	0	0	0	0	0	0	0	0	0	0	0	0	400[256];
803	Freescale	MKL43Z256xxx4 internal (allow security)	0	0	1	35	5	32	1	0	0	0	0	0	0	0	0	0	0	0	0	400[256];
804	Freescale	MKL46Z128xxx4 internal	0	0	1	35	4	32	1	0	0	0	0	0	0	0	0	0	0	0	0	400[128];
805	Freescale	MKL46Z128xxx4 internal (allow security)	0	0	1	35	5	32	1	0	0	0	0	0	0	0	0	0	0	0	0	400[128];
806	Freescale	MKL46Z256xxx4 internal	0	0	1	35	4	32	1	0	0	0	0	0	0	0	0	0	0	0	0	400[256];
807	Freescale	MKL46Z256xxx4 internal (allow security)	0	0	1	35	5	32	1	0	0	0	0	0	0	0	0	0	0	0	0	400[256];
808	Freescale	MKL82Z128xxx7 internal	0	0	1	91	4	32	1	0	0	0	0	0	0	0	0	0	0	0	0	800[64];
809	Freescale	MKL82Z128xxx7 internal (allow security)	0	0	1	91	5	32	1	0	0	0	0	0	0	0	0	0	0	0	0	800[64];
810	Freescale	MKM13Z64xxx5 internal	0	0	1	35	6	32	1	0	0	0	0	0	0	0	0	0	0	0	0	400[64];
811	Freescale	MKM13Z64xxx5 internal (allow security)	0	0	1	35	7	32	1	0	0	0	0	0	0	0	0	0	0	0	0	400[64];
812	Freescale	MKM14Z64xxx5 internal	0	0	1	35	6	32	1	0	0	0	0	0	0	0	0	0	0	0	0	400[64];
813	Freescale	MKM14Z64xxx5 internal (allow security)	0	0	1	35	7	32	1	0	0	0	0	0	0	0	0	0	0	0	0	400[64];
814	Freescale	MKM14Z128xxx5 internal	0	0	1	35	6	32	1	0	0	0	0	0	0	0	0	0	0	0	0	400[128];
815	Freescale	MKM14Z128xxx5 internal (allow security)	0	0	1	35	7	32	1	0	0	0	0	0	0	0	0	0	0	0	0	400[128];
816	Freescale	MKM32Z64xxx5 internal	0	0	1	35	6	32	1	0	0	0	0	0	0	0	0	0	0	0	0	400[64];
817	Freescale	MKM32Z64xxx5 internal (allow security)	0	0	1	35	7	32	1	0	0	0	0	0	0	0	0	0	0	0	0	400[64];
818	Freescale	MKM33Z64xxx5 internal	0	0	1	35	6	32	1	0	0	0	0	0	0	0	0	0	0	0	0	400[64];
819	Freescale	MKM33Z64xxx5 internal (allow security)	0	0	1	35	7	32	1	0	0	0	0	0	0	0	0	0	0	0	0	400[64];
820	Freescale	MKM33Z128xxx5 internal	0	0	1	35	6	32	1	0	0	0	0	0	0	0	0	0	0	0	0	400[128];
821	Freescale	MKM33Z128xxx5 internal (allow security)	0	0	1	35	7	32	1	0	0	0	0	0	0	0	0	0	0	0	0	400[128];
822	Freescale	MKM34Z128xxx5 internal	0	0	1	35	6	32	1	0	0	0	0	0	0	0	0	0	0	0	0	400[128];
823	Freescale	MKM34Z128xxx5 internal (allow security)	0	0	1	35	7	32	1	0	0	0	0	0	0	0	0	0	0	0	0	400[128];
824	Freescale	MKM34Z256xxx7 internal	0	0	1	35	6	32	1	0	0	0	0	0	0	0	0	0	0	0	0	800[128];
825	Freescale	MKM34Z256xxx7 internal (allow security)	0	0	1	35	7	32	1	0	0	0	0	0	0	0	0	0	0	0	0	800[128];
826	Freescale	MKM34Z256xxx5 internal	0	0	1	35	6	32	1	0	0	0	0	0	0	0	0	0	0	0	0	800[128];
827	Freescale	MKM34Z256xxx5 internal (allow security)	0	0	1	35	7	32	1	0	0	0	0	0	0	0	0	0	0	0	0	800[128];
828	Freescale	MKM38Z128xxx5 internal	0	0	1	35	6	32	1	0	0	0	0	0	0	0	0	0	0	0	0	400[128];
829	Freescale	MKM38Z128xxx5 internal (allow security)	0	0	1	35	7	32	1	0	0	0	0	0	0	0	0	0	0	0	0	400[128];
830	Freescale	MKS22FN128xxx12 internal	0	0	1	35	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	800[64];
831	Freescale	MKS22FN128xxx12 internal (allow security)	0	0	1	35	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	800[64];
832	Freescale	MKS22FN256xxx12 internal	0	0	1	35	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	800[128];
833	Freescale	MKS22FN256xxx12 internal (allow security)	0	0	1	35	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	800[128];
834	Freescale	MKV10Z16xxx7 internal	0	0	1	53	4	32	1	0	0	0	0	0	0	0	0	0	0	0	0	400[16];
835	Freescale	MKV10Z16xxx7 internal (allow security)	0	0	1	53	5	32	1	0	0	0	0	0	0	0	0	0	0	0	0	400[16];
836	Freescale	MKV10Z32xxx7 internal	0	0	1	53	4	32	1	0	0	0	0	0	0	0	0	0	0	0	0	400[32];
837	Freescale	MKV10Z32xxx7 internal (allow security)	0	0	1	53	5	32	1	0	0	0	0	0	0	0	0	0	0	0	0	400[32];
838	Freescale	MKV10Z64xxx7 internal	0	0	1	53	4	32	1	0	0	0	0	0	0	0	0	0	0	0	0	800[32];
839	Freescale	MKV10Z64xxx7 internal (allow security)	0	0	1	53	5	32	1	0	0	0	0	0	0	0	0	0	0	0	0	800[32];
840	Freescale	MKV10Z128xxx7 internal	0	0	1	53	4	32	1	0	0	0	0	0	0	0	0	0	0	0	0	800[64];
841	Freescale	MKV10Z128xxx7 internal (allow security)	0	0	1	53	5	32	1	0	0	0	0	0	0	0	0	0	0	0	0	800[64];
842	Freescale	MKV11Z64xxx7 internal	0	0	1	53	4	32	1	0	0	0	0	0	0	0	0	0	0	0	0	800[32];
843	Freescale	MKV11Z64xxx7 internal (allow security)	0	0	1	53	5	32	1	0	0	0	0	0	0	0	0	0	0	0	0	800[32];
844	Freescale	MKV11Z128xxx7 internal	0	0	1	53	4	32	1	0	0	0	0	0	0	0	0	0	0	0	0	800[64];
845	Freescale	MKV11Z128xxx7 internal (allow security)	0	0	1	53	5	32	1	0	0	0	0	0	0	0	0	0	0	0	0	800[64];
846	Freescale	MKV30F64xxx10 internal	0	0	1	35	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	800[32];
847	Freescale	MKV30F64xxx10 internal (allow security)	0	0	1	35	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	800[32];
848	Freescale	MKV30F128xxx10 internal	0	0	1	35	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	800[64];
849	Freescale	MKV30F128xxx10 internal (allow security)	0	0	1	35	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	800[64];
850	Freescale	MKV31F128xxx10 internal	0	0	1	35	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	800[64];
851	Freescale	MKV31F128xxx10 internal (allow security)	0	0	1	35	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	800[64];
852	Freescale	MKV31F256xxx12 internal	0	0	1	35	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	800[128];
853	Freescale	MKV31F256xxx12 internal (allow security)	0	0	1	35	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	800[128];
854	Freescale	MKV31F512xxx12 internal	0	0	1	35	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	800[256];
855	Freescale	MKV31F512xxx12 internal (allow security)	0	0	1	35	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	800[256];
856	Freescale	MKV42F128xxx16 internal	0	0	1	35	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	400[128];
857	Freescale	MKV42F128xxx16 internal (allow security)	0	0	1	35	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	400[128];
858	Freescale	MKV42F256xxx16 internal	0	0	1	35	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	400[256];
859	Freescale	MKV42F256xxx16 internal (allow security)	0	0	1	35	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	400[256];
860	Freescale	MKV42F64xxx16 internal	0	0	1	35	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	400[64];
861	Freescale	MKV42F64xxx16 internal (allow security)	0	0	1	35	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	400[64];
862	Freescale	MKV44F128xxx16 internal	0	0	1	35	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	400[128];
863	Freescale	MKV44F128xxx16 internal (allow security)	0	0	1	35	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	400[128];
864	Freescale	MKV44F256xxx16 internal	0	0	1	35	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	400[256];
865	Freescale	MKV44F256xxx16 internal (allow security)	0	0	1	35	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	400[256];
866	Freescale	MKV44F64xxx16 internal	0	0	1	35	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	400[64];
867	Freescale	MKV44F64xxx16 internal (allow security)	0	0	1	35	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	400[64];
868	Freescale	MKV46F128xxx16 internal	0	0	1	35	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	400[128];
869	Freescale	MKV46F128xxx16 internal (allow security)	0	0	1	35	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	400[128];
870	Freescale	MKV46F256xxx16 internal	0	0	1	35	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	1000[64];
871	Freescale	MKV46F256xxx16 internal (allow security)	0	0	1	35	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	1000[64];
872	Freescale	MKV56F512xxx24 internal	0	0	1	35	8	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[64];
873	Freescale	MKV56F512xxx24 internal (allow security)	0	0	1	35	9	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[64];
874	Freescale	MKV56F1M0xxx24 internal	0	0	1	35	8	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[128];
875	Freescale	MKV56F1M0xxx24 internal (allow security)	0	0	1	35	9	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[128];
876	Freescale	MPC5602B internal	0	0	1	38	0	32	1	1	0	0	0	0	0	0	0	0	0	0	0	8000; 4000[2]; 8000[2]; 20000[1]; 4000[4], 800000;
877	Freescale	MPC5602B (allow shadow) internal	0	0	1	38	1	32	1	1	0	0	0	0	0	0	0	0	0	0	0	8000; 4000[2]; 8000[2]; 20000[1]; 4000[1], 200000; 4000[4], 800000;
878	Freescale	MPC5602C internal	0	0	1	38	0	32	1	1	0	0	0	0	0	0	0	0	0	0	0	8000; 4000[2]; 8000[2]; 20000[1]; 4000[4], 800000;
879	Freescale	MPC5602C (allow shadow) internal	0	0	1	38	1	32	1	1	0	0	0	0	0	0	0	0	0	0	0	8000; 4000[2]; 8000[2]; 20000[1]; 4000[1], 200000; 4000[4], 800000;
880	Freescale	MPC5602D internal	0	0	1	38	0	32	1	1	0	0	0	0	0	0	0	0	0	0	0	8000; 4000[2]; 8000[2]; 20000[1]; 4000[4], 800000;
881	Freescale	MPC5602D (allow shadow) internal	0	0	1	38	1	32	1	1	0	0	0	0	0	0	0	0	0	0	0	8000; 4000[2]; 8000[2]; 20000[1]; 4000[1], 200000; 4000[4], 800000;
882	Freescale	MPC5603B internal	0	0	1	38	0	32	1	1	0	0	0	0	0	0	0	0	0	0	0	8000; 4000[2]; 8000[2]; 20000[2]; 4000[4], 800000;
883	Freescale	MPC5603B (allow shadow) internal	0	0	1	38	1	32	1	1	0	0	0	0	0	0	0	0	0	0	0	8000; 4000[2]; 8000[2]; 20000[2]; 4000[1], 200000; 4000[4], 800000;
884	Freescale	MPC5603C internal	0	0	1	38	0	32	1	1	0	0	0	0	0	0	0	0	0	0	0	8000; 4000[2]; 8000[2]; 20000[2]; 4000[4], 800000;
885	Freescale	MPC5603C (allow shadow) internal	0	0	1	38	1	32	1	1	0	0	0	0	0	0	0	0	0	0	0	8000; 4000[2]; 8000[2]; 20000[2]; 4000[1], 200000; 4000[4], 800000;
886	Freescale	MPC5604B internal	0	0	1	38	0	32	1	1	0	0	0	0	0	0	0	0	0	0	0	8000; 4000[2]; 8000[2]; 20000[3]; 4000[4], 800000;
887	Freescale	MPC5604B (allow shadow) internal	0	0	1	38	1	32	1	1	0	0	0	0	0	0	0	0	0	0	0	8000; 4000[2]; 8000[2]; 20000[3]; 4000[1], 200000; 4000[4], 800000;
888	Freescale	MPC5604C internal	0	0	1	38	0	32	1	1	0	0	0	0	0	0	0	0	0	0	0	8000; 4000[2]; 8000[2]; 20000[3]; 4000[4], 800000;
889	Freescale	MPC5604C (allow shadow) internal	0	0	1	38	1	32	1	1	0	0	0	0	0	0	0	0	0	0	0	8000; 4000[2]; 8000[2]; 20000[3]; 4000[1], 200000; 4000[4], 800000;
890	Freescale	MPC5605B internal	0	0	1	38	0	32	1	1	0	0	0	0	0	0	0	0	0	0	0	8000; 4000[2]; 8000[2]; 20000[5]; 4000[4], 800000;
891	Freescale	MPC5605B (allow shadow) internal	0	0	1	38	1	32	1	1	0	0	0	0	0	0	0	0	0	0	0	8000; 4000[2]; 8000[2]; 20000[5]; 4000[1], 200000; 4000[4], 800000;
892	Freescale	MPC5606B internal	0	0	1	38	0	32	1	1	0	0	0	0	0	0	0	0	0	0	0	8000; 4000[2]; 8000[2]; 20000[7]; 4000[4], 800000;
893	Freescale	MPC5606B (allow shadow) internal	0	0	1	38	1	32	1	1	0	0	0	0	0	0	0	0	0	0	0	8000; 4000[2]; 8000[2]; 20000[7]; 4000[1], 200000; 4000[4], 800000;
894	Freescale	MPC5607B internal	0	0	1	38	0	32	1	1	0	0	0	0	0	0	0	0	0	0	0	8000; 4000[2]; 8000[2]; 20000[11]; 4000[4], 800000;
895	Freescale	MPC5607B (allow shadow) internal	0	0	1	38	1	32	1	1	0	0	0	0	0	0	0	0	0	0	0	8000; 4000[2]; 8000[2]; 20000[11]; 4000[1], 200000; 4000[4], 800000;
896	Freescale	PCK20LN128 internal	0	0	1	35	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	400[128];
897	Freescale	PCK20LN128 internal (allow security)	0	0	1	35	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	400[128];
898	Freescale	MKW01Z128xxx4 internal	0	0	1	35	4	32	1	0	0	0	0	0	0	0	0	0	0	0	0	400[128];
899	Freescale	MKW01Z128xxx4 internal (allow security)	0	0	1	35	5	32	1	0	0	0	0	0	0	0	0	0	0	0	0	400[128];
900	Freescale	MKW20Z160xxx4 internal	0	0	1	35	4	32	1	0	0	0	0	0	0	0	0	0	0	0	0	400[160];
901	Freescale	MKW20Z160xxx4 internal (allow security)	0	0	1	35	5	32	1	0	0	0	0	0	0	0	0	0	0	0	0	400[160];
902	Freescale	MKW21D128xxx5 internal	0	0	1	35	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	800[64];
903	Freescale	MKW21D128xxx5 internal (allow security)	0	0	1	35	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	800[64];
904	Freescale	MKW21D256xxx5 internal	0	0	1	35	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	800[128];
905	Freescale	MKW21D256xxx5 internal (allow security)	0	0	1	35	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	800[128];
906	Freescale	MKW21D512xxx5 internal	0	0	1	35	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	800[256];
907	Freescale	MKW21D512xxx5 internal (allow security)	0	0	1	35	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	800[256];
908	Freescale	MKW21Z256xxx4 internal	0	0	1	35	4	32	1	0	0	0	0	0	0	0	0	0	0	0	0	800[128];
909	Freescale	MKW21Z256xxx4 internal (allow security)	0	0	5	35	5	32	1	0	0	0	0	0	0	0	0	0	0	0	0	800[128];
910	Freescale	MKW21Z512xxx4 internal	0	0	1	35	4	32	1	0	0	0	0	0	0	0	0	0	0	0	0	800[256];
911	Freescale	MKW21Z512xxx4 internal (allow security)	0	0	5	35	5	32	1	0	0	0	0	0	0	0	0	0	0	0	0	800[256];
912	Freescale	MKW22D512xxx5 internal	0	0	1	35	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	800[256];
913	Freescale	MKW22D512xxx5 internal (allow security)	0	0	1	35	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	800[256];
914	Freescale	MKW24D512xxx5 internal	0	0	1	35	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	800[256];
915	Freescale	MKW24D512xxx5 internal (allow security)	0	0	1	35	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	800[256];
916	Freescale	MKW30Z160xxx4 internal	0	0	1	35	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	400[160];
917	Freescale	MKW30Z160xxx4 internal (allow security)	0	0	1	35	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	400[160];
918	Freescale	MKW31Z256xxx4 internal	0	0	1	35	4	32	1	0	0	0	0	0	0	0	0	0	0	0	0	800[128];
919	Freescale	MKW31Z256xxx4 internal (allow security)	0	0	5	35	5	32	1	0	0	0	0	0	0	0	0	0	0	0	0	800[128];
920	Freescale	MKW31Z512xxx4 internal	0	0	1	35	4	32	1	0	0	0	0	0	0	0	0	0	0	0	0	800[256];
921	Freescale	MKW31Z512xxx4 internal (allow security)	0	0	5	35	5	32	1	0	0	0	0	0	0	0	0	0	0	0	0	800[256];
922	Freescale	MKW40Z160xxx4 internal	0	0	1	35	4	32	1	0	0	0	0	0	0	0	0	0	0	0	0	400[160];
923	Freescale	MKW40Z160xxx4 internal (allow security)	0	0	5	35	5	32	1	0	0	0	0	0	0	0	0	0	0	0	0	400[160];
924	Freescale	MKW41Z256xxx4 internal	0	0	1	35	4	32	1	0	0	0	0	0	0	0	0	0	0	0	0	800[128];
925	Freescale	MKW41Z256xxx4 internal (allow security)	0	0	5	35	5	32	1	0	0	0	0	0	0	0	0	0	0	0	0	800[128];
926	Freescale	MKW41Z512xxx4 internal	0	0	1	35	4	32	1	0	0	0	0	0	0	0	0	0	0	0	0	800[256];
927	Freescale	MKW41Z512xxx4 internal (allow security)	0	0	5	35	5	32	1	0	0	0	0	0	0	0	0	0	0	0	0	800[256];
928	Freescale	WPR1516 internal	0	0	1	84	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	200[32];
929	Freescale	WPR1516 internal (allow security)	0	0	1	84	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	200[32];
930	Freescale	S32K144 internal	0	0	1	91	6	32	1	0	0	0	0	0	0	0	0	0	0	0	0	1000[128];
931	Freescale	S32K144 internal (allow security)	0	0	1	91	7	32	1	0	0	0	0	0	0	0	0	0	0	0	0	1000[128];
932	Freescale	SKEAZN8xxx4 internal	0	0	1	53	8	32	1	0	0	0	0	0	0	0	0	0	0	0	0	200[16];
933	Freescale	SKEAZN8xxx4 internal (allow security)	0	0	1	53	9	32	1	0	0	0	0	0	0	0	0	0	0	0	0	200[16];
934	Freescale	SKEAZN16xxx2 internal	0	0	1	53	2	32	1	0	0	0	0	0	0	0	0	0	0	0	0	200[32];
935	Freescale	SKEAZN16xxx2 internal (allow security)	0	0	1	53	3	32	1	0	0	0	0	0	0	0	0	0	0	0	0	200[32];
936	Freescale	SKEAZN32xxx2 internal	0	0	1	53	2	32	1	0	0	0	0	0	0	0	0	0	0	0	0	200[64];
937	Freescale	SKEAZN32xxx2 internal (allow security)	0	0	1	53	3	32	1	0	0	0	0	0	0	0	0	0	0	0	0	200[64];
938	Freescale	SKEAZN64xxx2 internal	0	0	1	53	2	32	1	0	0	0	0	0	0	0	0	0	0	0	0	200[128];
939	Freescale	SKEAZN64xxx2 internal (allow security)	0	0	1	53	3	32	1	0	0	0	0	0	0	0	0	0	0	0	0	200[128];
940	Freescale	SKEAZ64xxx4 internal	0	0	1	53	6	32	1	0	0	0	0	0	0	0	0	0	0	0	0	200[128];
941	Freescale	SKEAZ64xxx4 internal (allow security)	0	0	1	53	7	32	1	0	0	0	0	0	0	0	0	0	0	0	0	200[128];
942	Freescale	SKEAZ128xxx4 internal	0	0	1	53	6	32	1	0	0	0	0	0	0	0	0	0	0	0	0	200[256];
943	Freescale	SKEAZ128xxx4 internal (allow security)	0	0	1	53	7	32	1	0	0	0	0	0	0	0	0	0	0	0	0	200[256];
944	Fujitsu	MB9AF102N internal	0	0	1	40	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	4000[2];18000[1];
945	Fujitsu	MB9AF102R internal	0	0	1	40	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	4000[2];18000[1];
946	Fujitsu	MB9AF104N internal	0	0	1	40	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	4000[2];18000[1];20000[1];
947	Fujitsu	MB9AF104R internal	0	0	1	40	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	4000[2];18000[1];20000[1];
948	Fujitsu	MB9AF111K internal	0	0	1	40	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	4000[2];8000[1];2000[4], 200C0000;
949	Fujitsu	MB9AF111L internal	0	0	1	40	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	4000[2];8000[1];
950	Fujitsu	MB9AF111M internal	0	0	1	40	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	4000[2];8000[1];
951	Fujitsu	MB9AF111N internal	0	0	1	40	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	4000[2];8000[1];
952	Fujitsu	MB9AF112K internal	0	0	1	40	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	4000[2];18000[1];2000[4], 200C0000;
953	Fujitsu	MB9AF112L internal	0	0	1	40	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	4000[2];18000[1];
954	Fujitsu	MB9AF112M internal	0	0	1	40	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	4000[2];18000[1];
955	Fujitsu	MB9AF112N internal	0	0	1	40	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	4000[2];18000[1];
956	Fujitsu	MB9AF114L internal	0	0	1	40	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	4000[2];18000[1];20000[1];
957	Fujitsu	MB9AF114M internal	0	0	1	40	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	4000[2];18000[1];20000[1];
958	Fujitsu	MB9AF114N internal	0	0	1	40	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	4000[2];18000[1];20000[1];
959	Fujitsu	MB9AF115M internal	0	0	1	40	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	4000[2];18000[1];20000[2];
960	Fujitsu	MB9AF115N internal	0	0	1	40	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	4000[2];18000[1];20000[2];
961	Fujitsu	MB9AF116M internal	0	0	1	40	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	4000[2];18000[1];20000[3];
962	Fujitsu	MB9AF116N internal	0	0	1	40	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	4000[2];18000[1];20000[3];
963	Fujitsu	MB9AF121K internal	0	0	1	40	5	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[7]; 1FF8[1];
964	Fujitsu	MB9AF121L internal	0	0	1	40	5	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[7]; 1FF8[1];
965	Fujitsu	MB9AF421K internal	0	0	1	40	5	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[7]; 1FF8[1];
966	Fujitsu	MB9AF421L internal	0	0	1	40	5	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[7]; 1FF8[1];
967	Fujitsu	MB9AF131K internal	0	0	1	40	2	32	1	0	0	0	0	0	0	0	0	0	0	0	0	4000[2];8000[1];
968	Fujitsu	MB9AF131KA internal	0	0	1	40	2	32	1	0	0	0	0	0	0	0	0	0	0	0	0	1000[1];F000[1];
969	Fujitsu	MB9AF131L internal	0	0	1	40	2	32	1	0	0	0	0	0	0	0	0	0	0	0	0	4000[2];8000[1];
970	Fujitsu	MB9AF131M internal	0	0	1	40	2	32	1	0	0	0	0	0	0	0	0	0	0	0	0	1000[1];F000[1];
971	Fujitsu	MB9AF131N internal	0	0	1	40	2	32	1	0	0	0	0	0	0	0	0	0	0	0	0	1000[1];F000[1];
972	Fujitsu	MB9AF132K internal	0	0	1	40	2	32	1	0	0	0	0	0	0	0	0	0	0	0	0	4000[2];18000[1];
973	Fujitsu	MB9AF132KA internal	0	0	1	40	2	32	1	0	0	0	0	0	0	0	0	0	0	0	0	1000[1];F000[1];10000[1];
974	Fujitsu	MB9AF132L internal	0	0	1	40	2	32	1	0	0	0	0	0	0	0	0	0	0	0	0	4000[2];18000[1];
975	Fujitsu	MB9AF132M internal	0	0	1	40	2	32	1	0	0	0	0	0	0	0	0	0	0	0	0	1000[1];F000[1];10000[1];
976	Fujitsu	MB9AF132N internal	0	0	1	40	2	32	1	0	0	0	0	0	0	0	0	0	0	0	0	1000[1];F000[1];10000[1];
977	Fujitsu	MB9AF141L internal	0	0	1	40	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[2];C000[1]; 2000[4], 200000;
978	Fujitsu	MB9AF141LA internal	0	0	1	40	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[2];C000[1]; 2000[4], 200000;
979	Fujitsu	MB9AF141M internal	0	0	1	40	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[2];C000[1]; 2000[4], 200000;
980	Fujitsu	MB9AF141MA internal	0	0	1	40	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[2];C000[1]; 2000[4], 200000;
981	Fujitsu	MB9AF141N internal	0	0	1	40	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[2];C000[1]; 2000[4], 200000;
982	Fujitsu	MB9AF141NA internal	0	0	1	40	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[2];C000[1]; 2000[4], 200000;
983	Fujitsu	MB9AF142L internal	0	0	1	40	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[2];C000[1];10000[1]; 2000[4], 200000;
984	Fujitsu	MB9AF142LA internal	0	0	1	40	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[2];C000[1];10000[1]; 2000[4], 200000;
985	Fujitsu	MB9AF142M internal	0	0	1	40	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[2];C000[1];10000[1]; 2000[4], 200000;
986	Fujitsu	MB9AF142MA internal	0	0	1	40	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[2];C000[1];10000[1]; 2000[4], 200000;
987	Fujitsu	MB9AF142N internal	0	0	1	40	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[2];C000[1];10000[1]; 2000[4], 200000;
988	Fujitsu	MB9AF142NA internal	0	0	1	40	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[2];C000[1];10000[1]; 2000[4], 200000;
989	Fujitsu	MB9AF144L internal	0	0	1	40	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[2];C000[1];10000[3]; 2000[4], 200000;
990	Fujitsu	MB9AF144LA internal	0	0	1	40	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[2];C000[1];10000[3]; 2000[4], 200000;
991	Fujitsu	MB9AF144M internal	0	0	1	40	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[2];C000[1];10000[3]; 2000[4], 200000;
992	Fujitsu	MB9AF144MA internal	0	0	1	40	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[2];C000[1];10000[3]; 2000[4], 200000;
993	Fujitsu	MB9AF144N internal	0	0	1	40	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[2];C000[1];10000[3]; 2000[4], 200000;
994	Fujitsu	MB9AF144NA internal	0	0	1	40	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[2];C000[1];10000[3]; 2000[4], 200000;
995	Fujitsu	MB9AF154M internal	0	0	1	40	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[2];C000[1];10000[3]; 2000[4], 200000;
996	Fujitsu	MB9AF154N internal	0	0	1	40	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[2];C000[1];10000[3]; 2000[4], 200000;
997	Fujitsu	MB9AF154R internal	0	0	1	40	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[2];C000[1];10000[3]; 2000[4], 200000;
998	Fujitsu	MB9AF155M internal	0	0	1	40	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[2];C000[1];10000[5]; 2000[4], 200000;
999	Fujitsu	MB9AF155N internal	0	0	1	40	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[2];C000[1];10000[5]; 2000[4], 200000;
1000	Fujitsu	MB9AF155R internal	0	0	1	40	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[2];C000[1];10000[5]; 2000[4], 200000;
1001	Fujitsu	MB9AF156M internal	0	0	1	40	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[2];C000[1];10000[7]; 2000[4], 200000;
1002	Fujitsu	MB9AF156N internal	0	0	1	40	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[2];C000[1];10000[7]; 2000[4], 200000;
1003	Fujitsu	MB9AF156R internal	0	0	1	40	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[2];C000[1];10000[7]; 2000[4], 200000;
1004	Fujitsu	MB9AF311K internal	0	0	1	40	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	4000[2];8000[1];2000[4], 200C0000;
1005	Fujitsu	MB9AF311L internal	0	0	1	40	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	4000[2];8000[1];
1006	Fujitsu	MB9AF311M internal	0	0	1	40	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	4000[2];8000[1];
1007	Fujitsu	MB9AF311N internal	0	0	1	40	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	4000[2];8000[1];
1008	Fujitsu	MB9AF312K internal	0	0	1	40	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	4000[2];18000[1];2000[4], 200C0000;
1009	Fujitsu	MB9AF312L internal	0	0	1	40	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	4000[2];18000[1];
1010	Fujitsu	MB9AF312M internal	0	0	1	40	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	4000[2];18000[1];
1011	Fujitsu	MB9AF312N internal	0	0	1	40	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	4000[2];18000[1];
1012	Fujitsu	MB9AF314L internal	0	0	1	40	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	4000[2];18000[1];20000[1];
1013	Fujitsu	MB9AF314M internal	0	0	1	40	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	4000[2];18000[1];20000[1];
1014	Fujitsu	MB9AF314N internal	0	0	1	40	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	4000[2];18000[1];20000[1];
1015	Fujitsu	MB9AF315M internal	0	0	1	40	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	4000[2];18000[1];20000[2];
1016	Fujitsu	MB9AF315N internal	0	0	1	40	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	4000[2];18000[1];20000[2];
1017	Fujitsu	MB9AF316M internal	0	0	1	40	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	4000[2];18000[1];20000[3];
1018	Fujitsu	MB9AF316N internal	0	0	1	40	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	4000[2];18000[1];20000[3];
1019	Fujitsu	MB9AF341L internal	0	0	1	40	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[2];C000[1]; 2000[4], 200000;
1020	Fujitsu	MB9AF341LA internal	0	0	1	40	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[2];C000[1]; 2000[4], 200000;
1021	Fujitsu	MB9AF341M internal	0	0	1	40	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[2];C000[1]; 2000[4], 200000;
1022	Fujitsu	MB9AF341MA internal	0	0	1	40	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[2];C000[1]; 2000[4], 200000;
1023	Fujitsu	MB9AF341N internal	0	0	1	40	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[2];C000[1]; 2000[4], 200000;
1024	Fujitsu	MB9AF341NA internal	0	0	1	40	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[2];C000[1]; 2000[4], 200000;
1025	Fujitsu	MB9AF342L internal	0	0	1	40	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[2];C000[1];10000[1]; 2000[4], 200000;
1026	Fujitsu	MB9AF342LA internal	0	0	1	40	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[2];C000[1];10000[1]; 2000[4], 200000;
1027	Fujitsu	MB9AF342M internal	0	0	1	40	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[2];C000[1];10000[1]; 2000[4], 200000;
1028	Fujitsu	MB9AF342MA internal	0	0	1	40	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[2];C000[1];10000[1]; 2000[4], 200000;
1029	Fujitsu	MB9AF342N internal	0	0	1	40	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[2];C000[1];10000[1]; 2000[4], 200000;
1030	Fujitsu	MB9AF342NA internal	0	0	1	40	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[2];C000[1];10000[1]; 2000[4], 200000;
1031	Fujitsu	MB9AF344L internal	0	0	1	40	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[2];C000[1];10000[3]; 2000[4], 200000;
1032	Fujitsu	MB9AF344LA internal	0	0	1	40	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[2];C000[1];10000[3]; 2000[4], 200000;
1033	Fujitsu	MB9AF344M internal	0	0	1	40	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[2];C000[1];10000[3]; 2000[4], 200000;
1034	Fujitsu	MB9AF344MA internal	0	0	1	40	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[2];C000[1];10000[3]; 2000[4], 200000;
1035	Fujitsu	MB9AF344N internal	0	0	1	40	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[2];C000[1];10000[3]; 2000[4], 200000;
1036	Fujitsu	MB9AF344NA internal	0	0	1	40	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[2];C000[1];10000[3]; 2000[4], 200000;
1037	Fujitsu	MB9AFA31L internal	0	0	1	40	2	32	1	0	0	0	0	0	0	0	0	0	0	0	0	1000[1];F000[1];
1038	Fujitsu	MB9AFA31LA internal	0	0	1	40	2	32	1	0	0	0	0	0	0	0	0	0	0	0	0	1000[1];F000[1];
1039	Fujitsu	MB9AFA31M internal	0	0	1	40	2	32	1	0	0	0	0	0	0	0	0	0	0	0	0	1000[1];F000[1];
1040	Fujitsu	MB9AFA31N internal	0	0	1	40	2	32	1	0	0	0	0	0	0	0	0	0	0	0	0	1000[1];F000[1];
1041	Fujitsu	MB9AFA32L internal	0	0	1	40	2	32	1	0	0	0	0	0	0	0	0	0	0	0	0	1000[1];F000[1];10000[1];
1042	Fujitsu	MB9AFA32LA internal	0	0	1	40	2	32	1	0	0	0	0	0	0	0	0	0	0	0	0	1000[1];F000[1];10000[1];
1043	Fujitsu	MB9AFA32M internal	0	0	1	40	2	32	1	0	0	0	0	0	0	0	0	0	0	0	0	1000[1];F000[1];10000[1];
1044	Fujitsu	MB9AFA32N internal	0	0	1	40	2	32	1	0	0	0	0	0	0	0	0	0	0	0	0	1000[1];F000[1];10000[1];
1045	Fujitsu	MB9AFA41L internal	0	0	1	40	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[2];C000[1]; 2000[4], 200000;
1046	Fujitsu	MB9AFA41LA internal	0	0	1	40	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[2];C000[1]; 2000[4], 200000;
1047	Fujitsu	MB9AFA41M internal	0	0	1	40	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[2];C000[1]; 2000[4], 200000;
1048	Fujitsu	MB9AFA41MA internal	0	0	1	40	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[2];C000[1]; 2000[4], 200000;
1049	Fujitsu	MB9AFA41N internal	0	0	1	40	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[2];C000[1]; 2000[4], 200000;
1050	Fujitsu	MB9AFA41NA internal	0	0	1	40	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[2];C000[1]; 2000[4], 200000;
1051	Fujitsu	MB9AFA42L internal	0	0	1	40	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[2];C000[1];10000[1]; 2000[4], 200000;
1052	Fujitsu	MB9AFA42LA internal	0	0	1	40	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[2];C000[1];10000[1]; 2000[4], 200000;
1053	Fujitsu	MB9AFA42M internal	0	0	1	40	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[2];C000[1];10000[1]; 2000[4], 200000;
1054	Fujitsu	MB9AFA42MA internal	0	0	1	40	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[2];C000[1];10000[1]; 2000[4], 200000;
1055	Fujitsu	MB9AFA42N internal	0	0	1	40	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[2];C000[1];10000[1]; 2000[4], 200000;
1056	Fujitsu	MB9AFA42NA internal	0	0	1	40	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[2];C000[1];10000[1]; 2000[4], 200000;
1057	Fujitsu	MB9AFA44L internal	0	0	1	40	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[2];C000[1];10000[3]; 2000[4], 200000;
1058	Fujitsu	MB9AFA44LA internal	0	0	1	40	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[2];C000[1];10000[3]; 2000[4], 200000;
1059	Fujitsu	MB9AFA44M internal	0	0	1	40	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[2];C000[1];10000[3]; 2000[4], 200000;
1060	Fujitsu	MB9AFA44MA internal	0	0	1	40	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[2];C000[1];10000[3]; 2000[4], 200000;
1061	Fujitsu	MB9AFA44N internal	0	0	1	40	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[2];C000[1];10000[3]; 2000[4], 200000;
1062	Fujitsu	MB9AFA44NA internal	0	0	1	40	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[2];C000[1];10000[3]; 2000[4], 200000;
1063	Fujitsu	MB9AFB41L internal	0	0	1	40	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[2];C000[1]; 2000[4], 200000;
1064	Fujitsu	MB9AFB41LA internal	0	0	1	40	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[2];C000[1]; 2000[4], 200000;
1065	Fujitsu	MB9AFB41M internal	0	0	1	40	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[2];C000[1]; 2000[4], 200000;
1066	Fujitsu	MB9AFB41MA internal	0	0	1	40	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[2];C000[1]; 2000[4], 200000;
1067	Fujitsu	MB9AFB41N internal	0	0	1	40	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[2];C000[1]; 2000[4], 200000;
1068	Fujitsu	MB9AFB41NA internal	0	0	1	40	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[2];C000[1]; 2000[4], 200000;
1069	Fujitsu	MB9AFB42L internal	0	0	1	40	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[2];C000[1];10000[1]; 2000[4], 200000;
1070	Fujitsu	MB9AFB42LA internal	0	0	1	40	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[2];C000[1];10000[1]; 2000[4], 200000;
1071	Fujitsu	MB9AFB42M internal	0	0	1	40	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[2];C000[1];10000[1]; 2000[4], 200000;
1072	Fujitsu	MB9AFB42MA internal	0	0	1	40	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[2];C000[1];10000[1]; 2000[4], 200000;
1073	Fujitsu	MB9AFB42N internal	0	0	1	40	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[2];C000[1];10000[1]; 2000[4], 200000;
1074	Fujitsu	MB9AFB42NA internal	0	0	1	40	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[2];C000[1];10000[1]; 2000[4], 200000;
1075	Fujitsu	MB9AFB44L internal	0	0	1	40	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[2];C000[1];10000[3]; 2000[4], 200000;
1076	Fujitsu	MB9AFB44LA internal	0	0	1	40	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[2];C000[1];10000[3]; 2000[4], 200000;
1077	Fujitsu	MB9AFB44M internal	0	0	1	40	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[2];C000[1];10000[3]; 2000[4], 200000;
1078	Fujitsu	MB9AFB44MA internal	0	0	1	40	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[2];C000[1];10000[3]; 2000[4], 200000;
1079	Fujitsu	MB9AFB44N internal	0	0	1	40	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[2];C000[1];10000[3]; 2000[4], 200000;
1080	Fujitsu	MB9AFB44NA internal	0	0	1	40	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[2];C000[1];10000[3]; 2000[4], 200000;
1081	Fujitsu	MB9BF104N internal	0	0	1	40	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	4000[2];18000[1];20000[1];
1082	Fujitsu	MB9BF104R internal	0	0	1	40	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	4000[2];18000[1];20000[1];
1083	Fujitsu	MB9BF105N internal	0	0	1	40	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	4000[2];18000[1];20000[2];
1084	Fujitsu	MB9BF105R internal	0	0	1	40	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	4000[2];18000[1];20000[2];
1085	Fujitsu	MB9BF106N internal	0	0	1	40	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	4000[2];18000[1];20000[3];
1086	Fujitsu	MB9BF106R internal	0	0	1	40	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	4000[2];18000[1];20000[3];
1087	Fujitsu	MB9BF112N internal	0	0	1	40	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	4000[2];18000[1]; 2000[4], 200C0000;
1088	Fujitsu	MB9BF112R internal	0	0	1	40	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	4000[2];18000[1]; 2000[4], 200C0000;
1089	Fujitsu	MB9BF114N internal	0	0	1	40	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	4000[2];18000[1];20000[1]; 2000[4], 200C0000;
1090	Fujitsu	MB9BF114R internal	0	0	1	40	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	4000[2];18000[1];20000[1]; 2000[4], 200C0000;
1091	Fujitsu	MB9BF115N internal	0	0	1	40	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	4000[2];18000[1];20000[2]; 2000[4], 200C0000;
1092	Fujitsu	MB9BF115R internal	0	0	1	40	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	4000[2];18000[1];20000[2]; 2000[4], 200C0000;
1093	Fujitsu	MB9BF116N internal	0	0	1	40	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	4000[2];18000[1];20000[3]; 2000[4], 200C0000;
1094	Fujitsu	MB9BF116R internal	0	0	1	40	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	4000[2];18000[1];20000[3]; 2000[4], 200C0000;
1095	Fujitsu	MB9BF116S internal	0	0	1	40	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	4000[2];18000[1];20000[3];
1096	Fujitsu	MB9BF116T internal	0	0	1	40	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	4000[2];18000[1];20000[3];
1097	Fujitsu	MB9BF117S internal	0	0	1	40	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	4000[2];18000[1];20000[5];
1098	Fujitsu	MB9BF117T internal	0	0	1	40	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	4000[2];18000[1];20000[5];
1099	Fujitsu	MB9BF118S internal	0	0	1	40	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	4000[2];18000[1];20000[7];
1100	Fujitsu	MB9BF118T internal	0	0	1	40	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	4000[2];18000[1];20000[7];
1101	Fujitsu	MB9BF121K internal	0	0	1	40	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[2];C000[1]; 2000[4], 200000;
1102	Fujitsu	MB9BF121L internal	0	0	1	40	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[2];C000[1]; 2000[4], 200000;
1103	Fujitsu	MB9BF121M internal	0	0	1	40	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[2];C000[1]; 2000[4], 200000;
1104	Fujitsu	MB9BF122K internal	0	0	1	40	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[2];C000[1];10000[1]; 2000[4], 200000;
1105	Fujitsu	MB9BF122L internal	0	0	1	40	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[2];C000[1];10000[1]; 2000[4], 200000;
1106	Fujitsu	MB9BF122M internal	0	0	1	40	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[2];C000[1];10000[1]; 2000[4], 200000;
1107	Fujitsu	MB9BF124K internal	0	0	1	40	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[2];C000[1];10000[3]; 2000[4], 200000;
1108	Fujitsu	MB9BF124L internal	0	0	1	40	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[2];C000[1];10000[3]; 2000[4], 200000;
1109	Fujitsu	MB9BF124M internal	0	0	1	40	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[2];C000[1];10000[3]; 2000[4], 200000;
1110	Fujitsu	MB9BF128S internal	0	0	1	40	3	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[2];C000[1]; 10000[15]; 2000[8], 00508000;
1111	Fujitsu	MB9BF128T internal	0	0	1	40	3	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[2];C000[1]; 10000[15]; 2000[8], 00508000;
1112	Fujitsu	MB9BF129S internal	0	0	1	40	3	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[2];C000[1]; 10000[23]; 2000[8], 00508000;
1113	Fujitsu	MB9BF129T internal	0	0	1	40	3	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[2];C000[1]; 10000[23]; 2000[8], 00508000;
1114	Fujitsu	MB9BF164K internal	0	0	1	40	2	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[4];8000[1];10000[7]; 2000[4], 200C0000;
1115	Fujitsu	MB9BF164L internal	0	0	1	40	2	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[4];8000[1];10000[7]; 2000[4], 200C0000;
1116	Fujitsu	MB9BF165K internal	0	0	1	40	2	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[4];8000[1];10000[7]; 2000[4], 200C0000;
1117	Fujitsu	MB9BF165L internal	0	0	1	40	2	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[4];8000[1];10000[7]; 2000[4], 200C0000;
1118	Fujitsu	MB9BF166K internal	0	0	1	40	2	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[4];8000[1];10000[7]; 2000[4], 200C0000;
1119	Fujitsu	MB9BF166L internal	0	0	1	40	2	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[4];8000[1];10000[7]; 2000[4], 200C0000;
1120	Fujitsu	MB9BF166M internal	0	0	1	40	2	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[4];8000[1];10000[7]; 2000[4], 200C0000;
1121	Fujitsu	MB9BF166N internal	0	0	1	40	2	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[4];8000[1];10000[7]; 2000[4], 200C0000;
1122	Fujitsu	MB9BF166R internal	0	0	1	40	2	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[4];8000[1];10000[7]; 2000[4], 200C0000;
1123	Fujitsu	MB9BF167M internal	0	0	1	40	2	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[4];8000[1];10000[11]; 2000[4], 200C0000;
1124	Fujitsu	MB9BF167N internal	0	0	1	40	2	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[4];8000[1];10000[11]; 2000[4], 200C0000;
1125	Fujitsu	MB9BF167R internal	0	0	1	40	2	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[4];8000[1];10000[11]; 2000[4], 200C0000;
1126	Fujitsu	MB9BF168M internal	0	0	1	40	2	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[4];8000[1];10000[15]; 2000[4], 200C0000;
1127	Fujitsu	MB9BF168N internal	0	0	1	40	2	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[4];8000[1];10000[15]; 2000[4], 200C0000;
1128	Fujitsu	MB9BF168R internal	0	0	1	40	2	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[4];8000[1];10000[15]; 2000[4], 200C0000;
1129	Fujitsu	MB9BF216S internal	0	0	1	40	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	4000[2];18000[1];20000[3];
1130	Fujitsu	MB9BF216T internal	0	0	1	40	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	4000[2];18000[1];20000[3];
1131	Fujitsu	MB9BF217S internal	0	0	1	40	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	4000[2];18000[1];20000[5];
1132	Fujitsu	MB9BF217T internal	0	0	1	40	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	4000[2];18000[1];20000[5];
1133	Fujitsu	MB9BF218S internal	0	0	1	40	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	4000[2];18000[1];20000[7];
1134	Fujitsu	MB9BF218T internal	0	0	1	40	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	4000[2];18000[1];20000[7];
1135	Fujitsu	MB9BF304N internal	0	0	1	40	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	4000[2];18000[1];20000[1];
1136	Fujitsu	MB9BF304R internal	0	0	1	40	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	4000[2];18000[1];20000[1];
1137	Fujitsu	MB9BF305N internal	0	0	1	40	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	4000[2];18000[1];20000[2];
1138	Fujitsu	MB9BF305R internal	0	0	1	40	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	4000[2];18000[1];20000[2];
1139	Fujitsu	MB9BF306N internal	0	0	1	40	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	4000[2];18000[1];20000[3];
1140	Fujitsu	MB9BF306R internal	0	0	1	40	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	4000[2];18000[1];20000[3];
1141	Fujitsu	MB9BF316S internal	0	0	1	40	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	4000[2];18000[1];20000[3];
1142	Fujitsu	MB9BF316T internal	0	0	1	40	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	4000[2];18000[1];20000[3];
1143	Fujitsu	MB9BF317S internal	0	0	1	40	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	4000[2];18000[1];20000[5];
1144	Fujitsu	MB9BF317T internal	0	0	1	40	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	4000[2];18000[1];20000[5];
1145	Fujitsu	MB9BF318S internal	0	0	1	40	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	4000[2];18000[1];20000[7];
1146	Fujitsu	MB9BF318T internal	0	0	1	40	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	4000[2];18000[1];20000[7];
1147	Fujitsu	MB9BF321K internal	0	0	1	40	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[2];C000[1]; 2000[4], 200000;
1148	Fujitsu	MB9BF321L internal	0	0	1	40	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[2];C000[1]; 2000[4], 200000;
1149	Fujitsu	MB9BF321M internal	0	0	1	40	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[2];C000[1]; 2000[4], 200000;
1150	Fujitsu	MB9BF322K internal	0	0	1	40	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[2];C000[1];10000[1]; 2000[4], 200000;
1151	Fujitsu	MB9BF322L internal	0	0	1	40	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[2];C000[1];10000[1]; 2000[4], 200000;
1152	Fujitsu	MB9BF322M internal	0	0	1	40	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[2];C000[1];10000[1]; 2000[4], 200000;
1153	Fujitsu	MB9BF324K internal	0	0	1	40	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[2];C000[1];10000[3]; 2000[4], 200000;
1154	Fujitsu	MB9BF324L internal	0	0	1	40	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[2];C000[1];10000[3]; 2000[4], 200000;
1155	Fujitsu	MB9BF324M internal	0	0	1	40	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[2];C000[1];10000[3]; 2000[4], 200000;
1156	Fujitsu	MB9BF328S internal	0	0	1	40	3	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[2];C000[1]; 10000[15]; 2000[8], 00508000;
1157	Fujitsu	MB9BF328T internal	0	0	1	40	3	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[2];C000[1]; 10000[15]; 2000[8], 00508000;
1158	Fujitsu	MB9BF329S internal	0	0	1	40	3	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[2];C000[1]; 10000[23]; 2000[8], 00508000;
1159	Fujitsu	MB9BF329T internal	0	0	1	40	3	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[2];C000[1]; 10000[23]; 2000[8], 00508000;
1160	Fujitsu	MB9BF364K internal	0	0	1	40	2	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[4];8000[1];10000[7]; 2000[4], 200C0000;
1161	Fujitsu	MB9BF364L internal	0	0	1	40	2	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[4];8000[1];10000[7]; 2000[4], 200C0000;
1162	Fujitsu	MB9BF365K internal	0	0	1	40	2	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[4];8000[1];10000[7]; 2000[4], 200C0000;
1163	Fujitsu	MB9BF365L internal	0	0	1	40	2	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[4];8000[1];10000[7]; 2000[4], 200C0000;
1164	Fujitsu	MB9BF366K internal	0	0	1	40	2	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[4];8000[1];10000[7]; 2000[4], 200C0000;
1165	Fujitsu	MB9BF366L internal	0	0	1	40	2	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[4];8000[1];10000[7]; 2000[4], 200C0000;
1166	Fujitsu	MB9BF366M internal	0	0	1	40	2	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[4];8000[1];10000[7]; 2000[4], 200C0000;
1167	Fujitsu	MB9BF366N internal	0	0	1	40	2	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[4];8000[1];10000[7]; 2000[4], 200C0000;
1168	Fujitsu	MB9BF366R internal	0	0	1	40	2	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[4];8000[1];10000[7]; 2000[4], 200C0000;
1169	Fujitsu	MB9BF367M internal	0	0	1	40	2	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[4];8000[1];10000[11]; 2000[4], 200C0000;
1170	Fujitsu	MB9BF367N internal	0	0	1	40	2	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[4];8000[1];10000[11]; 2000[4], 200C0000;
1171	Fujitsu	MB9BF367R internal	0	0	1	40	2	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[4];8000[1];10000[11]; 2000[4], 200C0000;
1172	Fujitsu	MB9BF368M internal	0	0	1	40	2	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[4];8000[1];10000[15]; 2000[4], 200C0000;
1173	Fujitsu	MB9BF368N internal	0	0	1	40	2	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[4];8000[1];10000[15]; 2000[4], 200C0000;
1174	Fujitsu	MB9BF368R internal	0	0	1	40	2	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[4];8000[1];10000[15]; 2000[4], 200C0000;
1175	Fujitsu	MB9BF404N internal	0	0	1	40	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	4000[2];18000[1];20000[1];
1176	Fujitsu	MB9BF404R internal	0	0	1	40	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	4000[2];18000[1];20000[1];
1177	Fujitsu	MB9BF405N internal	0	0	1	40	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	4000[2];18000[1];20000[2];
1178	Fujitsu	MB9BF405R internal	0	0	1	40	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	4000[2];18000[1];20000[2];
1179	Fujitsu	MB9BF406N internal	0	0	1	40	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	4000[2];18000[1];20000[3];
1180	Fujitsu	MB9BF406R internal	0	0	1	40	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	4000[2];18000[1];20000[3];
1181	Fujitsu	MB9BF412N internal	0	0	1	40	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	4000[2];18000[1]; 2000[4], 200C0000;
1182	Fujitsu	MB9BF412R internal	0	0	1	40	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	4000[2];18000[1]; 2000[4], 200C0000;
1183	Fujitsu	MB9BF414N internal	0	0	1	40	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	4000[2];18000[1];20000[1]; 2000[4], 200C0000;
1184	Fujitsu	MB9BF414R internal	0	0	1	40	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	4000[2];18000[1];20000[1]; 2000[4], 200C0000;
1185	Fujitsu	MB9BF415N internal	0	0	1	40	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	4000[2];18000[1];20000[2]; 2000[4], 200C0000;
1186	Fujitsu	MB9BF415R internal	0	0	1	40	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	4000[2];18000[1];20000[2]; 2000[4], 200C0000;
1187	Fujitsu	MB9BF416N internal	0	0	1	40	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	4000[2];18000[1];20000[3]; 2000[4], 200C0000;
1188	Fujitsu	MB9BF416R internal	0	0	1	40	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	4000[2];18000[1];20000[3]; 2000[4], 200C0000;
1189	Fujitsu	MB9BF416S internal	0	0	1	40	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	4000[2];18000[1];20000[3];
1190	Fujitsu	MB9BF416T internal	0	0	1	40	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	4000[2];18000[1];20000[3];
1191	Fujitsu	MB9BF417S internal	0	0	1	40	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	4000[2];18000[1];20000[5];
1192	Fujitsu	MB9BF417T internal	0	0	1	40	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	4000[2];18000[1];20000[5];
1193	Fujitsu	MB9BF418S internal	0	0	1	40	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	4000[2];18000[1];20000[7];
1194	Fujitsu	MB9BF418T internal	0	0	1	40	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	4000[2];18000[1];20000[7];
1195	Fujitsu	MB9BF428S internal	0	0	1	40	3	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[2];C000[1]; 10000[15]; 2000[8], 00508000;
1196	Fujitsu	MB9BF428T internal	0	0	1	40	3	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[2];C000[1]; 10000[15]; 2000[8], 00508000;
1197	Fujitsu	MB9BF429S internal	0	0	1	40	3	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[2];C000[1]; 10000[23]; 2000[8], 00508000;
1198	Fujitsu	MB9BF429T internal	0	0	1	40	3	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[2];C000[1]; 10000[23]; 2000[8], 00508000;
1199	Fujitsu	MB9BF464K internal	0	0	1	40	2	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[4];8000[1];10000[7]; 2000[4], 200C0000;
1200	Fujitsu	MB9BF464L internal	0	0	1	40	2	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[4];8000[1];10000[7]; 2000[4], 200C0000;
1201	Fujitsu	MB9BF465K internal	0	0	1	40	2	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[4];8000[1];10000[7]; 2000[4], 200C0000;
1202	Fujitsu	MB9BF465L internal	0	0	1	40	2	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[4];8000[1];10000[7]; 2000[4], 200C0000;
1203	Fujitsu	MB9BF466K internal	0	0	1	40	2	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[4];8000[1];10000[7]; 2000[4], 200C0000;
1204	Fujitsu	MB9BF466L internal	0	0	1	40	2	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[4];8000[1];10000[7]; 2000[4], 200C0000;
1205	Fujitsu	MB9BF466M internal	0	0	1	40	2	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[4];8000[1];10000[7]; 2000[4], 200C0000;
1206	Fujitsu	MB9BF466N internal	0	0	1	40	2	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[4];8000[1];10000[7]; 2000[4], 200C0000;
1207	Fujitsu	MB9BF466R internal	0	0	1	40	2	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[4];8000[1];10000[7]; 2000[4], 200C0000;
1208	Fujitsu	MB9BF467M internal	0	0	1	40	2	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[4];8000[1];10000[11]; 2000[4], 200C0000;
1209	Fujitsu	MB9BF467N internal	0	0	1	40	2	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[4];8000[1];10000[11]; 2000[4], 200C0000;
1210	Fujitsu	MB9BF467R internal	0	0	1	40	2	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[4];8000[1];10000[11]; 2000[4], 200C0000;
1211	Fujitsu	MB9BF468M internal	0	0	1	40	2	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[4];8000[1];10000[15]; 2000[4], 200C0000;
1212	Fujitsu	MB9BF468N internal	0	0	1	40	2	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[4];8000[1];10000[15]; 2000[4], 200C0000;
1213	Fujitsu	MB9BF468R internal	0	0	1	40	2	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[4];8000[1];10000[15]; 2000[4], 200C0000;
1214	Fujitsu	MB9BF504N internal	0	0	1	40	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	4000[2];18000[1];20000[1];
1215	Fujitsu	MB9BF504R internal	0	0	1	40	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	4000[2];18000[1];20000[1];
1216	Fujitsu	MB9BF505N internal	0	0	1	40	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	4000[2];18000[1];20000[2];
1217	Fujitsu	MB9BF505R internal	0	0	1	40	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	4000[2];18000[1];20000[2];
1218	Fujitsu	MB9BF506N internal	0	0	1	40	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	4000[2];18000[1];20000[3];
1219	Fujitsu	MB9BF506R internal	0	0	1	40	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	4000[2];18000[1];20000[3];
1220	Fujitsu	MB9BF512N internal	0	0	1	40	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	4000[2];18000[1]; 2000[4], 200C0000;
1221	Fujitsu	MB9BF512R internal	0	0	1	40	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	4000[2];18000[1]; 2000[4], 200C0000;
1222	Fujitsu	MB9BF514N internal	0	0	1	40	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	4000[2];18000[1];20000[1]; 2000[4], 200C0000;
1223	Fujitsu	MB9BF514R internal	0	0	1	40	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	4000[2];18000[1];20000[1]; 2000[4], 200C0000;
1224	Fujitsu	MB9BF515N internal	0	0	1	40	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	4000[2];18000[1];20000[2]; 2000[4], 200C0000;
1225	Fujitsu	MB9BF515R internal	0	0	1	40	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	4000[2];18000[1];20000[2]; 2000[4], 200C0000;
1226	Fujitsu	MB9BF516N internal	0	0	1	40	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	4000[2];18000[1];20000[3]; 2000[4], 200C0000;
1227	Fujitsu	MB9BF516R internal	0	0	1	40	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	4000[2];18000[1];20000[3]; 2000[4], 200C0000;
1228	Fujitsu	MB9BF516S internal	0	0	1	40	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	4000[2];18000[1];20000[3];
1229	Fujitsu	MB9BF516T internal	0	0	1	40	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	4000[2];18000[1];20000[3];
1230	Fujitsu	MB9BF517S internal	0	0	1	40	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	4000[2];18000[1];20000[5];
1231	Fujitsu	MB9BF517T internal	0	0	1	40	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	4000[2];18000[1];20000[5];
1232	Fujitsu	MB9BF518S internal	0	0	1	40	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	4000[2];18000[1];20000[7];
1233	Fujitsu	MB9BF518T internal	0	0	1	40	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	4000[2];18000[1];20000[7];
1234	Fujitsu	MB9BF521K internal	0	0	1	40	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[2];C000[1]; 2000[4], 200000;
1235	Fujitsu	MB9BF521L internal	0	0	1	40	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[2];C000[1]; 2000[4], 200000;
1236	Fujitsu	MB9BF521M internal	0	0	1	40	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[2];C000[1]; 2000[4], 200000;
1237	Fujitsu	MB9BF522K internal	0	0	1	40	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[2];C000[1];10000[1]; 2000[4], 200000;
1238	Fujitsu	MB9BF522L internal	0	0	1	40	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[2];C000[1];10000[1]; 2000[4], 200000;
1239	Fujitsu	MB9BF522M internal	0	0	1	40	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[2];C000[1];10000[1]; 2000[4], 200000;
1240	Fujitsu	MB9BF524K internal	0	0	1	40	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[2];C000[1];10000[3]; 2000[4], 200000;
1241	Fujitsu	MB9BF524L internal	0	0	1	40	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[2];C000[1];10000[3]; 2000[4], 200000;
1242	Fujitsu	MB9BF524M internal	0	0	1	40	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[2];C000[1];10000[3]; 2000[4], 200000;
1243	Fujitsu	MB9BF528S internal	0	0	1	40	3	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[2];C000[1]; 10000[15]; 2000[8], 00508000;
1244	Fujitsu	MB9BF528T internal	0	0	1	40	3	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[2];C000[1]; 10000[15]; 2000[8], 00508000;
1245	Fujitsu	MB9BF529S internal	0	0	1	40	3	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[2];C000[1]; 10000[23]; 2000[8], 00508000;
1246	Fujitsu	MB9BF529T internal	0	0	1	40	3	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[2];C000[1]; 10000[23]; 2000[8], 00508000;
1247	Fujitsu	MB9BF564K internal	0	0	1	40	2	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[4];8000[1];10000[7]; 2000[4], 200C0000;
1248	Fujitsu	MB9BF564L internal	0	0	1	40	2	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[4];8000[1];10000[7]; 2000[4], 200C0000;
1249	Fujitsu	MB9BF565K internal	0	0	1	40	2	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[4];8000[1];10000[7]; 2000[4], 200C0000;
1250	Fujitsu	MB9BF565L internal	0	0	1	40	2	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[4];8000[1];10000[7]; 2000[4], 200C0000;
1251	Fujitsu	MB9BF566K internal	0	0	1	40	2	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[4];8000[1];10000[7]; 2000[4], 200C0000;
1252	Fujitsu	MB9BF566L internal	0	0	1	40	2	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[4];8000[1];10000[7]; 2000[4], 200C0000;
1253	Fujitsu	MB9BF566M internal	0	0	1	40	2	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[4];8000[1];10000[7]; 2000[4], 200C0000;
1254	Fujitsu	MB9BF566N internal	0	0	1	40	2	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[4];8000[1];10000[7]; 2000[4], 200C0000;
1255	Fujitsu	MB9BF566R internal	0	0	1	40	2	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[4];8000[1];10000[7]; 2000[4], 200C0000;
1256	Fujitsu	MB9BF567M internal	0	0	1	40	2	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[4];8000[1];10000[11]; 2000[4], 200C0000;
1257	Fujitsu	MB9BF567N internal	0	0	1	40	2	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[4];8000[1];10000[11]; 2000[4], 200C0000;
1258	Fujitsu	MB9BF567R internal	0	0	1	40	2	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[4];8000[1];10000[11]; 2000[4], 200C0000;
1259	Fujitsu	MB9BF568M internal	0	0	1	40	2	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[4];8000[1];10000[15]; 2000[4], 200C0000;
1260	Fujitsu	MB9BF568N internal	0	0	1	40	2	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[4];8000[1];10000[15]; 2000[4], 200C0000;
1261	Fujitsu	MB9BF568R internal	0	0	1	40	2	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[4];8000[1];10000[15]; 2000[4], 200C0000;
1262	Fujitsu	MB9BF616S internal	0	0	1	40	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	4000[2];18000[1];20000[3];
1263	Fujitsu	MB9BF616T internal	0	0	1	40	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	4000[2];18000[1];20000[3];
1264	Fujitsu	MB9BF617S internal	0	0	1	40	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	4000[2];18000[1];20000[5];
1265	Fujitsu	MB9BF617T internal	0	0	1	40	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	4000[2];18000[1];20000[5];
1266	Fujitsu	MB9BF618S internal	0	0	1	40	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	4000[2];18000[1];20000[7];
1267	Fujitsu	MB9BF618T internal	0	0	1	40	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	4000[2];18000[1];20000[7];
1268	Fujitsu	MB9BFD16S internal	0	0	1	40	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	4000[2];18000[1];20000[3];
1269	Fujitsu	MB9BFD16T internal	0	0	1	40	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	4000[2];18000[1];20000[3];
1270	Fujitsu	MB9BFD17S internal	0	0	1	40	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	4000[2];18000[1];20000[5];
1271	Fujitsu	MB9BFD17T internal	0	0	1	40	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	4000[2];18000[1];20000[5];
1272	Fujitsu	MB9BFD18S internal	0	0	1	40	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	4000[2];18000[1];20000[7];
1273	Fujitsu	MB9BFD18T internal	0	0	1	40	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	4000[2];18000[1];20000[7];
1274	Fujitsu	MB9DF125 internal	0	0	1	54	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	20000[8]; 4000[4], 7F0000;
1275	Fujitsu	MB9DF126 internal	0	0	1	54	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	40000[8]; 4000[8], 7E0000;
1276	Fujitsu	MB9EF126 internal	0	0	1	54	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	40000[8]; 4000[8], 7E0000;
1277	Fujitsu	MB9EF226 internal	0	0	1	54	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	40000[8]; 4000[8], 7E0000;
1278	Fujitsu	MBM29DL322BE/BD	42256	40056	0	1	0	16	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[8]; 10000[63];
1279	Fujitsu	MBM29DL322TE/TD	42255	40055	0	1	0	16	1	0	0	0	0	0	0	0	0	0	0	0	0	10000[63]; 2000[8];
1280	Fujitsu	MBM29LV160B	042249	040049	0	1	0	16	1	0	0	0	0	0	0	0	0	0	0	0	0	4000; 2000[2]; 8000; 10000[31];
1281	Fujitsu	MBM29LV160T	0422C4	0400C4	0	1	0	16	1	0	0	0	0	0	0	0	0	0	0	0	0	10000[31]; 8000; 2000[2]; 4000;
1282	Fujitsu	MBM29LV650U	0422D7	0400D7	0	1	0	16	1	0	0	0	0	0	0	0	0	0	0	0	0	10000[128];
1283	Fujitsu	S6E1A11B0A internal	0	0	1	40	4	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[3];8000[1];
1284	Fujitsu	S6E1A11C0A internal	0	0	1	40	4	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[3];8000[1];
1285	Fujitsu	S6E1A12B0A internal	0	0	1	40	4	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[3];8000[2];
1286	Fujitsu	S6E1A12C0A internal	0	0	1	40	4	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[3];8000[2];
1287	Holtek	HT32F1251 internal	0	0	1	52	0	32	1	1	0	0	0	0	0	0	0	0	0	0	0	400[8];
1288	Holtek	HT32F1251 internal optbytes	0	0	1	52	0	32	1	1	0	0	0	0	0	0	0	0	0	0	0	400[8]; 400[1], 1FF00000;
1289	Holtek	HT32F1252 internal	0	0	1	52	0	32	1	1	0	0	0	0	0	0	0	0	0	0	0	400[16];
1290	Holtek	HT32F1252 internal optbytes	0	0	1	52	0	32	1	1	0	0	0	0	0	0	0	0	0	0	0	400[16]; 400[1], 1FF00000;
1291	Holtek	HT32F1253 internal	0	0	1	52	0	32	1	1	0	0	0	0	0	0	0	0	0	0	0	400[31];
1292	Holtek	HT32F1253 internal optbytes	0	0	1	52	0	32	1	1	0	0	0	0	0	0	0	0	0	0	0	400[31]; 400[1], 1FF00000;
1293	Holtek	HT32F1755 internal	0	0	1	52	0	32	1	1	0	0	0	0	0	0	0	0	0	0	0	400[127];
1294	Holtek	HT32F1755 internal optbytes	0	0	1	52	0	32	1	1	0	0	0	0	0	0	0	0	0	0	0	400[127]; 400[1], 1FF00000;
1295	Holtek	HT32F1765 internal	0	0	1	52	0	32	1	1	0	0	0	0	0	0	0	0	0	0	0	400[127];
1296	Holtek	HT32F1765 internal optbytes	0	0	1	52	0	32	1	1	0	0	0	0	0	0	0	0	0	0	0	400[127]; 400[1], 1FF00000;
1297	Holtek	HT32F2755 internal	0	0	1	52	0	32	1	1	0	0	0	0	0	0	0	0	0	0	0	400[127];
1298	Holtek	HT32F2755 internal optbytes	0	0	1	52	0	32	1	1	0	0	0	0	0	0	0	0	0	0	0	400[127]; 400[1], 1FF00000;
1299	Intel	28F004B3B	8900D5	8900D5	0	2	0	8	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[8]; 10000[7];
1300	Intel	28F004B3T	8900D4	8900D4	0	2	0	8	1	0	0	0	0	0	0	0	0	0	0	0	0	10000[7]; 2000[8];
1301	Intel	28F008B3B	8900D3	8900D3	0	2	0	8	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[8]; 10000[15];
1302	Intel	28F008B3T	8900D2	8900D2	0	2	0	8	1	0	0	0	0	0	0	0	0	0	0	0	0	10000[15]; 2000[8];
1303	Intel	28F016B3B	8900D1	8900D1	0	2	0	8	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[8]; 10000[31];
1304	Intel	28F016B3T	8900D0	8900D0	0	2	0	8	1	0	0	0	0	0	0	0	0	0	0	0	0	10000[31]; 2000[8];
1305	Intel	28F128J3	890018	890018	0	10	0	16	1	0	0	1	0	1	0	0	0	0	2	0	0	20000[128];
1306	Intel	28F128K18	898806	890006	0	10	0	16	1	0	0	1	0	0	0	0	0	0	1	0	0	20000[128];
1307	Intel	28F128K3	898802	890002	0	10	0	16	1	0	0	1	0	0	0	0	0	0	1	0	0	20000[128];
1308	Intel	28F128P30B	89881B	89001B	0	10	0	16	1	0	0	1	0	0	0	0	0	0	1	0	0	8000[4]; 20000[127];
1309	Intel	28F128P30T	898818	890018	0	10	0	16	1	0	0	1	0	0	0	0	0	0	1	0	0	20000[127]; 8000[4];
1310	Intel	28F128P33B	898821	890021	0	10	0	16	1	0	0	1	0	0	0	0	0	0	1	0	0	8000[4]; 20000[127];
1311	Intel	28F128P33T	89881E	89001E	0	10	0	16	1	0	0	1	0	0	0	0	0	0	1	0	0	20000[127]; 8000[4];
1312	Intel	28F128W18B	898867	890067	0	2	0	16	1	0	0	1	0	0	0	0	0	0	1	0	0	2000[8]; 10000[255];
1313	Intel	28F128W18T	898866	890066	0	2	0	16	1	0	0	1	0	0	0	0	0	0	1	0	0	10000[255]; 2000[8];
1314	Intel	28F160B3B	898891	890091	0	2	0	16	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[8]; 10000[31];
1315	Intel	28F160B3T	898890	890090	0	2	0	16	1	0	0	0	0	0	0	0	0	0	0	0	0	10000[31]; 2000[8];
1316	Intel	28F160C3B	8988C3	8900C3	0	2	0	16	1	0	0	1	0	0	0	0	0	0	1	0	0	2000[8]; 10000[31];
1317	Intel	28F160C3T	8988C2	8900C2	0	2	0	16	1	0	0	1	0	0	0	0	0	0	1	0	0	10000[31]; 2000[8];
1318	Intel	28F256J3	89001D	89001D	0	10	0	16	1	0	0	1	0	1	0	0	0	0	1	0	0	20000[256];
1319	Intel	28F256K18	898807	890007	0	10	0	16	1	0	0	1	0	0	0	0	0	0	1	0	0	20000[256];
1320	Intel	28F256K3	898803	890003	0	10	0	16	1	0	0	1	0	0	0	0	0	0	1	0	0	20000[256];
1321	Intel	28F256P30B	89891C	89001C	0	10	0	16	1	0	0	1	0	0	0	0	0	0	1	0	0	8000[4]; 20000[255];
1322	Intel	28F256P30T	898919	890019	0	10	0	16	1	0	0	1	0	0	0	0	0	0	1	0	0	20000[255]; 8000[4];
1323	Intel	28F256P33B	898922	890022	0	10	0	16	1	0	0	1	0	0	0	0	0	0	1	0	0	8000[4]; 20000[255];
1324	Intel	28F256P33T	89891F	89001F	0	10	0	16	1	0	0	1	0	0	0	0	0	0	1	0	0	20000[255]; 8000[4];
1325	Intel	28F320B3B	898897	890097	0	2	0	16	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[8]; 10000[63];
1326	Intel	28F320B3T	898896	890096	0	2	0	16	1	0	0	0	0	0	0	0	0	0	0	0	0	10000[63]; 2000[8];
1327	Intel	28F320C3B	8988C5	8900C5	0	2	0	16	1	0	0	1	0	0	0	0	0	0	1	0	0	2000[8]; 10000[63];
1328	Intel	28F320C3T	8988C4	8900C4	0	2	0	16	1	0	0	1	0	0	0	0	0	0	1	0	0	10000[63]; 2000[8];
1329	Intel	28F320J3	890016	890016	0	10	0	16	1	0	0	1	0	1	0	0	0	0	1	0	0	20000[32];
1330	Intel	28F320W18B	898863	890063	0	2	0	16	1	0	0	1	0	0	0	0	0	0	1	0	0	2000[8]; 10000[63];
1331	Intel	28F320W18T	898862	890062	0	2	0	16	1	0	0	1	0	0	0	0	0	0	1	0	0	10000[63]; 2000[8];
1332	Intel	28F400B3B	898895	890095	0	2	0	16	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[8]; 10000[7];
1333	Intel	28F400B3T	898894	890094	0	2	0	16	1	0	0	0	0	0	0	0	0	0	0	0	0	10000[7]; 2000[8];
1334	Intel	28F640B3B	898899	890099	0	2	0	16	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[8]; 10000[127];
1335	Intel	28F640B3T	898898	890098	0	2	0	16	1	0	0	0	0	0	0	0	0	0	0	0	0	10000[127]; 2000[8];
1336	Intel	28F640C3B	8988CD	8900CD	0	2	0	16	1	0	0	1	0	0	0	0	0	0	1	0	0	2000[8]; 10000[127];
1337	Intel	28F640C3T	8988CC	8900CC	0	2	0	16	1	0	0	1	0	0	0	0	0	0	1	0	0	10000[127]; 2000[8];
1338	Intel	28F640J3	890017	890017	0	10	0	16	1	0	0	1	0	1	0	0	0	0	1	0	0	20000[64];
1339	Intel	28F640K18	898805	890005	0	10	0	16	1	0	0	1	0	0	0	0	0	0	1	0	0	20000[64];
1340	Intel	28F640K3	898801	890001	0	10	0	16	1	0	0	1	0	0	0	0	0	0	1	0	0	20000[64];
1341	Intel	28F640P30B	89881A	89001A	0	10	0	16	1	0	0	1	0	0	0	0	0	0	1	0	0	8000[4]; 20000[63];
1342	Intel	28F640P30T	898817	890017	0	10	0	16	1	0	0	1	0	0	0	0	0	0	1	0	0	20000[63]; 8000[4];
1343	Intel	28F640P33B	898820	890020	0	10	0	16	1	0	0	1	0	0	0	0	0	0	1	0	0	8000[4]; 20000[63];
1344	Intel	28F640P33T	89881D	89001D	0	10	0	16	1	0	0	1	0	0	0	0	0	0	1	0	0	20000[63]; 8000[4];
1345	Intel	28F640W18B	898865	890065	0	2	0	16	1	0	0	1	0	0	0	0	0	0	1	0	0	2000[8]; 10000[127];
1346	Intel	28F640W18T	898864	890064	0	2	0	16	1	0	0	1	0	0	0	0	0	0	1	0	0	10000[127]; 2000[8];
1347	Intel	28F800B3B	898893	890093	0	2	0	16	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[8]; 10000[15];
1348	Intel	28F800B3T	898892	890092	0	2	0	16	1	0	0	0	0	0	0	0	0	0	0	0	0	10000[15]; 2000[8];
1349	Intel	28F800C3B	8988C1	8900C1	0	2	0	16	1	0	0	1	0	0	0	0	0	0	1	0	0	2000[8]; 10000[15];
1350	Intel	28F800C3T	8988C0	8900C0	0	2	0	16	1	0	0	1	0	0	0	0	0	0	1	0	0	10000[15]; 2000[8];
1351	Infineon	TLE9842 internal	0	0	1	65	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	1000[8];
1352	Infineon	TLE9843 internal	0	0	1	65	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	1000[11];
1353	Infineon	TLE9844 internal	0	0	1	65	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	1000[15];
1354	Infineon	TLE9845 internal	0	0	1	65	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	1000[11];
1355	Infineon	TLE9861 internal	0	0	1	65	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	1000[9];
1356	Infineon	TLE9867 internal	0	0	1	65	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	1000[16];
1357	Infineon	TLE9869 internal	0	0	1	65	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	1000[32];
1358	Infineon	TLE9871 internal	0	0	1	65	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	1000[9];
1359	Infineon	TLE9877 internal	0	0	1	65	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	1000[16];
1360	Infineon	TLE9879 internal	0	0	1	65	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	1000[32];
1361	Infineon	UMFx110 internal	0	0	1	67	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	1000[29];
1362	Infineon	UMFx110 internal (allow security)	0	0	1	67	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	1000[32];
1363	Infineon	UMFx120 internal	0	0	1	67	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	1000[62];
1364	Infineon	UMFx120 internal (allow security)	0	0	1	67	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	1000[65];
1365	Infineon	XMC1100-0008 internal	0	0	1	55	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	100[32];
1366	Infineon	XMC1100-0016 internal	0	0	1	55	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	100[64];
1367	Infineon	XMC1100-0032 internal	0	0	1	55	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	100[128];
1368	Infineon	XMC1100-0064 internal	0	0	1	55	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	100[256];
1369	Infineon	XMC1200-0200 internal	0	0	1	55	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	100[800];
1370	Infineon	XMC1201-0016 internal	0	0	1	55	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	100[64];
1371	Infineon	XMC1201-0032 internal	0	0	1	55	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	100[128];
1372	Infineon	XMC1201-0064 internal	0	0	1	55	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	100[256];
1373	Infineon	XMC1201-0128 internal	0	0	1	55	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	100[512];
1374	Infineon	XMC1201-0200 internal	0	0	1	55	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	100[800];
1375	Infineon	XMC1202-0016 internal	0	0	1	55	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	100[64];
1376	Infineon	XMC1202-0032 internal	0	0	1	55	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	100[128];
1377	Infineon	XMC1202-0064 internal	0	0	1	55	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	100[256];
1378	Infineon	XMC1203-0016 internal	0	0	1	55	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	100[64];
1379	Infineon	XMC1203-0032 internal	0	0	1	55	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	100[128];
1380	Infineon	XMC1203-0064 internal	0	0	1	55	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	100[256];
1381	Infineon	XMC1203-0128 internal	0	0	1	55	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	100[512];
1382	Infineon	XMC1203-0200 internal	0	0	1	55	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	100[800];
1383	Infineon	XMC1301-0008 internal	0	0	1	55	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	100[32];
1384	Infineon	XMC1301-0016 internal	0	0	1	55	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	100[64];
1385	Infineon	XMC1301-0032 internal	0	0	1	55	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	100[128];
1386	Infineon	XMC1301-0064 internal	0	0	1	55	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	100[256];
1387	Infineon	XMC1302-0016 internal	0	0	1	55	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	100[64];
1388	Infineon	XMC1302-0032 internal	0	0	1	55	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	100[128];
1389	Infineon	XMC1302-0064 internal	0	0	1	55	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	100[256];
1390	Infineon	XMC1302-0128 internal	0	0	1	55	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	100[512];
1391	Infineon	XMC1302-0200 internal	0	0	1	55	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	100[800];
1392	Infineon	XMC1401-0064 internal	0	0	1	55	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	100[256];
1393	Infineon	XMC1401-0128 internal	0	0	1	55	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	100[512];
1394	Infineon	XMC1402-0032 internal	0	0	1	55	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	100[128];
1395	Infineon	XMC1402-0064 internal	0	0	1	55	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	100[256];
1396	Infineon	XMC1402-0128 internal	0	0	1	55	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	100[512];
1397	Infineon	XMC1402-0200 internal	0	0	1	55	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	100[800];
1398	Infineon	XMC1403-0064 internal	0	0	1	55	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	100[256];
1399	Infineon	XMC1403-0128 internal	0	0	1	55	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	100[512];
1400	Infineon	XMC1403-0200 internal	0	0	1	55	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	100[800];
1401	Infineon	XMC1404-0064 internal	0	0	1	55	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	100[256];
1402	Infineon	XMC1404-0128 internal	0	0	1	55	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	100[512];
1403	Infineon	XMC1404-0200 internal	0	0	1	55	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	100[800];
1404	Infineon	XMC4100-128 internal	0	0	1	45	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	10000[2];
1405	Infineon	XMC4104-64 internal	0	0	1	45	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	10000[1];
1406	Infineon	XMC4104-128 internal	0	0	1	45	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	10000[2];
1407	Infineon	XMC4200-256 internal	0	0	1	45	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	10000[2]; 20000[1];
1408	Infineon	XMC4400-256 internal	0	0	1	45	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	10000[2]; 20000[1];
1409	Infineon	XMC4300-256 internal	0	0	1	45	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	10000[2]; 20000[1];
1410	Infineon	XMC4400-512 internal	0	0	1	45	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	10000[2]; 20000[1]; 40000[1];
1411	Infineon	XMC4402-256 internal	0	0	1	45	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	10000[2]; 20000[1];
1412	Infineon	XMC4500-768 internal	0	0	1	45	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	10000[2]; 20000[1]; 40000[2];
1413	Infineon	XMC4500-1024 internal	0	0	1	45	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	10000[2]; 20000[1]; 40000[3];
1414	Infineon	XMC4502 internal	0	0	1	45	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	10000[2]; 20000[1]; 40000[2];
1415	Infineon	XMC4504 internal	0	0	1	45	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	10000[2]; 20000[1]; 40000[1];
1416	Infineon	XMC4700-1536 internal	0	0	1	45	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	10000[2]; 20000[1]; 40000[5];
1417	Infineon	XMC4700-2048 internal	0	0	1	45	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	10000[2]; 20000[1]; 40000[7];
1418	Infineon	XMC4800-1024 internal	0	0	1	45	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	10000[2]; 20000[1]; 40000[3];
1419	Infineon	XMC4800-1536 internal	0	0	1	45	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	10000[2]; 20000[1]; 40000[5];
1420	Infineon	XMC4800-2048 internal	0	0	1	45	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	10000[2]; 20000[1]; 40000[7];
1421	Itron	TRIFECTA internal	0	0	1	30	0	32	1	1	0	0	0	0	0	0	0	0	0	0	0	1000[128]; 800[64], 100000;
1422	Itron	TRIFECTA internal (Allow info blocks)	0	0	1	30	1	32	1	1	0	0	0	0	0	0	0	0	0	0	0	1000[132]; 800[65], 100000;
1423	Luminary	LM3S101 internal	0	0	1	18	0	32	1	1	0	0	0	0	0	0	0	0	0	0	0	400[8];
1424	Luminary	LM3S102 internal	0	0	1	18	0	32	1	1	0	0	0	0	0	0	0	0	0	0	0	400[8];
1425	Luminary	LM3S300 internal	0	0	1	18	0	32	1	1	0	0	0	0	0	0	0	0	0	0	0	400[16];
1426	Luminary	LM3S301 internal	0	0	1	18	0	32	1	1	0	0	0	0	0	0	0	0	0	0	0	400[16];
1427	Luminary	LM3S308 internal	0	0	1	18	0	32	1	1	0	0	0	0	0	0	0	0	0	0	0	400[16];
1428	Luminary	LM3S310 internal	0	0	1	18	0	32	1	1	0	0	0	0	0	0	0	0	0	0	0	400[16];
1429	Luminary	LM3S315 internal	0	0	1	18	0	32	1	1	0	0	0	0	0	0	0	0	0	0	0	400[16];
1430	Luminary	LM3S316 internal	0	0	1	18	0	32	1	1	0	0	0	0	0	0	0	0	0	0	0	400[16];
1431	Luminary	LM3S317 internal	0	0	1	18	0	32	1	1	0	0	0	0	0	0	0	0	0	0	0	400[16];
1432	Luminary	LM3S328 internal	0	0	1	18	0	32	1	1	0	0	0	0	0	0	0	0	0	0	0	400[16];
1433	Luminary	LM3S600 internal	0	0	1	18	0	32	1	1	0	0	0	0	0	0	0	0	0	0	0	400[32];
1434	Luminary	LM3S601 internal	0	0	1	18	0	32	1	1	0	0	0	0	0	0	0	0	0	0	0	400[32];
1435	Luminary	LM3S608 internal	0	0	1	18	0	32	1	1	0	0	0	0	0	0	0	0	0	0	0	400[32];
1436	Luminary	LM3S610 internal	0	0	1	18	0	32	1	1	0	0	0	0	0	0	0	0	0	0	0	400[32];
1437	Luminary	LM3S611 internal	0	0	1	18	0	32	1	1	0	0	0	0	0	0	0	0	0	0	0	400[32];
1438	Luminary	LM3S612 internal	0	0	1	18	0	32	1	1	0	0	0	0	0	0	0	0	0	0	0	400[32];
1439	Luminary	LM3S613 internal	0	0	1	18	0	32	1	1	0	0	0	0	0	0	0	0	0	0	0	400[32];
1440	Luminary	LM3S615 internal	0	0	1	18	0	32	1	1	0	0	0	0	0	0	0	0	0	0	0	400[32];
1441	Luminary	LM3S617 internal	0	0	1	18	0	32	1	1	0	0	0	0	0	0	0	0	0	0	0	400[32];
1442	Luminary	LM3S618 internal	0	0	1	18	0	32	1	1	0	0	0	0	0	0	0	0	0	0	0	400[32];
1443	Luminary	LM3S628 internal	0	0	1	18	0	32	1	1	0	0	0	0	0	0	0	0	0	0	0	400[32];
1444	Luminary	LM3S800 internal	0	0	1	18	0	32	1	1	0	0	0	0	0	0	0	0	0	0	0	400[64];
1445	Luminary	LM3S801 internal	0	0	1	18	0	32	1	1	0	0	0	0	0	0	0	0	0	0	0	400[64];
1446	Luminary	LM3S808 internal	0	0	1	18	0	32	1	1	0	0	0	0	0	0	0	0	0	0	0	400[64];
1447	Luminary	LM3S811 internal	0	0	1	18	0	32	1	1	0	0	0	0	0	0	0	0	0	0	0	400[64];
1448	Luminary	LM3S812 internal	0	0	1	18	0	32	1	1	0	0	0	0	0	0	0	0	0	0	0	400[64];
1449	Luminary	LM3S815 internal	0	0	1	18	0	32	1	1	0	0	0	0	0	0	0	0	0	0	0	400[64];
1450	Luminary	LM3S817 internal	0	0	1	18	0	32	1	1	0	0	0	0	0	0	0	0	0	0	0	400[64];
1451	Luminary	LM3S818 internal	0	0	1	18	0	32	1	1	0	0	0	0	0	0	0	0	0	0	0	400[64];
1452	Luminary	LM3S828 internal	0	0	1	18	0	32	1	1	0	0	0	0	0	0	0	0	0	0	0	400[64];
1453	Luminary	LM3S1110 internal	0	0	1	18	0	32	1	1	0	0	0	0	0	0	0	0	0	0	0	400[64];
1454	Luminary	LM3S1133 internal	0	0	1	18	0	32	1	1	0	0	0	0	0	0	0	0	0	0	0	400[64];
1455	Luminary	LM3S1138 internal	0	0	1	18	0	32	1	1	0	0	0	0	0	0	0	0	0	0	0	400[64];
1456	Luminary	LM3S1150 internal	0	0	1	18	0	32	1	1	0	0	0	0	0	0	0	0	0	0	0	400[64];
1457	Luminary	LM3S1162 internal	0	0	1	18	0	32	1	1	0	0	0	0	0	0	0	0	0	0	0	400[64];
1458	Luminary	LM3S1165 internal	0	0	1	18	0	32	1	1	0	0	0	0	0	0	0	0	0	0	0	400[64];
1459	Luminary	LM3S1166 internal	0	0	1	18	0	32	1	1	0	0	0	0	0	0	0	0	0	0	0	400[64];
1460	Luminary	LM3S1332 internal	0	0	1	18	0	32	1	1	0	0	0	0	0	0	0	0	0	0	0	400[96];
1461	Luminary	LM3S1435 internal	0	0	1	18	0	32	1	1	0	0	0	0	0	0	0	0	0	0	0	400[96];
1462	Luminary	LM3S1439 internal	0	0	1	18	0	32	1	1	0	0	0	0	0	0	0	0	0	0	0	400[96];
1463	Luminary	LM3S1512 internal	0	0	1	18	0	32	1	1	0	0	0	0	0	0	0	0	0	0	0	400[96];
1464	Luminary	LM3S1538 internal	0	0	1	18	0	32	1	1	0	0	0	0	0	0	0	0	0	0	0	400[96];
1465	Luminary	LM3S1601 internal	0	0	1	18	0	32	1	1	0	0	0	0	0	0	0	0	0	0	0	400[128];
1466	Luminary	LM3S1607 internal	0	0	1	18	1	32	1	1	0	0	0	0	0	0	0	0	0	0	0	400[128];
1467	Luminary	LM3S1608 internal	0	0	1	18	0	32	1	1	0	0	0	0	0	0	0	0	0	0	0	400[128];
1468	Luminary	LM3S1620 internal	0	0	1	18	0	32	1	1	0	0	0	0	0	0	0	0	0	0	0	400[128];
1469	Luminary	LM3S1621 internal	0	0	1	18	1	32	1	1	0	0	0	0	0	0	0	0	0	0	0	400[128];
1470	Luminary	LM3S1625 internal	0	0	1	18	1	32	1	1	0	0	0	0	0	0	0	0	0	0	0	400[128];
1471	Luminary	LM3S1626 internal	0	0	1	18	1	32	1	1	0	0	0	0	0	0	0	0	0	0	0	400[128];
1472	Luminary	LM3S1627 internal	0	0	1	18	1	32	1	1	0	0	0	0	0	0	0	0	0	0	0	400[128];
1473	Luminary	LM3S1635 internal	0	0	1	18	0	32	1	1	0	0	0	0	0	0	0	0	0	0	0	400[128];
1474	Luminary	LM3S1636 internal	0	0	1	18	0	32	1	1	0	0	0	0	0	0	0	0	0	0	0	400[128];
1475	Luminary	LM3S1637 internal	0	0	1	18	0	32	1	1	0	0	0	0	0	0	0	0	0	0	0	400[128];
1476	Luminary	LM3S1651 internal	0	0	1	18	1	32	1	1	0	0	0	0	0	0	0	0	0	0	0	400[128];
1477	Luminary	LM3S1751 internal	0	0	1	18	0	32	1	1	0	0	0	0	0	0	0	0	0	0	0	400[128];
1478	Luminary	LM3S1776 internal	0	0	1	18	1	32	1	1	0	0	0	0	0	0	0	0	0	0	0	400[128];
1479	Luminary	LM3S1811 internal	0	0	1	18	1	32	1	1	0	0	0	0	0	0	0	0	0	0	0	400[256];
1480	Luminary	LM3S1816 internal	0	0	1	18	1	32	1	1	0	0	0	0	0	0	0	0	0	0	0	400[256];
1481	Luminary	LM3S1850 internal	0	0	1	18	0	32	1	1	0	0	0	0	0	0	0	0	0	0	0	400[256];
1482	Luminary	LM3S1911 internal	0	0	1	18	0	32	1	1	0	0	0	0	0	0	0	0	0	0	0	400[256];
1483	Luminary	LM3S1918 internal	0	0	1	18	0	32	1	1	0	0	0	0	0	0	0	0	0	0	0	400[256];
1484	Luminary	LM3S1937 internal	0	0	1	18	0	32	1	1	0	0	0	0	0	0	0	0	0	0	0	400[256];
1485	Luminary	LM3S1958 internal	0	0	1	18	0	32	1	1	0	0	0	0	0	0	0	0	0	0	0	400[256];
1486	Luminary	LM3S1960 internal	0	0	1	18	0	32	1	1	0	0	0	0	0	0	0	0	0	0	0	400[256];
1487	Luminary	LM3S1968 internal	0	0	1	18	0	32	1	1	0	0	0	0	0	0	0	0	0	0	0	400[256];
1488	Luminary	LM3S1969 internal	0	0	1	18	0	32	1	1	0	0	0	0	0	0	0	0	0	0	0	400[256];
1489	Luminary	LM3S1B21 internal	0	0	1	18	1	32	1	1	0	0	0	0	0	0	0	0	0	0	0	400[256];
1490	Luminary	LM3S1C21 internal	0	0	1	18	1	32	1	1	0	0	0	0	0	0	0	0	0	0	0	400[512];
1491	Luminary	LM3S1C26 internal	0	0	1	18	1	32	1	1	0	0	0	0	0	0	0	0	0	0	0	400[512];
1492	Luminary	LM3S1C58 internal	0	0	1	18	1	32	1	1	0	0	0	0	0	0	0	0	0	0	0	400[512];
1493	Luminary	LM3S1D21 internal	0	0	1	18	1	32	1	1	0	0	0	0	0	0	0	0	0	0	0	400[512];
1494	Luminary	LM3S1D26 internal	0	0	1	18	1	32	1	1	0	0	0	0	0	0	0	0	0	0	0	400[512];
1495	Luminary	LM3S1F11 internal	0	0	1	18	1	32	1	1	0	0	0	0	0	0	0	0	0	0	0	400[384];
1496	Luminary	LM3S1F16 internal	0	0	1	18	0	32	1	1	0	0	0	0	0	0	0	0	0	0	0	400[384];
1497	Luminary	LM3S1G21 internal	0	0	1	18	1	32	1	1	0	0	0	0	0	0	0	0	0	0	0	400[384];
1498	Luminary	LM3S1G58 internal	0	0	1	18	1	32	1	1	0	0	0	0	0	0	0	0	0	0	0	400[384];
1499	Luminary	LM3S1H11 internal	0	0	1	18	1	32	1	1	0	0	0	0	0	0	0	0	0	0	0	400[512];
1500	Luminary	LM3S1H16 internal	0	0	1	18	1	32	1	1	0	0	0	0	0	0	0	0	0	0	0	400[512];
1501	Luminary	LM3S1J11 internal	0	0	1	18	1	32	1	1	0	0	0	0	0	0	0	0	0	0	0	400[128];
1502	Luminary	LM3S1J16 internal	0	0	1	18	1	32	1	1	0	0	0	0	0	0	0	0	0	0	0	400[128];
1503	Luminary	LM3S1N11 internal	0	0	1	18	1	32	1	1	0	0	0	0	0	0	0	0	0	0	0	400[64];
1504	Luminary	LM3S1N16 internal	0	0	1	18	1	32	1	1	0	0	0	0	0	0	0	0	0	0	0	400[64];
1505	Luminary	LM3S1P51 internal	0	0	1	18	1	32	1	1	0	0	0	0	0	0	0	0	0	0	0	400[64];
1506	Luminary	LM3S1R21 internal	0	0	1	18	1	32	1	1	0	0	0	0	0	0	0	0	0	0	0	400[256];
1507	Luminary	LM3S1R26 internal	0	0	1	18	1	32	1	1	0	0	0	0	0	0	0	0	0	0	0	400[256];
1508	Luminary	LM3S1W16 internal	0	0	1	18	1	32	1	1	0	0	0	0	0	0	0	0	0	0	0	400[32];
1509	Luminary	LM3S1Z16 internal	0	0	1	18	1	32	1	1	0	0	0	0	0	0	0	0	0	0	0	400[16];
1510	Luminary	LM3S2016 internal	0	0	1	18	1	32	1	1	0	0	0	0	0	0	0	0	0	0	0	400[384];
1511	Luminary	LM3S2110 internal	0	0	1	18	0	32	1	1	0	0	0	0	0	0	0	0	0	0	0	400[64];
1512	Luminary	LM3S2139 internal	0	0	1	18	0	32	1	1	0	0	0	0	0	0	0	0	0	0	0	400[64];
1513	Luminary	LM3S2276 internal	0	0	1	18	1	32	1	1	0	0	0	0	0	0	0	0	0	0	0	400[64];
1514	Luminary	LM3S2410 internal	0	0	1	18	0	32	1	1	0	0	0	0	0	0	0	0	0	0	0	400[96];
1515	Luminary	LM3S2412 internal	0	0	1	18	0	32	1	1	0	0	0	0	0	0	0	0	0	0	0	400[96];
1516	Luminary	LM3S2432 internal	0	0	1	18	0	32	1	1	0	0	0	0	0	0	0	0	0	0	0	400[96];
1517	Luminary	LM3S2533 internal	0	0	1	18	0	32	1	1	0	0	0	0	0	0	0	0	0	0	0	400[96];
1518	Luminary	LM3S2601 internal	0	0	1	18	0	32	1	1	0	0	0	0	0	0	0	0	0	0	0	400[128];
1519	Luminary	LM3S2608 internal	0	0	1	18	0	32	1	1	0	0	0	0	0	0	0	0	0	0	0	400[128];
1520	Luminary	LM3S2616 internal	0	0	1	18	0	32	1	1	0	0	0	0	0	0	0	0	0	0	0	400[128];
1521	Luminary	LM3S2671 internal	0	0	1	18	1	32	1	1	0	0	0	0	0	0	0	0	0	0	0	400[128];
1522	Luminary	LM3S2620 internal	0	0	1	18	0	32	1	1	0	0	0	0	0	0	0	0	0	0	0	400[128];
1523	Luminary	LM3S2637 internal	0	0	1	18	0	32	1	1	0	0	0	0	0	0	0	0	0	0	0	400[128];
1524	Luminary	LM3S2651 internal	0	0	1	18	0	32	1	1	0	0	0	0	0	0	0	0	0	0	0	400[128];
1525	Luminary	LM3S2678 internal	0	0	1	18	0	32	1	1	0	0	0	0	0	0	0	0	0	0	0	400[128];
1526	Luminary	LM3S2730 internal	0	0	1	18	0	32	1	1	0	0	0	0	0	0	0	0	0	0	0	400[128];
1527	Luminary	LM3S2739 internal	0	0	1	18	0	32	1	1	0	0	0	0	0	0	0	0	0	0	0	400[128];
1528	Luminary	LM3S2776 internal	0	0	1	18	1	32	1	1	0	0	0	0	0	0	0	0	0	0	0	400[128];
1529	Luminary	LM3S2793 internal	0	0	1	18	1	32	1	1	0	0	0	0	0	0	0	0	0	0	0	400[128];
1530	Luminary	LM3S2911 internal	0	0	1	18	0	32	1	1	0	0	0	0	0	0	0	0	0	0	0	400[256];
1531	Luminary	LM3S2918 internal	0	0	1	18	0	32	1	1	0	0	0	0	0	0	0	0	0	0	0	400[256];
1532	Luminary	LM3S2919 internal	0	0	1	18	0	32	1	1	0	0	0	0	0	0	0	0	0	0	0	400[256];
1533	Luminary	LM3S2939 internal	0	0	1	18	0	32	1	1	0	0	0	0	0	0	0	0	0	0	0	400[256];
1534	Luminary	LM3S2948 internal	0	0	1	18	0	32	1	1	0	0	0	0	0	0	0	0	0	0	0	400[256];
1535	Luminary	LM3S2950 internal	0	0	1	18	0	32	1	1	0	0	0	0	0	0	0	0	0	0	0	400[256];
1536	Luminary	LM3S2965 internal	0	0	1	18	0	32	1	1	0	0	0	0	0	0	0	0	0	0	0	400[256];
1537	Luminary	LM3S2B93 internal	0	0	1	18	1	32	1	1	0	0	0	0	0	0	0	0	0	0	0	400[256];
1538	Luminary	LM3S2D93 internal	0	0	1	18	1	32	1	1	0	0	0	0	0	0	0	0	0	0	0	400[512];
1539	Luminary	LM3S2U93 internal	0	0	1	18	1	32	1	1	0	0	0	0	0	0	0	0	0	0	0	400[384];
1540	Luminary	LM3S3634 internal	0	0	1	18	1	32	1	1	0	0	0	0	0	0	0	0	0	0	0	400[128];
1541	Luminary	LM3S3651 internal	0	0	1	18	1	32	1	1	0	0	0	0	0	0	0	0	0	0	0	400[128];
1542	Luminary	LM3S3654 internal	0	0	1	18	1	32	1	1	0	0	0	0	0	0	0	0	0	0	0	400[128];
1543	Luminary	LM3S3739 internal	0	0	1	18	0	32	1	1	0	0	0	0	0	0	0	0	0	0	0	400[128];
1544	Luminary	LM3S3748 internal	0	0	1	18	0	32	1	1	0	0	0	0	0	0	0	0	0	0	0	400[128];
1545	Luminary	LM3S3749 internal	0	0	1	18	0	32	1	1	0	0	0	0	0	0	0	0	0	0	0	400[128];
1546	Luminary	LM3S3826 internal	0	0	1	18	0	32	1	1	0	0	0	0	0	0	0	0	0	0	0	400[256];
1547	Luminary	LM3S3J26 internal	0	0	1	18	0	32	1	1	0	0	0	0	0	0	0	0	0	0	0	400[128];
1548	Luminary	LM3S3N26 internal	0	0	1	18	0	32	1	1	0	0	0	0	0	0	0	0	0	0	0	400[64];
1549	Luminary	LM3S3W26 internal	0	0	1	18	0	32	1	1	0	0	0	0	0	0	0	0	0	0	0	400[32];
1550	Luminary	LM3S3Z26 internal	0	0	1	18	0	32	1	1	0	0	0	0	0	0	0	0	0	0	0	400[16];
1551	Luminary	LM3S5632 internal	0	0	1	18	0	32	1	1	0	0	0	0	0	0	0	0	0	0	0	400[128];
1552	Luminary	LM3S5651 internal	0	0	1	18	1	32	1	1	0	0	0	0	0	0	0	0	0	0	0	400[128];
1553	Luminary	LM3S5652 internal	0	0	1	18	1	32	1	1	0	0	0	0	0	0	0	0	0	0	0	400[128];
1554	Luminary	LM3S5656 internal	0	0	1	18	1	32	1	1	0	0	0	0	0	0	0	0	0	0	0	400[128];
1555	Luminary	LM3S5662 internal	0	0	1	18	1	32	1	1	0	0	0	0	0	0	0	0	0	0	0	400[128];
1556	Luminary	LM3S5732 internal	0	0	1	18	1	32	1	1	0	0	0	0	0	0	0	0	0	0	0	400[128];
1557	Luminary	LM3S5737 internal	0	0	1	18	1	32	1	1	0	0	0	0	0	0	0	0	0	0	0	400[128];
1558	Luminary	LM3S5739 internal	0	0	1	18	1	32	1	1	0	0	0	0	0	0	0	0	0	0	0	400[128];
1559	Luminary	LM3S5747 internal	0	0	1	18	1	32	1	1	0	0	0	0	0	0	0	0	0	0	0	400[128];
1560	Luminary	LM3S5749 internal	0	0	1	18	1	32	1	1	0	0	0	0	0	0	0	0	0	0	0	400[128];
1561	Luminary	LM3S5752 internal	0	0	1	18	1	32	1	1	0	0	0	0	0	0	0	0	0	0	0	400[128];
1562	Luminary	LM3S5762 internal	0	0	1	18	1	32	1	1	0	0	0	0	0	0	0	0	0	0	0	400[128];
1563	Luminary	LM3S5791 internal	0	0	1	18	1	32	1	1	0	0	0	0	0	0	0	0	0	0	0	400[128];
1564	Luminary	LM3S5951 internal	0	0	1	18	1	32	1	1	0	0	0	0	0	0	0	0	0	0	0	400[256];
1565	Luminary	LM3S5956 internal	0	0	1	18	1	32	1	1	0	0	0	0	0	0	0	0	0	0	0	400[256];
1566	Luminary	LM3S5B91 internal	0	0	1	18	1	32	1	1	0	0	0	0	0	0	0	0	0	0	0	400[256];
1567	Luminary	LM3S5C31 internal	0	0	1	18	1	32	1	1	0	0	0	0	0	0	0	0	0	0	0	400[512];
1568	Luminary	LM3S5C36 internal	0	0	1	18	1	32	1	1	0	0	0	0	0	0	0	0	0	0	0	400[512];
1569	Luminary	LM3S5C51 internal	0	0	1	18	1	32	1	1	0	0	0	0	0	0	0	0	0	0	0	400[512];
1570	Luminary	LM3S5C56 internal	0	0	1	18	1	32	1	1	0	0	0	0	0	0	0	0	0	0	0	400[512];
1571	Luminary	LM3S5K31 internal	0	0	1	18	1	32	1	1	0	0	0	0	0	0	0	0	0	0	0	400[128];
1572	Luminary	LM3S5K36 internal	0	0	1	18	1	32	1	1	0	0	0	0	0	0	0	0	0	0	0	400[128];
1573	Luminary	LM3S5P31 internal	0	0	1	18	1	32	1	1	0	0	0	0	0	0	0	0	0	0	0	400[64];
1574	Luminary	LM3S5P36 internal	0	0	1	18	1	32	1	1	0	0	0	0	0	0	0	0	0	0	0	400[64];
1575	Luminary	LM3S5P3B internal	0	0	1	18	1	32	1	1	0	0	0	0	0	0	0	0	0	0	0	400[64];
1576	Luminary	LM3S5P51 internal	0	0	1	18	1	32	1	1	0	0	0	0	0	0	0	0	0	0	0	400[64];
1577	Luminary	LM3S5P56 internal	0	0	1	18	1	32	1	1	0	0	0	0	0	0	0	0	0	0	0	400[64];
1578	Luminary	LM3S5R31 internal	0	0	1	18	1	32	1	1	0	0	0	0	0	0	0	0	0	0	0	400[256];
1579	Luminary	LM3S5R36 internal	0	0	1	18	1	32	1	1	0	0	0	0	0	0	0	0	0	0	0	400[256];
1580	Luminary	LM3S5T36 internal	0	0	1	18	1	32	1	1	0	0	0	0	0	0	0	0	0	0	0	400[32];
1581	Luminary	LM3S5U91 internal	0	0	1	18	1	32	1	1	0	0	0	0	0	0	0	0	0	0	0	400[384];
1582	Luminary	LM3S5Y36 internal	0	0	1	18	1	32	1	1	0	0	0	0	0	0	0	0	0	0	0	400[16];
1583	Luminary	LM3S6100 internal	0	0	1	18	0	32	1	1	0	0	0	0	0	0	0	0	0	0	0	400[64];
1584	Luminary	LM3S6110 internal	0	0	1	18	0	32	1	1	0	0	0	0	0	0	0	0	0	0	0	400[64];
1585	Luminary	LM3S6420 internal	0	0	1	18	0	32	1	1	0	0	0	0	0	0	0	0	0	0	0	400[96];
1586	Luminary	LM3S6422 internal	0	0	1	18	0	32	1	1	0	0	0	0	0	0	0	0	0	0	0	400[96];
1587	Luminary	LM3S6432 internal	0	0	1	18	0	32	1	1	0	0	0	0	0	0	0	0	0	0	0	400[96];
1588	Luminary	LM3S6537 internal	0	0	1	18	0	32	1	1	0	0	0	0	0	0	0	0	0	0	0	400[96];
1589	Luminary	LM3S6610 internal	0	0	1	18	0	32	1	1	0	0	0	0	0	0	0	0	0	0	0	400[128];
1590	Luminary	LM3S6611 internal	0	0	1	18	0	32	1	1	0	0	0	0	0	0	0	0	0	0	0	400[128];
1591	Luminary	LM3S6618 internal	0	0	1	18	0	32	1	1	0	0	0	0	0	0	0	0	0	0	0	400[128];
1592	Luminary	LM3S6633 internal	0	0	1	18	0	32	1	1	0	0	0	0	0	0	0	0	0	0	0	400[128];
1593	Luminary	LM3S6637 internal	0	0	1	18	0	32	1	1	0	0	0	0	0	0	0	0	0	0	0	400[128];
1594	Luminary	LM3S6730 internal	0	0	1	18	0	32	1	1	0	0	0	0	0	0	0	0	0	0	0	400[128];
1595	Luminary	LM3S6753 internal	0	0	1	18	0	32	1	1	0	0	0	0	0	0	0	0	0	0	0	400[128];
1596	Luminary	LM3S6911 internal	0	0	1	18	0	32	1	1	0	0	0	0	0	0	0	0	0	0	0	400[256];
1597	Luminary	LM3S6916 internal	0	0	1	18	0	32	1	1	0	0	0	0	0	0	0	0	0	0	0	400[256];
1598	Luminary	LM3S6918 internal	0	0	1	18	0	32	1	1	0	0	0	0	0	0	0	0	0	0	0	400[256];
1599	Luminary	LM3S6938 internal	0	0	1	18	0	32	1	1	0	0	0	0	0	0	0	0	0	0	0	400[256];
1600	Luminary	LM3S6950 internal	0	0	1	18	0	32	1	1	0	0	0	0	0	0	0	0	0	0	0	400[256];
1601	Luminary	LM3S6952 internal	0	0	1	18	0	32	1	1	0	0	0	0	0	0	0	0	0	0	0	400[256];
1602	Luminary	LM3S6965 internal	0	0	1	18	0	32	1	1	0	0	0	0	0	0	0	0	0	0	0	400[256];
1603	Luminary	LM3S6C11 internal	0	0	1	18	1	32	1	1	0	0	0	0	0	0	0	0	0	0	0	400[512];
1604	Luminary	LM3S6C65 internal	0	0	1	18	1	32	1	1	0	0	0	0	0	0	0	0	0	0	0	400[512];
1605	Luminary	LM3S6G11 internal	0	0	1	18	1	32	1	1	0	0	0	0	0	0	0	0	0	0	0	400[384];
1606	Luminary	LM3S6G65 internal	0	0	1	18	1	32	1	1	0	0	0	0	0	0	0	0	0	0	0	400[384];
1607	Luminary	LM3S8530 internal	0	0	1	18	0	32	1	1	0	0	0	0	0	0	0	0	0	0	0	400[96];
1608	Luminary	LM3S8538 internal	0	0	1	18	0	32	1	1	0	0	0	0	0	0	0	0	0	0	0	400[96];
1609	Luminary	LM3S8630 internal	0	0	1	18	0	32	1	1	0	0	0	0	0	0	0	0	0	0	0	400[128];
1610	Luminary	LM3S8730 internal	0	0	1	18	0	32	1	1	0	0	0	0	0	0	0	0	0	0	0	400[128];
1611	Luminary	LM3S8733 internal	0	0	1	18	0	32	1	1	0	0	0	0	0	0	0	0	0	0	0	400[128];
1612	Luminary	LM3S8738 internal	0	0	1	18	0	32	1	1	0	0	0	0	0	0	0	0	0	0	0	400[128];
1613	Luminary	LM3S8930 internal	0	0	1	18	0	32	1	1	0	0	0	0	0	0	0	0	0	0	0	400[256];
1614	Luminary	LM3S8933 internal	0	0	1	18	0	32	1	1	0	0	0	0	0	0	0	0	0	0	0	400[256];
1615	Luminary	LM3S8938 internal	0	0	1	18	0	32	1	1	0	0	0	0	0	0	0	0	0	0	0	400[256];
1616	Luminary	LM3S8962 internal	0	0	1	18	0	32	1	1	0	0	0	0	0	0	0	0	0	0	0	400[256];
1617	Luminary	LM3S8970 internal	0	0	1	18	0	32	1	1	0	0	0	0	0	0	0	0	0	0	0	400[256];
1618	Luminary	LM3S8971 internal	0	0	1	18	0	32	1	1	0	0	0	0	0	0	0	0	0	0	0	400[256];
1619	Luminary	LM3S8C62 internal	0	0	1	18	1	32	1	1	0	0	0	0	0	0	0	0	0	0	0	400[512];
1620	Luminary	LM3S8G62 internal	0	0	1	18	1	32	1	1	0	0	0	0	0	0	0	0	0	0	0	400[384];
1621	Luminary	LM3S9781 internal	0	0	1	18	1	32	1	1	0	0	0	0	0	0	0	0	0	0	0	400[128];
1622	Luminary	LM3S9790 internal	0	0	1	18	1	32	1	1	0	0	0	0	0	0	0	0	0	0	0	400[128];
1623	Luminary	LM3S9792 internal	0	0	1	18	1	32	1	1	0	0	0	0	0	0	0	0	0	0	0	400[128];
1624	Luminary	LM3S9997 internal	0	0	1	18	1	32	1	1	0	0	0	0	0	0	0	0	0	0	0	400[256];
1625	Luminary	LM3S9971 internal	0	0	1	18	1	32	1	1	0	0	0	0	0	0	0	0	0	0	0	400[256];
1626	Luminary	LM3S9B81 internal	0	0	1	18	1	32	1	1	0	0	0	0	0	0	0	0	0	0	0	400[256];
1627	Luminary	LM3S9B90 internal	0	0	1	18	1	32	1	1	0	0	0	0	0	0	0	0	0	0	0	400[256];
1628	Luminary	LM3S9B92 internal	0	0	1	18	1	32	1	1	0	0	0	0	0	0	0	0	0	0	0	400[256];
1629	Luminary	LM3S9B95 internal	0	0	1	18	1	32	1	1	0	0	0	0	0	0	0	0	0	0	0	400[256];
1630	Luminary	LM3S9B96 internal	0	0	1	18	1	32	1	1	0	0	0	0	0	0	0	0	0	0	0	400[256];
1631	Luminary	LM3S9BN2 internal	0	0	1	18	1	32	1	1	0	0	0	0	0	0	0	0	0	0	0	400[256];
1632	Luminary	LM3S9BN5 internal	0	0	1	18	1	32	1	1	0	0	0	0	0	0	0	0	0	0	0	400[256];
1633	Luminary	LM3S9BN6 internal	0	0	1	18	1	32	1	1	0	0	0	0	0	0	0	0	0	0	0	400[256];
1634	Luminary	LM3S9C97 internal	0	0	1	18	1	32	1	1	0	0	0	0	0	0	0	0	0	0	0	400[512];
1635	Luminary	LM3S9CN5 internal	0	0	1	18	1	32	1	1	0	0	0	0	0	0	0	0	0	0	0	400[512];
1636	Luminary	LM3S9D81 internal	0	0	1	18	1	32	1	1	0	0	0	0	0	0	0	0	0	0	0	400[512];
1637	Luminary	LM3S9D90 internal	0	0	1	18	1	32	1	1	0	0	0	0	0	0	0	0	0	0	0	400[512];
1638	Luminary	LM3S9D92 internal	0	0	1	18	1	32	1	1	0	0	0	0	0	0	0	0	0	0	0	400[512];
1639	Luminary	LM3S9D95 internal	0	0	1	18	1	32	1	1	0	0	0	0	0	0	0	0	0	0	0	400[512];
1640	Luminary	LM3S9D96 internal	0	0	1	18	1	32	1	1	0	0	0	0	0	0	0	0	0	0	0	400[512];
1641	Luminary	LM3S9DN5 internal	0	0	1	18	1	32	1	1	0	0	0	0	0	0	0	0	0	0	0	400[512];
1642	Luminary	LM3S9DN6 internal	0	0	1	18	1	32	1	1	0	0	0	0	0	0	0	0	0	0	0	400[512];
1643	Luminary	LM3S9G97 internal	0	0	1	18	1	32	1	1	0	0	0	0	0	0	0	0	0	0	0	400[384];
1644	Luminary	LM3S9GN5 internal	0	0	1	18	1	32	1	1	0	0	0	0	0	0	0	0	0	0	0	400[384];
1645	Luminary	LM3S9L71 internal	0	0	1	18	1	32	1	1	0	0	0	0	0	0	0	0	0	0	0	400[128];
1646	Luminary	LM3S9L97 internal	0	0	1	18	1	32	1	1	0	0	0	0	0	0	0	0	0	0	0	400[128];
1647	Luminary	LM3S9U81 internal	0	0	1	18	1	32	1	1	0	0	0	0	0	0	0	0	0	0	0	400[384];
1648	Luminary	LM3S9U90 internal	0	0	1	18	1	32	1	1	0	0	0	0	0	0	0	0	0	0	0	400[384];
1649	Luminary	LM3S9U92 internal	0	0	1	18	1	32	1	1	0	0	0	0	0	0	0	0	0	0	0	400[384];
1650	Luminary	LM3S9U95 internal	0	0	1	18	1	32	1	1	0	0	0	0	0	0	0	0	0	0	0	400[384];
1651	Luminary	LM3S9U96 internal	0	0	1	18	1	32	1	1	0	0	0	0	0	0	0	0	0	0	0	400[384];
1652	Macronix	MX29LV040	C2004F	C2004F	0	1	0	8	1	0	0	0	0	0	0	0	0	0	0	0	0	10000[8];
1653	Macronix	MX29GL128EL	C2227E	C2007E	0	16	0	16	1	0	0	0	0	0	0	0	0	0	0	0	0	20000[128];
1654	Macronix	MX29GL128EH	C2227E	C2007E	0	16	0	16	1	0	0	0	0	0	0	0	0	0	0	0	0	20000[128];
1655	Macronix	MX29GL256EL	C2227E	C2007E	0	16	0	16	1	0	0	0	0	0	0	0	0	0	0	0	0	20000[256];
1656	Macronix	MX29GL256EH	C2227E	C2007E	0	16	0	16	1	0	0	0	0	0	0	0	0	0	0	0	0	20000[256];
1657	Macronix	MX29L1611	C200F8	C200F8	0	1	0	16	1	0	0	0	0	0	0	0	0	0	0	0	0	10000[32];
1658	Macronix	MX29LV128DB	C2227A	C2007A	0	1	0	16	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[8]; 10000[255];
1659	Macronix	MX29LV128DT	C2227E	C2007E	0	1	0	16	1	0	0	0	0	0	0	0	0	0	0	0	0	10000[255]; 2000[8];
1660	Macronix	MX29LV128E	C2227E	C2007E	0	1	0	16	1	0	0	0	0	0	0	0	0	0	0	0	0	20000[256];
1661	Macronix	MX29LV160CB	C22249	C20049	0	1	0	16	1	0	0	0	0	0	0	0	0	0	0	0	0	4000; 2000[2]; 8000; 10000[31];
1662	Macronix	MX29LV160CT	C222C4	C200C4	0	1	0	16	1	0	0	0	0	0	0	0	0	0	0	0	0	10000[31]; 8000; 2000[2]; 4000;
1663	Macronix	MX29LV160CB	C22249	C20049	0	1	0	16	1	0	0	0	0	0	0	0	0	0	0	0	0	4000; 2000[2]; 8000; 10000[31];
1664	Macronix	MX29LV160CT	C222C4	C200C4	0	1	0	16	1	0	0	0	0	0	0	0	0	0	0	0	0	10000[31]; 8000; 2000[2]; 4000;
1665	Macronix	MX29LV256E	C2227E	C2007E	0	1	0	16	1	0	0	0	0	0	0	0	0	0	0	0	0	20000[128];
1666	Macronix	MX29LV320AB	C222A8	C200A8	0	1	0	16	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[8]; 10000[63];
1667	Macronix	MX29LV320AT	C222A7	C200A7	0	1	0	16	1	0	0	0	0	0	0	0	0	0	0	0	0	10000[63]; 2000[8];
1668	Macronix	MX29LV320DB	C222A8	C200A8	0	1	0	16	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[8]; 10000[63];
1669	Macronix	MX29LV320DT	C222A7	C200A7	0	1	0	16	1	0	0	0	0	0	0	0	0	0	0	0	0	10000[63]; 2000[8];
1670	Macronix	MX29LV400CB	C222BA	C200BA	0	1	0	16	1	0	0	0	0	0	0	0	0	0	0	0	0	4000; 2000[2]; 8000; 10000[7];
1671	Macronix	MX29LV400CT	C222B9	C200B9	0	1	0	16	1	0	0	0	0	0	0	0	0	0	0	0	0	10000[7]; 8000; 2000[2]; 4000;
1672	Macronix	MX29LV640EB	C222CB	C200CB	0	1	0	16	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[8]; 10000[127];
1673	Macronix	MX29LV640ET	C222C9	C200C9	0	1	0	16	1	0	0	0	0	0	0	0	0	0	0	0	0	10000[127]; 2000[8];
1674	Macronix	MX29LV800CB	C2225B	C2005B	0	1	0	16	1	0	0	0	0	0	0	0	0	0	0	0	0	4000; 2000[2]; 8000; 10000[15];
1675	Macronix	MX29LV800CT	C222DA	C200DA	0	1	0	16	1	0	0	0	0	0	0	0	0	0	0	0	0	10000[15]; 8000; 2000[2]; 4000;
1676	Marvell	88MC200 internal	0	0	1	63	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	1000[256];
1677	Maxim	MAX32550 internal	0	0	1	78	0	32	1	1	0	0	0	0	0	0	0	0	0	0	0	1000[256];
1678	Maxim	MAX32555 internal	0	0	1	78	1	32	1	1	0	0	0	0	0	0	0	0	0	0	0	200[1024];
1679	Microsemi	M2S005 internal	0	0	1	69	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	80[1024];
1680	Microsemi	M2S010 internal	0	0	1	69	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	80[2048];
1681	Microsemi	M2S025 internal	0	0	1	69	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	80[2048];
1682	Microsemi	M2S050 internal	0	0	1	69	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	80[2048];
1683	Microsemi	M2S080 internal	0	0	1	69	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	80[4096];
1684	Microsemi	M2S120 internal	0	0	1	69	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	80[4096];
1685	Micronas	HVC4223F internal	0	0	1	96	0	32	1	1	0	0	0	0	0	0	0	0	0	0	0	800[16]; 80[4], 4FE00000;
1686	Nordic Semi	nRF51422_xxAA internal	0	0	1	48	0	32	1	1	0	0	0	0	0	0	0	0	0	0	0	400[256]; 400, 10001000;
1687	Nordic Semi	nRF51422_xxAB internal	0	0	1	48	0	32	1	1	0	0	0	0	0	0	0	0	0	0	0	400[128]; 400, 10001000;
1688	Nordic Semi	nRF51422_xxAC internal	0	0	1	48	0	32	1	1	0	0	0	0	0	0	0	0	0	0	0	400[256]; 400, 10001000;
1689	Nordic Semi	nRF51802_xxAA internal	0	0	1	48	0	32	1	1	0	0	0	0	0	0	0	0	0	0	0	400[256]; 400, 10001000;
1690	Nordic Semi	nRF51822_xxAA internal	0	0	1	48	0	32	1	1	0	0	0	0	0	0	0	0	0	0	0	400[256]; 400, 10001000;
1691	Nordic Semi	nRF51822_xxAB internal	0	0	1	48	0	32	1	1	0	0	0	0	0	0	0	0	0	0	0	400[128]; 400, 10001000;
1692	Nordic Semi	nRF51822_xxAC internal	0	0	1	48	0	32	1	1	0	0	0	0	0	0	0	0	0	0	0	400[256]; 400, 10001000;
1693	Nordic Semi	nRF52832_xxAA internal	0	0	1	48	0	32	1	1	0	0	0	0	0	0	0	0	0	0	0	1000[128]; 1000, 10001000;
1694	Numonyx	M29W128GH	20227E	20007E	0	16	0	16	1	0	0	0	0	0	0	0	0	0	0	0	0	20000[128];
1695	Numonyx	M29W128GL	20227E	20007E	0	16	0	16	1	0	0	0	0	0	0	0	0	0	0	0	0	20000[128];
1696	Numonyx	M29W256GH	20227E	20007E	0	16	0	16	1	0	0	0	0	0	0	0	0	0	0	0	0	20000[256];
1697	Numonyx	M29W256GL	20227E	20007E	0	16	0	16	1	0	0	0	0	0	0	0	0	0	0	0	0	20000[256];
1698	Numonyx	M29W320EB	202257	200057	0	1	0	16	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[8]; 10000[63];
1699	Numonyx	M29W320ET	202256	200056	0	1	0	16	1	0	0	0	0	0	0	0	0	0	0	0	0	10000[63]; 2000[8];
1700	Numonyx	M29W640GB	20227E	20007E	0	16	0	16	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[8];10000[127];
1701	Numonyx	M29W640GH	20227E	20007E	0	16	0	16	1	0	0	0	0	0	0	0	0	0	0	0	0	10000[128];
1702	Numonyx	M29W640GL	20227E	20007E	0	16	0	16	1	0	0	0	0	0	0	0	0	0	0	0	0	10000[128];
1703	Numonyx	M29W640GT	20227E	20007E	0	16	0	16	1	0	0	0	0	0	0	0	0	0	0	0	0	10000[127];2000[8];
1704	Nuvoton	NUC029LAN internal	0	0	1	59	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	200[128];
1705	Nuvoton	NUC029TAN internal	0	0	1	59	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	200[64];
1706	Nuvoton	NUC029FAE internal	0	0	1	59	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	200[32];
1707	Nuvoton	M0516xxx internal	0	0	1	59	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	200[128];
1708	Nuvoton	M052xxx internal	0	0	1	59	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	200[16];
1709	Nuvoton	M054xxx internal	0	0	1	59	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	200[32];
1710	Nuvoton	M058xxx internal	0	0	1	59	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	200[64];
1711	Nuvoton	MINI51xxN internal	0	0	1	59	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	200[8];
1712	Nuvoton	MINI52xxN internal	0	0	1	59	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	200[16];
1713	Nuvoton	MINI54xxN internal	0	0	1	59	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	200[32];
1714	Nuvoton	NANO1xxxA0xx internal	0	0	1	59	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	200[16];
1715	Nuvoton	NANO1xxxA1xx internal	0	0	1	59	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	200[16];
1716	Nuvoton	NANO1xxxA2xx internal	0	0	1	59	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	200[16];
1717	Nuvoton	NANO1xxxA3xx internal	0	0	1	59	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	200[16];
1718	Nuvoton	NANO1xxxB0xx internal	0	0	1	59	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	200[32];
1719	Nuvoton	NANO1xxxB1xx internal	0	0	1	59	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	200[32];
1720	Nuvoton	NANO1xxxB2xx internal	0	0	1	59	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	200[32];
1721	Nuvoton	NANO1xxxB3xx internal	0	0	1	59	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	200[32];
1722	Nuvoton	NANO1xxxC0xx internal	0	0	1	59	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	200[64];
1723	Nuvoton	NANO1xxxC1xx internal	0	0	1	59	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	200[64];
1724	Nuvoton	NANO1xxxC2xx internal	0	0	1	59	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	200[64];
1725	Nuvoton	NANO1xxxC3xx internal	0	0	1	59	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	200[64];
1726	Nuvoton	NANO1xxxD0xx internal	0	0	1	59	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	200[128];
1727	Nuvoton	NANO1xxxD1xx internal	0	0	1	59	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	200[128];
1728	Nuvoton	NANO1xxxD2xx internal	0	0	1	59	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	200[128];
1729	Nuvoton	NANO1xxxD3xx internal	0	0	1	59	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	200[128];
1730	Nuvoton	NANO1xxxE0xx internal	0	0	1	59	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	200[246];
1731	Nuvoton	NANO1xxxE1xx internal	0	0	1	59	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	200[246];
1732	Nuvoton	NANO1xxxE2xx internal	0	0	1	59	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	200[246];
1733	Nuvoton	NANO1xxxE3xx internal	0	0	1	59	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	200[246];
1734	Nuvoton	NUC100xC1 internal	0	0	1	59	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	200[64];
1735	Nuvoton	NUC100xC2 internal	0	0	1	59	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	200[64];
1736	Nuvoton	NUC100xC3 internal	0	0	1	59	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	200[64];
1737	Nuvoton	NUC100xD1 internal	0	0	1	59	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	200[128];
1738	Nuvoton	NUC100xD2 internal	0	0	1	59	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	200[128];
1739	Nuvoton	NUC100xD3 internal	0	0	1	59	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	200[128];
1740	Nuvoton	NUC100xE1 internal	0	0	1	59	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	200[256];
1741	Nuvoton	NUC100xE2 internal	0	0	1	59	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	200[256];
1742	Nuvoton	NUC100xE3 internal	0	0	1	59	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	200[256];
1743	Nuvoton	NUC120xA1 internal	0	0	1	59	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	200[16];
1744	Nuvoton	NUC120xA2 internal	0	0	1	59	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	200[16];
1745	Nuvoton	NUC120xA3 internal	0	0	1	59	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	200[16];
1746	Nuvoton	NUC120xB1 internal	0	0	1	59	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	200[32];
1747	Nuvoton	NUC120xB2 internal	0	0	1	59	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	200[32];
1748	Nuvoton	NUC120xB3 internal	0	0	1	59	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	200[32];
1749	Nuvoton	NUC120xC1 internal	0	0	1	59	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	200[64];
1750	Nuvoton	NUC120xC2 internal	0	0	1	59	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	200[64];
1751	Nuvoton	NUC120xC3 internal	0	0	1	59	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	200[64];
1752	Nuvoton	NUC120xD1 internal	0	0	1	59	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	200[128];
1753	Nuvoton	NUC120xD2 internal	0	0	1	59	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	200[128];
1754	Nuvoton	NUC120xD3 internal	0	0	1	59	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	200[128];
1755	Nuvoton	NUC120xE1 internal	0	0	1	59	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	200[256];
1756	Nuvoton	NUC120xE2 internal	0	0	1	59	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	200[256];
1757	Nuvoton	NUC120xE3 internal	0	0	1	59	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	200[256];
1758	Nuvoton	NUC122xC1 internal	0	0	1	59	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	200[64];
1759	Nuvoton	NUC122xC2 internal	0	0	1	59	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	200[64];
1760	Nuvoton	NUC122xD1 internal	0	0	1	59	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	200[128];
1761	Nuvoton	NUC122xD2 internal	0	0	1	59	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	200[128];
1762	Nuvoton	NUC123xA1 internal	0	0	1	59	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	200[16];
1763	Nuvoton	NUC123xA2 internal	0	0	1	59	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	200[16];
1764	Nuvoton	NUC123xA3 internal	0	0	1	59	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	200[16];
1765	Nuvoton	NUC123xA4 internal	0	0	1	59	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	200[16];
1766	Nuvoton	NUC123xB1 internal	0	0	1	59	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	200[32];
1767	Nuvoton	NUC123xB2 internal	0	0	1	59	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	200[32];
1768	Nuvoton	NUC123xB3 internal	0	0	1	59	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	200[32];
1769	Nuvoton	NUC123xB4 internal	0	0	1	59	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	200[32];
1770	Nuvoton	NUC123xC1 internal	0	0	1	59	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	200[64];
1771	Nuvoton	NUC123xC2 internal	0	0	1	59	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	200[64];
1772	Nuvoton	NUC123xC3 internal	0	0	1	59	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	200[64];
1773	Nuvoton	NUC123xC4 internal	0	0	1	59	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	200[64];
1774	Nuvoton	NUC123xD1 internal	0	0	1	59	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	200[128];
1775	Nuvoton	NUC123xD2 internal	0	0	1	59	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	200[128];
1776	Nuvoton	NUC123xD3 internal	0	0	1	59	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	200[128];
1777	Nuvoton	NUC123xD4 internal	0	0	1	59	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	200[128];
1778	Nuvoton	NUC123xE1 internal	0	0	1	59	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	200[256];
1779	Nuvoton	NUC123xE2 internal	0	0	1	59	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	200[256];
1780	Nuvoton	NUC123xE3 internal	0	0	1	59	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	200[256];
1781	Nuvoton	NUC123xE4 internal	0	0	1	59	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	200[256];
1782	Nuvoton	NUC130xA1 internal	0	0	1	59	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	200[16];
1783	Nuvoton	NUC130xA2 internal	0	0	1	59	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	200[16];
1784	Nuvoton	NUC130xA3 internal	0	0	1	59	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	200[16];
1785	Nuvoton	NUC130xB1 internal	0	0	1	59	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	200[32];
1786	Nuvoton	NUC130xB2 internal	0	0	1	59	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	200[32];
1787	Nuvoton	NUC130xB3 internal	0	0	1	59	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	200[32];
1788	Nuvoton	NUC130xC1 internal	0	0	1	59	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	200[64];
1789	Nuvoton	NUC130xC2 internal	0	0	1	59	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	200[64];
1790	Nuvoton	NUC130xC3 internal	0	0	1	59	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	200[64];
1791	Nuvoton	NUC130xD1 internal	0	0	1	59	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	200[128];
1792	Nuvoton	NUC130xD2 internal	0	0	1	59	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	200[128];
1793	Nuvoton	NUC130xD3 internal	0	0	1	59	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	200[128];
1794	Nuvoton	NUC130xE1 internal	0	0	1	59	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	200[256];
1795	Nuvoton	NUC130xE2 internal	0	0	1	59	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	200[256];
1796	Nuvoton	NUC130xE3 internal	0	0	1	59	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	200[256];
1797	Nuvoton	NUC131Lxxxx internal	0	0	1	59	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	200[72];
1798	Nuvoton	NUC131Sxxxx internal	0	0	1	59	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	200[136];
1799	Nuvoton	NUC140xC1 internal	0	0	1	59	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	200[64];
1800	Nuvoton	NUC140xD2 internal	0	0	1	59	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	200[128];
1801	Nuvoton	NUC140xE3 internal	0	0	1	59	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	200[256];
1802	Nuvoton	NUC200xC1 internal	0	0	1	59	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	200[64];
1803	Nuvoton	NUC200xC2 internal	0	0	1	59	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	200[64];
1804	Nuvoton	NUC200xC3 internal	0	0	1	59	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	200[64];
1805	Nuvoton	NUC200xD1 internal	0	0	1	59	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	200[128];
1806	Nuvoton	NUC200xD2 internal	0	0	1	59	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	200[128];
1807	Nuvoton	NUC200xD3 internal	0	0	1	59	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	200[128];
1808	Nuvoton	NUC200xE1 internal	0	0	1	59	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	200[256];
1809	Nuvoton	NUC200xE2 internal	0	0	1	59	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	200[256];
1810	Nuvoton	NUC200xE3 internal	0	0	1	59	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	200[256];
1811	Nuvoton	NUC220xC1 internal	0	0	1	59	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	200[64];
1812	Nuvoton	NUC220xC2 internal	0	0	1	59	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	200[64];
1813	Nuvoton	NUC220xC3 internal	0	0	1	59	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	200[64];
1814	Nuvoton	NUC220xD1 internal	0	0	1	59	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	200[128];
1815	Nuvoton	NUC220xD2 internal	0	0	1	59	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	200[128];
1816	Nuvoton	NUC220xD3 internal	0	0	1	59	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	200[128];
1817	Nuvoton	NUC220xE1 internal	0	0	1	59	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	200[256];
1818	Nuvoton	NUC220xE2 internal	0	0	1	59	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	200[256];
1819	Nuvoton	NUC220xE3 internal	0	0	1	59	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	200[256];
1820	NXP	LPC810M021 internal	0	0	1	24	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	400[4];
1821	NXP	LPC811M001 internal	0	0	1	24	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	400[8];
1822	NXP	LPC812M101 internal	0	0	1	24	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	400[16];
1823	NXP	LPC822M101 internal	0	0	1	24	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	400[16];
1824	NXP	LPC824M201 internal	0	0	1	24	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	400[32];
1825	NXP	LPC1102 internal	0	0	1	24	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	1000[4];
1826	NXP	LPC1110 internal	0	0	1	24	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	1000[1];
1827	NXP	LPC1111/002 internal	0	0	1	24	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	1000[2];
1828	NXP	LPC1111/101 internal	0	0	1	24	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	1000[2];
1829	NXP	LPC1111/102 internal	0	0	1	24	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	1000[2];
1830	NXP	LPC1111/103 internal	0	0	1	24	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	1000[2];
1831	NXP	LPC1111/201 internal	0	0	1	24	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	1000[2];
1832	NXP	LPC1111/202 internal	0	0	1	24	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	1000[2];
1833	NXP	LPC1111/203 internal	0	0	1	24	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	1000[2];
1834	NXP	LPC1112/101 internal	0	0	1	24	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	1000[4];
1835	NXP	LPC1112/102 internal	0	0	1	24	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	1000[4];
1836	NXP	LPC1112/103 internal	0	0	1	24	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	1000[4];
1837	NXP	LPC1112/201 internal	0	0	1	24	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	1000[4];
1838	NXP	LPC1112/202 internal	0	0	1	24	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	1000[4];
1839	NXP	LPC1112/203 internal	0	0	1	24	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	1000[4];
1840	NXP	LPC1113/201 internal	0	0	1	24	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	1000[6];
1841	NXP	LPC1113/202 internal	0	0	1	24	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	1000[6];
1842	NXP	LPC1113/203 internal	0	0	1	24	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	1000[6];
1843	NXP	LPC1113/301 internal	0	0	1	24	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	1000[6];
1844	NXP	LPC1113/302 internal	0	0	1	24	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	1000[6];
1845	NXP	LPC1113/303 internal	0	0	1	24	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	1000[6];
1846	NXP	LPC1114/102 internal	0	0	1	24	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	1000[8];
1847	NXP	LPC1114/201 internal	0	0	1	24	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	1000[8];
1848	NXP	LPC1114/202 internal	0	0	1	24	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	1000[8];
1849	NXP	LPC1114/203 internal	0	0	1	24	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	1000[8];
1850	NXP	LPC1114/301 internal	0	0	1	24	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	1000[8];
1851	NXP	LPC1114/302 internal	0	0	1	24	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	1000[8];
1852	NXP	LPC1114/303 internal	0	0	1	24	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	1000[8];
1853	NXP	LPC1114/323 internal	0	0	1	24	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	1000[12];
1854	NXP	LPC1114/333 internal	0	0	1	24	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	1000[14];
1855	NXP	LPC1115/303 internal	0	0	1	24	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	1000[16];
1856	NXP	LPC1101LVUK internal	0	0	1	24	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	1000[8];
1857	NXP	LPC1102LVUK internal	0	0	1	24	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	1000[8];
1858	NXP	LPC1112LV/003 internal	0	0	1	24	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	1000[4];
1859	NXP	LPC1112LV/103 internal	0	0	1	24	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	1000[4];
1860	NXP	LPC1114LV/103 internal	0	0	1	24	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	1000[8];
1861	NXP	LPC1114LV/303 internal	0	0	1	24	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	1000[8];
1862	NXP	LPC1124 internal	0	0	1	24	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	1000[8];
1863	NXP	LPC1125 internal	0	0	1	24	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	1000[16];
1864	NXP	LPC11A02UK internal	0	0	1	24	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	1000[4];
1865	NXP	LPC11A04UK internal	0	0	1	24	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	1000[8];
1866	NXP	LPC11A11 internal	0	0	1	24	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	1000[2];
1867	NXP	LPC11A12 internal	0	0	1	24	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	1000[4];
1868	NXP	LPC11A13 internal	0	0	1	24	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	1000[6];
1869	NXP	LPC11A14 internal	0	0	1	24	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	1000[8];
1870	NXP	LPC11C12/301 internal	0	0	1	24	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	1000[4];
1871	NXP	LPC11C14/301 internal	0	0	1	24	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	1000[8];
1872	NXP	LPC11C22/301 internal	0	0	1	24	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	1000[4];
1873	NXP	LPC11C24/301 internal	0	0	1	24	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	1000[8];
1874	NXP	LPC11D14/302 internal	0	0	1	24	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	1000[8];
1875	NXP	LPC11E11/101 internal	0	0	1	24	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	1000[2];
1876	NXP	LPC11E12/201 internal	0	0	1	24	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	1000[4];
1877	NXP	LPC11E13/301 internal	0	0	1	24	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	1000[6];
1878	NXP	LPC11E14/401 internal	0	0	1	24	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	1000[8];
1879	NXP	LPC11E36/501 internal	0	0	1	24	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	1000[24];
1880	NXP	LPC11E37/501 internal	0	0	1	24	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	1000[32];
1881	NXP	LPC11E66 internal	0	0	1	24	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	1000[16];
1882	NXP	LPC11E67 internal	0	0	1	24	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	1000[24]; 8000[1];
1883	NXP	LPC11E68 internal	0	0	1	24	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	1000[24]; 8000[5];
1884	NXP	LPC11U12 internal	0	0	1	24	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	1000[4];
1885	NXP	LPC11U13 internal	0	0	1	24	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	1000[6];
1886	NXP	LPC11U14 internal	0	0	1	24	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	1000[8];
1887	NXP	LPC11U23 internal	0	0	1	24	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	1000[6];
1888	NXP	LPC11U24/301 internal	0	0	1	24	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	1000[8];
1889	NXP	LPC11U24/401 internal	0	0	1	24	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	1000[8];
1890	NXP	LPC11U34/311 internal	0	0	1	24	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	1000[10];
1891	NXP	LPC11U34/421 internal	0	0	1	24	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	1000[12];
1892	NXP	LPC11U35/401 internal	0	0	1	24	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	1000[16];
1893	NXP	LPC11U35/501 internal	0	0	1	24	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	1000[16];
1894	NXP	LPC11U36/401 internal	0	0	1	24	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	1000[24];
1895	NXP	LPC11U37/401 internal	0	0	1	24	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	1000[32];
1896	NXP	LPC11U37/501 internal	0	0	1	24	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	1000[32];
1897	NXP	LPC11U67 internal	0	0	1	24	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	1000[24]; 8000[1];
1898	NXP	LPC11U68 internal	0	0	1	24	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	1000[24]; 8000[5];
1899	NXP	LPC1224/101 internal	0	0	1	24	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	1000[8];
1900	NXP	LPC1224/121 internal	0	0	1	24	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	1000[12];
1901	NXP	LPC1225/301 internal	0	0	1	24	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	1000[16];
1902	NXP	LPC1225/321 internal	0	0	1	24	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	1000[20];
1903	NXP	LPC1226/301 internal	0	0	1	24	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	1000[24];
1904	NXP	LPC1227/301 internal	0	0	1	24	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	1000[32];
1905	NXP	LPC1311 internal	0	0	1	24	2	32	1	0	0	0	0	0	0	0	0	0	0	0	0	1000[2];
1906	NXP	LPC1313 internal	0	0	1	24	2	32	1	0	0	0	0	0	0	0	0	0	0	0	0	1000[8];
1907	NXP	LPC1315 internal	0	0	1	24	2	32	1	0	0	0	0	0	0	0	0	0	0	0	0	1000[8];
1908	NXP	LPC1316 internal	0	0	1	24	2	32	1	0	0	0	0	0	0	0	0	0	0	0	0	1000[12];
1909	NXP	LPC1317 internal	0	0	1	24	2	32	1	0	0	0	0	0	0	0	0	0	0	0	0	1000[16];
1910	NXP	LPC1342 internal	0	0	1	24	2	32	1	0	0	0	0	0	0	0	0	0	0	0	0	1000[4];
1911	NXP	LPC1343 internal	0	0	1	24	2	32	1	0	0	0	0	0	0	0	0	0	0	0	0	1000[8];
1912	NXP	LPC1345 internal	0	0	1	24	2	32	1	0	0	0	0	0	0	0	0	0	0	0	0	1000[8];
1913	NXP	LPC1346 internal	0	0	1	24	2	32	1	0	0	0	0	0	0	0	0	0	0	0	0	1000[12];
1914	NXP	LPC1347 internal	0	0	1	24	2	32	1	0	0	0	0	0	0	0	0	0	0	0	0	1000[16];
1915	NXP	LPC1517 internal	0	0	1	24	3	32	1	0	0	0	0	0	0	0	0	0	0	0	0	1000[16];
1916	NXP	LPC1518 internal	0	0	1	24	3	32	1	0	0	0	0	0	0	0	0	0	0	0	0	1000[32];
1917	NXP	LPC1519 internal	0	0	1	24	3	32	1	0	0	0	0	0	0	0	0	0	0	0	0	1000[64];
1918	NXP	LPC1547 internal	0	0	1	24	3	32	1	0	0	0	0	0	0	0	0	0	0	0	0	1000[16];
1919	NXP	LPC1548 internal	0	0	1	24	3	32	1	0	0	0	0	0	0	0	0	0	0	0	0	1000[32];
1920	NXP	LPC1549 internal	0	0	1	24	3	32	1	0	0	0	0	0	0	0	0	0	0	0	0	1000[64];
1921	NXP	LPC1751 internal	0	0	1	24	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	1000[8];
1922	NXP	LPC1752 internal	0	0	1	24	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	1000[16];
1923	NXP	LPC1754 internal	0	0	1	24	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	1000[16]; 8000[2];
1924	NXP	LPC1756 internal	0	0	1	24	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	1000[16]; 8000[6];
1925	NXP	LPC1758 internal	0	0	1	24	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	1000[16]; 8000[14];
1926	NXP	LPC1759 internal	0	0	1	24	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	1000[16]; 8000[14];
1927	NXP	LPC1763 internal	0	0	1	24	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	1000[16]; 8000[6];
1928	NXP	LPC1764 internal	0	0	1	24	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	1000[16]; 8000[2];
1929	NXP	LPC1765 internal	0	0	1	24	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	1000[16]; 8000[6];
1930	NXP	LPC1766 internal	0	0	1	24	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	1000[16]; 8000[6];
1931	NXP	LPC1767 internal	0	0	1	24	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	1000[16]; 8000[14];
1932	NXP	LPC1768 internal	0	0	1	24	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	1000[16]; 8000[14];
1933	NXP	LPC1769 internal	0	0	1	24	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	1000[16]; 8000[14];
1934	NXP	LPC1772 internal	0	0	1	24	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	1000[16];
1935	NXP	LPC1774 internal	0	0	1	24	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	1000[16]; 8000[2];
1936	NXP	LPC1776 internal	0	0	1	24	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	1000[16]; 8000[6];
1937	NXP	LPC1777 internal	0	0	1	24	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	1000[16]; 8000[14];
1938	NXP	LPC1778 internal	0	0	1	24	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	1000[16]; 8000[14];
1939	NXP	LPC1785 internal	0	0	1	24	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	1000[16]; 8000[6];
1940	NXP	LPC1786 internal	0	0	1	24	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	1000[16]; 8000[6];
1941	NXP	LPC1787 internal	0	0	1	24	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	1000[16]; 8000[14];
1942	NXP	LPC1788 internal	0	0	1	24	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	1000[16]; 8000[14];
1943	NXP	LPC1810 SPIFI	0	0	1	56	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	20000[512];
1944	NXP	LPC1812 internal	0	0	1	49	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[8]; 10000[7];
1945	NXP	LPC1813 internal	0	0	1	49	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[8]; 10000[3]; 2000[8], 1000000; 10000[3];
1946	NXP	LPC1815 internal	0	0	1	49	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[8]; 10000[5]; 2000[8], 1000000; 10000[5];
1947	NXP	LPC1817 internal	0	0	1	49	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[8]; 10000[7]; 2000[8], 1000000; 10000[7];
1948	NXP	LPC1820 SPIFI	0	0	1	56	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	20000[512];
1949	NXP	LPC1822 internal	0	0	1	49	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[8]; 10000[7];
1950	NXP	LPC1823 internal	0	0	1	49	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[8]; 10000[3]; 2000[8], 1000000; 10000[3];
1951	NXP	LPC1825 internal	0	0	1	49	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[8]; 10000[5]; 2000[8], 1000000; 10000[5];
1952	NXP	LPC1827 internal	0	0	1	49	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[8]; 10000[7]; 2000[8], 1000000; 10000[7];
1953	NXP	LPC1830 SPIFI	0	0	1	56	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	20000[512];
1954	NXP	LPC1833 internal	0	0	1	49	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[8]; 10000[3]; 2000[8], 1000000; 10000[3];
1955	NXP	LPC1837 internal	0	0	1	49	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[8]; 10000[7]; 2000[8], 1000000; 10000[7];
1956	NXP	LPC1850 SPIFI	0	0	1	56	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	20000[512];
1957	NXP	LPC1853 internal	0	0	1	49	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[8]; 10000[3]; 2000[8], 1000000; 10000[3];
1958	NXP	LPC1857 internal	0	0	1	49	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[8]; 10000[7]; 2000[8], 1000000; 10000[7];
1959	NXP	LPC2101 internal	0	0	1	4	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	1000[2];
1960	NXP	LPC2102 internal	0	0	1	4	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	1000[4];
1961	NXP	LPC2103 internal	0	0	1	4	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	1000[8];
1962	NXP	LPC2104 internal	0	0	1	4	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[15];
1963	NXP	LPC2105 internal	0	0	1	4	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[15];
1964	NXP	LPC2106 internal	0	0	1	4	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[15];
1965	NXP	LPC2109 internal	0	0	1	4	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[8];
1966	NXP	LPC2114 internal	0	0	1	4	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[15];
1967	NXP	LPC2119 internal	0	0	1	4	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[15];
1968	NXP	LPC2124 internal	0	0	1	4	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[8]; 10000[2]; 2000[7];
1969	NXP	LPC2129 internal	0	0	1	4	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[8]; 10000[2]; 2000[7];
1970	NXP	LPC2131 internal	0	0	1	4	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	1000[8];
1971	NXP	LPC2132 internal	0	0	1	4	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	1000[8]; 8000[1];
1972	NXP	LPC2134 internal	0	0	1	4	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	1000[8]; 8000[3];
1973	NXP	LPC2136 internal	0	0	1	4	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	1000[8]; 8000[7];
1974	NXP	LPC2138 internal	0	0	1	4	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	1000[8]; 8000[14]; 1000[5];
1975	NXP	LPC2141 internal	0	0	1	4	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	1000[8];
1976	NXP	LPC2142 internal	0	0	1	4	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	1000[8]; 8000[1];
1977	NXP	LPC2144 internal	0	0	1	4	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	1000[8]; 8000[3];
1978	NXP	LPC2146 internal	0	0	1	4	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	1000[8]; 8000[7];
1979	NXP	LPC2148 internal	0	0	1	4	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	1000[8]; 8000[14]; 1000[5];
1980	NXP	LPC2157 internal	0	0	1	4	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	1000[8]; 8000[14]; 1000[5];
1981	NXP	LPC2158 internal	0	0	1	4	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	1000[8]; 8000[14]; 1000[5];
1982	NXP	LPC2194 internal	0	0	1	4	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[8]; 10000[2]; 2000[7];
1983	NXP	LPC2212 internal	0	0	1	4	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[15];
1984	NXP	LPC2214 internal	0	0	1	4	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[8]; 10000[2]; 2000[7];
1985	NXP	LPC2292 internal	0	0	1	4	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[8]; 10000[2]; 2000[7];
1986	NXP	LPC2294 internal	0	0	1	4	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[8]; 10000[2]; 2000[7];
1987	NXP	LPC2361 internal	0	0	1	4	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	1000[8]; 8000[1];
1988	NXP	LPC2362 internal	0	0	1	4	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	1000[8]; 8000[3];
1989	NXP	LPC2364 internal	0	0	1	4	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	1000[8]; 8000[3];
1990	NXP	LPC2365 internal	0	0	1	4	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	1000[8]; 8000[7];
1991	NXP	LPC2366 internal	0	0	1	4	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	1000[8]; 8000[7];
1992	NXP	LPC2367 internal	0	0	1	4	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	1000[8]; 8000[14]; 1000[6];
1993	NXP	LPC2368 internal	0	0	1	4	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	1000[8]; 8000[14]; 1000[6];
1994	NXP	LPC2377 internal	0	0	1	4	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	1000[8]; 8000[14]; 1000[6];
1995	NXP	LPC2378 internal	0	0	1	4	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	1000[8]; 8000[14]; 1000[6];
1996	NXP	LPC2387 internal	0	0	1	4	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	1000[8]; 8000[14]; 1000[6];
1997	NXP	LPC2388 internal	0	0	1	4	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	1000[8]; 8000[14]; 1000[6];
1998	NXP	LPC2458 internal	0	0	1	4	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	1000[8]; 8000[14]; 1000[6];
1999	NXP	LPC2468 internal	0	0	1	4	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	1000[8]; 8000[14]; 1000[6];
2000	NXP	LPC2478 internal	0	0	1	4	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	1000[8]; 8000[14]; 1000[6];
2001	NXP	LPC2880 internal	0	0	1	27	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	10000[15]; 2000[8];
2002	NXP	LPC2888 internal	0	0	1	27	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	10000[15]; 2000[8];
2003	NXP	LPC2917 internal	0	0	1	15	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[8]; 10000[7];
2004	NXP	LPC2919 internal	0	0	1	15	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[8]; 10000[11];
2005	NXP	LPC2921 internal	0	0	1	15	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[8]; 10000[1];
2006	NXP	LPC2923 internal	0	0	1	15	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[8]; 10000[3];
2007	NXP	LPC2925 internal	0	0	1	15	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[8]; 10000[7];
2008	NXP	LPC2926 internal	0	0	1	15	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[8]; 10000[3];
2009	NXP	LPC2927 internal	0	0	1	15	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[8]; 10000[7];
2010	NXP	LPC2929 internal	0	0	1	15	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[8]; 10000[11];
2011	NXP	LPC2939 internal	0	0	1	15	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[8]; 10000[11];
2012	NXP	LPC4072 internal	0	0	1	24	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	1000[16];
2013	NXP	LPC4074 internal	0	0	1	24	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	1000[16]; 8000[2];
2014	NXP	LPC4076 internal	0	0	1	24	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	1000[16]; 8000[6];
2015	NXP	LPC4078 internal	0	0	1	24	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	1000[16]; 8000[14];
2016	NXP	LPC4310_M4 SPIFI	0	0	1	56	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	20000[512];
2017	NXP	LPC4312_M4 internal	0	0	1	49	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[8]; 10000[7];
2018	NXP	LPC4313_M4 internal	0	0	1	49	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[8]; 10000[3]; 2000[8], 1000000; 10000[3];
2019	NXP	LPC4315_M4 internal	0	0	1	49	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[8]; 10000[5]; 2000[8], 1000000; 10000[5];
2020	NXP	LPC4317_M4 internal	0	0	1	49	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[8]; 10000[7]; 2000[8], 1000000; 10000[7];
2021	NXP	LPC4320_M4 SPIFI	0	0	1	56	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	20000[512];
2022	NXP	LPC4322_M4 internal	0	0	1	49	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[8]; 10000[7];
2023	NXP	LPC4323_M4 internal	0	0	1	49	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[8]; 10000[3]; 2000[8], 1000000; 10000[3];
2024	NXP	LPC4325_M4 internal	0	0	1	49	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[8]; 10000[5]; 2000[8], 1000000; 10000[5];
2025	NXP	LPC4327_M4 internal	0	0	1	49	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[8]; 10000[7]; 2000[8], 1000000; 10000[7];
2026	NXP	LPC4330_M4 SPIFI	0	0	1	56	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	20000[512];
2027	NXP	LPC4333_M4 internal	0	0	1	49	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[8]; 10000[3]; 2000[8], 1000000; 10000[3];
2028	NXP	LPC4337_M4 internal	0	0	1	49	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[8]; 10000[7]; 2000[8], 1000000; 10000[7];
2029	NXP	LPC4350_M4 SPIFI	0	0	1	56	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	20000[512];
2030	NXP	LPC4353_M4 internal	0	0	1	49	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[8]; 10000[3]; 2000[8], 1000000; 10000[3];
2031	NXP	LPC4357_M4 internal	0	0	1	49	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[8]; 10000[7]; 2000[8], 1000000; 10000[7];
2032	NXP	LPC4088 internal	0	0	1	24	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	1000[16]; 8000[14];
2033	NXP	LPC54101x256_M4 internal	0	0	1	24	4	32	1	0	0	0	0	0	0	0	0	0	0	0	0	8000[8];
2034	NXP	LPC54101x512_M4 internal	0	0	1	24	4	32	1	0	0	0	0	0	0	0	0	0	0	0	0	8000[16];
2035	NXP	LPC54102x256_M4 internal	0	0	1	24	4	32	1	0	0	0	0	0	0	0	0	0	0	0	0	8000[8];
2036	NXP	LPC54102x512_M4 internal	0	0	1	24	4	32	1	0	0	0	0	0	0	0	0	0	0	0	0	8000[16];
2037	NXP	LPC5411xx128_M4 internal	0	0	1	24	5	32	1	0	0	0	0	0	0	0	0	0	0	0	0	8000[4];
2038	NXP	LPC5411xx256_M4 internal	0	0	1	24	5	32	1	0	0	0	0	0	0	0	0	0	0	0	0	8000[8];
2039	NXP	PCF87750 internal	0	0	1	11	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	800[192];
2040	NXP	PN7360AU internal	0	0	1	99	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	40[56]; 80[640], 1E00;
2041	NXP	PN7462AU internal	0	0	1	99	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	40[56]; 80[1264], 1E00;
2042	NXP	SJA2010 internal	0	0	1	15	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	10000[11]; 2000[8];
2043	NXP	SJA2510 internal	0	0	1	15	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	10000[11]; 2000[8];
2044	OKI	ML67Q4002 internal	0	0	1	14	1	32	1	1	0	0	0	0	0	0	0	0	0	0	0	800[128];
2045	OKI	ML67Q4003 internal	0	0	1	14	1	32	1	1	0	0	0	0	0	0	0	0	0	0	0	800[256];
2046	OKI	ML67Q4050 internal	0	0	1	14	0	32	1	1	0	0	0	0	0	0	0	0	0	0	0	1000[16];
2047	OKI	ML67Q4051 internal	0	0	1	14	0	32	1	1	0	0	0	0	0	0	0	0	0	0	0	1000[32];
2048	OKI	ML67Q4060 internal	0	0	1	14	0	32	1	1	0	0	0	0	0	0	0	0	0	0	0	1000[16];
2049	OKI	ML67Q4061 internal	0	0	1	14	0	32	1	1	0	0	0	0	0	0	0	0	0	0	0	1000[32];
2050	OKI	ML67Q5250 internal	0	0	1	14	2	32	1	1	0	0	0	0	0	0	0	0	0	0	0	1000[32];
2051	ON Semi	Q32M210 internal	0	0	1	44	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	800[128];
2052	Realtek	RTL8762 internal	0	0	1	93	0	32	1	1	0	0	0	0	0	0	0	0	0	0	0	800[128];
2053	Renesas	R-IN32M3 internal	0	0	1	66	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	10000[512];
2054	Renesas	R5F51101 internal	0	0	1	61	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	400[32];
2055	Renesas	R5F51103 internal	0	0	1	61	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	400[64];
2056	Renesas	R5F51104 internal	0	0	1	61	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	400[96];
2057	Renesas	R5F51105 internal	0	0	1	61	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	400[128];
2058	Renesas	R5F5110J internal	0	0	1	61	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	400[16];
2059	Renesas	R5F5110H internal	0	0	1	61	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	400[8];
2060	Renesas	R5F51111 internal	0	0	1	61	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	400[8]; 400[32], FFEF8000;
2061	Renesas	R5F51113 internal	0	0	1	61	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	400[8]; 400[64], FFEF0000;
2062	Renesas	R5F51114 internal	0	0	1	61	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	400[8]; 400[96], FFEE8000;
2063	Renesas	R5F51115 internal	0	0	1	61	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	400[8]; 400[128], FFEE0000;
2064	Renesas	R5F51116 internal	0	0	1	61	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	400[8]; 400[256], FFEC0000;
2065	Renesas	R5F51117 internal	0	0	1	61	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	400[8]; 400[384], FFEA0000;
2066	Renesas	R5F51118 internal	0	0	1	61	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	400[8]; 400[512], FFE80000;
2067	Renesas	R5F5111J internal	0	0	1	61	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	400[8]; 400[16], FFEFC000;
2068	Renesas	R5F51135 internal	0	0	1	61	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	400[8]; 400[128], FFEE0000;
2069	Renesas	R5F51136 internal	0	0	1	61	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	400[8]; 400[256], FFEC0000;
2070	Renesas	R5F51137 internal	0	0	1	61	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	400[8]; 400[384], FFEA0000;
2071	Renesas	R5F51138 internal	0	0	1	61	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	400[8]; 400[512], FFE80000;
2072	Renesas	R5F52103 internal	0	0	1	31	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	100[32]; 800[32], FFEF0000;
2073	Renesas	R5F52104 internal	0	0	1	31	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	100[32]; 800[48], FFEE8000;
2074	Renesas	R5F52105 internal	0	0	1	31	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	100[32]; 800[64], FFEE0000;
2075	Renesas	R5F52106 internal	0	0	1	31	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	100[32]; 800[128], FFEC0000;
2076	Renesas	R5F52107 internal	0	0	1	31	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	100[32]; 800[192], FFEA0000;
2077	Renesas	R5F52108 internal	0	0	1	31	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	100[32]; 800[256], FFE80000;
2078	Renesas	R5F5210A internal	0	0	1	31	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	100[32]; 800[384], FFE40000;
2079	Renesas	R5F5210B internal	0	0	1	31	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	100[32]; 800[512], FFE00000;
2080	Renesas	R5F52201 internal	0	0	1	31	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	100[32]; 800[16], FFEF8000;
2081	Renesas	R5F52203 internal	0	0	1	31	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	100[32]; 800[32], FFEF0000;
2082	Renesas	R5F52205 internal	0	0	1	31	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	100[32]; 800[64], FFEE0000;
2083	Renesas	R5F52206 internal	0	0	1	31	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	100[32]; 800[128], FFEC0000;
2084	Renesas	R5F52305 internal	0	0	1	61	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	400[8]; 800[64], FFEE0000;
2085	Renesas	R5F52306 internal	0	0	1	61	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	400[8]; 800[128], FFEC0000;
2086	Renesas	R5F52315 internal	0	0	1	61	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	400[8]; 800[64], FFEE0000;
2087	Renesas	R5F52316 internal	0	0	1	61	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	400[8]; 800[128], FFEC0000;
2088	Renesas	R5F52317 internal	0	0	1	61	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	400[8]; 800[192], FFEA0000;
2089	Renesas	R5F52318 internal	0	0	1	61	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	400[8]; 800[256], FFE80000;
2090	Renesas	R5F523T3 internal	0	0	1	61	2	32	1	0	0	0	0	0	0	0	0	0	0	0	0	800[32];
2091	Renesas	R5F523T5 internal	0	0	1	61	2	32	1	0	0	0	0	0	0	0	0	0	0	0	0	800[64];
2092	Renesas	R5F56104 internal	0	0	1	31	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	20000[1]; 10000[9]; 2000[8];
2093	Renesas	R5F56104 internal allow DataFlash	0	0	1	31	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[4]; 20000[1], FFE40000; 10000[9]; 2000[8];
2094	Renesas	R5F56106 internal	0	0	1	31	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	20000[3]; 10000[9]; 2000[8];
2095	Renesas	R5F56106 internal allow DataFlash	0	0	1	31	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[4]; 20000[3], FFE00000; 10000[9]; 2000[8];
2096	Renesas	R5F56107 internal	0	0	1	31	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	20000[7]; 10000[9]; 2000[8];
2097	Renesas	R5F56107 internal allow DataFlash	0	0	1	31	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[4]; 20000[7], FFD80000; 10000[9]; 2000[8];
2098	Renesas	R5F56108 internal	0	0	1	31	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	20000[11]; 10000[9]; 2000[8];
2099	Renesas	R5F56108 internal allow DataFlash	0	0	1	31	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[4]; 20000[11], FFD00000; 10000[9]; 2000[8];
2100	Renesas	R5F562x6 internal	0	0	1	31	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	4000[14]; 1000[8];
2101	Renesas	R5F562x6 internal allow DataFlash	0	0	1	31	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	800[16]; 4000[14], FFEC0000; 1000[8];
2102	Renesas	R5F562x7 internal	0	0	1	31	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	4000[22]; 1000[8];
2103	Renesas	R5F562x7 internal allow DataFlash	0	0	1	31	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	800[16]; 4000[22], FFEA0000; 1000[8];
2104	Renesas	R5F562x8 internal	0	0	1	31	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	4000[30]; 1000[8];
2105	Renesas	R5F562x8 internal allow DataFlash	0	0	1	31	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	800[16]; 4000[30], FFE80000; 1000[8];
2106	Renesas	R5F562G7 internal	0	0	1	31	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	4000[6]; 1000[8];
2107	Renesas	R5F562G7 internal allow DataFlash	0	0	1	31	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	800[4]; 4000[6], FFEE0000; 1000[8];
2108	Renesas	R5F562GA internal	0	0	1	31	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	4000[14]; 1000[8];
2109	Renesas	R5F562GA internal allow DataFlash	0	0	1	31	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	800[16]; 4000[14], FFEC0000; 1000[8];
2110	Renesas	R5F562T6 internal	0	0	1	31	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	4000[2]; 1000[8];
2111	Renesas	R5F562T6 internal allow DataFlash	0	0	1	31	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	800[4]; 4000[2], FFEF0000; 1000[8];
2112	Renesas	R5F562T7 internal	0	0	1	31	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	4000[6]; 1000[8];
2113	Renesas	R5F562T7 internal allow DataFlash	0	0	1	31	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	800[4]; 4000[6], FFEE0000; 1000[8];
2114	Renesas	R5F562TA internal	0	0	1	31	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	4000[14]; 1000[8];
2115	Renesas	R5F562TA internal allow DataFlash	0	0	1	31	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	800[16]; 4000[14], FFEC0000; 1000[8];
2116	Renesas	R5F56316 internal	0	0	1	31	2	32	1	0	0	0	0	0	0	0	0	0	0	0	0	4000[14]; 1000[8];
2117	Renesas	R5F56316 internal allow DataFlash	0	0	1	31	2	32	1	0	0	0	0	0	0	0	0	0	0	0	0	100[128]; 4000[14], FFEC0000; 1000[8];
2118	Renesas	R5F563T4 internal	0	0	1	31	3	32	1	0	0	0	0	0	0	0	0	0	0	0	0	1000[8];
2119	Renesas	R5F563T4 internal allow DataFlash	0	0	1	31	3	32	1	0	0	0	0	0	0	0	0	0	0	0	0	100[32]; 1000[8], FFEF8000;
2120	Renesas	R5F563T5 internal	0	0	1	31	3	32	1	0	0	0	0	0	0	0	0	0	0	0	0	4000[1]; 1000[8];
2121	Renesas	R5F563T5 internal allow DataFlash	0	0	1	31	3	32	1	0	0	0	0	0	0	0	0	0	0	0	0	100[32]; 4000[1], FFEF4000; 1000[8];
2122	Renesas	R5F563T6 internal	0	0	1	31	3	32	1	0	0	0	0	0	0	0	0	0	0	0	0	4000[2]; 1000[8];
2123	Renesas	R5F563T6 internal allow DataFlash	0	0	1	31	3	32	1	0	0	0	0	0	0	0	0	0	0	0	0	100[32]; 4000[2], FFEF0000; 1000[8];
2124	Renesas	R5F563TB internal	0	0	1	31	3	32	1	0	0	0	0	0	0	0	0	0	0	0	0	4000[14]; 1000[8];
2125	Renesas	R5F563TB internal allow DataFlash	0	0	1	31	3	32	1	0	0	0	0	0	0	0	0	0	0	0	0	100[32]; 4000[14], FFEC0000; 1000[8];
2126	Renesas	R5F563TC internal	0	0	1	31	3	32	1	0	0	0	0	0	0	0	0	0	0	0	0	4000[22]; 1000[8];
2127	Renesas	R5F563TC internal allow DataFlash	0	0	1	31	3	32	1	0	0	0	0	0	0	0	0	0	0	0	0	100[32]; 4000[22], FFEA0000; 1000[8];
2128	Renesas	R5F563TE internal	0	0	1	31	3	32	1	0	0	0	0	0	0	0	0	0	0	0	0	4000[30]; 1000[8];
2129	Renesas	R5F563TE internal allow DataFlash	0	0	1	31	3	32	1	0	0	0	0	0	0	0	0	0	0	0	0	100[32]; 4000[30], FFE80000; 1000[8];
2130	Renesas	R5F563x7 internal	0	0	1	31	2	32	1	0	0	0	0	0	0	0	0	0	0	0	0	4000[22]; 1000[8];
2131	Renesas	R5F563x7 internal allow DataFlash	0	0	1	31	2	32	1	0	0	0	0	0	0	0	0	0	0	0	0	100[128]; 4000[22], FFEA0000; 1000[8];
2132	Renesas	R5F563x8 internal	0	0	1	31	2	32	1	0	0	0	0	0	0	0	0	0	0	0	0	4000[30]; 1000[8];
2133	Renesas	R5F563x8 internal allow DataFlash	0	0	1	31	2	32	1	0	0	0	0	0	0	0	0	0	0	0	0	100[128]; 4000[30], FFE80000; 1000[8];
2134	Renesas	R5F563xA internal	0	0	1	31	2	32	1	0	0	0	0	0	0	0	0	0	0	0	0	8000[8]; 4000[30]; 1000[8];
2135	Renesas	R5F563xA internal allow DataFlash	0	0	1	31	2	32	1	0	0	0	0	0	0	0	0	0	0	0	0	100[128]; 8000[8], FFE40000; 4000[30]; 1000[8];
2136	Renesas	R5F563xB internal	0	0	1	31	2	32	1	0	0	0	0	0	0	0	0	0	0	0	0	8000[16]; 4000[30]; 1000[8];
2137	Renesas	R5F563xB internal allow DataFlash	0	0	1	31	2	32	1	0	0	0	0	0	0	0	0	0	0	0	0	100[128]; 8000[16], FFE00000; 4000[30]; 1000[8];
2138	Renesas	R5F563xD internal	0	0	1	31	2	32	1	0	0	0	0	0	0	0	0	0	0	0	0	10000[8]; 8000[16]; 4000[30]; 1000[8];
2139	Renesas	R5F563xD internal allow DataFlash	0	0	1	31	2	32	1	0	0	0	0	0	0	0	0	0	0	0	0	100[128]; 10000[8], FFD80000; 8000[16]; 4000[30]; 1000[8];
2140	Renesas	R5F563xE internal	0	0	1	31	2	32	1	0	0	0	0	0	0	0	0	0	0	0	0	10000[16]; 8000[16]; 4000[30]; 1000[8];
2141	Renesas	R5F563xE internal allow DataFlash	0	0	1	31	2	32	1	0	0	0	0	0	0	0	0	0	0	0	0	100[128]; 10000[16], FFD00000; 8000[16]; 4000[30]; 1000[8];
2142	Renesas	R5F563xF internal	0	0	1	31	2	32	1	0	0	0	0	0	0	0	0	0	0	0	0	10000[16]; 8000[16]; 4000[30]; 1000[8];
2143	Renesas	R5F563xF internal allow DataFlash	0	0	1	31	2	32	1	0	0	0	0	0	0	0	0	0	0	0	0	100[128]; 10000[16], FFD00000; 8000[16]; 4000[30]; 1000[8];
2144	Renesas	R5F563xG internal	0	0	1	31	2	32	1	0	0	0	0	0	0	0	0	0	0	0	0	10000[8]; 8000[16]; 4000[30]; 1000[8];
2145	Renesas	R5F563xG internal allow DataFlash	0	0	1	31	2	32	1	0	0	0	0	0	0	0	0	0	0	0	0	100[128]; 10000[8], FFD80000; 8000[16]; 4000[30]; 1000[8];
2146	Renesas	R5F563xJ internal	0	0	1	31	2	32	1	0	0	0	0	0	0	0	0	0	0	0	0	10000[8]; 8000[16]; 4000[30]; 1000[8];
2147	Renesas	R5F563xJ internal allow DataFlash	0	0	1	31	2	32	1	0	0	0	0	0	0	0	0	0	0	0	0	100[128]; 10000[8], FFD80000; 8000[16]; 4000[30]; 1000[8];
2148	Renesas	R5F563xK internal	0	0	1	31	2	32	1	0	0	0	0	0	0	0	0	0	0	0	0	10000[16]; 8000[16]; 4000[30]; 1000[8];
2149	Renesas	R5F563xK internal allow DataFlash	0	0	1	31	2	32	1	0	0	0	0	0	0	0	0	0	0	0	0	100[128]; 10000[16], FFD00000; 8000[16]; 4000[30]; 1000[8];
2150	Renesas	R5F563xM internal	0	0	1	31	2	32	1	0	0	0	0	0	0	0	0	0	0	0	0	4000[14]; 1000[8];
2151	Renesas	R5F563xM internal allow DataFlash	0	0	1	31	2	32	1	0	0	0	0	0	0	0	0	0	0	0	0	100[128]; 4000[14], FFEC0000; 1000[8];
2152	Renesas	R5F563xN internal	0	0	1	31	2	32	1	0	0	0	0	0	0	0	0	0	0	0	0	4000[22]; 1000[8];
2153	Renesas	R5F563xN internal allow DataFlash	0	0	1	31	2	32	1	0	0	0	0	0	0	0	0	0	0	0	0	100[128]; 4000[22], FFEA0000; 1000[8];
2154	Renesas	R5F563xP internal	0	0	1	31	2	32	1	0	0	0	0	0	0	0	0	0	0	0	0	4000[30]; 1000[8];
2155	Renesas	R5F563xP internal allow DataFlash	0	0	1	31	2	32	1	0	0	0	0	0	0	0	0	0	0	0	0	100[128]; 4000[30], FFE80000; 1000[8];
2156	Renesas	R5F563xW internal	0	0	1	31	2	32	1	0	0	0	0	0	0	0	0	0	0	0	0	8000[16]; 4000[30]; 1000[8];
2157	Renesas	R5F563xW internal allow DataFlash	0	0	1	31	2	32	1	0	0	0	0	0	0	0	0	0	0	0	0	100[128]; 8000[16], FFE00000; 4000[30]; 1000[8];
2158	Renesas	R5F563xY internal	0	0	1	31	2	32	1	0	0	0	0	0	0	0	0	0	0	0	0	8000[16]; 4000[30]; 1000[8];
2159	Renesas	R5F563xY internal allow DataFlash	0	0	1	31	2	32	1	0	0	0	0	0	0	0	0	0	0	0	0	100[128]; 8000[16], FFE00000; 4000[30]; 1000[8];
2160	Renesas	R5F564MF internal	0	0	1	81	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	100[256]; 8000[62], FFD00000; 2000[8];
2161	Renesas	R5F564MG internal	0	0	1	81	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	100[256]; 8000[78], FFC80000; 2000[8];
2162	Renesas	R5F564MJ internal	0	0	1	81	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	100[256]; 8000[94], FFC00000; 2000[8];
2163	Renesas	R5F564ML internal	0	0	1	81	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	100[256]; 8000[126], FFB00000; 2000[8];
2164	Renesas	R5F571MF internal	0	0	1	81	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	100[256]; 8000[62], FFD00000; 2000[8];
2165	Renesas	R5F571MG internal	0	0	1	81	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	100[256]; 8000[78], FFC80000; 2000[8];
2166	Renesas	R5F571MJ internal	0	0	1	81	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	100[256]; 8000[94], FFC00000; 2000[8];
2167	Renesas	R5F571ML internal	0	0	1	81	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	100[256]; 8000[126], FFB00000; 2000[8];
2168	Renesas	R7FS7G2 internal	0	0	1	80	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[8]; 8000[126]; 100[256], 40100000;
2169	Renesas	R7FS3A7 internal	0	0	1	80	2	32	1	0	0	0	0	0	0	0	0	0	0	0	0	800[512]; 30[1], 1010008; 400[16], 40100000;
2170	Renesas	R7FS12476 internal	0	0	1	80	3	32	1	0	0	0	0	0	0	0	0	0	0	0	0	400[64]; 30[1], 1010008; 400[4], 40100000;
2171	Renesas	R7FS12477 internal	0	0	1	80	3	32	1	0	0	0	0	0	0	0	0	0	0	0	0	400[128]; 30[1], 1010008; 400[4], 40100000;
2172	Renesas	R7S721000 internal	0	0	1	70	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	40000[256];
2173	Renesas	R7S721000_DualSPI internal	0	0	1	70	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	80000[128];
2174	Renesas	R7S721001 internal	0	0	1	70	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	40000[256];
2175	Renesas	R7S721001_DualSPI internal	0	0	1	70	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	80000[128];
2176	Renesas	R7S721020 internal	0	0	1	70	4	32	1	0	0	0	0	0	0	0	0	0	0	0	0	40000[256];
2177	Renesas	R7S721020_DualSPI internal	0	0	1	70	5	32	1	0	0	0	0	0	0	0	0	0	0	0	0	80000[128];
2178	Renesas	R7S721021 internal	0	0	1	70	4	32	1	0	0	0	0	0	0	0	0	0	0	0	0	40000[256];
2179	Renesas	R7S721021_DualSPI internal	0	0	1	70	5	32	1	0	0	0	0	0	0	0	0	0	0	0	0	80000[128];
2180	Renesas	R7S910xxx internal	0	0	1	70	2	32	1	0	0	0	0	0	0	0	0	0	0	0	0	10000[1024];
2181	Samsung	S3F441FX internal	0	0	1	7	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	200[512];
2182	Samsung	S3F445HX internal	0	0	1	7	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	200[1024];
2183	Samsung	S3FN21B internal	0	0	1	41	0	32	1	1	0	0	0	0	0	0	0	0	0	0	0	4000[4];
2184	Samsung	S3FN21B internal allow JTAG protect	0	0	1	41	1	32	1	1	0	0	0	0	0	0	0	0	0	0	0	4000[4];
2185	Samsung	S3FN21C internal	0	0	1	41	0	32	1	1	0	0	0	0	0	0	0	0	0	0	0	4000[6];
2186	Samsung	S3FN21C internal allow JTAG protect	0	0	1	41	1	32	1	1	0	0	0	0	0	0	0	0	0	0	0	4000[6];
2187	Samsung	S3FN21D internal	0	0	1	41	0	32	1	1	0	0	0	0	0	0	0	0	0	0	0	4000[8];
2188	Samsung	S3FN21D internal allow JTAG protect	0	0	1	41	1	32	1	1	0	0	0	0	0	0	0	0	0	0	0	4000[8];
2189	Samsung	S3FN41F internal	0	0	1	41	0	32	1	1	0	0	0	0	0	0	0	0	0	0	0	4000[16];
2190	Samsung	S3FN41F internal allow JTAG protect	0	0	1	41	1	32	1	1	0	0	0	0	0	0	0	0	0	0	0	4000[16];
2191	Samsung	S3FN60D internal	0	0	1	39	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[16];
2192	Samsung	K8P6415UQB	EC257E	EC007E	0	1	0	16	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[8];10000[126];2000[8];
2193	Sharp	LH28F128BFHED (Bank0)	B000B0	B000B0	0	10	0	16	1	0	0	1	0	0	0	0	0	0	1	0	0	10000[127]; 2000[8];
2194	Sharp	LH28F128BFHED (Bank1)	B000B1	B000B1	0	10	0	16	1	0	0	1	0	0	0	0	0	0	1	0	0	2000[8]; 10000[127];
2195	Sharp	LH28F128BFHT	B00011	B00011	0	10	0	16	1	0	0	1	0	0	0	0	0	0	1	0	0	2000[8]; 10000[255];
2196	Sharp	LH28F128SPHTD	B00018	B00018	0	10	0	16	1	0	0	1	0	0	0	0	0	0	1	0	0	20000[128];
2197	Sharp	LH28F640BFHE-PBTL	B000B1	B000B1	0	10	0	16	1	0	0	1	0	0	0	0	0	0	1	0	0	2000[8]; 10000[127];
2198	Sharp	LH28F640BFHE-PTTL	B000B0	B000B0	0	10	0	16	1	0	0	1	0	0	0	0	0	0	1	0	0	10000[127]; 2000[8];
2199	Sharp	LH28F640BFHG-PBTL	B000B1	B000B1	0	10	0	16	1	0	0	1	0	0	0	0	0	0	1	0	0	2000[8]; 10000[127];
2200	Sharp	LH28F640BFHG-PTTL	B000B0	B000B0	0	10	0	16	1	0	0	1	0	0	0	0	0	0	1	0	0	10000[127]; 2000[8];
2201	Sharp	LH28F800BJHE-PBTL	B000ED	B000ED	0	10	0	16	1	0	0	1	0	0	0	0	0	0	1	0	0	2000[8]; 10000[15];
2202	Sharp	LH28F800BJE-PTTL	B000EC	B000EC	0	2	0	16	1	0	0	1	0	0	0	0	0	0	1	0	0	10000[15]; 2000[8];
2203	Sharp	LHF00L29	B000A5	B000A5	0	2	0	16	1	0	0	1	0	0	0	0	0	0	1	0	0	2000[8]; 10000[1]; 20000[15];
2204	Silicon Labs	EFM32HGxxxF32 internal	0	0	1	28	0	32	1	0	0	0	0	0	0	0	0	0	0	1	1	400[32]; 400[1], FE00000; 400[1], FE04000;
2205	Silicon Labs	EFM32HGxxxF64 internal	0	0	1	28	0	32	1	0	0	0	0	0	0	0	0	0	0	1	1	400[64]; 400[1], FE00000; 400[1], FE04000;
2206	Silicon Labs	EM351 internal	0	0	1	29	0	32	1	1	0	0	0	0	0	0	0	0	0	0	0	800[64];
2207	Silicon Labs	EM351 (allow CIB) internal	0	0	1	29	1	32	1	1	0	0	0	0	0	0	0	0	0	0	0	800[64]; 800[1], 40800;
2208	Silicon Labs	EM357 internal	0	0	1	29	0	32	1	1	0	0	0	0	0	0	0	0	0	0	0	800[96];
2209	Silicon Labs	EM357 (allow CIB) internal	0	0	1	29	1	32	1	1	0	0	0	0	0	0	0	0	0	0	0	800[96]; 800[1], 40800;
2210	Silicon Labs	EFM32PG1BxxxF128 internal	0	0	1	28	1	32	1	0	0	0	0	0	0	0	0	0	0	1	1	800[64]; 800[1], FE00000; 800[1], FE04000;
2211	Silicon Labs	EFM32PG1BxxxF256 internal	0	0	1	28	1	32	1	0	0	0	0	0	0	0	0	0	0	1	1	800[128]; 800[1], FE00000; 800[1], FE04000;
2212	Silicon Labs	EFM32JG1BxxxF128 internal	0	0	1	28	1	32	1	0	0	0	0	0	0	0	0	0	0	1	1	800[64]; 800[1], FE00000; 800[1], FE04000;
2213	Silicon Labs	EFM32JG1BxxxF256 internal	0	0	1	28	1	32	1	0	0	0	0	0	0	0	0	0	0	1	1	800[128]; 800[1], FE00000; 800[1], FE04000;
2214	Silicon Labs	EFR32BG1xxxxF128 internal	0	0	1	28	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	800[64]; 800[1], FE00000; 800[1], FE04000;
2215	Silicon Labs	EFR32BG1xxxxF256 internal	0	0	1	28	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	800[128]; 800[1], FE00000; 800[1], FE04000;
2216	Silicon Labs	EFR32FG1xxxxF128 internal	0	0	1	28	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	800[64]; 800[1], FE00000; 800[1], FE04000;
2217	Silicon Labs	EFR32FG1xxxxF256 internal	0	0	1	28	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	800[128]; 800[1], FE00000; 800[1], FE04000;
2218	Silicon Labs	EFR32FG1xxxxF32 internal	0	0	1	28	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	200[64]; 200[1], FE00000; 200[1], FE04000;
2219	Silicon Labs	EFR32FG1xxxxF64 internal	0	0	1	28	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	800[32]; 800[1], FE00000; 800[1], FE04000;
2220	Silicon Labs	EFR32MG1xxxxF256 internal	0	0	1	28	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	800[128]; 800[1], FE00000; 800[1], FE04000;
2221	Silicon Labs	EZR32LGxxxF64 internal	0	0	1	28	0	32	1	0	0	0	0	0	0	0	0	0	0	1	1	800[32]; 800[1], FE00000; 800[1], FE04000;
2222	Silicon Labs	EZR32LGxxxF128 internal	0	0	1	28	0	32	1	0	0	0	0	0	0	0	0	0	0	1	1	800[64]; 800[1], FE00000; 800[1], FE04000;
2223	Silicon Labs	EZR32LGxxxF256 internal	0	0	1	28	0	32	1	0	0	0	0	0	0	0	0	0	0	1	1	800[128]; 800[1], FE00000; 800[1], FE04000;
2224	Silicon Labs	EZR32WGxxxF64 internal	0	0	1	28	0	32	1	0	0	0	0	0	0	0	0	0	0	1	1	800[32]; 800[1], FE00000; 800[1], FE04000;
2225	Silicon Labs	EZR32WGxxxF128 internal	0	0	1	28	0	32	1	0	0	0	0	0	0	0	0	0	0	1	1	800[64]; 800[1], FE00000; 800[1], FE04000;
2226	Silicon Labs	EZR32WGxxxF256 internal	0	0	1	28	0	32	1	0	0	0	0	0	0	0	0	0	0	1	1	800[128]; 800[1], FE00000; 800[1], FE04000;
2227	Silicon Labs	SiM3C134 internal	0	0	1	73	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	400[32];4[1], 3FFFC;
2228	Silicon Labs	SiM3C136 internal	0	0	1	73	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	400[32];4[1], 3FFFC;
2229	Silicon Labs	SiM3C144 internal	0	0	1	73	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	400[64];4[1], 3FFFC;
2230	Silicon Labs	SiM3C146 internal	0	0	1	73	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	400[64];4[1], 3FFFC;
2231	Silicon Labs	SiM3C154 internal	0	0	1	73	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	400[128];4[1], 3FFFC;
2232	Silicon Labs	SiM3C156 internal	0	0	1	73	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	400[128];4[1], 3FFFC;
2233	Silicon Labs	SiM3C157 internal	0	0	1	73	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	400[128];4[1], 3FFFC;
2234	Silicon Labs	SiM3C164 internal	0	0	1	73	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	400[256];
2235	Silicon Labs	SiM3C166 internal	0	0	1	73	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	400[256];
2236	Silicon Labs	SiM3C167 internal	0	0	1	73	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	400[256];
2237	Silicon Labs	SiM3L134 internal	0	0	1	73	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	400[32];4[1], 3FFFC;
2238	Silicon Labs	SiM3L136 internal	0	0	1	73	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	400[32];4[1], 3FFFC;
2239	Silicon Labs	SiM3L144 internal	0	0	1	73	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	400[64];4[1], 3FFFC;
2240	Silicon Labs	SiM3L146 internal	0	0	1	73	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	400[64];4[1], 3FFFC;
2241	Silicon Labs	SiM3L154 internal	0	0	1	73	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	400[128];4[1], 3FFFC;
2242	Silicon Labs	SiM3L156 internal	0	0	1	73	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	400[128];4[1], 3FFFC;
2243	Silicon Labs	SiM3L157 internal	0	0	1	73	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	400[128];4[1], 3FFFC;
2244	Silicon Labs	SiM3L164 internal	0	0	1	73	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	400[256];
2245	Silicon Labs	SiM3L166 internal	0	0	1	73	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	400[256];
2246	Silicon Labs	SiM3L167 internal	0	0	1	73	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	400[256];
2247	Silicon Labs	SiM3U134 internal	0	0	1	73	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	400[32];4[1], 3FFFC;
2248	Silicon Labs	SiM3U136 internal	0	0	1	73	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	400[32];4[1], 3FFFC;
2249	Silicon Labs	SiM3U144 internal	0	0	1	73	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	400[64];4[1], 3FFFC;
2250	Silicon Labs	SiM3U146 internal	0	0	1	73	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	400[64];4[1], 3FFFC;
2251	Silicon Labs	SiM3U154 internal	0	0	1	73	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	400[128];4[1], 3FFFC;
2252	Silicon Labs	SiM3U156 internal	0	0	1	73	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	400[128];4[1], 3FFFC;
2253	Silicon Labs	SiM3U157 internal	0	0	1	73	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	400[128];4[1], 3FFFC;
2254	Silicon Labs	SiM3U164 internal	0	0	1	73	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	400[256];
2255	Silicon Labs	SiM3U166 internal	0	0	1	73	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	400[256];
2256	Silicon Labs	SiM3U167 internal	0	0	1	73	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	400[256];
2257	Sirona	Sirona 2x16	0122DA	0100DA	0	1	1	16	1	0	0	0	0	0	0	0	0	0	0	0	0	10000[15]; 8000; 2000[2]; 4000; 10000[15], 2000000; 8000; 2000[2]; 4000;
2258	Spansion	MB9AF121K internal	0	0	1	40	5	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[7]; 1FF8[1];
2259	Spansion	MB9AF121L internal	0	0	1	40	5	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[7]; 1FF8[1];
2260	Spansion	MB9AF421K internal	0	0	1	40	5	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[7]; 1FF8[1];
2261	Spansion	MB9AF421L internal	0	0	1	40	5	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[7]; 1FF8[1];
2262	Spansion	MB9AF102N internal	0	0	1	40	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	4000[2];18000[1];
2263	Spansion	MB9AF102R internal	0	0	1	40	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	4000[2];18000[1];
2264	Spansion	MB9AF104N internal	0	0	1	40	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	4000[2];18000[1];20000[1];
2265	Spansion	MB9AF104R internal	0	0	1	40	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	4000[2];18000[1];20000[1];
2266	Spansion	MB9AF111K internal	0	0	1	40	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	4000[2];8000[1];2000[4], 200C0000;
2267	Spansion	MB9AF111L internal	0	0	1	40	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	4000[2];8000[1];
2268	Spansion	MB9AF111M internal	0	0	1	40	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	4000[2];8000[1];
2269	Spansion	MB9AF111N internal	0	0	1	40	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	4000[2];8000[1];
2270	Spansion	MB9AF112K internal	0	0	1	40	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	4000[2];18000[1];2000[4], 200C0000;
2271	Spansion	MB9AF112L internal	0	0	1	40	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	4000[2];18000[1];
2272	Spansion	MB9AF112M internal	0	0	1	40	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	4000[2];18000[1];
2273	Spansion	MB9AF112N internal	0	0	1	40	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	4000[2];18000[1];
2274	Spansion	MB9AF114L internal	0	0	1	40	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	4000[2];18000[1];20000[1];
2275	Spansion	MB9AF114M internal	0	0	1	40	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	4000[2];18000[1];20000[1];
2276	Spansion	MB9AF114N internal	0	0	1	40	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	4000[2];18000[1];20000[1];
2277	Spansion	MB9AF115M internal	0	0	1	40	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	4000[2];18000[1];20000[2];
2278	Spansion	MB9AF115N internal	0	0	1	40	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	4000[2];18000[1];20000[2];
2279	Spansion	MB9AF116M internal	0	0	1	40	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	4000[2];18000[1];20000[3];
2280	Spansion	MB9AF116N internal	0	0	1	40	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	4000[2];18000[1];20000[3];
2281	Spansion	MB9AF131K internal	0	0	1	40	2	32	1	0	0	0	0	0	0	0	0	0	0	0	0	4000[2];8000[1];
2282	Spansion	MB9AF131KA internal	0	0	1	40	2	32	1	0	0	0	0	0	0	0	0	0	0	0	0	1000[1];F000[1];
2283	Spansion	MB9AF131L internal	0	0	1	40	2	32	1	0	0	0	0	0	0	0	0	0	0	0	0	4000[2];8000[1];
2284	Spansion	MB9AF131M internal	0	0	1	40	2	32	1	0	0	0	0	0	0	0	0	0	0	0	0	1000[1];F000[1];
2285	Spansion	MB9AF131N internal	0	0	1	40	2	32	1	0	0	0	0	0	0	0	0	0	0	0	0	1000[1];F000[1];
2286	Spansion	MB9AF132K internal	0	0	1	40	2	32	1	0	0	0	0	0	0	0	0	0	0	0	0	4000[2];18000[1];
2287	Spansion	MB9AF132KA internal	0	0	1	40	2	32	1	0	0	0	0	0	0	0	0	0	0	0	0	1000[1];F000[1];10000[1];
2288	Spansion	MB9AF132L internal	0	0	1	40	2	32	1	0	0	0	0	0	0	0	0	0	0	0	0	4000[2];18000[1];
2289	Spansion	MB9AF132M internal	0	0	1	40	2	32	1	0	0	0	0	0	0	0	0	0	0	0	0	1000[1];F000[1];10000[1];
2290	Spansion	MB9AF132N internal	0	0	1	40	2	32	1	0	0	0	0	0	0	0	0	0	0	0	0	1000[1];F000[1];10000[1];
2291	Spansion	MB9AF141L internal	0	0	1	40	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[2];C000[1]; 2000[4], 200000;
2292	Spansion	MB9AF141LA internal	0	0	1	40	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[2];C000[1]; 2000[4], 200000;
2293	Spansion	MB9AF141M internal	0	0	1	40	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[2];C000[1]; 2000[4], 200000;
2294	Spansion	MB9AF141MA internal	0	0	1	40	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[2];C000[1]; 2000[4], 200000;
2295	Spansion	MB9AF141N internal	0	0	1	40	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[2];C000[1]; 2000[4], 200000;
2296	Spansion	MB9AF141NA internal	0	0	1	40	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[2];C000[1]; 2000[4], 200000;
2297	Spansion	MB9AF142L internal	0	0	1	40	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[2];C000[1];10000[1]; 2000[4], 200000;
2298	Spansion	MB9AF142LA internal	0	0	1	40	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[2];C000[1];10000[1]; 2000[4], 200000;
2299	Spansion	MB9AF142M internal	0	0	1	40	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[2];C000[1];10000[1]; 2000[4], 200000;
2300	Spansion	MB9AF142MA internal	0	0	1	40	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[2];C000[1];10000[1]; 2000[4], 200000;
2301	Spansion	MB9AF142N internal	0	0	1	40	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[2];C000[1];10000[1]; 2000[4], 200000;
2302	Spansion	MB9AF142NA internal	0	0	1	40	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[2];C000[1];10000[1]; 2000[4], 200000;
2303	Spansion	MB9AF144L internal	0	0	1	40	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[2];C000[1];10000[3]; 2000[4], 200000;
2304	Spansion	MB9AF144LA internal	0	0	1	40	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[2];C000[1];10000[3]; 2000[4], 200000;
2305	Spansion	MB9AF144M internal	0	0	1	40	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[2];C000[1];10000[3]; 2000[4], 200000;
2306	Spansion	MB9AF144MA internal	0	0	1	40	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[2];C000[1];10000[3]; 2000[4], 200000;
2307	Spansion	MB9AF144N internal	0	0	1	40	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[2];C000[1];10000[3]; 2000[4], 200000;
2308	Spansion	MB9AF144NA internal	0	0	1	40	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[2];C000[1];10000[3]; 2000[4], 200000;
2309	Spansion	MB9AF154M internal	0	0	1	40	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[2];C000[1];10000[3]; 2000[4], 200000;
2310	Spansion	MB9AF154N internal	0	0	1	40	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[2];C000[1];10000[3]; 2000[4], 200000;
2311	Spansion	MB9AF154R internal	0	0	1	40	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[2];C000[1];10000[3]; 2000[4], 200000;
2312	Spansion	MB9AF155M internal	0	0	1	40	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[2];C000[1];10000[5]; 2000[4], 200000;
2313	Spansion	MB9AF155N internal	0	0	1	40	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[2];C000[1];10000[5]; 2000[4], 200000;
2314	Spansion	MB9AF155R internal	0	0	1	40	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[2];C000[1];10000[5]; 2000[4], 200000;
2315	Spansion	MB9AF156M internal	0	0	1	40	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[2];C000[1];10000[7]; 2000[4], 200000;
2316	Spansion	MB9AF156N internal	0	0	1	40	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[2];C000[1];10000[7]; 2000[4], 200000;
2317	Spansion	MB9AF156R internal	0	0	1	40	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[2];C000[1];10000[7]; 2000[4], 200000;
2318	Spansion	MB9AF311K internal	0	0	1	40	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	4000[2];8000[1];2000[4], 200C0000;
2319	Spansion	MB9AF311L internal	0	0	1	40	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	4000[2];8000[1];
2320	Spansion	MB9AF311M internal	0	0	1	40	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	4000[2];8000[1];
2321	Spansion	MB9AF311N internal	0	0	1	40	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	4000[2];8000[1];
2322	Spansion	MB9AF312K internal	0	0	1	40	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	4000[2];18000[1];2000[4], 200C0000;
2323	Spansion	MB9AF312L internal	0	0	1	40	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	4000[2];18000[1];
2324	Spansion	MB9AF312M internal	0	0	1	40	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	4000[2];18000[1];
2325	Spansion	MB9AF312N internal	0	0	1	40	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	4000[2];18000[1];
2326	Spansion	MB9AF314L internal	0	0	1	40	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	4000[2];18000[1];20000[1];
2327	Spansion	MB9AF314M internal	0	0	1	40	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	4000[2];18000[1];20000[1];
2328	Spansion	MB9AF314N internal	0	0	1	40	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	4000[2];18000[1];20000[1];
2329	Spansion	MB9AF315M internal	0	0	1	40	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	4000[2];18000[1];20000[2];
2330	Spansion	MB9AF315N internal	0	0	1	40	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	4000[2];18000[1];20000[2];
2331	Spansion	MB9AF316M internal	0	0	1	40	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	4000[2];18000[1];20000[3];
2332	Spansion	MB9AF316N internal	0	0	1	40	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	4000[2];18000[1];20000[3];
2333	Spansion	MB9AF341L internal	0	0	1	40	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[2];C000[1]; 2000[4], 200000;
2334	Spansion	MB9AF341LA internal	0	0	1	40	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[2];C000[1]; 2000[4], 200000;
2335	Spansion	MB9AF341M internal	0	0	1	40	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[2];C000[1]; 2000[4], 200000;
2336	Spansion	MB9AF341MA internal	0	0	1	40	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[2];C000[1]; 2000[4], 200000;
2337	Spansion	MB9AF341N internal	0	0	1	40	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[2];C000[1]; 2000[4], 200000;
2338	Spansion	MB9AF341NA internal	0	0	1	40	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[2];C000[1]; 2000[4], 200000;
2339	Spansion	MB9AF342L internal	0	0	1	40	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[2];C000[1];10000[1]; 2000[4], 200000;
2340	Spansion	MB9AF342LA internal	0	0	1	40	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[2];C000[1];10000[1]; 2000[4], 200000;
2341	Spansion	MB9AF342M internal	0	0	1	40	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[2];C000[1];10000[1]; 2000[4], 200000;
2342	Spansion	MB9AF342MA internal	0	0	1	40	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[2];C000[1];10000[1]; 2000[4], 200000;
2343	Spansion	MB9AF342N internal	0	0	1	40	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[2];C000[1];10000[1]; 2000[4], 200000;
2344	Spansion	MB9AF342NA internal	0	0	1	40	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[2];C000[1];10000[1]; 2000[4], 200000;
2345	Spansion	MB9AF344L internal	0	0	1	40	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[2];C000[1];10000[3]; 2000[4], 200000;
2346	Spansion	MB9AF344LA internal	0	0	1	40	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[2];C000[1];10000[3]; 2000[4], 200000;
2347	Spansion	MB9AF344M internal	0	0	1	40	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[2];C000[1];10000[3]; 2000[4], 200000;
2348	Spansion	MB9AF344MA internal	0	0	1	40	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[2];C000[1];10000[3]; 2000[4], 200000;
2349	Spansion	MB9AF344N internal	0	0	1	40	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[2];C000[1];10000[3]; 2000[4], 200000;
2350	Spansion	MB9AF344NA internal	0	0	1	40	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[2];C000[1];10000[3]; 2000[4], 200000;
2351	Spansion	MB9AFA31L internal	0	0	1	40	2	32	1	0	0	0	0	0	0	0	0	0	0	0	0	1000[1];F000[1];
2352	Spansion	MB9AFA31LA internal	0	0	1	40	2	32	1	0	0	0	0	0	0	0	0	0	0	0	0	1000[1];F000[1];
2353	Spansion	MB9AFA31M internal	0	0	1	40	2	32	1	0	0	0	0	0	0	0	0	0	0	0	0	1000[1];F000[1];
2354	Spansion	MB9AFA31N internal	0	0	1	40	2	32	1	0	0	0	0	0	0	0	0	0	0	0	0	1000[1];F000[1];
2355	Spansion	MB9AFA32L internal	0	0	1	40	2	32	1	0	0	0	0	0	0	0	0	0	0	0	0	1000[1];F000[1];10000[1];
2356	Spansion	MB9AFA32LA internal	0	0	1	40	2	32	1	0	0	0	0	0	0	0	0	0	0	0	0	1000[1];F000[1];10000[1];
2357	Spansion	MB9AFA32M internal	0	0	1	40	2	32	1	0	0	0	0	0	0	0	0	0	0	0	0	1000[1];F000[1];10000[1];
2358	Spansion	MB9AFA32N internal	0	0	1	40	2	32	1	0	0	0	0	0	0	0	0	0	0	0	0	1000[1];F000[1];10000[1];
2359	Spansion	MB9AFA41L internal	0	0	1	40	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[2];C000[1]; 2000[4], 200000;
2360	Spansion	MB9AFA41LA internal	0	0	1	40	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[2];C000[1]; 2000[4], 200000;
2361	Spansion	MB9AFA41M internal	0	0	1	40	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[2];C000[1]; 2000[4], 200000;
2362	Spansion	MB9AFA41MA internal	0	0	1	40	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[2];C000[1]; 2000[4], 200000;
2363	Spansion	MB9AFA41N internal	0	0	1	40	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[2];C000[1]; 2000[4], 200000;
2364	Spansion	MB9AFA41NA internal	0	0	1	40	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[2];C000[1]; 2000[4], 200000;
2365	Spansion	MB9AFA42L internal	0	0	1	40	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[2];C000[1];10000[1]; 2000[4], 200000;
2366	Spansion	MB9AFA42LA internal	0	0	1	40	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[2];C000[1];10000[1]; 2000[4], 200000;
2367	Spansion	MB9AFA42M internal	0	0	1	40	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[2];C000[1];10000[1]; 2000[4], 200000;
2368	Spansion	MB9AFA42MA internal	0	0	1	40	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[2];C000[1];10000[1]; 2000[4], 200000;
2369	Spansion	MB9AFA42N internal	0	0	1	40	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[2];C000[1];10000[1]; 2000[4], 200000;
2370	Spansion	MB9AFA42NA internal	0	0	1	40	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[2];C000[1];10000[1]; 2000[4], 200000;
2371	Spansion	MB9AFA44L internal	0	0	1	40	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[2];C000[1];10000[3]; 2000[4], 200000;
2372	Spansion	MB9AFA44LA internal	0	0	1	40	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[2];C000[1];10000[3]; 2000[4], 200000;
2373	Spansion	MB9AFA44M internal	0	0	1	40	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[2];C000[1];10000[3]; 2000[4], 200000;
2374	Spansion	MB9AFA44MA internal	0	0	1	40	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[2];C000[1];10000[3]; 2000[4], 200000;
2375	Spansion	MB9AFA44N internal	0	0	1	40	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[2];C000[1];10000[3]; 2000[4], 200000;
2376	Spansion	MB9AFA44NA internal	0	0	1	40	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[2];C000[1];10000[3]; 2000[4], 200000;
2377	Spansion	MB9AFB41L internal	0	0	1	40	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[2];C000[1]; 2000[4], 200000;
2378	Spansion	MB9AFB41LA internal	0	0	1	40	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[2];C000[1]; 2000[4], 200000;
2379	Spansion	MB9AFB41M internal	0	0	1	40	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[2];C000[1]; 2000[4], 200000;
2380	Spansion	MB9AFB41MA internal	0	0	1	40	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[2];C000[1]; 2000[4], 200000;
2381	Spansion	MB9AFB41N internal	0	0	1	40	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[2];C000[1]; 2000[4], 200000;
2382	Spansion	MB9AFB41NA internal	0	0	1	40	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[2];C000[1]; 2000[4], 200000;
2383	Spansion	MB9AFB42L internal	0	0	1	40	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[2];C000[1];10000[1]; 2000[4], 200000;
2384	Spansion	MB9AFB42LA internal	0	0	1	40	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[2];C000[1];10000[1]; 2000[4], 200000;
2385	Spansion	MB9AFB42M internal	0	0	1	40	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[2];C000[1];10000[1]; 2000[4], 200000;
2386	Spansion	MB9AFB42MA internal	0	0	1	40	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[2];C000[1];10000[1]; 2000[4], 200000;
2387	Spansion	MB9AFB42N internal	0	0	1	40	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[2];C000[1];10000[1]; 2000[4], 200000;
2388	Spansion	MB9AFB42NA internal	0	0	1	40	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[2];C000[1];10000[1]; 2000[4], 200000;
2389	Spansion	MB9AFB44L internal	0	0	1	40	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[2];C000[1];10000[3]; 2000[4], 200000;
2390	Spansion	MB9AFB44LA internal	0	0	1	40	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[2];C000[1];10000[3]; 2000[4], 200000;
2391	Spansion	MB9AFB44M internal	0	0	1	40	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[2];C000[1];10000[3]; 2000[4], 200000;
2392	Spansion	MB9AFB44MA internal	0	0	1	40	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[2];C000[1];10000[3]; 2000[4], 200000;
2393	Spansion	MB9AFB44N internal	0	0	1	40	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[2];C000[1];10000[3]; 2000[4], 200000;
2394	Spansion	MB9AFB44NA internal	0	0	1	40	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[2];C000[1];10000[3]; 2000[4], 200000;
2395	Spansion	MB9BF104N internal	0	0	1	40	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	4000[2];18000[1];20000[1];
2396	Spansion	MB9BF104R internal	0	0	1	40	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	4000[2];18000[1];20000[1];
2397	Spansion	MB9BF105N internal	0	0	1	40	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	4000[2];18000[1];20000[2];
2398	Spansion	MB9BF105R internal	0	0	1	40	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	4000[2];18000[1];20000[2];
2399	Spansion	MB9BF106N internal	0	0	1	40	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	4000[2];18000[1];20000[3];
2400	Spansion	MB9BF106R internal	0	0	1	40	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	4000[2];18000[1];20000[3];
2401	Spansion	MB9BF112N internal	0	0	1	40	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	4000[2];18000[1]; 2000[4], 200C0000;
2402	Spansion	MB9BF112R internal	0	0	1	40	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	4000[2];18000[1]; 2000[4], 200C0000;
2403	Spansion	MB9BF114N internal	0	0	1	40	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	4000[2];18000[1];20000[1]; 2000[4], 200C0000;
2404	Spansion	MB9BF114R internal	0	0	1	40	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	4000[2];18000[1];20000[1]; 2000[4], 200C0000;
2405	Spansion	MB9BF115N internal	0	0	1	40	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	4000[2];18000[1];20000[2]; 2000[4], 200C0000;
2406	Spansion	MB9BF115R internal	0	0	1	40	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	4000[2];18000[1];20000[2]; 2000[4], 200C0000;
2407	Spansion	MB9BF116N internal	0	0	1	40	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	4000[2];18000[1];20000[3]; 2000[4], 200C0000;
2408	Spansion	MB9BF116R internal	0	0	1	40	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	4000[2];18000[1];20000[3]; 2000[4], 200C0000;
2409	Spansion	MB9BF116S internal	0	0	1	40	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	4000[2];18000[1];20000[3];
2410	Spansion	MB9BF116T internal	0	0	1	40	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	4000[2];18000[1];20000[3];
2411	Spansion	MB9BF117S internal	0	0	1	40	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	4000[2];18000[1];20000[5];
2412	Spansion	MB9BF117T internal	0	0	1	40	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	4000[2];18000[1];20000[5];
2413	Spansion	MB9BF118S internal	0	0	1	40	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	4000[2];18000[1];20000[7];
2414	Spansion	MB9BF118T internal	0	0	1	40	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	4000[2];18000[1];20000[7];
2415	Spansion	MB9BF121K internal	0	0	1	40	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[2];C000[1]; 2000[4], 200000;
2416	Spansion	MB9BF121L internal	0	0	1	40	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[2];C000[1]; 2000[4], 200000;
2417	Spansion	MB9BF121M internal	0	0	1	40	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[2];C000[1]; 2000[4], 200000;
2418	Spansion	MB9BF122K internal	0	0	1	40	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[2];C000[1];10000[1]; 2000[4], 200000;
2419	Spansion	MB9BF122L internal	0	0	1	40	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[2];C000[1];10000[1]; 2000[4], 200000;
2420	Spansion	MB9BF122M internal	0	0	1	40	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[2];C000[1];10000[1]; 2000[4], 200000;
2421	Spansion	MB9BF124K internal	0	0	1	40	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[2];C000[1];10000[3]; 2000[4], 200000;
2422	Spansion	MB9BF124L internal	0	0	1	40	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[2];C000[1];10000[3]; 2000[4], 200000;
2423	Spansion	MB9BF124M internal	0	0	1	40	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[2];C000[1];10000[3]; 2000[4], 200000;
2424	Spansion	MB9BF128S internal	0	0	1	40	3	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[2];C000[1]; 10000[15]; 2000[8], 00508000;
2425	Spansion	MB9BF128T internal	0	0	1	40	3	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[2];C000[1]; 10000[15]; 2000[8], 00508000;
2426	Spansion	MB9BF129S internal	0	0	1	40	3	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[2];C000[1]; 10000[23]; 2000[8], 00508000;
2427	Spansion	MB9BF129T internal	0	0	1	40	3	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[2];C000[1]; 10000[23]; 2000[8], 00508000;
2428	Spansion	MB9BF164K internal	0	0	1	40	2	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[4];8000[1];10000[7]; 2000[4], 200C0000;
2429	Spansion	MB9BF164L internal	0	0	1	40	2	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[4];8000[1];10000[7]; 2000[4], 200C0000;
2430	Spansion	MB9BF165K internal	0	0	1	40	2	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[4];8000[1];10000[7]; 2000[4], 200C0000;
2431	Spansion	MB9BF165L internal	0	0	1	40	2	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[4];8000[1];10000[7]; 2000[4], 200C0000;
2432	Spansion	MB9BF166K internal	0	0	1	40	2	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[4];8000[1];10000[7]; 2000[4], 200C0000;
2433	Spansion	MB9BF166L internal	0	0	1	40	2	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[4];8000[1];10000[7]; 2000[4], 200C0000;
2434	Spansion	MB9BF166M internal	0	0	1	40	2	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[4];8000[1];10000[7]; 2000[4], 200C0000;
2435	Spansion	MB9BF166N internal	0	0	1	40	2	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[4];8000[1];10000[7]; 2000[4], 200C0000;
2436	Spansion	MB9BF166R internal	0	0	1	40	2	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[4];8000[1];10000[7]; 2000[4], 200C0000;
2437	Spansion	MB9BF167M internal	0	0	1	40	2	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[4];8000[1];10000[11]; 2000[4], 200C0000;
2438	Spansion	MB9BF167N internal	0	0	1	40	2	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[4];8000[1];10000[11]; 2000[4], 200C0000;
2439	Spansion	MB9BF167R internal	0	0	1	40	2	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[4];8000[1];10000[11]; 2000[4], 200C0000;
2440	Spansion	MB9BF168M internal	0	0	1	40	2	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[4];8000[1];10000[15]; 2000[4], 200C0000;
2441	Spansion	MB9BF168N internal	0	0	1	40	2	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[4];8000[1];10000[15]; 2000[4], 200C0000;
2442	Spansion	MB9BF168R internal	0	0	1	40	2	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[4];8000[1];10000[15]; 2000[4], 200C0000;
2443	Spansion	MB9BF216S internal	0	0	1	40	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	4000[2];18000[1];20000[3];
2444	Spansion	MB9BF216T internal	0	0	1	40	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	4000[2];18000[1];20000[3];
2445	Spansion	MB9BF217S internal	0	0	1	40	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	4000[2];18000[1];20000[5];
2446	Spansion	MB9BF217T internal	0	0	1	40	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	4000[2];18000[1];20000[5];
2447	Spansion	MB9BF218S internal	0	0	1	40	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	4000[2];18000[1];20000[7];
2448	Spansion	MB9BF218T internal	0	0	1	40	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	4000[2];18000[1];20000[7];
2449	Spansion	MB9BF304N internal	0	0	1	40	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	4000[2];18000[1];20000[1];
2450	Spansion	MB9BF304R internal	0	0	1	40	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	4000[2];18000[1];20000[1];
2451	Spansion	MB9BF305N internal	0	0	1	40	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	4000[2];18000[1];20000[2];
2452	Spansion	MB9BF305R internal	0	0	1	40	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	4000[2];18000[1];20000[2];
2453	Spansion	MB9BF306N internal	0	0	1	40	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	4000[2];18000[1];20000[3];
2454	Spansion	MB9BF306R internal	0	0	1	40	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	4000[2];18000[1];20000[3];
2455	Spansion	MB9BF316S internal	0	0	1	40	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	4000[2];18000[1];20000[3];
2456	Spansion	MB9BF316T internal	0	0	1	40	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	4000[2];18000[1];20000[3];
2457	Spansion	MB9BF317S internal	0	0	1	40	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	4000[2];18000[1];20000[5];
2458	Spansion	MB9BF317T internal	0	0	1	40	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	4000[2];18000[1];20000[5];
2459	Spansion	MB9BF318S internal	0	0	1	40	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	4000[2];18000[1];20000[7];
2460	Spansion	MB9BF318T internal	0	0	1	40	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	4000[2];18000[1];20000[7];
2461	Spansion	MB9BF321K internal	0	0	1	40	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[2];C000[1]; 2000[4], 200000;
2462	Spansion	MB9BF321L internal	0	0	1	40	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[2];C000[1]; 2000[4], 200000;
2463	Spansion	MB9BF321M internal	0	0	1	40	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[2];C000[1]; 2000[4], 200000;
2464	Spansion	MB9BF322K internal	0	0	1	40	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[2];C000[1];10000[1]; 2000[4], 200000;
2465	Spansion	MB9BF322L internal	0	0	1	40	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[2];C000[1];10000[1]; 2000[4], 200000;
2466	Spansion	MB9BF322M internal	0	0	1	40	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[2];C000[1];10000[1]; 2000[4], 200000;
2467	Spansion	MB9BF324K internal	0	0	1	40	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[2];C000[1];10000[3]; 2000[4], 200000;
2468	Spansion	MB9BF324L internal	0	0	1	40	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[2];C000[1];10000[3]; 2000[4], 200000;
2469	Spansion	MB9BF324M internal	0	0	1	40	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[2];C000[1];10000[3]; 2000[4], 200000;
2470	Spansion	MB9BF328S internal	0	0	1	40	3	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[2];C000[1]; 10000[15]; 2000[8], 00508000;
2471	Spansion	MB9BF328T internal	0	0	1	40	3	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[2];C000[1]; 10000[15]; 2000[8], 00508000;
2472	Spansion	MB9BF329S internal	0	0	1	40	3	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[2];C000[1]; 10000[23]; 2000[8], 00508000;
2473	Spansion	MB9BF329T internal	0	0	1	40	3	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[2];C000[1]; 10000[23]; 2000[8], 00508000;
2474	Spansion	MB9BF364K internal	0	0	1	40	2	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[4];8000[1];10000[7]; 2000[4], 200C0000;
2475	Spansion	MB9BF364L internal	0	0	1	40	2	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[4];8000[1];10000[7]; 2000[4], 200C0000;
2476	Spansion	MB9BF365K internal	0	0	1	40	2	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[4];8000[1];10000[7]; 2000[4], 200C0000;
2477	Spansion	MB9BF365L internal	0	0	1	40	2	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[4];8000[1];10000[7]; 2000[4], 200C0000;
2478	Spansion	MB9BF366K internal	0	0	1	40	2	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[4];8000[1];10000[7]; 2000[4], 200C0000;
2479	Spansion	MB9BF366L internal	0	0	1	40	2	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[4];8000[1];10000[7]; 2000[4], 200C0000;
2480	Spansion	MB9BF366M internal	0	0	1	40	2	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[4];8000[1];10000[7]; 2000[4], 200C0000;
2481	Spansion	MB9BF366N internal	0	0	1	40	2	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[4];8000[1];10000[7]; 2000[4], 200C0000;
2482	Spansion	MB9BF366R internal	0	0	1	40	2	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[4];8000[1];10000[7]; 2000[4], 200C0000;
2483	Spansion	MB9BF367M internal	0	0	1	40	2	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[4];8000[1];10000[11]; 2000[4], 200C0000;
2484	Spansion	MB9BF367N internal	0	0	1	40	2	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[4];8000[1];10000[11]; 2000[4], 200C0000;
2485	Spansion	MB9BF367R internal	0	0	1	40	2	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[4];8000[1];10000[11]; 2000[4], 200C0000;
2486	Spansion	MB9BF368M internal	0	0	1	40	2	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[4];8000[1];10000[15]; 2000[4], 200C0000;
2487	Spansion	MB9BF368N internal	0	0	1	40	2	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[4];8000[1];10000[15]; 2000[4], 200C0000;
2488	Spansion	MB9BF368R internal	0	0	1	40	2	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[4];8000[1];10000[15]; 2000[4], 200C0000;
2489	Spansion	MB9BF404N internal	0	0	1	40	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	4000[2];18000[1];20000[1];
2490	Spansion	MB9BF404R internal	0	0	1	40	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	4000[2];18000[1];20000[1];
2491	Spansion	MB9BF405N internal	0	0	1	40	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	4000[2];18000[1];20000[2];
2492	Spansion	MB9BF405R internal	0	0	1	40	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	4000[2];18000[1];20000[2];
2493	Spansion	MB9BF406N internal	0	0	1	40	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	4000[2];18000[1];20000[3];
2494	Spansion	MB9BF406R internal	0	0	1	40	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	4000[2];18000[1];20000[3];
2495	Spansion	MB9BF412N internal	0	0	1	40	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	4000[2];18000[1]; 2000[4], 200C0000;
2496	Spansion	MB9BF412R internal	0	0	1	40	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	4000[2];18000[1]; 2000[4], 200C0000;
2497	Spansion	MB9BF414N internal	0	0	1	40	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	4000[2];18000[1];20000[1]; 2000[4], 200C0000;
2498	Spansion	MB9BF414R internal	0	0	1	40	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	4000[2];18000[1];20000[1]; 2000[4], 200C0000;
2499	Spansion	MB9BF415N internal	0	0	1	40	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	4000[2];18000[1];20000[2]; 2000[4], 200C0000;
2500	Spansion	MB9BF415R internal	0	0	1	40	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	4000[2];18000[1];20000[2]; 2000[4], 200C0000;
2501	Spansion	MB9BF416N internal	0	0	1	40	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	4000[2];18000[1];20000[3]; 2000[4], 200C0000;
2502	Spansion	MB9BF416R internal	0	0	1	40	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	4000[2];18000[1];20000[3]; 2000[4], 200C0000;
2503	Spansion	MB9BF416S internal	0	0	1	40	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	4000[2];18000[1];20000[3];
2504	Spansion	MB9BF416T internal	0	0	1	40	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	4000[2];18000[1];20000[3];
2505	Spansion	MB9BF417S internal	0	0	1	40	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	4000[2];18000[1];20000[5];
2506	Spansion	MB9BF417T internal	0	0	1	40	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	4000[2];18000[1];20000[5];
2507	Spansion	MB9BF418S internal	0	0	1	40	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	4000[2];18000[1];20000[7];
2508	Spansion	MB9BF418T internal	0	0	1	40	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	4000[2];18000[1];20000[7];
2509	Spansion	MB9BF428S internal	0	0	1	40	3	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[2];C000[1]; 10000[15]; 2000[8], 00508000;
2510	Spansion	MB9BF428T internal	0	0	1	40	3	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[2];C000[1]; 10000[15]; 2000[8], 00508000;
2511	Spansion	MB9BF429S internal	0	0	1	40	3	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[2];C000[1]; 10000[23]; 2000[8], 00508000;
2512	Spansion	MB9BF429T internal	0	0	1	40	3	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[2];C000[1]; 10000[23]; 2000[8], 00508000;
2513	Spansion	MB9BF464K internal	0	0	1	40	2	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[4];8000[1];10000[7]; 2000[4], 200C0000;
2514	Spansion	MB9BF464L internal	0	0	1	40	2	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[4];8000[1];10000[7]; 2000[4], 200C0000;
2515	Spansion	MB9BF465K internal	0	0	1	40	2	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[4];8000[1];10000[7]; 2000[4], 200C0000;
2516	Spansion	MB9BF465L internal	0	0	1	40	2	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[4];8000[1];10000[7]; 2000[4], 200C0000;
2517	Spansion	MB9BF466K internal	0	0	1	40	2	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[4];8000[1];10000[7]; 2000[4], 200C0000;
2518	Spansion	MB9BF466L internal	0	0	1	40	2	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[4];8000[1];10000[7]; 2000[4], 200C0000;
2519	Spansion	MB9BF466M internal	0	0	1	40	2	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[4];8000[1];10000[7]; 2000[4], 200C0000;
2520	Spansion	MB9BF466N internal	0	0	1	40	2	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[4];8000[1];10000[7]; 2000[4], 200C0000;
2521	Spansion	MB9BF466R internal	0	0	1	40	2	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[4];8000[1];10000[7]; 2000[4], 200C0000;
2522	Spansion	MB9BF467M internal	0	0	1	40	2	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[4];8000[1];10000[11]; 2000[4], 200C0000;
2523	Spansion	MB9BF467N internal	0	0	1	40	2	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[4];8000[1];10000[11]; 2000[4], 200C0000;
2524	Spansion	MB9BF467R internal	0	0	1	40	2	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[4];8000[1];10000[11]; 2000[4], 200C0000;
2525	Spansion	MB9BF468M internal	0	0	1	40	2	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[4];8000[1];10000[15]; 2000[4], 200C0000;
2526	Spansion	MB9BF468N internal	0	0	1	40	2	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[4];8000[1];10000[15]; 2000[4], 200C0000;
2527	Spansion	MB9BF468R internal	0	0	1	40	2	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[4];8000[1];10000[15]; 2000[4], 200C0000;
2528	Spansion	MB9BF504N internal	0	0	1	40	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	4000[2];18000[1];20000[1];
2529	Spansion	MB9BF504R internal	0	0	1	40	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	4000[2];18000[1];20000[1];
2530	Spansion	MB9BF505N internal	0	0	1	40	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	4000[2];18000[1];20000[2];
2531	Spansion	MB9BF505R internal	0	0	1	40	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	4000[2];18000[1];20000[2];
2532	Spansion	MB9BF506N internal	0	0	1	40	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	4000[2];18000[1];20000[3];
2533	Spansion	MB9BF506R internal	0	0	1	40	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	4000[2];18000[1];20000[3];
2534	Spansion	MB9BF512N internal	0	0	1	40	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	4000[2];18000[1]; 2000[4], 200C0000;
2535	Spansion	MB9BF512R internal	0	0	1	40	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	4000[2];18000[1]; 2000[4], 200C0000;
2536	Spansion	MB9BF514N internal	0	0	1	40	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	4000[2];18000[1];20000[1]; 2000[4], 200C0000;
2537	Spansion	MB9BF514R internal	0	0	1	40	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	4000[2];18000[1];20000[1]; 2000[4], 200C0000;
2538	Spansion	MB9BF515N internal	0	0	1	40	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	4000[2];18000[1];20000[2]; 2000[4], 200C0000;
2539	Spansion	MB9BF515R internal	0	0	1	40	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	4000[2];18000[1];20000[2]; 2000[4], 200C0000;
2540	Spansion	MB9BF516N internal	0	0	1	40	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	4000[2];18000[1];20000[3]; 2000[4], 200C0000;
2541	Spansion	MB9BF516R internal	0	0	1	40	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	4000[2];18000[1];20000[3]; 2000[4], 200C0000;
2542	Spansion	MB9BF516S internal	0	0	1	40	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	4000[2];18000[1];20000[3];
2543	Spansion	MB9BF516T internal	0	0	1	40	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	4000[2];18000[1];20000[3];
2544	Spansion	MB9BF517S internal	0	0	1	40	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	4000[2];18000[1];20000[5];
2545	Spansion	MB9BF517T internal	0	0	1	40	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	4000[2];18000[1];20000[5];
2546	Spansion	MB9BF518S internal	0	0	1	40	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	4000[2];18000[1];20000[7];
2547	Spansion	MB9BF518T internal	0	0	1	40	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	4000[2];18000[1];20000[7];
2548	Spansion	MB9BF521K internal	0	0	1	40	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[2];C000[1]; 2000[4], 200000;
2549	Spansion	MB9BF521L internal	0	0	1	40	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[2];C000[1]; 2000[4], 200000;
2550	Spansion	MB9BF521M internal	0	0	1	40	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[2];C000[1]; 2000[4], 200000;
2551	Spansion	MB9BF522K internal	0	0	1	40	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[2];C000[1];10000[1]; 2000[4], 200000;
2552	Spansion	MB9BF522L internal	0	0	1	40	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[2];C000[1];10000[1]; 2000[4], 200000;
2553	Spansion	MB9BF522M internal	0	0	1	40	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[2];C000[1];10000[1]; 2000[4], 200000;
2554	Spansion	MB9BF524K internal	0	0	1	40	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[2];C000[1];10000[3]; 2000[4], 200000;
2555	Spansion	MB9BF524L internal	0	0	1	40	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[2];C000[1];10000[3]; 2000[4], 200000;
2556	Spansion	MB9BF524M internal	0	0	1	40	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[2];C000[1];10000[3]; 2000[4], 200000;
2557	Spansion	MB9BF528S internal	0	0	1	40	3	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[2];C000[1]; 10000[15]; 2000[8], 00508000;
2558	Spansion	MB9BF528T internal	0	0	1	40	3	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[2];C000[1]; 10000[15]; 2000[8], 00508000;
2559	Spansion	MB9BF529S internal	0	0	1	40	3	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[2];C000[1]; 10000[23]; 2000[8], 00508000;
2560	Spansion	MB9BF529T internal	0	0	1	40	3	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[2];C000[1]; 10000[23]; 2000[8], 00508000;
2561	Spansion	MB9BF564K internal	0	0	1	40	2	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[4];8000[1];10000[7]; 2000[4], 200C0000;
2562	Spansion	MB9BF564L internal	0	0	1	40	2	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[4];8000[1];10000[7]; 2000[4], 200C0000;
2563	Spansion	MB9BF565K internal	0	0	1	40	2	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[4];8000[1];10000[7]; 2000[4], 200C0000;
2564	Spansion	MB9BF565L internal	0	0	1	40	2	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[4];8000[1];10000[7]; 2000[4], 200C0000;
2565	Spansion	MB9BF566K internal	0	0	1	40	2	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[4];8000[1];10000[7]; 2000[4], 200C0000;
2566	Spansion	MB9BF566L internal	0	0	1	40	2	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[4];8000[1];10000[7]; 2000[4], 200C0000;
2567	Spansion	MB9BF566M internal	0	0	1	40	2	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[4];8000[1];10000[7]; 2000[4], 200C0000;
2568	Spansion	MB9BF566N internal	0	0	1	40	2	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[4];8000[1];10000[7]; 2000[4], 200C0000;
2569	Spansion	MB9BF566R internal	0	0	1	40	2	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[4];8000[1];10000[7]; 2000[4], 200C0000;
2570	Spansion	MB9BF567M internal	0	0	1	40	2	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[4];8000[1];10000[11]; 2000[4], 200C0000;
2571	Spansion	MB9BF567N internal	0	0	1	40	2	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[4];8000[1];10000[11]; 2000[4], 200C0000;
2572	Spansion	MB9BF567R internal	0	0	1	40	2	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[4];8000[1];10000[11]; 2000[4], 200C0000;
2573	Spansion	MB9BF568M internal	0	0	1	40	2	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[4];8000[1];10000[15]; 2000[4], 200C0000;
2574	Spansion	MB9BF568N internal	0	0	1	40	2	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[4];8000[1];10000[15]; 2000[4], 200C0000;
2575	Spansion	MB9BF568R internal	0	0	1	40	2	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[4];8000[1];10000[15]; 2000[4], 200C0000;
2576	Spansion	MB9BF616S internal	0	0	1	40	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	4000[2];18000[1];20000[3];
2577	Spansion	MB9BF616T internal	0	0	1	40	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	4000[2];18000[1];20000[3];
2578	Spansion	MB9BF617S internal	0	0	1	40	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	4000[2];18000[1];20000[5];
2579	Spansion	MB9BF617T internal	0	0	1	40	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	4000[2];18000[1];20000[5];
2580	Spansion	MB9BF618S internal	0	0	1	40	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	4000[2];18000[1];20000[7];
2581	Spansion	MB9BF618T internal	0	0	1	40	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	4000[2];18000[1];20000[7];
2582	Spansion	MB9BFD16S internal	0	0	1	40	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	4000[2];18000[1];20000[3];
2583	Spansion	MB9BFD16T internal	0	0	1	40	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	4000[2];18000[1];20000[3];
2584	Spansion	MB9BFD17S internal	0	0	1	40	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	4000[2];18000[1];20000[5];
2585	Spansion	MB9BFD17T internal	0	0	1	40	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	4000[2];18000[1];20000[5];
2586	Spansion	MB9BFD18S internal	0	0	1	40	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	4000[2];18000[1];20000[7];
2587	Spansion	MB9BFD18T internal	0	0	1	40	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	4000[2];18000[1];20000[7];
2588	Spansion	MBM29DL322BE/BD	42256	40056	0	1	0	16	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[8]; 10000[63];
2589	Spansion	MBM29DL322TE/TD	42255	40055	0	1	0	16	1	0	0	0	0	0	0	0	0	0	0	0	0	10000[63]; 2000[8];
2590	Spansion	MBM29LV160B	042249	040049	0	1	0	16	1	0	0	0	0	0	0	0	0	0	0	0	0	4000; 2000[2]; 8000; 10000[31];
2591	Spansion	MBM29LV160T	0422C4	0400C4	0	1	0	16	1	0	0	0	0	0	0	0	0	0	0	0	0	10000[31]; 8000; 2000[2]; 4000;
2592	Spansion	MBM29LV650U	0422D7	0400D7	0	1	0	16	1	0	0	0	0	0	0	0	0	0	0	0	0	10000[128];
2593	Spansion	S6E1A11B0A internal	0	0	1	40	4	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[3];8000[1];
2594	Spansion	S6E1A11C0A internal	0	0	1	40	4	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[3];8000[1];
2595	Spansion	S6E1A12B0A internal	0	0	1	40	4	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[3];8000[2];
2596	Spansion	S6E1A12C0A internal	0	0	1	40	4	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[3];8000[2];
2597	Spansion	S29AL008Jxxxxx01	0122DA	0100DA	0	1	0	16	1	0	0	0	0	0	0	0	0	0	0	0	0	10000[15]; 8000; 2000[2]; 4000;
2598	Spansion	S29AL008Jxxxxx02	01225B	01005B	0	1	0	16	1	0	0	0	0	0	0	0	0	0	0	0	0	4000; 2000[2]; 8000; 10000[15];
2599	Spansion	S29AL008Dxxxxxx1	0122DA	0100DA	0	1	0	16	1	0	0	0	0	0	0	0	0	0	0	0	0	10000[15]; 8000; 2000[2]; 4000;
2600	Spansion	S29AL008Dxxxxxx2	01225B	01005B	0	1	0	16	1	0	0	0	0	0	0	0	0	0	0	0	0	4000; 2000[2]; 8000; 10000[15];
2601	Spansion	S29AL016Dxxxxxx1	0122C4	0100C4	0	1	0	16	1	0	0	0	0	0	0	0	0	0	0	0	0	10000[31]; 8000; 2000[2]; 4000;
2602	Spansion	S29AL016Dxxxxxx2	012249	010049	0	1	0	16	1	0	0	0	0	0	0	0	0	0	0	0	0	4000; 2000[2]; 8000; 10000[31];
2603	Spansion	S29AL016Jxxxxxx1	0122C4	0100C4	0	1	0	16	1	0	0	0	0	0	0	0	0	0	0	0	0	10000[31]; 8000; 2000[2]; 4000;
2604	Spansion	S29AL016Jxxxxxx2	012249	010049	0	1	0	16	1	0	0	0	0	0	0	0	0	0	0	0	0	4000; 2000[2]; 8000; 10000[31];
2605	Spansion	S29AL016Jxxxxxx3	0122C4	0100C4	0	1	0	16	1	0	0	0	0	0	0	0	0	0	0	0	0	10000[31]; 8000; 2000[2]; 4000;
2606	Spansion	S29AL016Jxxxxxx4	012249	010049	0	1	0	16	1	0	0	0	0	0	0	0	0	0	0	0	0	4000; 2000[2]; 8000; 10000[31];
2607	Spansion	S29AL032Dxxxxxx0	0122A3	0100A3	0	1	0	16	1	0	0	0	0	0	0	0	0	0	0	0	0	10000[64];
2608	Spansion	S29AL032Dxxxxxx3	0122F6	0100F6	0	1	0	16	1	0	0	0	0	0	0	0	0	0	0	0	0	10000[63]; 2000[8];
2609	Spansion	S29AL032Dxxxxxx4	0122F9	0100F9	0	1	0	16	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[8]; 10000[63];
2610	Spansion	S29GL01GP	01227E	01007E	0	16	0	16	1	0	0	0	0	0	0	0	0	0	0	0	0	20000[1024];
2611	Spansion	S29GL01GS	01227E	01007E	0	16	0	16	1	0	0	0	0	0	0	0	0	0	0	0	0	20000[1024];
2612	Spansion	S29GL032AxR1	01227E	01007E	0	16	0	16	1	0	0	0	0	0	0	0	0	0	0	0	0	10000[64];
2613	Spansion	S29GL032AxR2	01227E	01007E	0	16	0	16	1	0	0	0	0	0	0	0	0	0	0	0	0	10000[64];
2614	Spansion	S29GL032AxR3	01227E	01007E	0	16	0	16	1	0	0	0	0	0	0	0	0	0	0	0	0	10000[63]; 2000[8];
2615	Spansion	S29GL032AxR4	01227E	01007E	0	16	0	16	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[8]; 10000[63];
2616	Spansion	S29GL032AxW3	01227E	01007E	0	16	0	16	1	0	0	0	0	0	0	0	0	0	0	0	0	10000[63]; 2000[8];
2617	Spansion	S29GL032AxW4	01227E	01007E	0	16	0	16	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[8]; 10000[63];
2618	Spansion	S29GL032MxR0	01227E	01007E	0	16	0	8	1	0	0	0	0	0	0	0	0	0	0	0	0	10000[64];
2619	Spansion	S29GL032MxR1	01227E	01007E	0	16	0	16	1	0	0	0	0	0	0	0	0	0	0	0	0	10000[64];
2620	Spansion	S29GL032MxR2	01227E	01007E	0	16	0	16	1	0	0	0	0	0	0	0	0	0	0	0	0	10000[64];
2621	Spansion	S29GL032MxR3	01227E	01007E	0	16	0	16	1	0	0	0	0	0	0	0	0	0	0	0	0	10000[63]; 2000[8];
2622	Spansion	S29GL032MxR4	01227E	01007E	0	16	0	16	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[8]; 10000[63];
2623	Spansion	S29GL032MxR5	01227E	01007E	0	16	0	16	1	0	0	0	0	0	0	0	0	0	0	0	0	10000[63]; 2000[8];
2624	Spansion	S29GL032MxR6	01227E	01007E	0	16	0	16	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[8]; 10000[63];
2625	Spansion	S29GL032Nxxxxx01	01227E	01007E	0	1	0	16	1	0	0	0	0	0	0	0	0	0	0	0	0	10000[64];
2626	Spansion	S29GL032Nxxxxx02	01227E	01007E	0	1	0	16	1	0	0	0	0	0	0	0	0	0	0	0	0	10000[64];
2627	Spansion	S29GL032Nxxxxx03	01227E	01007E	0	1	0	16	1	0	0	0	0	0	0	0	0	0	0	0	0	10000[63]; 2000[8];
2628	Spansion	S29GL032Nxxxxx04	01227E	01007E	0	1	0	16	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[8]; 10000[63];
2629	Spansion	S29GL032NxxxxxV1	01227E	01007E	0	1	0	16	1	0	0	0	0	0	0	0	0	0	0	0	0	10000[64];
2630	Spansion	S29GL032NxxxxxV2	01227E	01007E	0	1	0	16	1	0	0	0	0	0	0	0	0	0	0	0	0	10000[64];
2631	Spansion	S29GL064MxR0	01227E	01007E	0	16	0	8	1	0	0	0	0	0	0	0	0	0	0	0	0	10000[128];
2632	Spansion	S29GL064MxR1	01227E	01007E	0	16	0	16	1	0	0	0	0	0	0	0	0	0	0	0	0	10000[128];
2633	Spansion	S29GL064MxR2	01227E	01007E	0	16	0	16	1	0	0	0	0	0	0	0	0	0	0	0	0	10000[128];
2634	Spansion	S29GL064MxR3	01227E	01007E	0	16	0	16	1	0	0	0	0	0	0	0	0	0	0	0	0	10000[127]; 2000[8];
2635	Spansion	S29GL064MxR4	01227E	01007E	0	16	0	16	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[8]; 10000[127];
2636	Spansion	S29GL064MxR5	01227E	01007E	0	16	0	16	1	0	0	0	0	0	0	0	0	0	0	0	0	10000[128];
2637	Spansion	S29GL064MxR6	01227E	01007E	0	16	0	16	1	0	0	0	0	0	0	0	0	0	0	0	0	10000[128];
2638	Spansion	S29GL064MxR7	01227E	01007E	0	16	0	16	1	0	0	0	0	0	0	0	0	0	0	0	0	10000[128];
2639	Spansion	S29GL064MxR8	01227E	01007E	0	16	0	16	1	0	0	0	0	0	0	0	0	0	0	0	0	10000[128];
2640	Spansion	S29GL064MxR9	01227E	01007E	0	16	0	16	1	0	0	0	0	0	0	0	0	0	0	0	0	10000[128];
2641	Spansion	S29GL064Nxxxxx01	01227E	01007E	0	1	0	16	1	0	0	0	0	0	0	0	0	0	0	0	0	10000[128];
2642	Spansion	S29GL064Nxxxxx02	01227E	01007E	0	1	0	16	1	0	0	0	0	0	0	0	0	0	0	0	0	10000[128];
2643	Spansion	S29GL064Nxxxxx03	01227E	01007E	0	1	0	16	1	0	0	0	0	0	0	0	0	0	0	0	0	10000[127]; 2000[8];
2644	Spansion	S29GL064Nxxxxx04	01227E	01007E	0	1	0	16	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[8]; 10000[127];
2645	Spansion	S29GL064Nxxxxx06	01227E	01007E	0	1	0	16	1	0	0	0	0	0	0	0	0	0	0	0	0	10000[128];
2646	Spansion	S29GL064Nxxxxx07	01227E	01007E	0	1	0	16	1	0	0	0	0	0	0	0	0	0	0	0	0	10000[128];
2647	Spansion	S29GL064NxxxxxV1	01227E	01007E	0	1	0	16	1	0	0	0	0	0	0	0	0	0	0	0	0	10000[128];
2648	Spansion	S29GL064NxxxxxV2	01227E	01007E	0	1	0	16	1	0	0	0	0	0	0	0	0	0	0	0	0	10000[128];
2649	Spansion	S29GL064NxxxxxV6	01227E	01007E	0	1	0	16	1	0	0	0	0	0	0	0	0	0	0	0	0	10000[128];
2650	Spansion	S29GL064NxxxxxV7	01227E	01007E	0	1	0	16	1	0	0	0	0	0	0	0	0	0	0	0	0	10000[128];
2651	Spansion	S29GL128M	01227E	01007E	0	16	0	16	1	0	0	0	0	0	0	0	0	0	0	0	0	10000[256];
2652	Spansion	S29GL128N	01227E	01007E	0	16	0	16	1	0	0	0	0	0	0	0	0	0	0	0	0	20000[128];
2653	Spansion	S29GL128P	01227E	01007E	0	16	0	16	1	0	0	0	0	0	0	0	0	0	0	0	0	20000[128];
2654	Spansion	S29GL128S	01227E	01007E	0	16	0	16	1	0	0	0	0	0	0	0	0	0	0	0	0	20000[128];
2655	Spansion	S29GL256M	01227E	01007E	0	16	0	16	1	0	0	0	0	0	0	0	0	0	0	0	0	10000[512];
2656	Spansion	S29GL256N	01227E	01007E	0	16	0	16	1	0	0	0	0	0	0	0	0	0	0	0	0	20000[256];
2657	Spansion	S29GL256P	01227E	01007E	0	16	0	16	1	0	0	0	0	0	0	0	0	0	0	0	0	20000[256];
2658	Spansion	S29GL256S	01227E	01007E	0	16	0	16	1	0	0	0	0	0	0	0	0	0	0	0	0	20000[256];
2659	Spansion	S29GL512N	01227E	01007E	0	16	0	16	1	0	0	0	0	0	0	0	0	0	0	0	0	20000[512];
2660	Spansion	S29GL512P	01227E	01007E	0	16	0	16	1	0	0	0	0	0	0	0	0	0	0	0	0	20000[512];
2661	Spansion	S29GL512S	01227E	01007E	0	16	0	16	1	0	0	0	0	0	0	0	0	0	0	0	0	20000[512];
2662	Spansion	S29JL032Hxxxxxx1	01227E	01007E	0	1	0	16	1	0	0	0	0	0	0	0	0	0	0	0	0	10000[63]; 2000[8];
2663	Spansion	S29JL032Hxxxxxx2	01227E	01007E	0	1	0	16	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[8]; 10000[63];
2664	Spansion	S29JL064Hxxxxx00	01227E	01007E	0	1	0	16	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[8]; 10000[126]; 2000[8];
2665	Spansion	S29PL032J	01227E	01007E	0	1	0	16	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[8]; 10000[62]; 2000[8];
2666	Spansion	S29PL064J	01227E	01007E	0	1	0	16	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[8]; 10000[126]; 2000[8];
2667	Spansion	S29PL127J	01227E	01007E	0	1	0	16	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[8]; 10000[254]; 2000[8];
2668	Spansion	S29WS064J	01227E	01007E	0	1	0	16	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[8]; 10000[126]; 2000[8];
2669	Spansion	S29WS128J	01227E	01007E	0	1	0	16	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[8]; 10000[254]; 2000[8];
2670	Spansion	S29WS128N	01227E	01007E	0	16	0	16	1	0	0	0	0	0	0	0	0	0	0	0	0	8000[4]; 20000[126]; 8000[4];
2671	Spansion	S29WS256N	01227E	01007E	0	16	0	16	1	0	0	0	0	0	0	0	0	0	0	0	0	8000[4]; 20000[254]; 8000[4];
2672	Spansion	S29WS128P	01227E	01007E	0	16	0	16	1	0	0	0	0	0	0	0	0	0	0	0	0	8000[4]; 20000[126]; 8000[4];
2673	Spansion	S29WS256P	01227E	01007E	0	16	0	16	1	0	0	0	0	0	0	0	0	0	0	0	0	8000[4]; 20000[254]; 8000[4];
2674	Spansion	S29WS512P	01227E	01007E	0	16	0	16	1	0	0	0	0	0	0	0	0	0	0	0	0	8000[4]; 20000[510]; 8000[4];
2675	Spansion	S6E2CC8 internal	0	0	1	40	6	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[4];8000[1];10000[15];2000[8], 00400000;
2676	Spansion	S6E2CC9 internal	0	0	1	40	6	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[4];8000[1];10000[15];2000[4];8000[1];10000[7];2000[8], 00400000;
2677	Spansion	S6E2CCA internal	0	0	1	40	6	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[4];8000[1];10000[15];2000[4];8000[1];10000[15];2000[8], 00400000;
2678	Spansion	S71PL032J	01227E	01007E	0	1	0	16	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[8]; 10000[62]; 2000[8];
2679	Spansion	S71PL064J	01227E	01007E	0	1	0	16	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[8]; 10000[126]; 2000[8];
2680	Spansion	S71PL127J	01227E	01007E	0	1	0	16	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[8]; 10000[254]; 2000[8];
2681	SST	SST32HF64A2	BF236C	BF006C	0	1	0	16	1	0	0	0	0	0	0	0	0	0	0	0	0	1000[2048];
2682	SST	SST32HF162	BF2782	BF0082	0	1	0	16	1	0	0	0	0	0	0	0	0	0	0	0	0	1000[256];
2683	SST	SST32HF164	BF2782	BF0082	0	1	0	16	1	0	0	0	0	0	0	0	0	0	0	0	0	1000[256];
2684	SST	SST32HF802	BF2781	BF0081	0	1	0	16	1	0	0	0	0	0	0	0	0	0	0	0	0	1000[512];
2685	SST	SST36VF3203	BF7354	BF0054	0	1	0	16	1	0	0	0	0	0	0	0	0	0	0	0	0	10000[64];
2686	SST	SST36VF3204	BF7353	BF0053	0	1	0	16	1	0	0	0	0	0	0	0	0	0	0	0	0	10000[64];
2687	SST	SST39LF200A	BF2789	BF0089	0	1	0	16	1	0	0	0	0	0	0	0	0	0	0	0	0	1000[64];
2688	SST	SST39LF400A	BF2780	BF0080	0	1	0	16	1	0	0	0	0	0	0	0	0	0	0	0	0	1000[128];
2689	SST	SST39LF800A	BF2781	BF0081	0	1	0	16	1	0	0	0	0	0	0	0	0	0	0	0	0	1000[256];
2690	SST	SST39LF160	BF2782	BF0082	0	1	0	16	1	0	0	0	0	0	0	0	0	0	0	0	0	1000[512];
2691	SST	SST39VF160	BF2782	BF0082	0	1	0	16	1	0	0	0	0	0	0	0	0	0	0	0	0	1000[512];
2692	SST	SST39VF1601	BF234B	BF004B	0	1	0	16	1	0	0	0	0	0	0	0	0	0	0	0	0	1000[512];
2693	SST	SST39VF1602	BF234A	BF004A	0	1	0	16	1	0	0	0	0	0	0	0	0	0	0	0	0	1000[512];
2694	SST	SST39VF1681	BF00C8	BF00C8	0	1	0	8	1	0	0	0	0	0	0	0	0	0	0	0	0	10000[32];
2695	SST	SST39VF1682	BF00C9	BF00C9	0	1	0	8	1	0	0	0	0	0	0	0	0	0	0	0	0	10000[32];
2696	SST	SST39VF200A	BF2789	BF0089	0	1	0	16	1	0	0	0	0	0	0	0	0	0	0	0	0	1000[64];
2697	SST	SST39VF3201	BF235B	BF005B	0	1	0	16	1	0	0	0	0	0	0	0	0	0	0	0	0	1000[1024];
2698	SST	SST39VF3202	BF235A	BF005A	0	1	0	16	1	0	0	0	0	0	0	0	0	0	0	0	0	1000[1024];
2699	SST	SST39VF400A	BF2780	BF0080	0	1	0	16	1	0	0	0	0	0	0	0	0	0	0	0	0	1000[128];
2700	SST	SST39VF6401	BF236B	BF006B	0	1	0	16	1	0	0	0	0	0	0	0	0	0	0	0	0	1000[2048];
2701	SST	SST39VF6401B	BF236D	BF006D	0	1	0	16	1	0	0	0	0	0	0	0	0	0	0	0	0	1000[2048];
2702	SST	SST39VF6402	BF236A	BF006A	0	1	0	16	1	0	0	0	0	0	0	0	0	0	0	0	0	1000[2048];
2703	SST	SST39VF6402B	BF236C	BF006C	0	1	0	16	1	0	0	0	0	0	0	0	0	0	0	0	0	1000[2048];
2704	SST	SST39VF800A	BF2781	BF0081	0	1	0	16	1	0	0	0	0	0	0	0	0	0	0	0	0	1000[256];
2705	ST	STCOMET05 internal	0	0	1	97	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	4000[2]; 8000[2]; 4000[2]; 10000[2]; 20000[2]; 20000[1], E0000;
2706	ST	STCOMET10 internal	0	0	1	97	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	4000[2]; 8000[2]; 4000[2]; 10000[2]; 20000[6];
2707	ST	LIS331EB internal	0	0	1	75	0	32	1	1	0	0	0	0	0	0	0	0	0	0	0	800[32];
2708	ST	M28W320FCB	2088BB	2000BB	0	2	0	16	1	0	0	1	0	0	0	0	0	0	1	0	0	2000[8]; 10000[63];
2709	ST	M28W320FCT	2088BA	2000BA	0	2	0	16	1	0	0	1	0	0	0	0	0	0	1	0	0	10000[63]; 2000[8];
2710	ST	M28W320FSB	20880B	20000B	0	2	0	16	1	0	0	1	0	0	0	0	0	0	1	0	0	2000[8]; 10000[63];
2711	ST	M28W320FST	20880A	20000A	0	2	0	16	1	0	0	1	0	0	0	0	0	0	1	0	0	10000[63]; 2000[8];
2712	ST	M28W640ECB	208849	200049	0	2	0	16	1	0	0	1	0	0	0	0	0	0	1	0	0	2000[8]; 10000[127];
2713	ST	M28W640ECT	208848	200048	0	2	0	16	1	0	0	1	0	0	0	0	0	0	1	0	0	10000[127]; 2000[8];
2714	ST	M28W640FCB	208849	200049	0	2	0	16	1	0	0	1	0	0	0	0	0	0	1	0	0	2000[8]; 10000[127];
2715	ST	M28W640FCT	208848	200048	0	2	0	16	1	0	0	1	0	0	0	0	0	0	1	0	0	10000[127]; 2000[8];
2716	ST	M28W640FSB	208859	200059	0	2	0	16	1	0	0	1	0	0	0	0	0	0	1	0	0	2000[8]; 10000[127];
2717	ST	M28W640FST	208858	200058	0	2	0	16	1	0	0	1	0	0	0	0	0	0	1	0	0	10000[127]; 2000[8];
2718	ST	M29DW128F	20227E	20007E	0	1	0	16	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[8]; 10000[254]; 2000[8];
2719	ST	M29DW323DB	20225F	20005F	0	1	0	16	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[8]; 10000[63];
2720	ST	M29DW323DT	20225E	20005E	0	1	0	16	1	0	0	0	0	0	0	0	0	0	0	0	0	10000[63]; 2000[8];
2721	ST	M29DW324DB	20225D	20005D	0	1	0	16	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[8]; 10000[63];
2722	ST	M29DW324DT	20225C	20005C	0	1	0	16	1	0	0	0	0	0	0	0	0	0	0	0	0	10000[63]; 2000[8];
2723	ST	M29DW640D	20227E	20007E	0	1	0	16	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[8]; 10000[126]; 2000[8];
2724	ST	M29DW641F	20227E	20007E	0	1	0	16	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[8]; 10000[126]; 2000[8];
2725	ST	M29W128FH	20227E	20007E	0	1	0	16	1	0	0	0	0	0	0	0	0	0	0	0	0	10000[256];
2726	ST	M29W128FL	20227E	20007E	0	1	0	16	1	0	0	0	0	0	0	0	0	0	0	0	0	10000[256];
2727	ST	M29W160DB	202249	200049	0	1	0	16	1	0	0	0	0	0	0	0	0	0	0	0	0	4000; 2000[2]; 8000; 10000[31];
2728	ST	M29W160DT	2022C4	2000C4	0	1	0	16	1	0	0	0	0	0	0	0	0	0	0	0	0	10000[31]; 8000; 2000[2]; 4000;
2729	ST	M29W160EB	202249	200049	0	1	0	16	1	0	0	0	0	0	0	0	0	0	0	0	0	4000; 2000[2]; 8000; 10000[31];
2730	ST	M29W160ET	2022C4	2000C4	0	1	0	16	1	0	0	0	0	0	0	0	0	0	0	0	0	10000[31]; 8000; 2000[2]; 4000;
2731	ST	M29W200BB	200057	200057	0	1	0	16	1	0	0	0	0	0	0	0	0	0	0	0	0	4000; 2000[2]; 8000; 10000[3];
2732	ST	M29W200BT	200051	200051	0	1	0	16	1	0	0	0	0	0	0	0	0	0	0	0	0	10000[3]; 8000; 2000[2]; 4000;
2733	ST	M29W320DB	2022CB	2000CB	0	1	0	16	1	0	0	0	0	0	0	0	0	0	0	0	0	4000; 2000[2]; 8000; 10000[63];
2734	ST	M29W320DT	2022CA	2000CA	0	1	0	16	1	0	0	0	0	0	0	0	0	0	0	0	0	10000[63]; 8000; 2000[2]; 4000;
2735	ST	M29W320EB	202257	200057	0	1	0	16	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[8]; 10000[63];
2736	ST	M29W320ET	202256	200056	0	1	0	16	1	0	0	0	0	0	0	0	0	0	0	0	0	10000[63]; 2000[8];
2737	ST	M29W400BB	2000EF	2000EF	0	1	0	16	1	0	0	0	0	0	0	0	0	0	0	0	0	4000; 2000[2]; 8000; 10000[7];
2738	ST	M29W400BT	2000EE	2000EE	0	1	0	16	1	0	0	0	0	0	0	0	0	0	0	0	0	10000[7]; 8000; 2000[2]; 4000;
2739	ST	M29W400DB	2000EF	2000EF	0	1	0	16	1	0	0	0	0	0	0	0	0	0	0	0	0	4000; 2000[2]; 8000; 10000[7];
2740	ST	M29W400DT	2000EE	2000EE	0	1	0	16	1	0	0	0	0	0	0	0	0	0	0	0	0	10000[7]; 8000; 2000[2]; 4000;
2741	ST	M29W640DB	2022DF	2000DF	0	1	0	16	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[8]; 10000[127];
2742	ST	M29W640DT	2022DE	2000DE	0	1	0	16	1	0	0	0	0	0	0	0	0	0	0	0	0	10000[127]; 2000[8];
2743	ST	M29W640FB	2022FD	2000FD	0	1	0	16	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[8]; 10000[127];
2744	ST	M29W640FT	2022ED	2000ED	0	1	0	16	1	0	0	0	0	0	0	0	0	0	0	0	0	10000[127]; 2000[8];
2745	ST	M29W800DB	20225B	20005B	0	1	0	16	1	0	0	0	0	0	0	0	0	0	0	0	0	4000; 2000[2]; 8000; 10000[15];
2746	ST	M29W800DT	2022D7	2000D7	0	1	0	16	1	0	0	0	0	0	0	0	0	0	0	0	0	10000[15]; 8000; 2000[2]; 4000;
2747	ST	M36W0R5040B5	208815	200015	0	2	0	16	1	0	0	0	0	0	0	0	0	0	0	0	0	10000[63]; 2000[8];
2748	ST	M36W0R5040T5	208814	200014	0	2	0	16	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[8]; 10000[63];
2749	ST	M36W0R6040B1	208811	200011	0	2	0	16	1	0	0	0	0	0	0	0	0	0	0	0	0	10000[127]; 2000[8];
2750	ST	M36W0R6040B3	208811	200011	0	2	0	16	1	0	0	0	0	0	0	0	0	0	0	0	0	10000[127]; 2000[8];
2751	ST	M36W0R6040T1	208810	200010	0	2	0	16	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[8]; 10000[127];
2752	ST	M36W0R6040T3	208810	200010	0	2	0	16	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[8]; 10000[127];
2753	ST	M36W0R6050B3	208811	200011	0	2	0	16	1	0	0	0	0	0	0	0	0	0	0	0	0	10000[127]; 2000[8];
2754	ST	M36W0R6050T3	208810	200010	0	2	0	16	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[8]; 10000[127];
2755	ST	M58WR016KB	208813	200013	0	1	0	16	1	0	0	0	0	0	0	0	0	0	0	0	0	10000[31]; 2000[8];
2756	ST	M58WR016KT	208812	200012	0	1	0	16	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[8]; 10000[31];
2757	ST	M58WR032KB	208815	200015	0	1	0	16	1	0	0	0	0	0	0	0	0	0	0	0	0	10000[63]; 2000[8];
2758	ST	M58WR032KT	208814	200014	0	1	0	16	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[8]; 10000[63];
2759	ST	M58WR064HB	208811	200011	0	1	0	16	1	0	0	0	0	0	0	0	0	0	0	0	0	10000[127]; 2000[8];
2760	ST	M58WR064HT	208810	200010	0	1	0	16	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[8]; 10000[127];
2761	ST	M58WR064KB	208811	200011	0	1	0	16	1	0	0	0	0	0	0	0	0	0	0	0	0	10000[127]; 2000[8];
2762	ST	M58WR064KT	208810	200010	0	1	0	16	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[8]; 10000[127];
2763	ST	M58LW064D	200017	200017	0	10	0	16	1	0	0	1	0	1	0	0	0	0	0	0	0	20000[64];
2764	ST	SPC5605B internal	0	0	1	38	0	32	1	1	0	0	0	0	0	0	0	0	0	0	0	8000; 4000[2]; 8000[2]; 20000[5]; 4000[4], 800000;
2765	ST	SPC5605B (allow shadow) internal	0	0	1	38	1	32	1	1	0	0	0	0	0	0	0	0	0	0	0	8000; 4000[2]; 8000[2]; 20000[5]; 4000[1], 200000; 4000[4], 800000;
2766	ST	SPC5606B internal	0	0	1	38	0	32	1	1	0	0	0	0	0	0	0	0	0	0	0	8000; 4000[2]; 8000[2]; 20000[7]; 4000[4], 800000;
2767	ST	SPC5606B (allow shadow) internal	0	0	1	38	1	32	1	1	0	0	0	0	0	0	0	0	0	0	0	8000; 4000[2]; 8000[2]; 20000[7]; 4000[1], 200000; 4000[4], 800000;
2768	ST	SPC5607B internal	0	0	1	38	0	32	1	1	0	0	0	0	0	0	0	0	0	0	0	8000; 4000[2]; 8000[2]; 20000[11]; 4000[4], 800000;
2769	ST	SPC5607B (allow shadow) internal	0	0	1	38	1	32	1	1	0	0	0	0	0	0	0	0	0	0	0	8000; 4000[2]; 8000[2]; 20000[11]; 4000[1], 200000; 4000[4], 800000;
2770	ST	SPC560B40 internal	0	0	1	38	0	32	1	1	0	0	0	0	0	0	0	0	0	0	0	8000; 4000[2]; 8000[2]; 20000; 4000[4], 800000;
2771	ST	SPC560B40 (allow shadow) internal	0	0	1	38	1	32	1	1	0	0	0	0	0	0	0	0	0	0	0	8000; 4000[2]; 8000[2]; 20000; 4000[1], 200000; 4000[4], 800000;
2772	ST	SPC560B44 internal	0	0	1	38	0	32	1	1	0	0	0	0	0	0	0	0	0	0	0	8000; 4000[2]; 8000[2]; 20000[2]; 4000[4], 800000;
2773	ST	SPC560B44 (allow shadow) internal	0	0	1	38	1	32	1	1	0	0	0	0	0	0	0	0	0	0	0	8000; 4000[2]; 8000[2]; 20000[2]; 4000[1], 200000; 4000[4], 800000;
2774	ST	SPC560B50 internal	0	0	1	38	0	32	1	1	0	0	0	0	0	0	0	0	0	0	0	8000; 4000[2]; 8000[2]; 20000[3]; 4000[4], 800000;
2775	ST	SPC560B50 (allow shadow) internal	0	0	1	38	1	32	1	1	0	0	0	0	0	0	0	0	0	0	0	8000; 4000[2]; 8000[2]; 20000[3]; 4000[1], 200000; 4000[4], 800000;
2776	ST	SPC560B54 internal	0	0	1	38	0	32	1	1	0	0	0	0	0	0	0	0	0	0	0	8000; 4000[2]; 8000[2]; 20000[5]; 4000[4], 800000;
2777	ST	SPC560B54 (allow shadow) internal	0	0	1	38	1	32	1	1	0	0	0	0	0	0	0	0	0	0	0	8000; 4000[2]; 8000[2]; 20000[5]; 4000[1], 200000; 4000[4], 800000;
2778	ST	SPC560B60 internal	0	0	1	38	0	32	1	1	0	0	0	0	0	0	0	0	0	0	0	8000; 4000[2]; 8000[2]; 20000[7]; 4000[4], 800000;
2779	ST	SPC560B60 (allow shadow) internal	0	0	1	38	1	32	1	1	0	0	0	0	0	0	0	0	0	0	0	8000; 4000[2]; 8000[2]; 20000[7]; 4000[1], 200000; 4000[4], 800000;
2780	ST	SPC560B64 internal	0	0	1	38	0	32	1	1	0	0	0	0	0	0	0	0	0	0	0	8000; 4000[2]; 8000[2]; 20000[11]; 4000[4], 800000;
2781	ST	SPC560B64 (allow shadow) internal	0	0	1	38	1	32	1	1	0	0	0	0	0	0	0	0	0	0	0	8000; 4000[2]; 8000[2]; 20000[11]; 4000[1], 200000; 4000[4], 800000;
2782	ST	SPC560C40 internal	0	0	1	38	0	32	1	1	0	0	0	0	0	0	0	0	0	0	0	8000; 4000[2]; 8000[2]; 20000; 4000[4], 800000;
2783	ST	SPC560C40 (allow shadow) internal	0	0	1	38	1	32	1	1	0	0	0	0	0	0	0	0	0	0	0	8000; 4000[2]; 8000[2]; 20000; 4000[1], 200000; 4000[4], 800000;
2784	ST	SPC560C44 internal	0	0	1	38	0	32	1	1	0	0	0	0	0	0	0	0	0	0	0	8000; 4000[2]; 8000[2]; 20000[2]; 4000[4], 800000;
2785	ST	SPC560C44 (allow shadow) internal	0	0	1	38	1	32	1	1	0	0	0	0	0	0	0	0	0	0	0	8000; 4000[2]; 8000[2]; 20000[2]; 4000[1], 200000; 4000[4], 800000;
2786	ST	SPC560C50 internal	0	0	1	38	0	32	1	1	0	0	0	0	0	0	0	0	0	0	0	8000; 4000[2]; 8000[2]; 20000[3]; 4000[4], 800000;
2787	ST	SPC560C50 (allow shadow) internal	0	0	1	38	1	32	1	1	0	0	0	0	0	0	0	0	0	0	0	8000; 4000[2]; 8000[2]; 20000[3]; 4000[1], 200000; 4000[4], 800000;
2788	ST	SPC560D30 internal	0	0	1	38	0	32	1	1	0	0	0	0	0	0	0	0	0	0	0	8000; 4000[2]; 8000[2]; 4000[4], 800000;
2789	ST	SPC560D30 (allow shadow) internal	0	0	1	38	1	32	1	1	0	0	0	0	0	0	0	0	0	0	0	8000; 4000[2]; 8000[2]; 4000[1], 200000; 4000[4], 800000;
2790	ST	SPC560D40 internal	0	0	1	38	0	32	1	1	0	0	0	0	0	0	0	0	0	0	0	8000; 4000[2]; 8000[2]; 20000[1]; 4000[4], 800000;
2791	ST	SPC560D40 (allow shadow) internal	0	0	1	38	1	32	1	1	0	0	0	0	0	0	0	0	0	0	0	8000; 4000[2]; 8000[2]; 20000[1]; 4000[1], 200000; 4000[4], 800000;
2792	ST	SPC560P34 internal	0	0	1	38	0	32	1	1	0	0	0	0	0	0	0	0	0	0	0	8000; 4000[2]; 8000[2]; 10000[1]; 4000[4], 800000;
2793	ST	SPC560P34 (allow shadow) internal	0	0	1	38	1	32	1	1	0	0	0	0	0	0	0	0	0	0	0	8000; 4000[2]; 8000[2]; 10000[1]; 4000[1], 200000; 4000[4], 800000;
2794	ST	SPC560P40 internal	0	0	1	38	0	32	1	1	0	0	0	0	0	0	0	0	0	0	0	8000; 4000[2]; 8000[2]; 20000[1]; 4000[4], 800000;
2795	ST	SPC560P40 (allow shadow) internal	0	0	1	38	1	32	1	1	0	0	0	0	0	0	0	0	0	0	0	8000; 4000[2]; 8000[2]; 20000[1]; 4000[1], 200000; 4000[4], 800000;
2796	ST	SPC560P44 internal	0	0	1	38	0	32	1	1	0	0	0	0	0	0	0	0	0	0	0	8000; 4000[2]; 8000[2]; 20000[2]; 4000[4], 800000;
2797	ST	SPC560P44 (allow shadow) internal	0	0	1	38	1	32	1	1	0	0	0	0	0	0	0	0	0	0	0	8000; 4000[2]; 8000[2]; 20000[2]; 4000[1], 200000; 4000[4], 800000;
2798	ST	SPC560P50 internal	0	0	1	38	0	32	1	1	0	0	0	0	0	0	0	0	0	0	0	8000; 4000[2]; 8000[2]; 20000[3]; 4000[4], 800000;
2799	ST	SPC560P50 (allow shadow) internal	0	0	1	38	1	32	1	1	0	0	0	0	0	0	0	0	0	0	0	8000; 4000[2]; 8000[2]; 20000[3]; 4000[1], 200000; 4000[4], 800000;
2800	ST	SPC560P54 internal	0	0	1	38	0	32	1	1	0	0	0	0	0	0	0	0	0	0	0	8000; 4000[2]; 8000[2]; 20000[5]; 4000[4], 800000;
2801	ST	SPC560P54 (allow shadow) internal	0	0	1	38	1	32	1	1	0	0	0	0	0	0	0	0	0	0	0	8000; 4000[2]; 8000[2]; 20000[5]; 4000[1], 200000; 4000[4], 800000;
2802	ST	SPC560P60 internal	0	0	1	38	0	32	1	1	0	0	0	0	0	0	0	0	0	0	0	8000; 4000[2]; 8000[2]; 20000[7]; 4000[4], 800000;
2803	ST	SPC560P60 (allow shadow) internal	0	0	1	38	1	32	1	1	0	0	0	0	0	0	0	0	0	0	0	8000; 4000[2]; 8000[2]; 20000[7]; 4000[1], 200000; 4000[4], 800000;
2804	ST	STA8088 internal	0	0	1	77	0	32	1	0	0	0	0	0	0	0	0	0	0	1	0	10000[256];
2805	ST	STM32F030x4 internal	0	0	1	17	6	32	1	1	0	0	0	0	0	0	0	0	0	1	1	400[16];
2806	ST	STM32F030x4 internal optbytes	0	0	1	17	7	32	1	1	0	0	0	0	0	0	0	0	0	1	1	10; 400[16], 2000000;
2807	ST	STM32F030x6 internal	0	0	1	17	6	32	1	1	0	0	0	0	0	0	0	0	0	1	1	400[32];
2808	ST	STM32F030x6 internal optbytes	0	0	1	17	7	32	1	1	0	0	0	0	0	0	0	0	0	1	1	10; 400[32], 2000000;
2809	ST	STM32F030x8 internal	0	0	1	17	6	32	1	1	0	0	0	0	0	0	0	0	0	1	1	400[64];
2810	ST	STM32F030x8 internal optbytes	0	0	1	17	7	32	1	1	0	0	0	0	0	0	0	0	0	1	1	10; 400[64], 2000000;
2811	ST	STM32F030xC internal	0	0	1	17	6	32	1	1	0	0	0	0	0	0	0	0	0	1	1	800[128];
2812	ST	STM32F030xC internal optbytes	0	0	1	17	7	32	1	1	0	0	0	0	0	0	0	0	0	1	1	10; 800[128], 2000000;
2813	ST	STM32F031x4 internal	0	0	1	17	6	32	1	1	0	0	0	0	0	0	0	0	0	1	1	400[16];
2814	ST	STM32F031x4 internal optbytes	0	0	1	17	7	32	1	1	0	0	0	0	0	0	0	0	0	1	1	10; 400[16], 2000000;
2815	ST	STM32F031x6 internal	0	0	1	17	6	32	1	1	0	0	0	0	0	0	0	0	0	1	1	400[32];
2816	ST	STM32F031x6 internal optbytes	0	0	1	17	7	32	1	1	0	0	0	0	0	0	0	0	0	1	1	10; 400[32], 2000000;
2817	ST	STM32F042x4 internal	0	0	1	17	0	32	1	1	0	0	0	0	0	0	0	0	0	1	1	400[16];
2818	ST	STM32F042x4 internal optbytes	0	0	1	17	1	32	1	1	0	0	0	0	0	0	0	0	0	1	1	10; 400[16], 2000000;
2819	ST	STM32F042x6 internal	0	0	1	17	0	32	1	1	0	0	0	0	0	0	0	0	0	1	1	400[32];
2820	ST	STM32F042x6 internal optbytes	0	0	1	17	1	32	1	1	0	0	0	0	0	0	0	0	0	1	1	10; 400[32], 2000000;
2821	ST	STM32F050x4 internal	0	0	1	17	6	32	1	1	0	0	0	0	0	0	0	0	0	1	1	400[16];
2822	ST	STM32F050x4 internal optbytes	0	0	1	17	7	32	1	1	0	0	0	0	0	0	0	0	0	1	1	10; 400[16], 2000000;
2823	ST	STM32F050x6 internal	0	0	1	17	6	32	1	1	0	0	0	0	0	0	0	0	0	1	1	400[32];
2824	ST	STM32F050x6 internal optbytes	0	0	1	17	7	32	1	1	0	0	0	0	0	0	0	0	0	1	1	10; 400[32], 2000000;
2825	ST	STM32F051x4 internal	0	0	1	17	6	32	1	1	0	0	0	0	0	0	0	0	0	1	1	400[16];
2826	ST	STM32F051x4 internal optbytes	0	0	1	17	7	32	1	1	0	0	0	0	0	0	0	0	0	1	1	10; 400[16], 2000000;
2827	ST	STM32F051x6 internal	0	0	1	17	6	32	1	1	0	0	0	0	0	0	0	0	0	1	1	400[32];
2828	ST	STM32F051x6 internal optbytes	0	0	1	17	7	32	1	1	0	0	0	0	0	0	0	0	0	1	1	10; 400[32], 2000000;
2829	ST	STM32F051x8 internal	0	0	1	17	6	32	1	1	0	0	0	0	0	0	0	0	0	1	1	400[64];
2830	ST	STM32F051x8 internal optbytes	0	0	1	17	7	32	1	1	0	0	0	0	0	0	0	0	0	1	1	10; 400[64], 2000000;
2831	ST	STM32F052x8 internal	0	0	1	17	6	32	1	1	0	0	0	0	0	0	0	0	0	1	1	400[64];
2832	ST	STM32F052x8 internal optbytes	0	0	1	17	7	32	1	1	0	0	0	0	0	0	0	0	0	1	1	10; 400[64], 2000000;
2833	ST	STM32F052xB internal	0	0	1	17	6	32	1	1	0	0	0	0	0	0	0	0	0	1	1	400[128];
2834	ST	STM32F052xB internal optbytes	0	0	1	17	7	32	1	1	0	0	0	0	0	0	0	0	0	1	1	10; 400[128], 2000000;
2835	ST	STM32F070x6 internal	0	0	1	17	6	32	1	1	0	0	0	0	0	0	0	0	0	1	1	800[16];
2836	ST	STM32F070x6 internal optbytes	0	0	1	17	7	32	1	1	0	0	0	0	0	0	0	0	0	1	1	10; 800[16] 2000000;
2837	ST	STM32F070x8 internal	0	0	1	17	6	32	1	1	0	0	0	0	0	0	0	0	0	1	1	800[32];
2838	ST	STM32F070x8 internal optbytes	0	0	1	17	7	32	1	1	0	0	0	0	0	0	0	0	0	1	1	10; 800[32] 2000000;
2839	ST	STM32F070xB internal	0	0	1	17	6	32	1	1	0	0	0	0	0	0	0	0	0	1	1	800[64];
2840	ST	STM32F070xB internal optbytes	0	0	1	17	7	32	1	1	0	0	0	0	0	0	0	0	0	1	1	10; 800[64] 2000000;
2841	ST	STM32F071xB internal	0	0	1	17	6	32	1	1	0	0	0	0	0	0	0	0	0	1	1	800[64];
2842	ST	STM32F071xB internal optbytes	0	0	1	17	7	32	1	1	0	0	0	0	0	0	0	0	0	1	1	10; 800[64], 2000000;
2843	ST	STM32F072x8 internal	0	0	1	17	6	32	1	1	0	0	0	0	0	0	0	0	0	1	1	800[32];
2844	ST	STM32F072x8 internal optbytes	0	0	1	17	7	32	1	1	0	0	0	0	0	0	0	0	0	1	1	10; 800[32], 2000000;
2845	ST	STM32F072xB internal	0	0	1	17	6	32	1	1	0	0	0	0	0	0	0	0	0	1	1	800[64];
2846	ST	STM32F072xB internal optbytes	0	0	1	17	7	32	1	1	0	0	0	0	0	0	0	0	0	1	1	10; 800[64], 2000000;
2847	ST	STM32F078xB internal	0	0	1	17	6	32	1	1	0	0	0	0	0	0	0	0	0	1	1	800[64];
2848	ST	STM32F078xB internal optbytes	0	0	1	17	7	32	1	1	0	0	0	0	0	0	0	0	0	1	1	10; 800[64], 2000000;
2849	ST	STM32F091xB internal	0	0	1	17	6	32	1	1	0	0	0	0	0	0	0	0	0	1	1	800[64];
2850	ST	STM32F091xB internal optbytes	0	0	1	17	7	32	1	1	0	0	0	0	0	0	0	0	0	1	1	10; 800[64], 2000000;
2851	ST	STM32F091xC internal	0	0	1	17	6	32	1	1	0	0	0	0	0	0	0	0	0	1	1	800[128];
2852	ST	STM32F091xC internal optbytes	0	0	1	17	7	32	1	1	0	0	0	0	0	0	0	0	0	1	1	10; 800[128], 2000000;
2853	ST	STM32F105x8 internal	0	0	1	17	0	32	1	1	0	0	0	0	0	0	0	0	0	1	1	800[32];
2854	ST	STM32F105x8 internal optbytes	0	0	1	17	1	32	1	1	0	0	0	0	0	0	0	0	0	1	1	10; 800[32], 2000000;
2855	ST	STM32F105xB internal	0	0	1	17	0	32	1	1	0	0	0	0	0	0	0	0	0	1	1	800[64];
2856	ST	STM32F105xB internal optbytes	0	0	1	17	1	32	1	1	0	0	0	0	0	0	0	0	0	1	1	10; 800[64], 2000000;
2857	ST	STM32F107xB internal	0	0	1	17	0	32	1	1	0	0	0	0	0	0	0	0	0	1	1	800[64];
2858	ST	STM32F107xB internal optbytes	0	0	1	17	1	32	1	1	0	0	0	0	0	0	0	0	0	1	1	10; 800[64], 2000000;
2859	ST	STM32F10xx4 internal	0	0	1	17	0	32	1	1	0	0	0	0	0	0	0	0	0	1	1	400[16];
2860	ST	STM32F10xx4 internal optbytes	0	0	1	17	1	32	1	1	0	0	0	0	0	0	0	0	0	1	1	10; 400[16], 2000000;
2861	ST	STM32F10xx6 internal	0	0	1	17	0	32	1	1	0	0	0	0	0	0	0	0	0	1	1	400[32];
2862	ST	STM32F10xx6 internal optbytes	0	0	1	17	1	32	1	1	0	0	0	0	0	0	0	0	0	1	1	10; 400[32], 2000000;
2863	ST	STM32F10xx8 internal	0	0	1	17	0	32	1	1	0	0	0	0	0	0	0	0	0	1	1	400[64];
2864	ST	STM32F10xx8 internal optbytes	0	0	1	17	1	32	1	1	0	0	0	0	0	0	0	0	0	1	1	10; 400[64], 2000000;
2865	ST	STM32F10xxB internal	0	0	1	17	0	32	1	1	0	0	0	0	0	0	0	0	0	1	1	400[128];
2866	ST	STM32F10xxB internal optbytes	0	0	1	17	1	32	1	1	0	0	0	0	0	0	0	0	0	1	1	10; 400[128], 2000000;
2867	ST	STM32F10xxC internal	0	0	1	17	0	32	1	1	0	0	0	0	0	0	0	0	0	1	1	800[128];
2868	ST	STM32F10xxC internal optbytes	0	0	1	17	1	32	1	1	0	0	0	0	0	0	0	0	0	1	1	10; 800[128], 2000000;
2869	ST	STM32F10xxD internal	0	0	1	17	0	32	1	1	0	0	0	0	0	0	0	0	0	1	1	800[192];
2870	ST	STM32F10xxD internal optbytes	0	0	1	17	1	32	1	1	0	0	0	0	0	0	0	0	0	1	1	10; 800[192], 2000000;
2871	ST	STM32F10xxE internal	0	0	1	17	0	32	1	1	0	0	0	0	0	0	0	0	0	1	1	800[256];
2872	ST	STM32F10xxE internal optbytes	0	0	1	17	1	32	1	1	0	0	0	0	0	0	0	0	0	1	1	10; 800[256], 2000000;
2873	ST	STM32F10xxF internal	0	0	1	17	2	32	1	1	0	0	0	0	0	0	0	0	0	1	1	800[384];
2874	ST	STM32F10xxF internal optbytes	0	0	1	17	3	32	1	1	0	0	0	0	0	0	0	0	0	1	1	10; 800[384], 2000000;
2875	ST	STM32F10xxG internal	0	0	1	17	2	32	1	1	0	0	0	0	0	0	0	0	0	1	1	800[512];
2876	ST	STM32F10xxG internal optbytes	0	0	1	17	3	32	1	1	0	0	0	0	0	0	0	0	0	1	1	10; 800[512], 2000000;
2877	ST	STM32F20xxB internal	0	0	1	37	0	32	1	0	0	0	0	0	0	0	0	0	0	1	1	4000[4]; 10000;
2878	ST	STM32F20xxC internal	0	0	1	37	0	32	1	0	0	0	0	0	0	0	0	0	0	1	1	4000[4]; 10000; 20000[1];
2879	ST	STM32F20xxE internal	0	0	1	37	0	32	1	0	0	0	0	0	0	0	0	0	0	1	1	4000[4]; 10000; 20000[3];
2880	ST	STM32F20xxF internal	0	0	1	37	0	32	1	0	0	0	0	0	0	0	0	0	0	1	1	4000[4]; 10000; 20000[5];
2881	ST	STM32F20xxG internal	0	0	1	37	0	32	1	0	0	0	0	0	0	0	0	0	0	1	1	4000[4]; 10000; 20000[7];
2882	ST	STM32F30xx4 internal	0	0	1	17	6	32	1	1	0	0	0	0	0	0	0	0	0	1	1	800[8];
2883	ST	STM32F30xx4 internal optbytes	0	0	1	17	7	32	1	1	0	0	0	0	0	0	0	0	0	1	1	10; 800[8], 2000000;
2884	ST	STM32F30xx6 internal	0	0	1	17	6	32	1	1	0	0	0	0	0	0	0	0	0	1	1	800[16];
2885	ST	STM32F30xx6 internal optbytes	0	0	1	17	7	32	1	1	0	0	0	0	0	0	0	0	0	1	1	10; 800[16], 2000000;
2886	ST	STM32F30xx8 internal	0	0	1	17	6	32	1	1	0	0	0	0	0	0	0	0	0	1	1	800[32];
2887	ST	STM32F30xx8 internal optbytes	0	0	1	17	7	32	1	1	0	0	0	0	0	0	0	0	0	1	1	10; 800[32], 2000000;
2888	ST	STM32F30xxB internal	0	0	1	17	6	32	1	1	0	0	0	0	0	0	0	0	0	1	1	800[64];
2889	ST	STM32F30xxB internal optbytes	0	0	1	17	7	32	1	1	0	0	0	0	0	0	0	0	0	1	1	10; 800[64], 2000000;
2890	ST	STM32F30xxC internal	0	0	1	17	6	32	1	1	0	0	0	0	0	0	0	0	0	1	1	800[128];
2891	ST	STM32F30xxC internal optbytes	0	0	1	17	7	32	1	1	0	0	0	0	0	0	0	0	0	1	1	10; 800[128], 2000000;
2892	ST	STM32F30xxD internal	0	0	1	17	6	32	1	1	0	0	0	0	0	0	0	0	0	1	1	800[192];
2893	ST	STM32F30xxD internal optbytes	0	0	1	17	7	32	1	1	0	0	0	0	0	0	0	0	0	1	1	10; 800[192], 2000000;
2894	ST	STM32F30xxE internal	0	0	1	17	6	32	1	1	0	0	0	0	0	0	0	0	0	1	1	800[256];
2895	ST	STM32F30xxE internal optbytes	0	0	1	17	7	32	1	1	0	0	0	0	0	0	0	0	0	1	1	10; 800[256], 2000000;
2896	ST	STM32F37xx8 internal	0	0	1	17	6	32	1	1	0	0	0	0	0	0	0	0	0	1	1	800[32];
2897	ST	STM32F37xx8 internal optbytes	0	0	1	17	7	32	1	1	0	0	0	0	0	0	0	0	0	1	1	10; 800[32], 2000000;
2898	ST	STM32F37xxB internal	0	0	1	17	6	32	1	1	0	0	0	0	0	0	0	0	0	1	1	800[64];
2899	ST	STM32F37xxB internal optbytes	0	0	1	17	7	32	1	1	0	0	0	0	0	0	0	0	0	1	1	10; 800[64], 2000000;
2900	ST	STM32F37xxC internal	0	0	1	17	6	32	1	1	0	0	0	0	0	0	0	0	0	1	1	800[128];
2901	ST	STM32F37xxC internal optbytes	0	0	1	17	7	32	1	1	0	0	0	0	0	0	0	0	0	1	1	10; 800[128], 2000000;
2902	ST	STM32F401xB internal	0	0	1	37	1	32	1	0	0	0	0	0	0	0	0	0	0	1	1	4000[4]; 10000;
2903	ST	STM32F401xC internal	0	0	1	37	1	32	1	0	0	0	0	0	0	0	0	0	0	1	1	4000[4]; 10000; 20000[1];
2904	ST	STM32F401xD internal	0	0	1	37	1	32	1	0	0	0	0	0	0	0	0	0	0	1	1	4000[4]; 10000; 20000[2];
2905	ST	STM32F401xE internal	0	0	1	37	1	32	1	0	0	0	0	0	0	0	0	0	0	1	1	4000[4]; 10000; 20000[3];
2906	ST	STM32F405xE internal	0	0	1	37	0	32	1	0	0	0	0	0	0	0	0	0	0	1	1	4000[4]; 10000; 20000[3];
2907	ST	STM32F405xG internal	0	0	1	37	0	32	1	0	0	0	0	0	0	0	0	0	0	1	1	4000[4]; 10000; 20000[7];
2908	ST	STM32F407xE internal	0	0	1	37	0	32	1	0	0	0	0	0	0	0	0	0	0	1	1	4000[4]; 10000; 20000[3];
2909	ST	STM32F407xG internal	0	0	1	37	0	32	1	0	0	0	0	0	0	0	0	0	0	1	1	4000[4]; 10000; 20000[7];
2910	ST	STM32F410x8 internal	0	0	1	37	0	32	1	0	0	0	0	0	0	0	0	0	0	1	1	4000[4];
2911	ST	STM32F410xB internal	0	0	1	37	0	32	1	0	0	0	0	0	0	0	0	0	0	1	1	4000[4]; 10000[1]
2912	ST	STM32F415xE internal	0	0	1	37	0	32	1	0	0	0	0	0	0	0	0	0	0	1	1	4000[4]; 10000; 20000[3];
2913	ST	STM32F415xG internal	0	0	1	37	0	32	1	0	0	0	0	0	0	0	0	0	0	1	1	4000[4]; 10000; 20000[7];
2914	ST	STM32F417xE internal	0	0	1	37	0	32	1	0	0	0	0	0	0	0	0	0	0	1	1	4000[4]; 10000; 20000[3];
2915	ST	STM32F417xG internal	0	0	1	37	0	32	1	0	0	0	0	0	0	0	0	0	0	1	1	4000[4]; 10000; 20000[7];
2916	ST	STM32F427xG internal	0	0	1	37	0	32	1	0	0	0	0	0	0	0	0	0	0	1	1	4000[4]; 10000; 20000[7];
2917	ST	STM32F427xI internal	0	0	1	37	0	32	1	0	0	0	0	0	0	0	0	0	0	1	1	4000[4]; 10000; 20000[7]; 4000[4]; 10000; 20000[7];
2918	ST	STM32F429xE internal	0	0	1	37	0	32	1	0	0	0	0	0	0	0	0	0	0	1	1	4000[4]; 10000; 20000[3];
2919	ST	STM32F429xG internal	0	0	1	37	0	32	1	0	0	0	0	0	0	0	0	0	0	1	1	4000[4]; 10000; 20000[7];
2920	ST	STM32F429xI internal	0	0	1	37	0	32	1	0	0	0	0	0	0	0	0	0	0	1	1	4000[4]; 10000; 20000[7]; 4000[4]; 10000; 20000[7];
2921	ST	STM32F437xG internal	0	0	1	37	0	32	1	0	0	0	0	0	0	0	0	0	0	1	1	4000[4]; 10000; 20000[7];
2922	ST	STM32F437xI internal	0	0	1	37	0	32	1	0	0	0	0	0	0	0	0	0	0	1	1	4000[4]; 10000; 20000[7]; 4000[4]; 10000; 20000[7];
2923	ST	STM32F439xG internal	0	0	1	37	0	32	1	0	0	0	0	0	0	0	0	0	0	1	1	4000[4]; 10000; 20000[7];
2924	ST	STM32F439xI internal	0	0	1	37	0	32	1	0	0	0	0	0	0	0	0	0	0	1	1	4000[4]; 10000; 20000[7]; 4000[4]; 10000; 20000[7];
2925	ST	STM32F746xE internal	0	0	1	88	0	32	1	1	0	0	0	0	0	0	0	0	0	0	0	8000[4]; 20000[1]; 40000[1];
2926	ST	STM32F746xG internal	0	0	1	88	0	32	1	1	0	0	0	0	0	0	0	0	0	0	0	8000[4]; 20000[1]; 40000[3];
2927	ST	STM32F756xE internal	0	0	1	88	0	32	1	1	0	0	0	0	0	0	0	0	0	0	0	8000[4]; 20000[1]; 40000[1];
2928	ST	STM32F756xG internal	0	0	1	88	0	32	1	1	0	0	0	0	0	0	0	0	0	0	0	8000[4]; 20000[1]; 40000[3];
2929	ST	STM32F469xG internal	0	0	1	37	0	32	1	0	0	0	0	0	0	0	0	0	0	1	1	4000[4]; 10000; 20000[7];
2930	ST	STM32F469xI internal	0	0	1	37	0	32	1	0	0	0	0	0	0	0	0	0	0	1	1	4000[4]; 10000; 20000[7]; 4000[4]; 10000; 20000[7];
2931	ST	STM32F479xG internal	0	0	1	37	0	32	1	0	0	0	0	0	0	0	0	0	0	1	1	4000[4]; 10000; 20000[7];
2932	ST	STM32F479xI internal	0	0	1	37	0	32	1	0	0	0	0	0	0	0	0	0	0	1	1	4000[4]; 10000; 20000[7]; 4000[4]; 10000; 20000[7];
2933	ST	STM32L0x1x4 internal optbytes	0	0	1	34	5	32	1	0	0	0	0	0	0	0	0	0	0	1	1	80[128]; 800[1], 80000; 10[2], 17F80000;
2934	ST	STM32L0x1x4 internal	0	0	1	34	5	32	1	0	0	0	0	0	0	0	0	0	0	1	1	80[128]; 800[1], 80000;
2935	ST	STM32L0x1x6 internal optbytes	0	0	1	34	5	32	1	0	0	0	0	0	0	0	0	0	0	1	1	80[256]; 800[1], 80000; 10[2], 17F80000;
2936	ST	STM32L0x1x6 internal	0	0	1	34	5	32	1	0	0	0	0	0	0	0	0	0	0	1	1	80[256]; 800[1], 80000;
2937	ST	STM32L0x1x8 internal optbytes	0	0	1	34	5	32	1	0	0	0	0	0	0	0	0	0	0	1	1	80[512]; 800[1], 80000; 10[2], 17F80000;
2938	ST	STM32L0x1x8 internal	0	0	1	34	5	32	1	0	0	0	0	0	0	0	0	0	0	1	1	80[512]; 800[1], 80000;
2939	ST	STM32L0x2x6 internal optbytes	0	0	1	34	5	32	1	0	0	0	0	0	0	0	0	0	0	1	1	80[256]; 800[1], 80000; 10[2], 17F80000;
2940	ST	STM32L0x2x6 internal	0	0	1	34	5	32	1	0	0	0	0	0	0	0	0	0	0	1	1	80[256]; 800[1], 80000;
2941	ST	STM32L0x2x8 internal optbytes	0	0	1	34	5	32	1	0	0	0	0	0	0	0	0	0	0	1	1	80[512]; 800[1], 80000; 10[2], 17F80000;
2942	ST	STM32L0x2x8 internal	0	0	1	34	5	32	1	0	0	0	0	0	0	0	0	0	0	1	1	80[512]; 800[1], 80000;
2943	ST	STM32L0x3x6 internal optbytes	0	0	1	34	5	32	1	0	0	0	0	0	0	0	0	0	0	1	1	80[256]; 800[1], 80000; 10[2], 17F80000;
2944	ST	STM32L0x3x6 internal	0	0	1	34	5	32	1	0	0	0	0	0	0	0	0	0	0	1	1	80[256]; 800[1], 80000;
2945	ST	STM32L0x3x8 internal optbytes	0	0	1	34	5	32	1	0	0	0	0	0	0	0	0	0	0	1	1	80[512]; 800[1], 80000; 10[2], 17F80000;
2946	ST	STM32L0x3x8 internal	0	0	1	34	5	32	1	0	0	0	0	0	0	0	0	0	0	1	1	80[512]; 800[1], 80000;
2947	ST	STM32L071x8 internal	0	0	1	89	0	32	1	1	0	0	0	0	0	0	0	0	0	1	1	80[512]; 400[3], 80000;
2948	ST	STM32L071x8 internal optbytes	0	0	1	89	0	32	1	1	0	0	0	0	0	0	0	0	0	1	1	80[512]; 400[3], 80000; 10[2], 17F80000;
2949	ST	STM32L071xB internal	0	0	1	89	1	32	1	1	0	0	0	0	0	0	0	0	0	1	1	80[1024]; 400[6], 80000;
2950	ST	STM32L071xB internal optbytes	1	0	1	89	1	32	1	1	0	0	0	0	0	0	0	0	0	1	1	80[1024]; 400[6], 80000; 10[2], 17F80000;
2951	ST	STM32L071xZ internal	0	0	1	89	1	32	1	1	0	0	0	0	0	0	0	0	0	1	1	80[1536]; 400[6], 80000;
2952	ST	STM32L071xZ internal optbytes	1	0	1	89	1	32	1	1	0	0	0	0	0	0	0	0	0	1	1	80[1536]; 400[6], 80000; 10[2], 17F80000;
2953	ST	STM32L072x8 internal	0	0	1	89	0	32	1	1	0	0	0	0	0	0	0	0	0	1	1	80[512]; 400[3], 80000;
2954	ST	STM32L072x8 internal optbytes	0	0	1	89	0	32	1	1	0	0	0	0	0	0	0	0	0	1	1	80[512]; 400[3], 80000; 10[2], 17F80000;
2955	ST	STM32L072xB internal	0	0	1	89	1	32	1	1	0	0	0	0	0	0	0	0	0	1	1	80[1024]; 400[6], 80000;
2956	ST	STM32L072xB internal optbytes	1	0	1	89	1	32	1	1	0	0	0	0	0	0	0	0	0	1	1	80[1024]; 400[6], 80000; 10[2], 17F80000;
2957	ST	STM32L072xZ internal	0	0	1	89	1	32	1	1	0	0	0	0	0	0	0	0	0	1	1	80[1536]; 400[6], 80000;
2958	ST	STM32L072xZ internal optbytes	1	0	1	89	1	32	1	1	0	0	0	0	0	0	0	0	0	1	1	80[1536]; 400[6], 80000; 10[2], 17F80000;
2959	ST	STM32L073x8 internal	0	0	1	89	0	32	1	1	0	0	0	0	0	0	0	0	0	1	1	80[512]; 400[3], 80000;
2960	ST	STM32L073x8 internal optbytes	0	0	1	89	0	32	1	1	0	0	0	0	0	0	0	0	0	1	1	80[512]; 400[3], 80000; 10[2], 17F80000;
2961	ST	STM32L073xB internal	0	0	1	89	1	32	1	1	0	0	0	0	0	0	0	0	0	1	1	80[1024]; 400[6], 80000;
2962	ST	STM32L073xB internal optbytes	0	0	1	89	1	32	1	1	0	0	0	0	0	0	0	0	0	1	1	80[1024]; 400[6], 80000; 10[2], 17F80000;
2963	ST	STM32L073xZ internal	0	0	1	89	1	32	1	1	0	0	0	0	0	0	0	0	0	1	1	80[1536]; 400[6], 80000;
2964	ST	STM32L073xZ internal optbytes	0	0	1	89	1	32	1	1	0	0	0	0	0	0	0	0	0	1	1	80[1536]; 400[6], 80000; 10[2], 17F80000;
2965	ST	STM32L083x8 internal	0	0	1	89	0	32	1	1	0	0	0	0	0	0	0	0	0	1	1	80[512]; 400[3], 80000;
2966	ST	STM32L083x8 internal optbytes	0	0	1	89	0	32	1	1	0	0	0	0	0	0	0	0	0	1	1	80[512]; 400[3], 80000; 10[2], 17F80000;
2967	ST	STM32L083xB internal	0	0	1	89	1	32	1	1	0	0	0	0	0	0	0	0	0	1	1	80[1024]; 400[6], 80000;
2968	ST	STM32L083xB internal optbytes	0	0	1	89	1	32	1	1	0	0	0	0	0	0	0	0	0	1	1	80[1024]; 400[6], 80000; 10[2], 17F80000;
2969	ST	STM32L083xZ internal	0	0	1	89	1	32	1	1	0	0	0	0	0	0	0	0	0	1	1	80[1536]; 400[6], 80000;
2970	ST	STM32L083xZ internal optbytes	0	0	1	89	1	32	1	1	0	0	0	0	0	0	0	0	0	1	1	80[1536]; 400[6], 80000; 10[2], 17F80000;
2971	ST	STM32L100x6 internal optbytes	0	0	1	34	0	32	1	0	0	0	0	0	0	0	0	0	0	1	1	100[128]; 800[1], 80000; 10[1], 17F80000;
2972	ST	STM32L100x6 internal	0	0	1	34	0	32	1	0	0	0	0	0	0	0	0	0	0	1	1	100[128]; 800[1], 80000;
2973	ST	STM32L100x8 internal optbytes	0	0	1	34	0	32	1	0	0	0	0	0	0	0	0	0	0	1	1	100[256]; 800[1], 80000; 10[1], 17F80000;
2974	ST	STM32L100x8 internal	0	0	1	34	0	32	1	0	0	0	0	0	0	0	0	0	0	1	1	100[256]; 800[1], 80000;
2975	ST	STM32L100xB internal optbytes	0	0	1	34	0	32	1	0	0	0	0	0	0	0	0	0	0	1	1	100[512]; 800[1], 80000; 10[1], 17F80000;
2976	ST	STM32L100xB internal	0	0	1	34	0	32	1	0	0	0	0	0	0	0	0	0	0	1	1	100[512]; 800[1], 80000;
2977	ST	STM32L100xC internal optbytes	0	0	1	34	2	32	1	0	0	0	0	0	0	0	0	0	0	1	1	100[1024]; 2000[1], 80000; 20[1], 17F80000;
2978	ST	STM32L100xC internal	0	0	1	34	2	32	1	0	0	0	0	0	0	0	0	0	0	1	1	100[1024]; 2000[1], 80000;
2979	ST	STM32L15xxB internal optbytes	0	0	1	34	1	32	1	0	0	0	0	0	0	0	0	0	0	1	1	100[512]; 1000[1], 80000; 10[1], 17F80000;
2980	ST	STM32L15xxB internal	0	0	1	34	1	32	1	0	0	0	0	0	0	0	0	0	0	1	1	100[512]; 1000[1], 80000;
2981	ST	STM32L15xxD internal optbytes	0	0	1	34	3	32	1	0	0	0	0	0	0	0	0	0	0	1	1	100[1536]; 3000[1], 80000; 20[1], 17F80000; 20[1], 17F80080;
2982	ST	STM32L15xxD internal	0	0	1	34	3	32	1	0	0	0	0	0	0	0	0	0	0	1	1	100[1536]; 3000[1], 80000;
2983	ST	STM32L15xxE internal optbytes	0	0	1	34	4	32	1	0	0	0	0	0	0	0	0	0	0	1	1	100[2048]; 4000[1], 80000; 20[1], 17F80000; 20[1], 17F80080;
2984	ST	STM32L15xxE internal	0	0	1	34	4	32	1	0	0	0	0	0	0	0	0	0	0	1	1	100[2048]; 4000[1], 80000;
2985	ST	STM32L16xxD internal optbytes	0	0	1	34	3	32	1	0	0	0	0	0	0	0	0	0	0	1	1	100[1536]; 3000[1], 80000; 20[1], 17F80000; 20[1], 17F80080;
2986	ST	STM32L16xxD internal	0	0	1	34	3	32	1	0	0	0	0	0	0	0	0	0	0	1	1	100[1536]; 3000[1], 80000;
2987	ST	STM32L16xxE internal optbytes	0	0	1	34	4	32	1	0	0	0	0	0	0	0	0	0	0	1	1	100[2048]; 4000[1], 80000; 20[1], 17F80000; 20[1], 17F80080;
2988	ST	STM32L16xxE internal	0	0	1	34	4	32	1	0	0	0	0	0	0	0	0	0	0	1	1	100[2048]; 4000[1], 80000;
2989	ST	STM32L476xC internal	0	0	1	87	0	32	1	1	0	0	0	0	0	0	0	0	0	0	0	800[128];
2990	ST	STM32L476xE internal	0	0	1	87	0	32	1	1	0	0	0	0	0	0	0	0	0	0	0	800[256];
2991	ST	STM32L476xG internal	0	0	1	87	0	32	1	1	0	0	0	0	0	0	0	0	0	0	0	800[512];
2992	ST	STM32L486xG internal	0	0	1	87	0	32	1	1	0	0	0	0	0	0	0	0	0	0	0	800[512];
2993	ST	STM32W108x8 internal	0	0	1	17	4	32	1	1	0	0	0	0	0	0	0	0	0	1	1	400[64];
2994	ST	STM32W108x8 internal optbytes	0	0	1	17	5	32	1	1	0	0	0	0	0	0	0	0	0	1	1	10; 400[64], 2000000;
2995	ST	STM32W108xB internal	0	0	1	17	4	32	1	1	0	0	0	0	0	0	0	0	0	1	1	400[128];
2996	ST	STM32W108xB internal optbytes	0	0	1	17	5	32	1	1	0	0	0	0	0	0	0	0	0	1	1	10; 400[128], 2000000;
2997	ST	STM32W108xC internal	0	0	1	17	4	32	1	1	0	0	0	0	0	0	0	0	0	1	1	800[128];
2998	ST	STM32W108xC internal optbytes	0	0	1	17	5	32	1	1	0	0	0	0	0	0	0	0	0	1	1	10; 800[128], 2000000;
2999	ST	STM32W108xZ internal	0	0	1	17	4	32	1	1	0	0	0	0	0	0	0	0	0	1	1	800[96];
3000	ST	STM32W108xZ internal optbytes	0	0	1	17	5	32	1	1	0	0	0	0	0	0	0	0	0	1	1	10; 800[96], 2000000;
3001	ST	STR71xFx0 internal	0	0	1	3	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[4]; 8000; 2000[2], C0000;
3002	ST	STR71xFx1 internal	0	0	1	3	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[4]; 8000; 10000; 2000[2], C0000;
3003	ST	STR71xFx2 internal	0	0	1	3	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[4]; 8000; 10000[3]; 2000[2], C0000;
3004	ST	STR73xFx0 internal	0	0	1	3	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[4]; 8000;
3005	ST	STR73xFx1 internal	0	0	1	3	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[4]; 8000; 10000;
3006	ST	STR73xFx2 internal	0	0	1	3	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[4]; 8000; 10000[3];
3007	ST	STR75xFx0 internal	0	0	1	3	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[4]; 8000; 2000[2], C0000;
3008	ST	STR75xFx1 internal	0	0	1	3	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[4]; 8000; 10000; 2000[2], C0000;
3009	ST	STR75xFx2 internal	0	0	1	3	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[4]; 8000; 10000[3]; 2000[2], C0000;
3010	ST	STR91xFx32 internal	0	0	1	13	0	16	1	0	0	0	0	0	0	0	0	0	0	0	0	10000[4]; 2000[4], 80000;
3011	ST	STR91xFx32 internal (Bootbank 1)	0	0	1	13	0	16	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[4]; 10000[4], 80000;
3012	ST	STR91xFx42 internal	0	0	1	13	0	16	1	0	0	0	0	0	0	0	0	0	0	0	0	10000[4]; 2000[4], 80000;
3013	ST	STR91xFx42 internal (Bootbank 1)	0	0	1	13	0	16	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[4]; 10000[4], 80000;
3014	ST	STR91xFx44 internal	0	0	1	13	0	16	1	0	0	0	0	0	0	0	0	0	0	0	0	10000[8]; 2000[4], 80000;
3015	ST	STR91xFx44 internal (Bootbank 1)	0	0	1	13	0	16	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[4]; 10000[8], 80000;
3016	ST	STR91xFx46 internal	0	0	1	13	1	16	1	0	0	0	0	0	0	0	0	0	0	0	0	10000[16]; 4000[8], 200000;
3017	ST	STR91xFx46 internal (Bootbank 1)	0	0	1	13	1	16	1	0	0	0	0	0	0	0	0	0	0	0	0	4000[8]; 10000[16], 200000;
3018	ST	STR91xFx47 internal	0	0	1	13	1	16	1	0	0	0	0	0	0	0	0	0	0	0	0	10000[32]; 4000[8], 200000;
3019	ST	STR91xFx47 internal (Bootbank 1)	0	0	1	13	1	16	1	0	0	0	0	0	0	0	0	0	0	0	0	4000[8]; 10000[32], 200000;
3020	TI	CC13xxF128 internal	0	0	1	60	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	1000[32];
3021	TI	CC2538xx53 internal	0	0	1	60	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	800[256];
3022	TI	CC2538xx23 internal	0	0	1	60	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	800[128];
3023	TI	CC2538xx11 internal	0	0	1	60	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	800[64];
3024	TI	CC26x0F128 internal	0	0	1	60	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	1000[32];
3025	TI	LM4C1xxxC3x internal	0	0	1	18	2	32	1	1	0	0	0	0	0	0	0	0	0	0	0	400[32];
3026	TI	LM4C1xxxD5x internal	0	0	1	18	2	32	1	1	0	0	0	0	0	0	0	0	0	0	0	400[64];
3027	TI	LM4C1xxxE6x internal	0	0	1	18	2	32	1	1	0	0	0	0	0	0	0	0	0	0	0	400[128];
3028	TI	LM4C1xxxH6x internal	0	0	1	18	2	32	1	1	0	0	0	0	0	0	0	0	0	0	0	400[256];
3029	TI	LM4C1xxxKCx internal	0	0	1	18	2	32	1	1	0	0	0	0	0	0	0	0	0	0	0	4000[32];
3030	TI	LM4C1xxxNCx internal	0	0	1	18	2	32	1	1	0	0	0	0	0	0	0	0	0	0	0	4000[64];
3031	TI	LM4F1xxB internal	0	0	1	18	1	32	1	1	0	0	0	0	0	0	0	0	0	0	0	400[32];
3032	TI	LM4F1xxC internal	0	0	1	18	1	32	1	1	0	0	0	0	0	0	0	0	0	0	0	400[64];
3033	TI	LM4F1xxE internal	0	0	1	18	1	32	1	1	0	0	0	0	0	0	0	0	0	0	0	400[128];
3034	TI	LM4F1xxH internal	0	0	1	18	1	32	1	1	0	0	0	0	0	0	0	0	0	0	0	400[256];
3035	TI	LM4F2xxE internal	0	0	1	18	1	32	1	1	0	0	0	0	0	0	0	0	0	0	0	400[128];
3036	TI	LM4F2xxH internal	0	0	1	18	1	32	1	1	0	0	0	0	0	0	0	0	0	0	0	400[256];
3037	TI	MSP432P401M internal	0	0	1	95	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	1000[32];
3038	TI	MSP432P401R internal	0	0	1	95	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	1000[64];
3039	TI	RM42L4xx internal	0	0	1	42	2	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[12]; 8000[1]; 20000[2]; 1000[4], F0200000;
3040	TI	RM46L4xx internal	0	0	1	42	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	4000[6]; 8000[1]; 20000[7]; 4000[4], F0200000;
3041	TI	RM46L6xx internal	0	0	1	42	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	4000[6]; 8000[1]; 20000[7]; 4000[4], F0200000;
3042	TI	RM46L8xx internal	0	0	1	42	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	4000[6]; 8000[1]; 20000[9]; 4000[4], F0200000;
3043	TI	RM48L5xx internal	0	0	1	42	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	8000[4]; 20000[15]; 4000[4], F0200000;
3044	TI	RM48L7xx internal	0	0	1	42	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	8000[4]; 20000[15]; 4000[4], F0200000;
3045	TI	RM48L9xx internal	0	0	1	42	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	8000[4]; 20000[23]; 4000[4], F0200000;
3046	TI	RM57L843ZWT internal	0	0	1	85	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	4000[6]; 8000[1]; 20000[3]; 40000[6];
3047	TI	TMS470R1A64 internal	0	0	1	9	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	1FE0; 2000[1],2000; 4000[3];
3048	TI	TMS470R1A64 internal (allow keys)	0	0	1	9	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[2]; 4000[3];
3049	TI	TMS470R1A128 internal	0	0	1	9	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	1FE0; 2000[1],2000; 4000[6]; 2000[2];
3050	TI	TMS470R1A128 internal (allow keys)	0	0	1	9	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[2]; 4000[6]; 2000[2];
3051	TI	TMS470R1A256 internal	0	0	1	9	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	1FE0; 2000[3],2000; 8000[6]; 2000[4];
3052	TI	TMS470R1A256 internal (allow keys)	0	0	1	9	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[4]; 8000[6]; 2000[4];
3053	TI	TMS470R1A288 internal	0	0	1	9	2	32	1	0	0	0	0	0	0	0	0	0	0	0	0	1FE0; 2000[3],2000; 10000[4],40000;
3054	TI	TMS470R1A288 internal (allow keys)	0	0	1	9	2	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[4]; 10000[4],40000;
3055	TI	TMS470R1A384 internal	0	0	1	9	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	1FE0; 2000[1],2000; 4000[6]; 2000[2]; 8000[8];
3056	TI	TMS470R1A384 internal (allow keys)	0	0	1	9	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[2]; 4000[6]; 2000[2]; 8000[8];
3057	TI	TMS470R1B512 internal	0	0	1	9	3	32	1	0	0	0	0	0	0	0	0	0	0	0	0	3FE0; 4000[1],4000; 8000[6]; 4000[2]; 10000[4];
3058	TI	TMS470R1B512 internal (allow keys)	0	0	1	9	3	32	1	0	0	0	0	0	0	0	0	0	0	0	0	4000[2]; 8000[6]; 4000[2]; 10000[4];
3059	TI	TMS470R1B768 internal	0	0	1	9	3	32	1	0	0	0	0	0	0	0	0	0	0	0	0	3FE0; 4000[1],4000; 8000[6]; 4000[2]; 10000[8];
3060	TI	TMS470R1B768 internal (allow keys)	0	0	1	9	3	32	1	0	0	0	0	0	0	0	0	0	0	0	0	4000[2]; 8000[6]; 4000[2]; 10000[8];
3061	TI	TMS470R1B1M internal	0	0	1	9	4	32	1	0	0	0	0	0	0	0	0	0	0	0	0	FFE0; 10000[15],10000;
3062	TI	TMS470R1B1M internal (allow keys)	0	0	1	9	4	32	1	0	0	0	0	0	0	0	0	0	0	0	0	10000[16];
3063	TI	TMS470R1VF288 internal	0	0	1	9	2	32	1	0	0	0	0	0	0	0	0	0	0	0	0	1FE0; 2000[3],2000; 10000[4],40000;
3064	TI	TMS470R1VF288 internal (allow keys)	0	0	1	9	2	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[4]; 10000[4],40000;
3065	TI	TMS470R1VF688 internal	0	0	1	9	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	1FE0; 2000[1],2000; 4000[6]; 2000[2]; 8000[4];
3066	TI	TMS470R1VF688 internal (allow keys)	0	0	1	9	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[2]; 4000[6]; 2000[2]; 8000[4];
3067	TI	TMS470R1VF689 internal	0	0	1	9	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	1FE0; 2000[1],2000; 4000[6]; 2000[2]; 8000[8];
3068	TI	TMS470R1VF689 internal (allow keys)	0	0	1	9	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[2]; 4000[6]; 2000[2]; 8000[8];
3069	TI	TMS570LC4357ZWT internal	0	0	1	85	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	4000[6]; 8000[1]; 20000[3]; 40000[6]; 20000[16];
3070	TI	TMS570LS02xx internal	0	0	1	42	2	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[12]; 8000[1]; 1000[4], F0200000;
3071	TI	TMS570LS03xx internal	0	0	1	42	2	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[12]; 8000[1]; 20000[1]; 1000[4], F0200000;
3072	TI	TMS570LS04xx internal	0	0	1	42	2	32	1	0	0	0	0	0	0	0	0	0	0	0	0	2000[12]; 8000[1]; 20000[2]; 1000[4], F0200000;
3073	TI	TMS570LS11xx internal	0	0	1	42	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	4000[6]; 8000[1]; 20000[7]; 4000[4], F0200000;
3074	TI	TMS570LS12xx internal	0	0	1	42	1	32	1	0	0	0	0	0	0	0	0	0	0	0	0	4000[6]; 8000[1]; 20000[9]; 4000[4], F0200000;
3075	TI	TMS570LS21xx internal	0	0	1	42	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	8000[4]; 20000[15]; 4000[4], F0200000;
3076	TI	TMS570LS31xx internal	0	0	1	42	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	8000[4]; 20000[23]; 4000[4], F0200000;
3077	TI	TMS570LS101xx internal	0	0	1	43	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	8000[3]; 2000[2]; 4000[1]; 10000[2]; 20000[6];
3078	TI	TMS570LS102xx internal	0	0	1	43	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	8000[3]; 2000[2]; 4000[1]; 10000[2]; 20000[6];
3079	TI	TMS570LS202xx internal	0	0	1	43	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	8000[3]; 2000[2]; 4000[1]; 10000[2]; 20000[14];
3080	Toshiba	TB6865FG internal	0	0	1	21	9	32	1	1	0	0	0	0	0	0	0	0	0	0	0	4000[2]; 8000[1]; 10000[1];
3081	Toshiba	TC58FVB160	980043	980043	0	1	0	16	1	0	0	0	0	0	0	0	0	0	0	0	0	4000; 2000[2]; 8000; 10000[31];
3082	Toshiba	TC58FVT160	9800C2	9800C2	0	1	0	16	1	0	0	0	0	0	0	0	0	0	0	0	0	10000[31]; 8000; 2000[2]; 4000;
3083	Toshiba	TMPM061FWFG internal	0	0	1	51	0	32	1	1	0	0	0	0	0	0	0	0	0	0	0	8000[4];
3084	Toshiba	TMPM321F10FG internal	0	0	1	21	4	32	1	1	0	0	0	0	0	0	0	0	0	0	0	8000[2]; 10000[1]; 20000[7];
3085	Toshiba	TMPM322F10FG internal	0	0	1	21	4	32	1	1	0	0	0	0	0	0	0	0	0	0	0	8000[2]; 10000[1]; 20000[7];
3086	Toshiba	TMPM323F10FG internal	0	0	1	21	4	32	1	1	0	0	0	0	0	0	0	0	0	0	0	8000[2]; 10000[1]; 20000[7];
3087	Toshiba	TMPM324F10FG internal	0	0	1	21	4	32	1	1	0	0	0	0	0	0	0	0	0	0	0	8000[2]; 10000[1]; 20000[7];
3088	Toshiba	TMPM330FDFG internal	0	0	1	21	0	32	1	1	0	0	0	0	0	0	0	0	0	0	0	8000[2]; 10000[1]; 20000[3];
3089	Toshiba	TMPM330FWFG internal	0	0	1	21	1	32	1	1	0	0	0	0	0	0	0	0	0	0	0	4000[2]; 8000[1]; 10000[1];
3090	Toshiba	TMPM330FYFG internal	0	0	1	21	0	32	1	1	0	0	0	0	0	0	0	0	0	0	0	8000[2]; 10000[1]; 20000[1];
3091	Toshiba	TMPM332FWUG internal	0	0	1	21	1	32	1	1	0	0	0	0	0	0	0	0	0	0	0	4000[2]; 8000[1]; 10000[1];
3092	Toshiba	TMPM333FDFG internal	0	0	1	21	0	32	1	1	0	0	0	0	0	0	0	0	0	0	0	8000[2]; 10000[1]; 20000[3];
3093	Toshiba	TMPM333FWFG internal	0	0	1	21	1	32	1	1	0	0	0	0	0	0	0	0	0	0	0	4000[2]; 8000[1]; 10000[1];
3094	Toshiba	TMPM333FYFG internal	0	0	1	21	0	32	1	1	0	0	0	0	0	0	0	0	0	0	0	8000[2]; 10000[1]; 20000[1];
3095	Toshiba	TMPM341FDXBG internal	0	0	1	21	6	32	1	1	0	0	0	0	0	0	0	0	0	0	0	8000[2]; 10000[1]; 20000[3];
3096	Toshiba	TMPM341FYXBG internal	0	0	1	21	7	32	1	1	0	0	0	0	0	0	0	0	0	0	0	4000[2]; 8000[1]; 10000[3];
3097	Toshiba	TMPM342FYXBG internal	0	0	1	21	9	32	1	1	0	0	0	0	0	0	0	0	0	0	0	4000[2]; 8000[1]; 10000[3];
3098	Toshiba	TMPM343F10XBG internal	0	0	1	51	6	32	1	1	0	0	0	0	0	0	0	0	0	0	0	8000[32];
3099	Toshiba	TMPM343FDXBG internal	0	0	1	51	6	32	1	1	0	0	0	0	0	0	0	0	0	0	0	8000[16]; 1000[1];
3100	Toshiba	TMPM343FEXBG internal	0	0	1	51	6	32	1	1	0	0	0	0	0	0	0	0	0	0	0	8000[24];
3101	Toshiba	TMPM350FDTFG internal	0	0	1	71	0	32	1	0	0	0	0	0	0	0	0	0	0	0	0	8000[2]; 10000[1]; 20000[3];
3102	Toshiba	TMPM351F10T internal	0	0	1	51	3	32	1	1	0	0	0	0	0	0	0	0	0	0	0	8000[32];
3103	Toshiba	TMPM358FDTFG internal	0	0	1	51	2	32	1	1	0	0	0	0	0	0	0	0	0	0	0	4000[4];8000[2];10000[6];
3104	Toshiba	TMPM360F20FG internal	0	0	1	21	2	32	1	1	0	0	0	0	0	0	0	0	0	0	0	8000[2]; 10000[1]; 20000[14]; 10000[1]; 8000[2];
3105	Toshiba	TMPM361F10FG internal	0	0	1	21	4	32	1	1	0	0	0	0	0	0	0	0	0	0	0	8000[2]; 10000[1]; 20000[7];
3106	Toshiba	TMPM362F10FG internal	0	0	1	21	4	32	1	1	0	0	0	0	0	0	0	0	0	0	0	8000[2]; 10000[1]; 20000[7];
3107	Toshiba	TMPM363F10FG internal	0	0	1	21	4	32	1	1	0	0	0	0	0	0	0	0	0	0	0	8000[2]; 10000[1]; 20000[7];
3108	Toshiba	TMPM364F10FG internal	0	0	1	21	4	32	1	1	0	0	0	0	0	0	0	0	0	0	0	8000[2]; 10000[1]; 20000[7];
3109	Toshiba	TMPM365FYXBG internal	0	0	1	21	9	32	1	1	0	0	0	0	0	0	0	0	0	0	0	4000[2]; 8000[1]; 10000[3];
3110	Toshiba	TMPM366FDFG internal	0	0	1	21	6	32	1	1	0	0	0	0	0	0	0	0	0	0	0	8000[2]; 10000[1]; 20000[3];
3111	Toshiba	TMPM366FDXBG internal	0	0	1	21	6	32	1	1	0	0	0	0	0	0	0	0	0	0	0	8000[2]; 10000[1]; 20000[3];
3112	Toshiba	TMPM366FWFG internal	0	0	1	21	6	32	1	1	0	0	0	0	0	0	0	0	0	0	0	8000[2]; 10000[1];
3113	Toshiba	TMPM366FWXBG internal	0	0	1	21	6	32	1	1	0	0	0	0	0	0	0	0	0	0	0	8000[2]; 10000[1];
3114	Toshiba	TMPM366FYFG internal	0	0	1	21	6	32	1	1	0	0	0	0	0	0	0	0	0	0	0	8000[2]; 10000[1]; 20000[1];
3115	Toshiba	TMPM366FYXBG internal	0	0	1	21	6	32	1	1	0	0	0	0	0	0	0	0	0	0	0	8000[2]; 10000[1]; 20000[1];
3116	Toshiba	TMPM367FDFG internal	0	0	1	21	6	32	1	1	0	0	0	0	0	0	0	0	0	0	0	8000[2]; 10000[1]; 20000[3];
3117	Toshiba	TMPM367FDXBG internal	0	0	1	21	6	32	1	1	0	0	0	0	0	0	0	0	0	0	0	8000[2]; 10000[1]; 20000[3];
3118	Toshiba	TMPM368FDFG internal	0	0	1	21	6	32	1	1	0	0	0	0	0	0	0	0	0	0	0	8000[2]; 10000[1]; 20000[3];
3119	Toshiba	TMPM368FDXBG internal	0	0	1	21	6	32	1	1	0	0	0	0	0	0	0	0	0	0	0	8000[2]; 10000[1]; 20000[3];
3120	Toshiba	TMPM369FDFG internal	0	0	1	21	6	32	1	1	0	0	0	0	0	0	0	0	0	0	0	8000[2]; 10000[1]; 20000[3];
3121	Toshiba	TMPM369FDXBG internal	0	0	1	21	6	32	1	1	0	0	0	0	0	0	0	0	0	0	0	8000[2]; 10000[1]; 20000[3];
3122	Toshiba	TMPM369FYFG internal	0	0	1	21	6	32	1	1	0	0	0	0	0	0	0	0	0	0	0	8000[2]; 10000[1]; 20000[1];
3123	Toshiba	TMPM36BF10FG internal	0	0	1	21	6	32	1	1	0	0	0	0	0	0	0	0	0	0	0	8000[2]; 10000[1]; 20000[7];
3124	Toshiba	TMPM36BFYFG internal	0	0	1	21	7	32	1	1	0	0	0	0	0	0	0	0	0	0	0	4000[2]; 8000[1]; 10000[3];
3125	Toshiba	TMPM370FYDFG internal	0	0	1	21	3	32	1	1	0	0	0	0	0	0	0	0	0	0	0	4000[2]; 8000[1]; 10000[3];
3126	Toshiba	TMPM370FYFG internal	0	0	1	21	3	32	1	1	0	0	0	0	0	0	0	0	0	0	0	4000[2]; 8000[1]; 10000[3];
3127	Toshiba	TMPM372FWUG internal	0	0	1	21	3	32	1	1	0	0	0	0	0	0	0	0	0	0	0	4000[2]; 8000[1]; 10000[1];
3128	Toshiba	TMPM373FWDUG internal	0	0	1	21	3	32	1	1	0	0	0	0	0	0	0	0	0	0	0	4000[2]; 8000[1]; 10000[1];
3129	Toshiba	TMPM374FWUG internal	0	0	1	21	3	32	1	1	0	0	0	0	0	0	0	0	0	0	0	4000[2]; 8000[1]; 10000[1];
3130	Toshiba	TMPM375FSDMG internal	0	0	1	51	5	32	1	1	0	0	0	0	0	0	0	0	0	0	0	8000[2];
3131	Toshiba	TMPM376FDDFG internal	0	0	1	21	8	32	1	1	0	0	0	0	0	0	0	0	0	0	0	8000[2]; 10000[1]; 20000[3];
3132	Toshiba	TMPM376FDFG internal	0	0	1	21	8	32	1	1	0	0	0	0	0	0	0	0	0	0	0	8000[2]; 10000[1]; 20000[3];
3133	Toshiba	TMPM377FDDFG internal	0	0	1	21	8	32	1	1	0	0	0	0	0	0	0	0	0	0	0	8000[2]; 10000[1]; 20000[3];
3134	Toshiba	TMPM377FDFG internal	0	0	1	21	8	32	1	1	0	0	0	0	0	0	0	0	0	0	0	8000[2]; 10000[1]; 20000[3];
3135	Toshiba	TMPM377FYDFG internal	0	0	1	21	8	32	1	1	0	0	0	0	0	0	0	0	0	0	0	8000[2]; 10000[1]; 20000[1];
3136	Toshiba	TMPM377FYFG internal	0	0	1	21	8	32	1	1	0	0	0	0	0	0	0	0	0	0	0	8000[2]; 10000[1]; 20000[1];
3137	Toshiba	TMPM380FDFG internal	0	0	1	21	8	32	1	1	0	0	0	0	0	0	0	0	0	0	0	8000[2]; 10000[1]; 20000[3];
3138	Toshiba	TMPM380FWDFG internal	0	0	1	21	3	32	1	1	0	0	0	0	0	0	0	0	0	0	0	4000[2]; 8000[1]; 10000[1];
3139	Toshiba	TMPM380FWFG internal	0	0	1	21	3	32	1	1	0	0	0	0	0	0	0	0	0	0	0	4000[2]; 8000[1]; 10000[1];
3140	Toshiba	TMPM380FYDFG internal	0	0	1	21	3	32	1	1	0	0	0	0	0	0	0	0	0	0	0	4000[2]; 8000[1]; 10000[3];
3141	Toshiba	TMPM380FYFG internal	0	0	1	21	3	32	1	1	0	0	0	0	0	0	0	0	0	0	0	4000[2]; 8000[1]; 10000[3];
3142	Toshiba	TMPM382FSFG internal	0	0	1	21	3	32	1	1	0	0	0	0	0	0	0	0	0	0	0	4000[2]; 8000[1];
3143	Toshiba	TMPM382FWFG internal	0	0	1	21	3	32	1	1	0	0	0	0	0	0	0	0	0	0	0	4000[2]; 8000[1]; 10000[1];
3144	Toshiba	TMPM384FDFG internal	0	0	1	21	8	32	1	1	0	0	0	0	0	0	0	0	0	0	0	8000[2]; 10000[1]; 20000[3];
3145	Toshiba	TMPM390FWFG internal	0	0	1	21	5	32	1	1	0	0	0	0	0	0	0	0	0	0	0	8000[4];
3146	Toshiba	TMPM395FWXBG internal	0	0	1	21	5	32	1	1	0	0	0	0	0	0	0	0	0	0	0	8000[4];
3147	Toshiba	TMPM440F10XBG internal	0	0	1	51	1	32	1	1	0	0	0	0	0	0	0	0	0	0	0	800[512];
3148	Toshiba	TMPM440FEXBG internal	0	0	1	51	1	32	1	1	0	0	0	0	0	0	0	0	0	0	0	800[256];
3149	Toshiba	TMPM461F10xx internal	0	0	1	51	4	32	1	1	0	0	0	0	0	0	0	0	0	0	0	8000[32];
3150	Toshiba	TMPM461F15xx internal	0	0	1	51	4	32	1	1	0	0	0	0	0	0	0	0	0	0	0	8000[48];
3151	Toshiba	TMPM462F10xx internal	0	0	1	51	4	32	1	1	0	0	0	0	0	0	0	0	0	0	0	8000[32];
3152	Toshiba	TMPM462F15xx internal	0	0	1	51	4	32	1	1	0	0	0	0	0	0	0	0	0	0	0	8000[48];
3153	Toshiba	TMPM46BF10xx internal	0	0	1	51	7	32	1	1	0	0	0	0	0	0	0	0	0	0	0	8000[32];
3154	Toshiba	TZ100x internal	0	0	1	90	0	32	1	1	0	0	0	0	0	0	0	0	0	0	0	1000[256];
3155	ZMDI	ZAMC4100 internal	0	0	1	92	0	32	1	1	0	0	0	0	0	0	0	0	0	0	0	200[64];
3156	ZMDI	ZSSC1956 internal	0	0	1	92	0	32	1	1	0	0	0	0	0	0	0	0	0	0	0	200[192];