1215 lines
39 KiB
C
1215 lines
39 KiB
C
/**
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******************************************************************************
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* @file stm32l0xx_hal_rcc_ex.c
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* @author MCD Application Team
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* @brief Extended RCC HAL module driver.
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* This file provides firmware functions to manage the following
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* functionalities RCC extension peripheral:
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* + Extended Peripheral Control functions
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* + Extended Clock Recovery System Control functions
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*
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******************************************************************************
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* @attention
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*
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* <h2><center>© Copyright(c) 2016 STMicroelectronics.
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* All rights reserved.</center></h2>
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*
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* This software component is licensed by ST under BSD 3-Clause license,
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* the "License"; You may not use this file except in compliance with the
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* License. You may obtain a copy of the License at:
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* opensource.org/licenses/BSD-3-Clause
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*
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******************************************************************************
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*/
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/* Includes ------------------------------------------------------------------*/
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#include "stm32l0xx_hal.h"
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/** @addtogroup STM32L0xx_HAL_Driver
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* @{
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*/
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#ifdef HAL_RCC_MODULE_ENABLED
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/** @defgroup RCCEx RCCEx
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* @brief RCC Extension HAL module driver
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* @{
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*/
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/* Private typedef -----------------------------------------------------------*/
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/* Private define ------------------------------------------------------------*/
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/** @defgroup RCCEx_Private_Constants RCCEx Private Constants
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* @{
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*/
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#if defined(USB)
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extern const uint8_t PLLMulTable[];
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#endif /* USB */
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/**
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* @}
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*/
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/* Private macro -------------------------------------------------------------*/
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/** @defgroup RCCEx_Private_Macros RCCEx Private Macros
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* @{
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*/
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/**
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* @}
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*/
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/* Private variables ---------------------------------------------------------*/
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/* Private function prototypes -----------------------------------------------*/
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/* Private functions ---------------------------------------------------------*/
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/** @defgroup RCCEx_Exported_Functions RCCEx Exported Functions
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* @{
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*/
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/** @defgroup RCCEx_Exported_Functions_Group1 Extended Peripheral Control functions
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* @brief Extended Peripheral Control functions
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*
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@verbatim
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===============================================================================
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##### Extended Peripheral Control functions #####
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===============================================================================
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[..]
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This subsection provides a set of functions allowing to control the RCC Clocks
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frequencies.
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[..]
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(@) Important note: Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to
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select the RTC clock source; in this case the Backup domain will be reset in
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order to modify the RTC Clock source, as consequence RTC registers (including
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the backup registers) are set to their reset values.
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@endverbatim
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* @{
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*/
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/**
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* @brief Initializes the RCC extended peripherals clocks according to the specified
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* parameters in the RCC_PeriphCLKInitTypeDef.
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* @param PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that
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* contains the configuration information for the Extended Peripherals clocks(USART1,USART2, LPUART1,
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* I2C1, I2C3, RTC, USB/RNG and LPTIM1 clocks).
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* @retval HAL status
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* @note If HAL_ERROR returned, first switch-OFF HSE clock oscillator with @ref HAL_RCC_OscConfig()
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* to possibly update HSE divider.
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*/
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HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
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{
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uint32_t tickstart;
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uint32_t temp_reg;
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FlagStatus pwrclkchanged = RESET;
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/* Check the parameters */
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assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection));
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/*------------------------------- RTC/LCD Configuration ------------------------*/
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if ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC)
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#if defined(LCD)
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|| (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LCD) == RCC_PERIPHCLK_LCD)
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#endif /* LCD */
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)
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{
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/* check for RTC Parameters used to output RTCCLK */
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if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC)
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{
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assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection));
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}
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#if defined(LCD)
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if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LCD) == RCC_PERIPHCLK_LCD)
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{
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assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->LCDClockSelection));
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}
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#endif /* LCD */
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/* As soon as function is called to change RTC clock source, activation of the
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power domain is done. */
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/* Requires to enable write access to Backup Domain of necessary */
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if(__HAL_RCC_PWR_IS_CLK_DISABLED())
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{
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__HAL_RCC_PWR_CLK_ENABLE();
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pwrclkchanged = SET;
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}
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if(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
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{
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/* Enable write access to Backup domain */
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SET_BIT(PWR->CR, PWR_CR_DBP);
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/* Wait for Backup domain Write protection disable */
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tickstart = HAL_GetTick();
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while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
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{
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if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
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{
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return HAL_TIMEOUT;
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}
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}
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}
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/* Check if user wants to change HSE RTC prescaler whereas HSE is enabled */
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temp_reg = (RCC->CR & RCC_CR_RTCPRE);
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if ((temp_reg != (PeriphClkInit->RTCClockSelection & RCC_CR_RTCPRE))
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#if defined (LCD)
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|| (temp_reg != (PeriphClkInit->LCDClockSelection & RCC_CR_RTCPRE))
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#endif /* LCD */
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)
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{ /* Check HSE State */
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if ((PeriphClkInit->RTCClockSelection & RCC_CSR_RTCSEL) == RCC_CSR_RTCSEL_HSE)
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{
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if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY))
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{
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/* To update HSE divider, first switch-OFF HSE clock oscillator*/
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return HAL_ERROR;
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}
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}
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}
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/* Reset the Backup domain only if the RTC Clock source selection is modified from reset value */
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temp_reg = (RCC->CSR & RCC_CSR_RTCSEL);
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if((temp_reg != 0x00000000U) && (((temp_reg != (PeriphClkInit->RTCClockSelection & RCC_CSR_RTCSEL)) \
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&& (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC))
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#if defined(LCD)
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|| ((temp_reg != (PeriphClkInit->LCDClockSelection & RCC_CSR_RTCSEL)) \
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&& (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LCD) == RCC_PERIPHCLK_LCD))
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#endif /* LCD */
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))
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{
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/* Store the content of CSR register before the reset of Backup Domain */
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temp_reg = (RCC->CSR & ~(RCC_CSR_RTCSEL));
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/* RTC Clock selection can be changed only if the Backup Domain is reset */
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__HAL_RCC_BACKUPRESET_FORCE();
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__HAL_RCC_BACKUPRESET_RELEASE();
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/* Restore the Content of CSR register */
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RCC->CSR = temp_reg;
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/* Wait for LSERDY if LSE was enabled */
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if (HAL_IS_BIT_SET(temp_reg, RCC_CSR_LSEON))
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{
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/* Get Start Tick */
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tickstart = HAL_GetTick();
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/* Wait till LSE is ready */
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while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == 0U)
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{
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if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
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{
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return HAL_TIMEOUT;
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}
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}
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}
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}
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__HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);
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/* Require to disable power clock if necessary */
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if(pwrclkchanged == SET)
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{
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__HAL_RCC_PWR_CLK_DISABLE();
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}
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}
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#if defined (RCC_CCIPR_USART1SEL)
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/*------------------------------- USART1 Configuration ------------------------*/
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if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1)
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{
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/* Check the parameters */
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assert_param(IS_RCC_USART1CLKSOURCE(PeriphClkInit->Usart1ClockSelection));
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/* Configure the USART1 clock source */
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__HAL_RCC_USART1_CONFIG(PeriphClkInit->Usart1ClockSelection);
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}
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#endif /* RCC_CCIPR_USART1SEL */
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/*----------------------------- USART2 Configuration --------------------------*/
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if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2)
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{
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/* Check the parameters */
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assert_param(IS_RCC_USART2CLKSOURCE(PeriphClkInit->Usart2ClockSelection));
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/* Configure the USART2 clock source */
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__HAL_RCC_USART2_CONFIG(PeriphClkInit->Usart2ClockSelection);
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}
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/*------------------------------ LPUART1 Configuration ------------------------*/
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if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1)
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{
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/* Check the parameters */
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assert_param(IS_RCC_LPUART1CLKSOURCE(PeriphClkInit->Lpuart1ClockSelection));
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/* Configure the LPUAR1 clock source */
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__HAL_RCC_LPUART1_CONFIG(PeriphClkInit->Lpuart1ClockSelection);
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}
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/*------------------------------ I2C1 Configuration ------------------------*/
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if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1)
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{
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/* Check the parameters */
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assert_param(IS_RCC_I2C1CLKSOURCE(PeriphClkInit->I2c1ClockSelection));
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/* Configure the I2C1 clock source */
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__HAL_RCC_I2C1_CONFIG(PeriphClkInit->I2c1ClockSelection);
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}
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#if defined (RCC_CCIPR_I2C3SEL)
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/*------------------------------ I2C3 Configuration ------------------------*/
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if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3)
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{
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/* Check the parameters */
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assert_param(IS_RCC_I2C3CLKSOURCE(PeriphClkInit->I2c3ClockSelection));
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/* Configure the I2C3 clock source */
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__HAL_RCC_I2C3_CONFIG(PeriphClkInit->I2c3ClockSelection);
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}
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#endif /* RCC_CCIPR_I2C3SEL */
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#if defined(USB)
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/*---------------------------- USB and RNG configuration --------------------*/
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if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USB) == (RCC_PERIPHCLK_USB))
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{
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assert_param(IS_RCC_USBCLKSOURCE(PeriphClkInit->UsbClockSelection));
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__HAL_RCC_USB_CONFIG(PeriphClkInit->UsbClockSelection);
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}
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#endif /* USB */
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/*---------------------------- LPTIM1 configuration ------------------------*/
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if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM1) == (RCC_PERIPHCLK_LPTIM1))
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{
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assert_param(IS_RCC_LPTIMCLK(PeriphClkInit->LptimClockSelection));
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__HAL_RCC_LPTIM1_CONFIG(PeriphClkInit->LptimClockSelection);
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}
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return HAL_OK;
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}
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/**
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* @brief Get the PeriphClkInit according to the internal RCC configuration registers.
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* @param PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that
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* returns the configuration information for the Extended Peripherals clocks(USART1,USART2, LPUART1,
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* I2C1, I2C3, RTC, USB/RNG and LPTIM1 clocks).
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* @retval None
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*/
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void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
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{
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uint32_t srcclk;
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/* Set all possible values for the extended clock type parameter -----------*/
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/* Common part first */
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PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_LPUART1 | \
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RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_RTC | \
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RCC_PERIPHCLK_LPTIM1;
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#if defined(RCC_CCIPR_USART1SEL)
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PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_USART1;
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#endif /* RCC_CCIPR_USART1SEL */
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#if defined(RCC_CCIPR_I2C3SEL)
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PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_I2C3;
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#endif /* RCC_CCIPR_I2C3SEL */
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#if defined(USB)
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PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_USB;
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#endif /* USB */
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#if defined(LCD)
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PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_LCD;
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#endif /* LCD */
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/* Get the RTC/LCD configuration -----------------------------------------------*/
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srcclk = __HAL_RCC_GET_RTC_SOURCE();
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if (srcclk != RCC_RTCCLKSOURCE_HSE_DIV2)
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{
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/* Source clock is LSE or LSI*/
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PeriphClkInit->RTCClockSelection = srcclk;
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}
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else
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{
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/* Source clock is HSE. Need to get the prescaler value*/
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PeriphClkInit->RTCClockSelection = srcclk | (READ_BIT(RCC->CR, RCC_CR_RTCPRE));
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}
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#if defined(LCD)
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PeriphClkInit->LCDClockSelection = PeriphClkInit->RTCClockSelection;
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#endif /* LCD */
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#if defined(RCC_CCIPR_USART1SEL)
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/* Get the USART1 configuration --------------------------------------------*/
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PeriphClkInit->Usart1ClockSelection = __HAL_RCC_GET_USART1_SOURCE();
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#endif /* RCC_CCIPR_USART1SEL */
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/* Get the USART2 clock source ---------------------------------------------*/
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PeriphClkInit->Usart2ClockSelection = __HAL_RCC_GET_USART2_SOURCE();
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/* Get the LPUART1 clock source ---------------------------------------------*/
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PeriphClkInit->Lpuart1ClockSelection = __HAL_RCC_GET_LPUART1_SOURCE();
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/* Get the I2C1 clock source -----------------------------------------------*/
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PeriphClkInit->I2c1ClockSelection = __HAL_RCC_GET_I2C1_SOURCE();
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#if defined(RCC_CCIPR_I2C3SEL)
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/* Get the I2C3 clock source -----------------------------------------------*/
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PeriphClkInit->I2c3ClockSelection = __HAL_RCC_GET_I2C3_SOURCE();
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#endif /* RCC_CCIPR_I2C3SEL */
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/* Get the LPTIM1 clock source -----------------------------------------------*/
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PeriphClkInit->LptimClockSelection = __HAL_RCC_GET_LPTIM1_SOURCE();
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/* Get the RTC clock source -----------------------------------------------*/
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PeriphClkInit->RTCClockSelection = __HAL_RCC_GET_RTC_SOURCE();
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#if defined(USB)
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/* Get the USB/RNG clock source -----------------------------------------------*/
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PeriphClkInit->UsbClockSelection = __HAL_RCC_GET_USB_SOURCE();
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#endif /* USB */
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}
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/**
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* @brief Return the peripheral clock frequency
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* @note Return 0 if peripheral clock is unknown
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* @param PeriphClk Peripheral clock identifier
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* This parameter can be one of the following values:
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* @arg @ref RCC_PERIPHCLK_RTC RTC peripheral clock
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* @arg @ref RCC_PERIPHCLK_LCD LCD peripheral clock (*)
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* @arg @ref RCC_PERIPHCLK_USB USB or RNG peripheral clock (*)
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* @arg @ref RCC_PERIPHCLK_USART1 USART1 peripheral clock (*)
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* @arg @ref RCC_PERIPHCLK_USART2 USART2 peripheral clock
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* @arg @ref RCC_PERIPHCLK_LPUART1 LPUART1 peripheral clock
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* @arg @ref RCC_PERIPHCLK_I2C1 I2C1 peripheral clock
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* @arg @ref RCC_PERIPHCLK_I2C2 I2C2 peripheral clock (*)
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* @arg @ref RCC_PERIPHCLK_I2C3 I2C3 peripheral clock (*)
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* @note (*) means that this peripheral is not present on all the devices
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* @retval Frequency in Hz (0: means that no available frequency for the peripheral)
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*/
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uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)
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{
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uint32_t frequency = 0U;
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uint32_t temp_reg, clkprediv, srcclk; /* no init needed */
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#if defined(USB)
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uint32_t pllmul, plldiv, pllvco; /* no init needed */
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#endif /* USB */
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/* Check the parameters */
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assert_param(IS_RCC_PERIPHCLOCK(PeriphClk));
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switch (PeriphClk)
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{
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case RCC_PERIPHCLK_RTC:
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#if defined(LCD)
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case RCC_PERIPHCLK_LCD:
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#endif /* LCD */
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{
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/* Get RCC CSR configuration ------------------------------------------------------*/
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temp_reg = RCC->CSR;
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/* Get the current RTC source */
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srcclk = __HAL_RCC_GET_RTC_SOURCE();
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/* Check if LSE is ready if RTC clock selection is LSE */
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if ((srcclk == RCC_RTCCLKSOURCE_LSE) && (HAL_IS_BIT_SET(temp_reg, RCC_CSR_LSERDY)))
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{
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frequency = LSE_VALUE;
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}
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/* Check if LSI is ready if RTC clock selection is LSI */
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else if (srcclk == RCC_RTCCLKSOURCE_LSI)
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{
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if (HAL_IS_BIT_SET(temp_reg, RCC_CSR_LSIRDY))
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{
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frequency = LSI_VALUE;
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}
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}
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/* Check if HSE is ready and if RTC clock selection is HSE */
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else if (srcclk == RCC_RTCCLKSOURCE_HSE_DIVX)
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{
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if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY))
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{
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/* Get the current HSE clock divider */
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clkprediv = __HAL_RCC_GET_RTC_HSE_PRESCALER();
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switch (clkprediv)
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{
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case RCC_RTC_HSE_DIV_16: /* HSE DIV16 has been selected */
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{
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frequency = HSE_VALUE / 16U;
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break;
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}
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case RCC_RTC_HSE_DIV_8: /* HSE DIV8 has been selected */
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{
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frequency = HSE_VALUE / 8U;
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break;
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}
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case RCC_RTC_HSE_DIV_4: /* HSE DIV4 has been selected */
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{
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frequency = HSE_VALUE / 4U;
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break;
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}
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default: /* HSE DIV2 has been selected */
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{
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frequency = HSE_VALUE / 2U;
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break;
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}
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}
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}
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}
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/* Clock not enabled for RTC */
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else
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{
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frequency = 0U;
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}
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break;
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}
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#if defined(USB)
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case RCC_PERIPHCLK_USB:
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{
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/* Get the current USB source */
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srcclk = __HAL_RCC_GET_USB_SOURCE();
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|
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if (srcclk == RCC_USBCLKSOURCE_PLL)
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{
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if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLRDY))
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{
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/* Get PLL clock source and multiplication factor ----------------------*/
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pllmul = RCC->CFGR & RCC_CFGR_PLLMUL;
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plldiv = RCC->CFGR & RCC_CFGR_PLLDIV;
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pllmul = PLLMulTable[(pllmul >> RCC_CFGR_PLLMUL_Pos)];
|
|
plldiv = (plldiv >> RCC_CFGR_PLLDIV_Pos) + 1U;
|
|
|
|
/* Compute PLL clock input */
|
|
if(__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSI)
|
|
{
|
|
if (READ_BIT(RCC->CR, RCC_CR_HSIDIVF) != 0U)
|
|
{
|
|
pllvco = (HSI_VALUE >> 2U);
|
|
}
|
|
else
|
|
{
|
|
pllvco = HSI_VALUE;
|
|
}
|
|
}
|
|
else /* HSE source */
|
|
{
|
|
pllvco = HSE_VALUE;
|
|
}
|
|
/* pllvco * pllmul / plldiv */
|
|
pllvco = (pllvco * pllmul);
|
|
frequency = (pllvco/ plldiv);
|
|
}
|
|
}
|
|
else if (srcclk == RCC_USBCLKSOURCE_HSI48)
|
|
{
|
|
if (HAL_IS_BIT_SET(RCC->CRRCR, RCC_CRRCR_HSI48RDY))
|
|
{
|
|
frequency = HSI48_VALUE;
|
|
}
|
|
}
|
|
else /* RCC_USBCLKSOURCE_NONE */
|
|
{
|
|
frequency = 0U;
|
|
}
|
|
break;
|
|
}
|
|
#endif /* USB */
|
|
#if defined(RCC_CCIPR_USART1SEL)
|
|
case RCC_PERIPHCLK_USART1:
|
|
{
|
|
/* Get the current USART1 source */
|
|
srcclk = __HAL_RCC_GET_USART1_SOURCE();
|
|
|
|
/* Check if USART1 clock selection is PCLK2 */
|
|
if (srcclk == RCC_USART1CLKSOURCE_PCLK2)
|
|
{
|
|
frequency = HAL_RCC_GetPCLK2Freq();
|
|
}
|
|
/* Check if HSI is ready and if USART1 clock selection is HSI */
|
|
else if (srcclk == RCC_USART1CLKSOURCE_HSI)
|
|
{
|
|
if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))
|
|
{
|
|
if (READ_BIT(RCC->CR, RCC_CR_HSIDIVF) != 0U)
|
|
{
|
|
frequency = (HSI_VALUE >> 2U);
|
|
}
|
|
else
|
|
{
|
|
frequency = HSI_VALUE;
|
|
}
|
|
}
|
|
}
|
|
/* Check if USART1 clock selection is SYSCLK */
|
|
else if (srcclk == RCC_USART1CLKSOURCE_SYSCLK)
|
|
{
|
|
frequency = HAL_RCC_GetSysClockFreq();
|
|
}
|
|
/* Check if LSE is ready and if USART1 clock selection is LSE */
|
|
else if (srcclk == RCC_USART1CLKSOURCE_LSE)
|
|
{
|
|
if (HAL_IS_BIT_SET(RCC->CSR, RCC_CSR_LSERDY))
|
|
{
|
|
frequency = LSE_VALUE;
|
|
}
|
|
}
|
|
/* Clock not enabled for USART1*/
|
|
else
|
|
{
|
|
frequency = 0U;
|
|
}
|
|
break;
|
|
}
|
|
#endif /* RCC_CCIPR_USART1SEL */
|
|
case RCC_PERIPHCLK_USART2:
|
|
{
|
|
/* Get the current USART2 source */
|
|
srcclk = __HAL_RCC_GET_USART2_SOURCE();
|
|
|
|
/* Check if USART2 clock selection is PCLK1 */
|
|
if (srcclk == RCC_USART2CLKSOURCE_PCLK1)
|
|
{
|
|
frequency = HAL_RCC_GetPCLK1Freq();
|
|
}
|
|
/* Check if HSI is ready and if USART2 clock selection is HSI */
|
|
else if (srcclk == RCC_USART2CLKSOURCE_HSI)
|
|
{
|
|
if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))
|
|
{
|
|
if (READ_BIT(RCC->CR, RCC_CR_HSIDIVF) != 0U)
|
|
{
|
|
frequency = (HSI_VALUE >> 2U);
|
|
}
|
|
else
|
|
{
|
|
frequency = HSI_VALUE;
|
|
}
|
|
}
|
|
}
|
|
/* Check if USART2 clock selection is SYSCLK */
|
|
else if (srcclk == RCC_USART2CLKSOURCE_SYSCLK)
|
|
{
|
|
frequency = HAL_RCC_GetSysClockFreq();
|
|
}
|
|
/* Check if LSE is ready and if USART2 clock selection is LSE */
|
|
else if (srcclk == RCC_USART2CLKSOURCE_LSE)
|
|
{
|
|
if (HAL_IS_BIT_SET(RCC->CSR, RCC_CSR_LSERDY))
|
|
{
|
|
frequency = LSE_VALUE;
|
|
}
|
|
}
|
|
/* Clock not enabled for USART2*/
|
|
else
|
|
{
|
|
frequency = 0U;
|
|
}
|
|
break;
|
|
}
|
|
case RCC_PERIPHCLK_LPUART1:
|
|
{
|
|
/* Get the current LPUART1 source */
|
|
srcclk = __HAL_RCC_GET_LPUART1_SOURCE();
|
|
|
|
/* Check if LPUART1 clock selection is PCLK1 */
|
|
if (srcclk == RCC_LPUART1CLKSOURCE_PCLK1)
|
|
{
|
|
frequency = HAL_RCC_GetPCLK1Freq();
|
|
}
|
|
/* Check if HSI is ready and if LPUART1 clock selection is HSI */
|
|
else if (srcclk == RCC_LPUART1CLKSOURCE_HSI)
|
|
{
|
|
if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))
|
|
{
|
|
if (READ_BIT(RCC->CR, RCC_CR_HSIDIVF) != 0U)
|
|
{
|
|
frequency = (HSI_VALUE >> 2U);
|
|
}
|
|
else
|
|
{
|
|
frequency = HSI_VALUE;
|
|
}
|
|
}
|
|
}
|
|
/* Check if LPUART1 clock selection is SYSCLK */
|
|
else if (srcclk == RCC_LPUART1CLKSOURCE_SYSCLK)
|
|
{
|
|
frequency = HAL_RCC_GetSysClockFreq();
|
|
}
|
|
/* Check if LSE is ready and if LPUART1 clock selection is LSE */
|
|
else if (srcclk == RCC_LPUART1CLKSOURCE_LSE)
|
|
{
|
|
if (HAL_IS_BIT_SET(RCC->CSR, RCC_CSR_LSERDY))
|
|
{
|
|
frequency = LSE_VALUE;
|
|
}
|
|
}
|
|
/* Clock not enabled for LPUART1*/
|
|
else
|
|
{
|
|
frequency = 0U;
|
|
}
|
|
break;
|
|
}
|
|
case RCC_PERIPHCLK_I2C1:
|
|
{
|
|
/* Get the current I2C1 source */
|
|
srcclk = __HAL_RCC_GET_I2C1_SOURCE();
|
|
|
|
/* Check if I2C1 clock selection is PCLK1 */
|
|
if (srcclk == RCC_I2C1CLKSOURCE_PCLK1)
|
|
{
|
|
frequency = HAL_RCC_GetPCLK1Freq();
|
|
}
|
|
/* Check if HSI is ready and if I2C1 clock selection is HSI */
|
|
else if (srcclk == RCC_I2C1CLKSOURCE_HSI)
|
|
{
|
|
if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))
|
|
{
|
|
if (READ_BIT(RCC->CR, RCC_CR_HSIDIVF) != 0U)
|
|
{
|
|
frequency = (HSI_VALUE >> 2U);
|
|
}
|
|
else
|
|
{
|
|
frequency = HSI_VALUE;
|
|
}
|
|
}
|
|
}
|
|
/* Check if I2C1 clock selection is SYSCLK */
|
|
else if (srcclk == RCC_I2C1CLKSOURCE_SYSCLK)
|
|
{
|
|
frequency = HAL_RCC_GetSysClockFreq();
|
|
}
|
|
/* Clock not enabled for I2C1*/
|
|
else
|
|
{
|
|
frequency = 0U;
|
|
}
|
|
break;
|
|
}
|
|
#if defined(I2C2)
|
|
case RCC_PERIPHCLK_I2C2:
|
|
{
|
|
|
|
/* Check if I2C2 on APB1 clock enabled*/
|
|
if (READ_BIT(RCC->APB1ENR, (RCC_APB1ENR_I2C2EN))==RCC_APB1ENR_I2C2EN)
|
|
{
|
|
frequency = HAL_RCC_GetPCLK1Freq();
|
|
}
|
|
else
|
|
{
|
|
frequency = 0U;
|
|
}
|
|
break;
|
|
}
|
|
#endif /* I2C2 */
|
|
|
|
#if defined(RCC_CCIPR_I2C3SEL)
|
|
case RCC_PERIPHCLK_I2C3:
|
|
{
|
|
/* Get the current I2C3 source */
|
|
srcclk = __HAL_RCC_GET_I2C3_SOURCE();
|
|
|
|
/* Check if I2C3 clock selection is PCLK1 */
|
|
if (srcclk == RCC_I2C3CLKSOURCE_PCLK1)
|
|
{
|
|
frequency = HAL_RCC_GetPCLK1Freq();
|
|
}
|
|
/* Check if HSI is ready and if I2C3 clock selection is HSI */
|
|
else if (srcclk == RCC_I2C3CLKSOURCE_HSI)
|
|
{
|
|
if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))
|
|
{
|
|
if (READ_BIT(RCC->CR, RCC_CR_HSIDIVF) != 0U)
|
|
{
|
|
frequency = (HSI_VALUE >> 2U);
|
|
}
|
|
else
|
|
{
|
|
frequency = HSI_VALUE;
|
|
}
|
|
}
|
|
}
|
|
/* Check if I2C3 clock selection is SYSCLK */
|
|
else if (srcclk == RCC_I2C3CLKSOURCE_SYSCLK)
|
|
{
|
|
frequency = HAL_RCC_GetSysClockFreq();
|
|
}
|
|
/* Clock not enabled for I2C3*/
|
|
else
|
|
{
|
|
frequency = 0U;
|
|
}
|
|
break;
|
|
}
|
|
#endif /* RCC_CCIPR_I2C3SEL */
|
|
default:
|
|
{
|
|
break;
|
|
}
|
|
}
|
|
return(frequency);
|
|
}
|
|
|
|
/**
|
|
* @brief Enables the LSE Clock Security System.
|
|
* @retval None
|
|
*/
|
|
void HAL_RCCEx_EnableLSECSS(void)
|
|
{
|
|
SET_BIT(RCC->CSR, RCC_CSR_LSECSSON) ;
|
|
}
|
|
|
|
/**
|
|
* @brief Disables the LSE Clock Security System.
|
|
* @note Once enabled this bit cannot be disabled, except after an LSE failure detection
|
|
* (LSECSSD=1). In that case the software MUST disable the LSECSSON bit.
|
|
* Reset by power on reset and RTC software reset (RTCRST bit).
|
|
* @retval None
|
|
*/
|
|
void HAL_RCCEx_DisableLSECSS(void)
|
|
{
|
|
/* Disable LSE CSS */
|
|
CLEAR_BIT(RCC->CSR, RCC_CSR_LSECSSON) ;
|
|
|
|
/* Disable LSE CSS IT */
|
|
__HAL_RCC_DISABLE_IT(RCC_IT_LSECSS);
|
|
}
|
|
|
|
/**
|
|
* @brief Enable the LSE Clock Security System IT & corresponding EXTI line.
|
|
* @note LSE Clock Security System IT is mapped on RTC EXTI line 19
|
|
* @retval None
|
|
*/
|
|
void HAL_RCCEx_EnableLSECSS_IT(void)
|
|
{
|
|
/* Enable LSE CSS */
|
|
SET_BIT(RCC->CSR, RCC_CSR_LSECSSON) ;
|
|
|
|
/* Enable LSE CSS IT */
|
|
__HAL_RCC_ENABLE_IT(RCC_IT_LSECSS);
|
|
|
|
/* Enable IT on EXTI Line 19 */
|
|
__HAL_RCC_LSECSS_EXTI_ENABLE_IT();
|
|
__HAL_RCC_LSECSS_EXTI_ENABLE_RISING_EDGE();
|
|
}
|
|
|
|
/**
|
|
* @brief Handle the RCC LSE Clock Security System interrupt request.
|
|
* @retval None
|
|
*/
|
|
void HAL_RCCEx_LSECSS_IRQHandler(void)
|
|
{
|
|
/* Check RCC LSE CSSF flag */
|
|
if(__HAL_RCC_GET_IT(RCC_IT_LSECSS))
|
|
{
|
|
/* RCC LSE Clock Security System interrupt user callback */
|
|
HAL_RCCEx_LSECSS_Callback();
|
|
|
|
/* Clear RCC LSE CSS pending bit */
|
|
__HAL_RCC_CLEAR_IT(RCC_IT_LSECSS);
|
|
}
|
|
}
|
|
|
|
/**
|
|
* @brief RCCEx LSE Clock Security System interrupt callback.
|
|
* @retval none
|
|
*/
|
|
__weak void HAL_RCCEx_LSECSS_Callback(void)
|
|
{
|
|
/* NOTE : This function should not be modified, when the callback is needed,
|
|
the @ref HAL_RCCEx_LSECSS_Callback should be implemented in the user file
|
|
*/
|
|
}
|
|
|
|
#if defined(SYSCFG_CFGR3_ENREF_HSI48)
|
|
/**
|
|
* @brief Enables Vrefint for the HSI48.
|
|
* @note This is functional only if the LOCK is not set
|
|
* @retval None
|
|
*/
|
|
void HAL_RCCEx_EnableHSI48_VREFINT(void)
|
|
{
|
|
/* Enable the Buffer for the ADC by setting SYSCFG_CFGR3_ENREF_HSI48 bit in SYSCFG_CFGR3 register */
|
|
SET_BIT (SYSCFG->CFGR3, SYSCFG_CFGR3_ENREF_HSI48);
|
|
}
|
|
|
|
/**
|
|
* @brief Disables the Vrefint for the HSI48.
|
|
* @note This is functional only if the LOCK is not set
|
|
* @retval None
|
|
*/
|
|
void HAL_RCCEx_DisableHSI48_VREFINT(void)
|
|
{
|
|
/* Disable the Vrefint by resetting SYSCFG_CFGR3_ENREF_HSI48 bit in SYSCFG_CFGR3 register */
|
|
CLEAR_BIT(SYSCFG->CFGR3, SYSCFG_CFGR3_ENREF_HSI48);
|
|
}
|
|
|
|
#endif /* SYSCFG_CFGR3_ENREF_HSI48 */
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
#if defined (CRS)
|
|
|
|
/** @defgroup RCCEx_Exported_Functions_Group3 Extended Clock Recovery System Control functions
|
|
* @brief Extended Clock Recovery System Control functions
|
|
*
|
|
@verbatim
|
|
===============================================================================
|
|
##### Extended Clock Recovery System Control functions #####
|
|
===============================================================================
|
|
[..]
|
|
For devices with Clock Recovery System feature (CRS), RCC Extention HAL driver can be used as follows:
|
|
|
|
(#) In System clock config, HSI48 needs to be enabled
|
|
|
|
(#) Enable CRS clock in IP MSP init which will use CRS functions
|
|
|
|
(#) Call CRS functions as follows:
|
|
(##) Prepare synchronization configuration necessary for HSI48 calibration
|
|
(+++) Default values can be set for frequency Error Measurement (reload and error limit)
|
|
and also HSI48 oscillator smooth trimming.
|
|
(+++) Macro @ref __HAL_RCC_CRS_RELOADVALUE_CALCULATE can be also used to calculate
|
|
directly reload value with target and synchronization frequencies values
|
|
(##) Call function @ref HAL_RCCEx_CRSConfig which
|
|
(+++) Reset CRS registers to their default values.
|
|
(+++) Configure CRS registers with synchronization configuration
|
|
(+++) Enable automatic calibration and frequency error counter feature
|
|
Note: When using USB LPM (Link Power Management) and the device is in Sleep mode, the
|
|
periodic USB SOF will not be generated by the host. No SYNC signal will therefore be
|
|
provided to the CRS to calibrate the HSI48 on the run. To guarantee the required clock
|
|
precision after waking up from Sleep mode, the LSE or reference clock on the GPIOs
|
|
should be used as SYNC signal.
|
|
|
|
(##) A polling function is provided to wait for complete synchronization
|
|
(+++) Call function @ref HAL_RCCEx_CRSWaitSynchronization()
|
|
(+++) According to CRS status, user can decide to adjust again the calibration or continue
|
|
application if synchronization is OK
|
|
|
|
(#) User can retrieve information related to synchronization in calling function
|
|
@ref HAL_RCCEx_CRSGetSynchronizationInfo()
|
|
|
|
(#) Regarding synchronization status and synchronization information, user can try a new calibration
|
|
in changing synchronization configuration and call again HAL_RCCEx_CRSConfig.
|
|
Note: When the SYNC event is detected during the downcounting phase (before reaching the zero value),
|
|
it means that the actual frequency is lower than the target (and so, that the TRIM value should be
|
|
incremented), while when it is detected during the upcounting phase it means that the actual frequency
|
|
is higher (and that the TRIM value should be decremented).
|
|
|
|
(#) In interrupt mode, user can resort to the available macros (__HAL_RCC_CRS_XXX_IT). Interrupts will go
|
|
through CRS Handler (RCC_IRQn/RCC_IRQHandler)
|
|
(++) Call function @ref HAL_RCCEx_CRSConfig()
|
|
(++) Enable RCC_IRQn (thanks to NVIC functions)
|
|
(++) Enable CRS interrupt (@ref __HAL_RCC_CRS_ENABLE_IT)
|
|
(++) Implement CRS status management in the following user callbacks called from
|
|
HAL_RCCEx_CRS_IRQHandler():
|
|
(+++) @ref HAL_RCCEx_CRS_SyncOkCallback()
|
|
(+++) @ref HAL_RCCEx_CRS_SyncWarnCallback()
|
|
(+++) @ref HAL_RCCEx_CRS_ExpectedSyncCallback()
|
|
(+++) @ref HAL_RCCEx_CRS_ErrorCallback()
|
|
|
|
(#) To force a SYNC EVENT, user can use the function @ref HAL_RCCEx_CRSSoftwareSynchronizationGenerate().
|
|
This function can be called before calling @ref HAL_RCCEx_CRSConfig (for instance in Systick handler)
|
|
|
|
@endverbatim
|
|
* @{
|
|
*/
|
|
|
|
/**
|
|
* @brief Start automatic synchronization for polling mode
|
|
* @param pInit Pointer on RCC_CRSInitTypeDef structure
|
|
* @retval None
|
|
*/
|
|
void HAL_RCCEx_CRSConfig(RCC_CRSInitTypeDef *pInit)
|
|
{
|
|
uint32_t value;
|
|
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_CRS_SYNC_DIV(pInit->Prescaler));
|
|
assert_param(IS_RCC_CRS_SYNC_SOURCE(pInit->Source));
|
|
assert_param(IS_RCC_CRS_SYNC_POLARITY(pInit->Polarity));
|
|
assert_param(IS_RCC_CRS_RELOADVALUE(pInit->ReloadValue));
|
|
assert_param(IS_RCC_CRS_ERRORLIMIT(pInit->ErrorLimitValue));
|
|
assert_param(IS_RCC_CRS_HSI48CALIBRATION(pInit->HSI48CalibrationValue));
|
|
|
|
/* CONFIGURATION */
|
|
|
|
/* Before configuration, reset CRS registers to their default values*/
|
|
__HAL_RCC_CRS_FORCE_RESET();
|
|
__HAL_RCC_CRS_RELEASE_RESET();
|
|
|
|
/* Set the SYNCDIV[2:0] bits according to Prescaler value */
|
|
/* Set the SYNCSRC[1:0] bits according to Source value */
|
|
/* Set the SYNCSPOL bit according to Polarity value */
|
|
value = (pInit->Prescaler | pInit->Source | pInit->Polarity);
|
|
/* Set the RELOAD[15:0] bits according to ReloadValue value */
|
|
value |= pInit->ReloadValue;
|
|
/* Set the FELIM[7:0] bits according to ErrorLimitValue value */
|
|
value |= (pInit->ErrorLimitValue << CRS_CFGR_FELIM_Pos);
|
|
WRITE_REG(CRS->CFGR, value);
|
|
|
|
/* Adjust HSI48 oscillator smooth trimming */
|
|
/* Set the TRIM[5:0] bits according to RCC_CRS_HSI48CalibrationValue value */
|
|
MODIFY_REG(CRS->CR, CRS_CR_TRIM, (pInit->HSI48CalibrationValue << CRS_CR_TRIM_Pos));
|
|
|
|
/* START AUTOMATIC SYNCHRONIZATION*/
|
|
|
|
/* Enable Automatic trimming & Frequency error counter */
|
|
SET_BIT(CRS->CR, CRS_CR_AUTOTRIMEN | CRS_CR_CEN);
|
|
}
|
|
|
|
/**
|
|
* @brief Generate the software synchronization event
|
|
* @retval None
|
|
*/
|
|
void HAL_RCCEx_CRSSoftwareSynchronizationGenerate(void)
|
|
{
|
|
SET_BIT(CRS->CR, CRS_CR_SWSYNC);
|
|
}
|
|
|
|
/**
|
|
* @brief Return synchronization info
|
|
* @param pSynchroInfo Pointer on RCC_CRSSynchroInfoTypeDef structure
|
|
* @retval None
|
|
*/
|
|
void HAL_RCCEx_CRSGetSynchronizationInfo(RCC_CRSSynchroInfoTypeDef *pSynchroInfo)
|
|
{
|
|
/* Check the parameter */
|
|
assert_param(pSynchroInfo != (void *)NULL);
|
|
|
|
/* Get the reload value */
|
|
pSynchroInfo->ReloadValue = (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_RELOAD));
|
|
|
|
/* Get HSI48 oscillator smooth trimming */
|
|
pSynchroInfo->HSI48CalibrationValue = (uint32_t)(READ_BIT(CRS->CR, CRS_CR_TRIM) >> CRS_CR_TRIM_Pos);
|
|
|
|
/* Get Frequency error capture */
|
|
pSynchroInfo->FreqErrorCapture = (uint32_t)(READ_BIT(CRS->ISR, CRS_ISR_FECAP) >> CRS_ISR_FECAP_Pos);
|
|
|
|
/* Get Frequency error direction */
|
|
pSynchroInfo->FreqErrorDirection = (uint32_t)(READ_BIT(CRS->ISR, CRS_ISR_FEDIR));
|
|
}
|
|
|
|
/**
|
|
* @brief Wait for CRS Synchronization status.
|
|
* @param Timeout Duration of the timeout
|
|
* @note Timeout is based on the maximum time to receive a SYNC event based on synchronization
|
|
* frequency.
|
|
* @note If Timeout set to HAL_MAX_DELAY, HAL_TIMEOUT will be never returned.
|
|
* @retval Combination of Synchronization status
|
|
* This parameter can be a combination of the following values:
|
|
* @arg @ref RCC_CRS_TIMEOUT
|
|
* @arg @ref RCC_CRS_SYNCOK
|
|
* @arg @ref RCC_CRS_SYNCWARN
|
|
* @arg @ref RCC_CRS_SYNCERR
|
|
* @arg @ref RCC_CRS_SYNCMISS
|
|
* @arg @ref RCC_CRS_TRIMOVF
|
|
*/
|
|
uint32_t HAL_RCCEx_CRSWaitSynchronization(uint32_t Timeout)
|
|
{
|
|
uint32_t crsstatus = RCC_CRS_NONE;
|
|
uint32_t tickstart;
|
|
|
|
/* Get timeout */
|
|
tickstart = HAL_GetTick();
|
|
|
|
/* Wait for CRS flag or timeout detection */
|
|
do
|
|
{
|
|
if(Timeout != HAL_MAX_DELAY)
|
|
{
|
|
if(((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
|
|
{
|
|
crsstatus = RCC_CRS_TIMEOUT;
|
|
}
|
|
}
|
|
/* Check CRS SYNCOK flag */
|
|
if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_SYNCOK))
|
|
{
|
|
/* CRS SYNC event OK */
|
|
crsstatus |= RCC_CRS_SYNCOK;
|
|
|
|
/* Clear CRS SYNC event OK bit */
|
|
__HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_SYNCOK);
|
|
}
|
|
|
|
/* Check CRS SYNCWARN flag */
|
|
if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_SYNCWARN))
|
|
{
|
|
/* CRS SYNC warning */
|
|
crsstatus |= RCC_CRS_SYNCWARN;
|
|
|
|
/* Clear CRS SYNCWARN bit */
|
|
__HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_SYNCWARN);
|
|
}
|
|
|
|
/* Check CRS TRIM overflow flag */
|
|
if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_TRIMOVF))
|
|
{
|
|
/* CRS SYNC Error */
|
|
crsstatus |= RCC_CRS_TRIMOVF;
|
|
|
|
/* Clear CRS Error bit */
|
|
__HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_TRIMOVF);
|
|
}
|
|
|
|
/* Check CRS Error flag */
|
|
if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_SYNCERR))
|
|
{
|
|
/* CRS SYNC Error */
|
|
crsstatus |= RCC_CRS_SYNCERR;
|
|
|
|
/* Clear CRS Error bit */
|
|
__HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_SYNCERR);
|
|
}
|
|
|
|
/* Check CRS SYNC Missed flag */
|
|
if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_SYNCMISS))
|
|
{
|
|
/* CRS SYNC Missed */
|
|
crsstatus |= RCC_CRS_SYNCMISS;
|
|
|
|
/* Clear CRS SYNC Missed bit */
|
|
__HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_SYNCMISS);
|
|
}
|
|
|
|
/* Check CRS Expected SYNC flag */
|
|
if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_ESYNC))
|
|
{
|
|
/* frequency error counter reached a zero value */
|
|
__HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_ESYNC);
|
|
}
|
|
} while(RCC_CRS_NONE == crsstatus);
|
|
|
|
return crsstatus;
|
|
}
|
|
|
|
/**
|
|
* @brief Handle the Clock Recovery System interrupt request.
|
|
* @retval None
|
|
*/
|
|
void HAL_RCCEx_CRS_IRQHandler(void)
|
|
{
|
|
uint32_t crserror = RCC_CRS_NONE;
|
|
/* Get current IT flags and IT sources values */
|
|
uint32_t itflags = READ_REG(CRS->ISR);
|
|
uint32_t itsources = READ_REG(CRS->CR);
|
|
|
|
/* Check CRS SYNCOK flag */
|
|
if(((itflags & RCC_CRS_FLAG_SYNCOK) != 0U) && ((itsources & RCC_CRS_IT_SYNCOK) != 0U))
|
|
{
|
|
/* Clear CRS SYNC event OK flag */
|
|
WRITE_REG(CRS->ICR, CRS_ICR_SYNCOKC);
|
|
|
|
/* user callback */
|
|
HAL_RCCEx_CRS_SyncOkCallback();
|
|
}
|
|
/* Check CRS SYNCWARN flag */
|
|
else if(((itflags & RCC_CRS_FLAG_SYNCWARN) != 0U) && ((itsources & RCC_CRS_IT_SYNCWARN) != 0U))
|
|
{
|
|
/* Clear CRS SYNCWARN flag */
|
|
WRITE_REG(CRS->ICR, CRS_ICR_SYNCWARNC);
|
|
|
|
/* user callback */
|
|
HAL_RCCEx_CRS_SyncWarnCallback();
|
|
}
|
|
/* Check CRS Expected SYNC flag */
|
|
else if(((itflags & RCC_CRS_FLAG_ESYNC) != 0U) && ((itsources & RCC_CRS_IT_ESYNC) != 0U))
|
|
{
|
|
/* frequency error counter reached a zero value */
|
|
WRITE_REG(CRS->ICR, CRS_ICR_ESYNCC);
|
|
|
|
/* user callback */
|
|
HAL_RCCEx_CRS_ExpectedSyncCallback();
|
|
}
|
|
/* Check CRS Error flags */
|
|
else
|
|
{
|
|
if(((itflags & RCC_CRS_FLAG_ERR) != 0U) && ((itsources & RCC_CRS_IT_ERR) != 0U))
|
|
{
|
|
if((itflags & RCC_CRS_FLAG_SYNCERR) != 0U)
|
|
{
|
|
crserror |= RCC_CRS_SYNCERR;
|
|
}
|
|
if((itflags & RCC_CRS_FLAG_SYNCMISS) != 0U)
|
|
{
|
|
crserror |= RCC_CRS_SYNCMISS;
|
|
}
|
|
if((itflags & RCC_CRS_FLAG_TRIMOVF) != 0U)
|
|
{
|
|
crserror |= RCC_CRS_TRIMOVF;
|
|
}
|
|
|
|
/* Clear CRS Error flags */
|
|
WRITE_REG(CRS->ICR, CRS_ICR_ERRC);
|
|
|
|
/* user error callback */
|
|
HAL_RCCEx_CRS_ErrorCallback(crserror);
|
|
}
|
|
}
|
|
}
|
|
|
|
/**
|
|
* @brief RCCEx Clock Recovery System SYNCOK interrupt callback.
|
|
* @retval none
|
|
*/
|
|
__weak void HAL_RCCEx_CRS_SyncOkCallback(void)
|
|
{
|
|
/* NOTE : This function should not be modified, when the callback is needed,
|
|
the @ref HAL_RCCEx_CRS_SyncOkCallback should be implemented in the user file
|
|
*/
|
|
}
|
|
|
|
/**
|
|
* @brief RCCEx Clock Recovery System SYNCWARN interrupt callback.
|
|
* @retval none
|
|
*/
|
|
__weak void HAL_RCCEx_CRS_SyncWarnCallback(void)
|
|
{
|
|
/* NOTE : This function should not be modified, when the callback is needed,
|
|
the @ref HAL_RCCEx_CRS_SyncWarnCallback should be implemented in the user file
|
|
*/
|
|
}
|
|
|
|
/**
|
|
* @brief RCCEx Clock Recovery System Expected SYNC interrupt callback.
|
|
* @retval none
|
|
*/
|
|
__weak void HAL_RCCEx_CRS_ExpectedSyncCallback(void)
|
|
{
|
|
/* NOTE : This function should not be modified, when the callback is needed,
|
|
the @ref HAL_RCCEx_CRS_ExpectedSyncCallback should be implemented in the user file
|
|
*/
|
|
}
|
|
|
|
/**
|
|
* @brief RCCEx Clock Recovery System Error interrupt callback.
|
|
* @param Error Combination of Error status.
|
|
* This parameter can be a combination of the following values:
|
|
* @arg @ref RCC_CRS_SYNCERR
|
|
* @arg @ref RCC_CRS_SYNCMISS
|
|
* @arg @ref RCC_CRS_TRIMOVF
|
|
* @retval none
|
|
*/
|
|
__weak void HAL_RCCEx_CRS_ErrorCallback(uint32_t Error)
|
|
{
|
|
/* Prevent unused argument(s) compilation warning */
|
|
UNUSED(Error);
|
|
|
|
/* NOTE : This function should not be modified, when the callback is needed,
|
|
the @ref HAL_RCCEx_CRS_ErrorCallback should be implemented in the user file
|
|
*/
|
|
}
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
#endif /* CRS */
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
#endif /* HAL_RCC_MODULE_ENABLED */
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|