18373 lines
702 KiB
Plaintext
18373 lines
702 KiB
Plaintext
|
|
|||
|
|
A141 Amplifier.elf: file format elf32-littlearm
|
|||
|
|
|
|||
|
|
Sections:
|
|||
|
|
Idx Name Size VMA LMA File off Algn
|
|||
|
|
0 .isr_vector 000000c0 08000000 08000000 00010000 2**0
|
|||
|
|
CONTENTS, ALLOC, LOAD, READONLY, DATA
|
|||
|
|
1 .text 00006f28 080000c0 080000c0 000100c0 2**2
|
|||
|
|
CONTENTS, ALLOC, LOAD, READONLY, CODE
|
|||
|
|
2 .rodata 000004a4 08006fe8 08006fe8 00016fe8 2**2
|
|||
|
|
CONTENTS, ALLOC, LOAD, READONLY, DATA
|
|||
|
|
3 .ARM 00000008 0800748c 0800748c 0001748c 2**2
|
|||
|
|
CONTENTS, ALLOC, LOAD, READONLY, DATA
|
|||
|
|
4 .init_array 00000004 08007494 08007494 00017494 2**2
|
|||
|
|
CONTENTS, ALLOC, LOAD, DATA
|
|||
|
|
5 .fini_array 00000004 08007498 08007498 00017498 2**2
|
|||
|
|
CONTENTS, ALLOC, LOAD, DATA
|
|||
|
|
6 .data 00000010 20000000 0800749c 00020000 2**2
|
|||
|
|
CONTENTS, ALLOC, LOAD, DATA
|
|||
|
|
7 .bss 00000398 20000010 080074ac 00020010 2**2
|
|||
|
|
ALLOC
|
|||
|
|
8 ._user_heap_stack 00000600 200003a8 080074ac 000203a8 2**0
|
|||
|
|
ALLOC
|
|||
|
|
9 .ARM.attributes 00000028 00000000 00000000 00020010 2**0
|
|||
|
|
CONTENTS, READONLY
|
|||
|
|
10 .debug_info 0001130a 00000000 00000000 00020038 2**0
|
|||
|
|
CONTENTS, READONLY, DEBUGGING
|
|||
|
|
11 .debug_abbrev 000029ed 00000000 00000000 00031342 2**0
|
|||
|
|
CONTENTS, READONLY, DEBUGGING
|
|||
|
|
12 .debug_aranges 00000e40 00000000 00000000 00033d30 2**3
|
|||
|
|
CONTENTS, READONLY, DEBUGGING
|
|||
|
|
13 .debug_ranges 00000d18 00000000 00000000 00034b70 2**3
|
|||
|
|
CONTENTS, READONLY, DEBUGGING
|
|||
|
|
14 .debug_line 00007152 00000000 00000000 00035888 2**0
|
|||
|
|
CONTENTS, READONLY, DEBUGGING
|
|||
|
|
15 .debug_str 000045bb 00000000 00000000 0003c9da 2**0
|
|||
|
|
CONTENTS, READONLY, DEBUGGING
|
|||
|
|
16 .comment 0000007c 00000000 00000000 00040f95 2**0
|
|||
|
|
CONTENTS, READONLY
|
|||
|
|
17 .debug_frame 00003434 00000000 00000000 00041014 2**2
|
|||
|
|
CONTENTS, READONLY, DEBUGGING
|
|||
|
|
|
|||
|
|
Disassembly of section .text:
|
|||
|
|
|
|||
|
|
080000c0 <__do_global_dtors_aux>:
|
|||
|
|
80000c0: b510 push {r4, lr}
|
|||
|
|
80000c2: 4c06 ldr r4, [pc, #24] ; (80000dc <__do_global_dtors_aux+0x1c>)
|
|||
|
|
80000c4: 7823 ldrb r3, [r4, #0]
|
|||
|
|
80000c6: 2b00 cmp r3, #0
|
|||
|
|
80000c8: d107 bne.n 80000da <__do_global_dtors_aux+0x1a>
|
|||
|
|
80000ca: 4b05 ldr r3, [pc, #20] ; (80000e0 <__do_global_dtors_aux+0x20>)
|
|||
|
|
80000cc: 2b00 cmp r3, #0
|
|||
|
|
80000ce: d002 beq.n 80000d6 <__do_global_dtors_aux+0x16>
|
|||
|
|
80000d0: 4804 ldr r0, [pc, #16] ; (80000e4 <__do_global_dtors_aux+0x24>)
|
|||
|
|
80000d2: e000 b.n 80000d6 <__do_global_dtors_aux+0x16>
|
|||
|
|
80000d4: bf00 nop
|
|||
|
|
80000d6: 2301 movs r3, #1
|
|||
|
|
80000d8: 7023 strb r3, [r4, #0]
|
|||
|
|
80000da: bd10 pop {r4, pc}
|
|||
|
|
80000dc: 20000010 .word 0x20000010
|
|||
|
|
80000e0: 00000000 .word 0x00000000
|
|||
|
|
80000e4: 08006fd0 .word 0x08006fd0
|
|||
|
|
|
|||
|
|
080000e8 <frame_dummy>:
|
|||
|
|
80000e8: 4b04 ldr r3, [pc, #16] ; (80000fc <frame_dummy+0x14>)
|
|||
|
|
80000ea: b510 push {r4, lr}
|
|||
|
|
80000ec: 2b00 cmp r3, #0
|
|||
|
|
80000ee: d003 beq.n 80000f8 <frame_dummy+0x10>
|
|||
|
|
80000f0: 4903 ldr r1, [pc, #12] ; (8000100 <frame_dummy+0x18>)
|
|||
|
|
80000f2: 4804 ldr r0, [pc, #16] ; (8000104 <frame_dummy+0x1c>)
|
|||
|
|
80000f4: e000 b.n 80000f8 <frame_dummy+0x10>
|
|||
|
|
80000f6: bf00 nop
|
|||
|
|
80000f8: bd10 pop {r4, pc}
|
|||
|
|
80000fa: 46c0 nop ; (mov r8, r8)
|
|||
|
|
80000fc: 00000000 .word 0x00000000
|
|||
|
|
8000100: 20000014 .word 0x20000014
|
|||
|
|
8000104: 08006fd0 .word 0x08006fd0
|
|||
|
|
|
|||
|
|
08000108 <__udivsi3>:
|
|||
|
|
8000108: 2200 movs r2, #0
|
|||
|
|
800010a: 0843 lsrs r3, r0, #1
|
|||
|
|
800010c: 428b cmp r3, r1
|
|||
|
|
800010e: d374 bcc.n 80001fa <__udivsi3+0xf2>
|
|||
|
|
8000110: 0903 lsrs r3, r0, #4
|
|||
|
|
8000112: 428b cmp r3, r1
|
|||
|
|
8000114: d35f bcc.n 80001d6 <__udivsi3+0xce>
|
|||
|
|
8000116: 0a03 lsrs r3, r0, #8
|
|||
|
|
8000118: 428b cmp r3, r1
|
|||
|
|
800011a: d344 bcc.n 80001a6 <__udivsi3+0x9e>
|
|||
|
|
800011c: 0b03 lsrs r3, r0, #12
|
|||
|
|
800011e: 428b cmp r3, r1
|
|||
|
|
8000120: d328 bcc.n 8000174 <__udivsi3+0x6c>
|
|||
|
|
8000122: 0c03 lsrs r3, r0, #16
|
|||
|
|
8000124: 428b cmp r3, r1
|
|||
|
|
8000126: d30d bcc.n 8000144 <__udivsi3+0x3c>
|
|||
|
|
8000128: 22ff movs r2, #255 ; 0xff
|
|||
|
|
800012a: 0209 lsls r1, r1, #8
|
|||
|
|
800012c: ba12 rev r2, r2
|
|||
|
|
800012e: 0c03 lsrs r3, r0, #16
|
|||
|
|
8000130: 428b cmp r3, r1
|
|||
|
|
8000132: d302 bcc.n 800013a <__udivsi3+0x32>
|
|||
|
|
8000134: 1212 asrs r2, r2, #8
|
|||
|
|
8000136: 0209 lsls r1, r1, #8
|
|||
|
|
8000138: d065 beq.n 8000206 <__udivsi3+0xfe>
|
|||
|
|
800013a: 0b03 lsrs r3, r0, #12
|
|||
|
|
800013c: 428b cmp r3, r1
|
|||
|
|
800013e: d319 bcc.n 8000174 <__udivsi3+0x6c>
|
|||
|
|
8000140: e000 b.n 8000144 <__udivsi3+0x3c>
|
|||
|
|
8000142: 0a09 lsrs r1, r1, #8
|
|||
|
|
8000144: 0bc3 lsrs r3, r0, #15
|
|||
|
|
8000146: 428b cmp r3, r1
|
|||
|
|
8000148: d301 bcc.n 800014e <__udivsi3+0x46>
|
|||
|
|
800014a: 03cb lsls r3, r1, #15
|
|||
|
|
800014c: 1ac0 subs r0, r0, r3
|
|||
|
|
800014e: 4152 adcs r2, r2
|
|||
|
|
8000150: 0b83 lsrs r3, r0, #14
|
|||
|
|
8000152: 428b cmp r3, r1
|
|||
|
|
8000154: d301 bcc.n 800015a <__udivsi3+0x52>
|
|||
|
|
8000156: 038b lsls r3, r1, #14
|
|||
|
|
8000158: 1ac0 subs r0, r0, r3
|
|||
|
|
800015a: 4152 adcs r2, r2
|
|||
|
|
800015c: 0b43 lsrs r3, r0, #13
|
|||
|
|
800015e: 428b cmp r3, r1
|
|||
|
|
8000160: d301 bcc.n 8000166 <__udivsi3+0x5e>
|
|||
|
|
8000162: 034b lsls r3, r1, #13
|
|||
|
|
8000164: 1ac0 subs r0, r0, r3
|
|||
|
|
8000166: 4152 adcs r2, r2
|
|||
|
|
8000168: 0b03 lsrs r3, r0, #12
|
|||
|
|
800016a: 428b cmp r3, r1
|
|||
|
|
800016c: d301 bcc.n 8000172 <__udivsi3+0x6a>
|
|||
|
|
800016e: 030b lsls r3, r1, #12
|
|||
|
|
8000170: 1ac0 subs r0, r0, r3
|
|||
|
|
8000172: 4152 adcs r2, r2
|
|||
|
|
8000174: 0ac3 lsrs r3, r0, #11
|
|||
|
|
8000176: 428b cmp r3, r1
|
|||
|
|
8000178: d301 bcc.n 800017e <__udivsi3+0x76>
|
|||
|
|
800017a: 02cb lsls r3, r1, #11
|
|||
|
|
800017c: 1ac0 subs r0, r0, r3
|
|||
|
|
800017e: 4152 adcs r2, r2
|
|||
|
|
8000180: 0a83 lsrs r3, r0, #10
|
|||
|
|
8000182: 428b cmp r3, r1
|
|||
|
|
8000184: d301 bcc.n 800018a <__udivsi3+0x82>
|
|||
|
|
8000186: 028b lsls r3, r1, #10
|
|||
|
|
8000188: 1ac0 subs r0, r0, r3
|
|||
|
|
800018a: 4152 adcs r2, r2
|
|||
|
|
800018c: 0a43 lsrs r3, r0, #9
|
|||
|
|
800018e: 428b cmp r3, r1
|
|||
|
|
8000190: d301 bcc.n 8000196 <__udivsi3+0x8e>
|
|||
|
|
8000192: 024b lsls r3, r1, #9
|
|||
|
|
8000194: 1ac0 subs r0, r0, r3
|
|||
|
|
8000196: 4152 adcs r2, r2
|
|||
|
|
8000198: 0a03 lsrs r3, r0, #8
|
|||
|
|
800019a: 428b cmp r3, r1
|
|||
|
|
800019c: d301 bcc.n 80001a2 <__udivsi3+0x9a>
|
|||
|
|
800019e: 020b lsls r3, r1, #8
|
|||
|
|
80001a0: 1ac0 subs r0, r0, r3
|
|||
|
|
80001a2: 4152 adcs r2, r2
|
|||
|
|
80001a4: d2cd bcs.n 8000142 <__udivsi3+0x3a>
|
|||
|
|
80001a6: 09c3 lsrs r3, r0, #7
|
|||
|
|
80001a8: 428b cmp r3, r1
|
|||
|
|
80001aa: d301 bcc.n 80001b0 <__udivsi3+0xa8>
|
|||
|
|
80001ac: 01cb lsls r3, r1, #7
|
|||
|
|
80001ae: 1ac0 subs r0, r0, r3
|
|||
|
|
80001b0: 4152 adcs r2, r2
|
|||
|
|
80001b2: 0983 lsrs r3, r0, #6
|
|||
|
|
80001b4: 428b cmp r3, r1
|
|||
|
|
80001b6: d301 bcc.n 80001bc <__udivsi3+0xb4>
|
|||
|
|
80001b8: 018b lsls r3, r1, #6
|
|||
|
|
80001ba: 1ac0 subs r0, r0, r3
|
|||
|
|
80001bc: 4152 adcs r2, r2
|
|||
|
|
80001be: 0943 lsrs r3, r0, #5
|
|||
|
|
80001c0: 428b cmp r3, r1
|
|||
|
|
80001c2: d301 bcc.n 80001c8 <__udivsi3+0xc0>
|
|||
|
|
80001c4: 014b lsls r3, r1, #5
|
|||
|
|
80001c6: 1ac0 subs r0, r0, r3
|
|||
|
|
80001c8: 4152 adcs r2, r2
|
|||
|
|
80001ca: 0903 lsrs r3, r0, #4
|
|||
|
|
80001cc: 428b cmp r3, r1
|
|||
|
|
80001ce: d301 bcc.n 80001d4 <__udivsi3+0xcc>
|
|||
|
|
80001d0: 010b lsls r3, r1, #4
|
|||
|
|
80001d2: 1ac0 subs r0, r0, r3
|
|||
|
|
80001d4: 4152 adcs r2, r2
|
|||
|
|
80001d6: 08c3 lsrs r3, r0, #3
|
|||
|
|
80001d8: 428b cmp r3, r1
|
|||
|
|
80001da: d301 bcc.n 80001e0 <__udivsi3+0xd8>
|
|||
|
|
80001dc: 00cb lsls r3, r1, #3
|
|||
|
|
80001de: 1ac0 subs r0, r0, r3
|
|||
|
|
80001e0: 4152 adcs r2, r2
|
|||
|
|
80001e2: 0883 lsrs r3, r0, #2
|
|||
|
|
80001e4: 428b cmp r3, r1
|
|||
|
|
80001e6: d301 bcc.n 80001ec <__udivsi3+0xe4>
|
|||
|
|
80001e8: 008b lsls r3, r1, #2
|
|||
|
|
80001ea: 1ac0 subs r0, r0, r3
|
|||
|
|
80001ec: 4152 adcs r2, r2
|
|||
|
|
80001ee: 0843 lsrs r3, r0, #1
|
|||
|
|
80001f0: 428b cmp r3, r1
|
|||
|
|
80001f2: d301 bcc.n 80001f8 <__udivsi3+0xf0>
|
|||
|
|
80001f4: 004b lsls r3, r1, #1
|
|||
|
|
80001f6: 1ac0 subs r0, r0, r3
|
|||
|
|
80001f8: 4152 adcs r2, r2
|
|||
|
|
80001fa: 1a41 subs r1, r0, r1
|
|||
|
|
80001fc: d200 bcs.n 8000200 <__udivsi3+0xf8>
|
|||
|
|
80001fe: 4601 mov r1, r0
|
|||
|
|
8000200: 4152 adcs r2, r2
|
|||
|
|
8000202: 4610 mov r0, r2
|
|||
|
|
8000204: 4770 bx lr
|
|||
|
|
8000206: e7ff b.n 8000208 <__udivsi3+0x100>
|
|||
|
|
8000208: b501 push {r0, lr}
|
|||
|
|
800020a: 2000 movs r0, #0
|
|||
|
|
800020c: f000 f806 bl 800021c <__aeabi_idiv0>
|
|||
|
|
8000210: bd02 pop {r1, pc}
|
|||
|
|
8000212: 46c0 nop ; (mov r8, r8)
|
|||
|
|
|
|||
|
|
08000214 <__aeabi_uidivmod>:
|
|||
|
|
8000214: 2900 cmp r1, #0
|
|||
|
|
8000216: d0f7 beq.n 8000208 <__udivsi3+0x100>
|
|||
|
|
8000218: e776 b.n 8000108 <__udivsi3>
|
|||
|
|
800021a: 4770 bx lr
|
|||
|
|
|
|||
|
|
0800021c <__aeabi_idiv0>:
|
|||
|
|
800021c: 4770 bx lr
|
|||
|
|
800021e: 46c0 nop ; (mov r8, r8)
|
|||
|
|
|
|||
|
|
08000220 <__aeabi_cdrcmple>:
|
|||
|
|
8000220: 4684 mov ip, r0
|
|||
|
|
8000222: 1c10 adds r0, r2, #0
|
|||
|
|
8000224: 4662 mov r2, ip
|
|||
|
|
8000226: 468c mov ip, r1
|
|||
|
|
8000228: 1c19 adds r1, r3, #0
|
|||
|
|
800022a: 4663 mov r3, ip
|
|||
|
|
800022c: e000 b.n 8000230 <__aeabi_cdcmpeq>
|
|||
|
|
800022e: 46c0 nop ; (mov r8, r8)
|
|||
|
|
|
|||
|
|
08000230 <__aeabi_cdcmpeq>:
|
|||
|
|
8000230: b51f push {r0, r1, r2, r3, r4, lr}
|
|||
|
|
8000232: f000 ff3f bl 80010b4 <__ledf2>
|
|||
|
|
8000236: 2800 cmp r0, #0
|
|||
|
|
8000238: d401 bmi.n 800023e <__aeabi_cdcmpeq+0xe>
|
|||
|
|
800023a: 2100 movs r1, #0
|
|||
|
|
800023c: 42c8 cmn r0, r1
|
|||
|
|
800023e: bd1f pop {r0, r1, r2, r3, r4, pc}
|
|||
|
|
|
|||
|
|
08000240 <__aeabi_dcmpeq>:
|
|||
|
|
8000240: b510 push {r4, lr}
|
|||
|
|
8000242: f000 fe99 bl 8000f78 <__eqdf2>
|
|||
|
|
8000246: 4240 negs r0, r0
|
|||
|
|
8000248: 3001 adds r0, #1
|
|||
|
|
800024a: bd10 pop {r4, pc}
|
|||
|
|
|
|||
|
|
0800024c <__aeabi_dcmplt>:
|
|||
|
|
800024c: b510 push {r4, lr}
|
|||
|
|
800024e: f000 ff31 bl 80010b4 <__ledf2>
|
|||
|
|
8000252: 2800 cmp r0, #0
|
|||
|
|
8000254: db01 blt.n 800025a <__aeabi_dcmplt+0xe>
|
|||
|
|
8000256: 2000 movs r0, #0
|
|||
|
|
8000258: bd10 pop {r4, pc}
|
|||
|
|
800025a: 2001 movs r0, #1
|
|||
|
|
800025c: bd10 pop {r4, pc}
|
|||
|
|
800025e: 46c0 nop ; (mov r8, r8)
|
|||
|
|
|
|||
|
|
08000260 <__aeabi_dcmple>:
|
|||
|
|
8000260: b510 push {r4, lr}
|
|||
|
|
8000262: f000 ff27 bl 80010b4 <__ledf2>
|
|||
|
|
8000266: 2800 cmp r0, #0
|
|||
|
|
8000268: dd01 ble.n 800026e <__aeabi_dcmple+0xe>
|
|||
|
|
800026a: 2000 movs r0, #0
|
|||
|
|
800026c: bd10 pop {r4, pc}
|
|||
|
|
800026e: 2001 movs r0, #1
|
|||
|
|
8000270: bd10 pop {r4, pc}
|
|||
|
|
8000272: 46c0 nop ; (mov r8, r8)
|
|||
|
|
|
|||
|
|
08000274 <__aeabi_dcmpgt>:
|
|||
|
|
8000274: b510 push {r4, lr}
|
|||
|
|
8000276: f000 feb9 bl 8000fec <__gedf2>
|
|||
|
|
800027a: 2800 cmp r0, #0
|
|||
|
|
800027c: dc01 bgt.n 8000282 <__aeabi_dcmpgt+0xe>
|
|||
|
|
800027e: 2000 movs r0, #0
|
|||
|
|
8000280: bd10 pop {r4, pc}
|
|||
|
|
8000282: 2001 movs r0, #1
|
|||
|
|
8000284: bd10 pop {r4, pc}
|
|||
|
|
8000286: 46c0 nop ; (mov r8, r8)
|
|||
|
|
|
|||
|
|
08000288 <__aeabi_dcmpge>:
|
|||
|
|
8000288: b510 push {r4, lr}
|
|||
|
|
800028a: f000 feaf bl 8000fec <__gedf2>
|
|||
|
|
800028e: 2800 cmp r0, #0
|
|||
|
|
8000290: da01 bge.n 8000296 <__aeabi_dcmpge+0xe>
|
|||
|
|
8000292: 2000 movs r0, #0
|
|||
|
|
8000294: bd10 pop {r4, pc}
|
|||
|
|
8000296: 2001 movs r0, #1
|
|||
|
|
8000298: bd10 pop {r4, pc}
|
|||
|
|
800029a: 46c0 nop ; (mov r8, r8)
|
|||
|
|
|
|||
|
|
0800029c <__aeabi_cfrcmple>:
|
|||
|
|
800029c: 4684 mov ip, r0
|
|||
|
|
800029e: 1c08 adds r0, r1, #0
|
|||
|
|
80002a0: 4661 mov r1, ip
|
|||
|
|
80002a2: e7ff b.n 80002a4 <__aeabi_cfcmpeq>
|
|||
|
|
|
|||
|
|
080002a4 <__aeabi_cfcmpeq>:
|
|||
|
|
80002a4: b51f push {r0, r1, r2, r3, r4, lr}
|
|||
|
|
80002a6: f000 fb03 bl 80008b0 <__lesf2>
|
|||
|
|
80002aa: 2800 cmp r0, #0
|
|||
|
|
80002ac: d401 bmi.n 80002b2 <__aeabi_cfcmpeq+0xe>
|
|||
|
|
80002ae: 2100 movs r1, #0
|
|||
|
|
80002b0: 42c8 cmn r0, r1
|
|||
|
|
80002b2: bd1f pop {r0, r1, r2, r3, r4, pc}
|
|||
|
|
|
|||
|
|
080002b4 <__aeabi_fcmpeq>:
|
|||
|
|
80002b4: b510 push {r4, lr}
|
|||
|
|
80002b6: f000 fa95 bl 80007e4 <__eqsf2>
|
|||
|
|
80002ba: 4240 negs r0, r0
|
|||
|
|
80002bc: 3001 adds r0, #1
|
|||
|
|
80002be: bd10 pop {r4, pc}
|
|||
|
|
|
|||
|
|
080002c0 <__aeabi_fcmplt>:
|
|||
|
|
80002c0: b510 push {r4, lr}
|
|||
|
|
80002c2: f000 faf5 bl 80008b0 <__lesf2>
|
|||
|
|
80002c6: 2800 cmp r0, #0
|
|||
|
|
80002c8: db01 blt.n 80002ce <__aeabi_fcmplt+0xe>
|
|||
|
|
80002ca: 2000 movs r0, #0
|
|||
|
|
80002cc: bd10 pop {r4, pc}
|
|||
|
|
80002ce: 2001 movs r0, #1
|
|||
|
|
80002d0: bd10 pop {r4, pc}
|
|||
|
|
80002d2: 46c0 nop ; (mov r8, r8)
|
|||
|
|
|
|||
|
|
080002d4 <__aeabi_fcmple>:
|
|||
|
|
80002d4: b510 push {r4, lr}
|
|||
|
|
80002d6: f000 faeb bl 80008b0 <__lesf2>
|
|||
|
|
80002da: 2800 cmp r0, #0
|
|||
|
|
80002dc: dd01 ble.n 80002e2 <__aeabi_fcmple+0xe>
|
|||
|
|
80002de: 2000 movs r0, #0
|
|||
|
|
80002e0: bd10 pop {r4, pc}
|
|||
|
|
80002e2: 2001 movs r0, #1
|
|||
|
|
80002e4: bd10 pop {r4, pc}
|
|||
|
|
80002e6: 46c0 nop ; (mov r8, r8)
|
|||
|
|
|
|||
|
|
080002e8 <__aeabi_fcmpgt>:
|
|||
|
|
80002e8: b510 push {r4, lr}
|
|||
|
|
80002ea: f000 faa1 bl 8000830 <__gesf2>
|
|||
|
|
80002ee: 2800 cmp r0, #0
|
|||
|
|
80002f0: dc01 bgt.n 80002f6 <__aeabi_fcmpgt+0xe>
|
|||
|
|
80002f2: 2000 movs r0, #0
|
|||
|
|
80002f4: bd10 pop {r4, pc}
|
|||
|
|
80002f6: 2001 movs r0, #1
|
|||
|
|
80002f8: bd10 pop {r4, pc}
|
|||
|
|
80002fa: 46c0 nop ; (mov r8, r8)
|
|||
|
|
|
|||
|
|
080002fc <__aeabi_fcmpge>:
|
|||
|
|
80002fc: b510 push {r4, lr}
|
|||
|
|
80002fe: f000 fa97 bl 8000830 <__gesf2>
|
|||
|
|
8000302: 2800 cmp r0, #0
|
|||
|
|
8000304: da01 bge.n 800030a <__aeabi_fcmpge+0xe>
|
|||
|
|
8000306: 2000 movs r0, #0
|
|||
|
|
8000308: bd10 pop {r4, pc}
|
|||
|
|
800030a: 2001 movs r0, #1
|
|||
|
|
800030c: bd10 pop {r4, pc}
|
|||
|
|
800030e: 46c0 nop ; (mov r8, r8)
|
|||
|
|
|
|||
|
|
08000310 <__aeabi_uldivmod>:
|
|||
|
|
8000310: 2b00 cmp r3, #0
|
|||
|
|
8000312: d111 bne.n 8000338 <__aeabi_uldivmod+0x28>
|
|||
|
|
8000314: 2a00 cmp r2, #0
|
|||
|
|
8000316: d10f bne.n 8000338 <__aeabi_uldivmod+0x28>
|
|||
|
|
8000318: 2900 cmp r1, #0
|
|||
|
|
800031a: d100 bne.n 800031e <__aeabi_uldivmod+0xe>
|
|||
|
|
800031c: 2800 cmp r0, #0
|
|||
|
|
800031e: d002 beq.n 8000326 <__aeabi_uldivmod+0x16>
|
|||
|
|
8000320: 2100 movs r1, #0
|
|||
|
|
8000322: 43c9 mvns r1, r1
|
|||
|
|
8000324: 1c08 adds r0, r1, #0
|
|||
|
|
8000326: b407 push {r0, r1, r2}
|
|||
|
|
8000328: 4802 ldr r0, [pc, #8] ; (8000334 <__aeabi_uldivmod+0x24>)
|
|||
|
|
800032a: a102 add r1, pc, #8 ; (adr r1, 8000334 <__aeabi_uldivmod+0x24>)
|
|||
|
|
800032c: 1840 adds r0, r0, r1
|
|||
|
|
800032e: 9002 str r0, [sp, #8]
|
|||
|
|
8000330: bd03 pop {r0, r1, pc}
|
|||
|
|
8000332: 46c0 nop ; (mov r8, r8)
|
|||
|
|
8000334: fffffee9 .word 0xfffffee9
|
|||
|
|
8000338: b403 push {r0, r1}
|
|||
|
|
800033a: 4668 mov r0, sp
|
|||
|
|
800033c: b501 push {r0, lr}
|
|||
|
|
800033e: 9802 ldr r0, [sp, #8]
|
|||
|
|
8000340: f000 f848 bl 80003d4 <__udivmoddi4>
|
|||
|
|
8000344: 9b01 ldr r3, [sp, #4]
|
|||
|
|
8000346: 469e mov lr, r3
|
|||
|
|
8000348: b002 add sp, #8
|
|||
|
|
800034a: bc0c pop {r2, r3}
|
|||
|
|
800034c: 4770 bx lr
|
|||
|
|
800034e: 46c0 nop ; (mov r8, r8)
|
|||
|
|
|
|||
|
|
08000350 <__aeabi_lmul>:
|
|||
|
|
8000350: b5f0 push {r4, r5, r6, r7, lr}
|
|||
|
|
8000352: 46ce mov lr, r9
|
|||
|
|
8000354: 4647 mov r7, r8
|
|||
|
|
8000356: 0415 lsls r5, r2, #16
|
|||
|
|
8000358: 0c2d lsrs r5, r5, #16
|
|||
|
|
800035a: 002e movs r6, r5
|
|||
|
|
800035c: b580 push {r7, lr}
|
|||
|
|
800035e: 0407 lsls r7, r0, #16
|
|||
|
|
8000360: 0c14 lsrs r4, r2, #16
|
|||
|
|
8000362: 0c3f lsrs r7, r7, #16
|
|||
|
|
8000364: 4699 mov r9, r3
|
|||
|
|
8000366: 0c03 lsrs r3, r0, #16
|
|||
|
|
8000368: 437e muls r6, r7
|
|||
|
|
800036a: 435d muls r5, r3
|
|||
|
|
800036c: 4367 muls r7, r4
|
|||
|
|
800036e: 4363 muls r3, r4
|
|||
|
|
8000370: 197f adds r7, r7, r5
|
|||
|
|
8000372: 0c34 lsrs r4, r6, #16
|
|||
|
|
8000374: 19e4 adds r4, r4, r7
|
|||
|
|
8000376: 469c mov ip, r3
|
|||
|
|
8000378: 42a5 cmp r5, r4
|
|||
|
|
800037a: d903 bls.n 8000384 <__aeabi_lmul+0x34>
|
|||
|
|
800037c: 2380 movs r3, #128 ; 0x80
|
|||
|
|
800037e: 025b lsls r3, r3, #9
|
|||
|
|
8000380: 4698 mov r8, r3
|
|||
|
|
8000382: 44c4 add ip, r8
|
|||
|
|
8000384: 464b mov r3, r9
|
|||
|
|
8000386: 4351 muls r1, r2
|
|||
|
|
8000388: 4343 muls r3, r0
|
|||
|
|
800038a: 0436 lsls r6, r6, #16
|
|||
|
|
800038c: 0c36 lsrs r6, r6, #16
|
|||
|
|
800038e: 0c25 lsrs r5, r4, #16
|
|||
|
|
8000390: 0424 lsls r4, r4, #16
|
|||
|
|
8000392: 4465 add r5, ip
|
|||
|
|
8000394: 19a4 adds r4, r4, r6
|
|||
|
|
8000396: 1859 adds r1, r3, r1
|
|||
|
|
8000398: 1949 adds r1, r1, r5
|
|||
|
|
800039a: 0020 movs r0, r4
|
|||
|
|
800039c: bc0c pop {r2, r3}
|
|||
|
|
800039e: 4690 mov r8, r2
|
|||
|
|
80003a0: 4699 mov r9, r3
|
|||
|
|
80003a2: bdf0 pop {r4, r5, r6, r7, pc}
|
|||
|
|
|
|||
|
|
080003a4 <__aeabi_f2uiz>:
|
|||
|
|
80003a4: 219e movs r1, #158 ; 0x9e
|
|||
|
|
80003a6: b510 push {r4, lr}
|
|||
|
|
80003a8: 05c9 lsls r1, r1, #23
|
|||
|
|
80003aa: 1c04 adds r4, r0, #0
|
|||
|
|
80003ac: f7ff ffa6 bl 80002fc <__aeabi_fcmpge>
|
|||
|
|
80003b0: 2800 cmp r0, #0
|
|||
|
|
80003b2: d103 bne.n 80003bc <__aeabi_f2uiz+0x18>
|
|||
|
|
80003b4: 1c20 adds r0, r4, #0
|
|||
|
|
80003b6: f000 fd79 bl 8000eac <__aeabi_f2iz>
|
|||
|
|
80003ba: bd10 pop {r4, pc}
|
|||
|
|
80003bc: 219e movs r1, #158 ; 0x9e
|
|||
|
|
80003be: 1c20 adds r0, r4, #0
|
|||
|
|
80003c0: 05c9 lsls r1, r1, #23
|
|||
|
|
80003c2: f000 fbd7 bl 8000b74 <__aeabi_fsub>
|
|||
|
|
80003c6: f000 fd71 bl 8000eac <__aeabi_f2iz>
|
|||
|
|
80003ca: 2380 movs r3, #128 ; 0x80
|
|||
|
|
80003cc: 061b lsls r3, r3, #24
|
|||
|
|
80003ce: 469c mov ip, r3
|
|||
|
|
80003d0: 4460 add r0, ip
|
|||
|
|
80003d2: e7f2 b.n 80003ba <__aeabi_f2uiz+0x16>
|
|||
|
|
|
|||
|
|
080003d4 <__udivmoddi4>:
|
|||
|
|
80003d4: b5f0 push {r4, r5, r6, r7, lr}
|
|||
|
|
80003d6: 4657 mov r7, sl
|
|||
|
|
80003d8: 464e mov r6, r9
|
|||
|
|
80003da: 4645 mov r5, r8
|
|||
|
|
80003dc: 46de mov lr, fp
|
|||
|
|
80003de: b5e0 push {r5, r6, r7, lr}
|
|||
|
|
80003e0: 0004 movs r4, r0
|
|||
|
|
80003e2: b083 sub sp, #12
|
|||
|
|
80003e4: 000d movs r5, r1
|
|||
|
|
80003e6: 4692 mov sl, r2
|
|||
|
|
80003e8: 4699 mov r9, r3
|
|||
|
|
80003ea: 428b cmp r3, r1
|
|||
|
|
80003ec: d82f bhi.n 800044e <__udivmoddi4+0x7a>
|
|||
|
|
80003ee: d02c beq.n 800044a <__udivmoddi4+0x76>
|
|||
|
|
80003f0: 4649 mov r1, r9
|
|||
|
|
80003f2: 4650 mov r0, sl
|
|||
|
|
80003f4: f000 ff30 bl 8001258 <__clzdi2>
|
|||
|
|
80003f8: 0029 movs r1, r5
|
|||
|
|
80003fa: 0006 movs r6, r0
|
|||
|
|
80003fc: 0020 movs r0, r4
|
|||
|
|
80003fe: f000 ff2b bl 8001258 <__clzdi2>
|
|||
|
|
8000402: 1a33 subs r3, r6, r0
|
|||
|
|
8000404: 4698 mov r8, r3
|
|||
|
|
8000406: 3b20 subs r3, #32
|
|||
|
|
8000408: 469b mov fp, r3
|
|||
|
|
800040a: d500 bpl.n 800040e <__udivmoddi4+0x3a>
|
|||
|
|
800040c: e074 b.n 80004f8 <__udivmoddi4+0x124>
|
|||
|
|
800040e: 4653 mov r3, sl
|
|||
|
|
8000410: 465a mov r2, fp
|
|||
|
|
8000412: 4093 lsls r3, r2
|
|||
|
|
8000414: 001f movs r7, r3
|
|||
|
|
8000416: 4653 mov r3, sl
|
|||
|
|
8000418: 4642 mov r2, r8
|
|||
|
|
800041a: 4093 lsls r3, r2
|
|||
|
|
800041c: 001e movs r6, r3
|
|||
|
|
800041e: 42af cmp r7, r5
|
|||
|
|
8000420: d829 bhi.n 8000476 <__udivmoddi4+0xa2>
|
|||
|
|
8000422: d026 beq.n 8000472 <__udivmoddi4+0x9e>
|
|||
|
|
8000424: 465b mov r3, fp
|
|||
|
|
8000426: 1ba4 subs r4, r4, r6
|
|||
|
|
8000428: 41bd sbcs r5, r7
|
|||
|
|
800042a: 2b00 cmp r3, #0
|
|||
|
|
800042c: da00 bge.n 8000430 <__udivmoddi4+0x5c>
|
|||
|
|
800042e: e079 b.n 8000524 <__udivmoddi4+0x150>
|
|||
|
|
8000430: 2200 movs r2, #0
|
|||
|
|
8000432: 2300 movs r3, #0
|
|||
|
|
8000434: 9200 str r2, [sp, #0]
|
|||
|
|
8000436: 9301 str r3, [sp, #4]
|
|||
|
|
8000438: 2301 movs r3, #1
|
|||
|
|
800043a: 465a mov r2, fp
|
|||
|
|
800043c: 4093 lsls r3, r2
|
|||
|
|
800043e: 9301 str r3, [sp, #4]
|
|||
|
|
8000440: 2301 movs r3, #1
|
|||
|
|
8000442: 4642 mov r2, r8
|
|||
|
|
8000444: 4093 lsls r3, r2
|
|||
|
|
8000446: 9300 str r3, [sp, #0]
|
|||
|
|
8000448: e019 b.n 800047e <__udivmoddi4+0xaa>
|
|||
|
|
800044a: 4282 cmp r2, r0
|
|||
|
|
800044c: d9d0 bls.n 80003f0 <__udivmoddi4+0x1c>
|
|||
|
|
800044e: 2200 movs r2, #0
|
|||
|
|
8000450: 2300 movs r3, #0
|
|||
|
|
8000452: 9200 str r2, [sp, #0]
|
|||
|
|
8000454: 9301 str r3, [sp, #4]
|
|||
|
|
8000456: 9b0c ldr r3, [sp, #48] ; 0x30
|
|||
|
|
8000458: 2b00 cmp r3, #0
|
|||
|
|
800045a: d001 beq.n 8000460 <__udivmoddi4+0x8c>
|
|||
|
|
800045c: 601c str r4, [r3, #0]
|
|||
|
|
800045e: 605d str r5, [r3, #4]
|
|||
|
|
8000460: 9800 ldr r0, [sp, #0]
|
|||
|
|
8000462: 9901 ldr r1, [sp, #4]
|
|||
|
|
8000464: b003 add sp, #12
|
|||
|
|
8000466: bc3c pop {r2, r3, r4, r5}
|
|||
|
|
8000468: 4690 mov r8, r2
|
|||
|
|
800046a: 4699 mov r9, r3
|
|||
|
|
800046c: 46a2 mov sl, r4
|
|||
|
|
800046e: 46ab mov fp, r5
|
|||
|
|
8000470: bdf0 pop {r4, r5, r6, r7, pc}
|
|||
|
|
8000472: 42a3 cmp r3, r4
|
|||
|
|
8000474: d9d6 bls.n 8000424 <__udivmoddi4+0x50>
|
|||
|
|
8000476: 2200 movs r2, #0
|
|||
|
|
8000478: 2300 movs r3, #0
|
|||
|
|
800047a: 9200 str r2, [sp, #0]
|
|||
|
|
800047c: 9301 str r3, [sp, #4]
|
|||
|
|
800047e: 4643 mov r3, r8
|
|||
|
|
8000480: 2b00 cmp r3, #0
|
|||
|
|
8000482: d0e8 beq.n 8000456 <__udivmoddi4+0x82>
|
|||
|
|
8000484: 07fb lsls r3, r7, #31
|
|||
|
|
8000486: 0872 lsrs r2, r6, #1
|
|||
|
|
8000488: 431a orrs r2, r3
|
|||
|
|
800048a: 4646 mov r6, r8
|
|||
|
|
800048c: 087b lsrs r3, r7, #1
|
|||
|
|
800048e: e00e b.n 80004ae <__udivmoddi4+0xda>
|
|||
|
|
8000490: 42ab cmp r3, r5
|
|||
|
|
8000492: d101 bne.n 8000498 <__udivmoddi4+0xc4>
|
|||
|
|
8000494: 42a2 cmp r2, r4
|
|||
|
|
8000496: d80c bhi.n 80004b2 <__udivmoddi4+0xde>
|
|||
|
|
8000498: 1aa4 subs r4, r4, r2
|
|||
|
|
800049a: 419d sbcs r5, r3
|
|||
|
|
800049c: 2001 movs r0, #1
|
|||
|
|
800049e: 1924 adds r4, r4, r4
|
|||
|
|
80004a0: 416d adcs r5, r5
|
|||
|
|
80004a2: 2100 movs r1, #0
|
|||
|
|
80004a4: 3e01 subs r6, #1
|
|||
|
|
80004a6: 1824 adds r4, r4, r0
|
|||
|
|
80004a8: 414d adcs r5, r1
|
|||
|
|
80004aa: 2e00 cmp r6, #0
|
|||
|
|
80004ac: d006 beq.n 80004bc <__udivmoddi4+0xe8>
|
|||
|
|
80004ae: 42ab cmp r3, r5
|
|||
|
|
80004b0: d9ee bls.n 8000490 <__udivmoddi4+0xbc>
|
|||
|
|
80004b2: 3e01 subs r6, #1
|
|||
|
|
80004b4: 1924 adds r4, r4, r4
|
|||
|
|
80004b6: 416d adcs r5, r5
|
|||
|
|
80004b8: 2e00 cmp r6, #0
|
|||
|
|
80004ba: d1f8 bne.n 80004ae <__udivmoddi4+0xda>
|
|||
|
|
80004bc: 465b mov r3, fp
|
|||
|
|
80004be: 9800 ldr r0, [sp, #0]
|
|||
|
|
80004c0: 9901 ldr r1, [sp, #4]
|
|||
|
|
80004c2: 1900 adds r0, r0, r4
|
|||
|
|
80004c4: 4169 adcs r1, r5
|
|||
|
|
80004c6: 2b00 cmp r3, #0
|
|||
|
|
80004c8: db22 blt.n 8000510 <__udivmoddi4+0x13c>
|
|||
|
|
80004ca: 002b movs r3, r5
|
|||
|
|
80004cc: 465a mov r2, fp
|
|||
|
|
80004ce: 40d3 lsrs r3, r2
|
|||
|
|
80004d0: 002a movs r2, r5
|
|||
|
|
80004d2: 4644 mov r4, r8
|
|||
|
|
80004d4: 40e2 lsrs r2, r4
|
|||
|
|
80004d6: 001c movs r4, r3
|
|||
|
|
80004d8: 465b mov r3, fp
|
|||
|
|
80004da: 0015 movs r5, r2
|
|||
|
|
80004dc: 2b00 cmp r3, #0
|
|||
|
|
80004de: db2c blt.n 800053a <__udivmoddi4+0x166>
|
|||
|
|
80004e0: 0026 movs r6, r4
|
|||
|
|
80004e2: 409e lsls r6, r3
|
|||
|
|
80004e4: 0033 movs r3, r6
|
|||
|
|
80004e6: 0026 movs r6, r4
|
|||
|
|
80004e8: 4647 mov r7, r8
|
|||
|
|
80004ea: 40be lsls r6, r7
|
|||
|
|
80004ec: 0032 movs r2, r6
|
|||
|
|
80004ee: 1a80 subs r0, r0, r2
|
|||
|
|
80004f0: 4199 sbcs r1, r3
|
|||
|
|
80004f2: 9000 str r0, [sp, #0]
|
|||
|
|
80004f4: 9101 str r1, [sp, #4]
|
|||
|
|
80004f6: e7ae b.n 8000456 <__udivmoddi4+0x82>
|
|||
|
|
80004f8: 4642 mov r2, r8
|
|||
|
|
80004fa: 2320 movs r3, #32
|
|||
|
|
80004fc: 1a9b subs r3, r3, r2
|
|||
|
|
80004fe: 4652 mov r2, sl
|
|||
|
|
8000500: 40da lsrs r2, r3
|
|||
|
|
8000502: 4641 mov r1, r8
|
|||
|
|
8000504: 0013 movs r3, r2
|
|||
|
|
8000506: 464a mov r2, r9
|
|||
|
|
8000508: 408a lsls r2, r1
|
|||
|
|
800050a: 0017 movs r7, r2
|
|||
|
|
800050c: 431f orrs r7, r3
|
|||
|
|
800050e: e782 b.n 8000416 <__udivmoddi4+0x42>
|
|||
|
|
8000510: 4642 mov r2, r8
|
|||
|
|
8000512: 2320 movs r3, #32
|
|||
|
|
8000514: 1a9b subs r3, r3, r2
|
|||
|
|
8000516: 002a movs r2, r5
|
|||
|
|
8000518: 4646 mov r6, r8
|
|||
|
|
800051a: 409a lsls r2, r3
|
|||
|
|
800051c: 0023 movs r3, r4
|
|||
|
|
800051e: 40f3 lsrs r3, r6
|
|||
|
|
8000520: 4313 orrs r3, r2
|
|||
|
|
8000522: e7d5 b.n 80004d0 <__udivmoddi4+0xfc>
|
|||
|
|
8000524: 4642 mov r2, r8
|
|||
|
|
8000526: 2320 movs r3, #32
|
|||
|
|
8000528: 2100 movs r1, #0
|
|||
|
|
800052a: 1a9b subs r3, r3, r2
|
|||
|
|
800052c: 2200 movs r2, #0
|
|||
|
|
800052e: 9100 str r1, [sp, #0]
|
|||
|
|
8000530: 9201 str r2, [sp, #4]
|
|||
|
|
8000532: 2201 movs r2, #1
|
|||
|
|
8000534: 40da lsrs r2, r3
|
|||
|
|
8000536: 9201 str r2, [sp, #4]
|
|||
|
|
8000538: e782 b.n 8000440 <__udivmoddi4+0x6c>
|
|||
|
|
800053a: 4642 mov r2, r8
|
|||
|
|
800053c: 2320 movs r3, #32
|
|||
|
|
800053e: 0026 movs r6, r4
|
|||
|
|
8000540: 1a9b subs r3, r3, r2
|
|||
|
|
8000542: 40de lsrs r6, r3
|
|||
|
|
8000544: 002f movs r7, r5
|
|||
|
|
8000546: 46b4 mov ip, r6
|
|||
|
|
8000548: 4097 lsls r7, r2
|
|||
|
|
800054a: 4666 mov r6, ip
|
|||
|
|
800054c: 003b movs r3, r7
|
|||
|
|
800054e: 4333 orrs r3, r6
|
|||
|
|
8000550: e7c9 b.n 80004e6 <__udivmoddi4+0x112>
|
|||
|
|
8000552: 46c0 nop ; (mov r8, r8)
|
|||
|
|
|
|||
|
|
08000554 <__aeabi_fdiv>:
|
|||
|
|
8000554: b5f0 push {r4, r5, r6, r7, lr}
|
|||
|
|
8000556: 4657 mov r7, sl
|
|||
|
|
8000558: 464e mov r6, r9
|
|||
|
|
800055a: 46de mov lr, fp
|
|||
|
|
800055c: 4645 mov r5, r8
|
|||
|
|
800055e: b5e0 push {r5, r6, r7, lr}
|
|||
|
|
8000560: 0244 lsls r4, r0, #9
|
|||
|
|
8000562: 0043 lsls r3, r0, #1
|
|||
|
|
8000564: 0fc6 lsrs r6, r0, #31
|
|||
|
|
8000566: b083 sub sp, #12
|
|||
|
|
8000568: 1c0f adds r7, r1, #0
|
|||
|
|
800056a: 0a64 lsrs r4, r4, #9
|
|||
|
|
800056c: 0e1b lsrs r3, r3, #24
|
|||
|
|
800056e: 46b2 mov sl, r6
|
|||
|
|
8000570: d053 beq.n 800061a <__aeabi_fdiv+0xc6>
|
|||
|
|
8000572: 2bff cmp r3, #255 ; 0xff
|
|||
|
|
8000574: d027 beq.n 80005c6 <__aeabi_fdiv+0x72>
|
|||
|
|
8000576: 2280 movs r2, #128 ; 0x80
|
|||
|
|
8000578: 00e4 lsls r4, r4, #3
|
|||
|
|
800057a: 04d2 lsls r2, r2, #19
|
|||
|
|
800057c: 4314 orrs r4, r2
|
|||
|
|
800057e: 227f movs r2, #127 ; 0x7f
|
|||
|
|
8000580: 4252 negs r2, r2
|
|||
|
|
8000582: 4690 mov r8, r2
|
|||
|
|
8000584: 4498 add r8, r3
|
|||
|
|
8000586: 2300 movs r3, #0
|
|||
|
|
8000588: 4699 mov r9, r3
|
|||
|
|
800058a: 469b mov fp, r3
|
|||
|
|
800058c: 027d lsls r5, r7, #9
|
|||
|
|
800058e: 0078 lsls r0, r7, #1
|
|||
|
|
8000590: 0ffb lsrs r3, r7, #31
|
|||
|
|
8000592: 0a6d lsrs r5, r5, #9
|
|||
|
|
8000594: 0e00 lsrs r0, r0, #24
|
|||
|
|
8000596: 9300 str r3, [sp, #0]
|
|||
|
|
8000598: d024 beq.n 80005e4 <__aeabi_fdiv+0x90>
|
|||
|
|
800059a: 28ff cmp r0, #255 ; 0xff
|
|||
|
|
800059c: d046 beq.n 800062c <__aeabi_fdiv+0xd8>
|
|||
|
|
800059e: 2380 movs r3, #128 ; 0x80
|
|||
|
|
80005a0: 2100 movs r1, #0
|
|||
|
|
80005a2: 00ed lsls r5, r5, #3
|
|||
|
|
80005a4: 04db lsls r3, r3, #19
|
|||
|
|
80005a6: 431d orrs r5, r3
|
|||
|
|
80005a8: 387f subs r0, #127 ; 0x7f
|
|||
|
|
80005aa: 4647 mov r7, r8
|
|||
|
|
80005ac: 1a38 subs r0, r7, r0
|
|||
|
|
80005ae: 464f mov r7, r9
|
|||
|
|
80005b0: 430f orrs r7, r1
|
|||
|
|
80005b2: 00bf lsls r7, r7, #2
|
|||
|
|
80005b4: 46b9 mov r9, r7
|
|||
|
|
80005b6: 0033 movs r3, r6
|
|||
|
|
80005b8: 9a00 ldr r2, [sp, #0]
|
|||
|
|
80005ba: 4f87 ldr r7, [pc, #540] ; (80007d8 <__aeabi_fdiv+0x284>)
|
|||
|
|
80005bc: 4053 eors r3, r2
|
|||
|
|
80005be: 464a mov r2, r9
|
|||
|
|
80005c0: 58ba ldr r2, [r7, r2]
|
|||
|
|
80005c2: 9301 str r3, [sp, #4]
|
|||
|
|
80005c4: 4697 mov pc, r2
|
|||
|
|
80005c6: 2c00 cmp r4, #0
|
|||
|
|
80005c8: d14e bne.n 8000668 <__aeabi_fdiv+0x114>
|
|||
|
|
80005ca: 2308 movs r3, #8
|
|||
|
|
80005cc: 4699 mov r9, r3
|
|||
|
|
80005ce: 33f7 adds r3, #247 ; 0xf7
|
|||
|
|
80005d0: 4698 mov r8, r3
|
|||
|
|
80005d2: 3bfd subs r3, #253 ; 0xfd
|
|||
|
|
80005d4: 469b mov fp, r3
|
|||
|
|
80005d6: 027d lsls r5, r7, #9
|
|||
|
|
80005d8: 0078 lsls r0, r7, #1
|
|||
|
|
80005da: 0ffb lsrs r3, r7, #31
|
|||
|
|
80005dc: 0a6d lsrs r5, r5, #9
|
|||
|
|
80005de: 0e00 lsrs r0, r0, #24
|
|||
|
|
80005e0: 9300 str r3, [sp, #0]
|
|||
|
|
80005e2: d1da bne.n 800059a <__aeabi_fdiv+0x46>
|
|||
|
|
80005e4: 2d00 cmp r5, #0
|
|||
|
|
80005e6: d126 bne.n 8000636 <__aeabi_fdiv+0xe2>
|
|||
|
|
80005e8: 2000 movs r0, #0
|
|||
|
|
80005ea: 2101 movs r1, #1
|
|||
|
|
80005ec: 0033 movs r3, r6
|
|||
|
|
80005ee: 9a00 ldr r2, [sp, #0]
|
|||
|
|
80005f0: 4f7a ldr r7, [pc, #488] ; (80007dc <__aeabi_fdiv+0x288>)
|
|||
|
|
80005f2: 4053 eors r3, r2
|
|||
|
|
80005f4: 4642 mov r2, r8
|
|||
|
|
80005f6: 1a10 subs r0, r2, r0
|
|||
|
|
80005f8: 464a mov r2, r9
|
|||
|
|
80005fa: 430a orrs r2, r1
|
|||
|
|
80005fc: 0092 lsls r2, r2, #2
|
|||
|
|
80005fe: 58ba ldr r2, [r7, r2]
|
|||
|
|
8000600: 001d movs r5, r3
|
|||
|
|
8000602: 4697 mov pc, r2
|
|||
|
|
8000604: 9b00 ldr r3, [sp, #0]
|
|||
|
|
8000606: 002c movs r4, r5
|
|||
|
|
8000608: 469a mov sl, r3
|
|||
|
|
800060a: 468b mov fp, r1
|
|||
|
|
800060c: 465b mov r3, fp
|
|||
|
|
800060e: 2b02 cmp r3, #2
|
|||
|
|
8000610: d131 bne.n 8000676 <__aeabi_fdiv+0x122>
|
|||
|
|
8000612: 4653 mov r3, sl
|
|||
|
|
8000614: 21ff movs r1, #255 ; 0xff
|
|||
|
|
8000616: 2400 movs r4, #0
|
|||
|
|
8000618: e038 b.n 800068c <__aeabi_fdiv+0x138>
|
|||
|
|
800061a: 2c00 cmp r4, #0
|
|||
|
|
800061c: d117 bne.n 800064e <__aeabi_fdiv+0xfa>
|
|||
|
|
800061e: 2304 movs r3, #4
|
|||
|
|
8000620: 4699 mov r9, r3
|
|||
|
|
8000622: 2300 movs r3, #0
|
|||
|
|
8000624: 4698 mov r8, r3
|
|||
|
|
8000626: 3301 adds r3, #1
|
|||
|
|
8000628: 469b mov fp, r3
|
|||
|
|
800062a: e7af b.n 800058c <__aeabi_fdiv+0x38>
|
|||
|
|
800062c: 20ff movs r0, #255 ; 0xff
|
|||
|
|
800062e: 2d00 cmp r5, #0
|
|||
|
|
8000630: d10b bne.n 800064a <__aeabi_fdiv+0xf6>
|
|||
|
|
8000632: 2102 movs r1, #2
|
|||
|
|
8000634: e7da b.n 80005ec <__aeabi_fdiv+0x98>
|
|||
|
|
8000636: 0028 movs r0, r5
|
|||
|
|
8000638: f000 fdf0 bl 800121c <__clzsi2>
|
|||
|
|
800063c: 1f43 subs r3, r0, #5
|
|||
|
|
800063e: 409d lsls r5, r3
|
|||
|
|
8000640: 2376 movs r3, #118 ; 0x76
|
|||
|
|
8000642: 425b negs r3, r3
|
|||
|
|
8000644: 1a18 subs r0, r3, r0
|
|||
|
|
8000646: 2100 movs r1, #0
|
|||
|
|
8000648: e7af b.n 80005aa <__aeabi_fdiv+0x56>
|
|||
|
|
800064a: 2103 movs r1, #3
|
|||
|
|
800064c: e7ad b.n 80005aa <__aeabi_fdiv+0x56>
|
|||
|
|
800064e: 0020 movs r0, r4
|
|||
|
|
8000650: f000 fde4 bl 800121c <__clzsi2>
|
|||
|
|
8000654: 1f43 subs r3, r0, #5
|
|||
|
|
8000656: 409c lsls r4, r3
|
|||
|
|
8000658: 2376 movs r3, #118 ; 0x76
|
|||
|
|
800065a: 425b negs r3, r3
|
|||
|
|
800065c: 1a1b subs r3, r3, r0
|
|||
|
|
800065e: 4698 mov r8, r3
|
|||
|
|
8000660: 2300 movs r3, #0
|
|||
|
|
8000662: 4699 mov r9, r3
|
|||
|
|
8000664: 469b mov fp, r3
|
|||
|
|
8000666: e791 b.n 800058c <__aeabi_fdiv+0x38>
|
|||
|
|
8000668: 230c movs r3, #12
|
|||
|
|
800066a: 4699 mov r9, r3
|
|||
|
|
800066c: 33f3 adds r3, #243 ; 0xf3
|
|||
|
|
800066e: 4698 mov r8, r3
|
|||
|
|
8000670: 3bfc subs r3, #252 ; 0xfc
|
|||
|
|
8000672: 469b mov fp, r3
|
|||
|
|
8000674: e78a b.n 800058c <__aeabi_fdiv+0x38>
|
|||
|
|
8000676: 2b03 cmp r3, #3
|
|||
|
|
8000678: d100 bne.n 800067c <__aeabi_fdiv+0x128>
|
|||
|
|
800067a: e0a5 b.n 80007c8 <__aeabi_fdiv+0x274>
|
|||
|
|
800067c: 4655 mov r5, sl
|
|||
|
|
800067e: 2b01 cmp r3, #1
|
|||
|
|
8000680: d000 beq.n 8000684 <__aeabi_fdiv+0x130>
|
|||
|
|
8000682: e081 b.n 8000788 <__aeabi_fdiv+0x234>
|
|||
|
|
8000684: 2301 movs r3, #1
|
|||
|
|
8000686: 2100 movs r1, #0
|
|||
|
|
8000688: 2400 movs r4, #0
|
|||
|
|
800068a: 402b ands r3, r5
|
|||
|
|
800068c: 0264 lsls r4, r4, #9
|
|||
|
|
800068e: 05c9 lsls r1, r1, #23
|
|||
|
|
8000690: 0a60 lsrs r0, r4, #9
|
|||
|
|
8000692: 07db lsls r3, r3, #31
|
|||
|
|
8000694: 4308 orrs r0, r1
|
|||
|
|
8000696: 4318 orrs r0, r3
|
|||
|
|
8000698: b003 add sp, #12
|
|||
|
|
800069a: bc3c pop {r2, r3, r4, r5}
|
|||
|
|
800069c: 4690 mov r8, r2
|
|||
|
|
800069e: 4699 mov r9, r3
|
|||
|
|
80006a0: 46a2 mov sl, r4
|
|||
|
|
80006a2: 46ab mov fp, r5
|
|||
|
|
80006a4: bdf0 pop {r4, r5, r6, r7, pc}
|
|||
|
|
80006a6: 2480 movs r4, #128 ; 0x80
|
|||
|
|
80006a8: 2300 movs r3, #0
|
|||
|
|
80006aa: 03e4 lsls r4, r4, #15
|
|||
|
|
80006ac: 21ff movs r1, #255 ; 0xff
|
|||
|
|
80006ae: e7ed b.n 800068c <__aeabi_fdiv+0x138>
|
|||
|
|
80006b0: 21ff movs r1, #255 ; 0xff
|
|||
|
|
80006b2: 2400 movs r4, #0
|
|||
|
|
80006b4: e7ea b.n 800068c <__aeabi_fdiv+0x138>
|
|||
|
|
80006b6: 2301 movs r3, #1
|
|||
|
|
80006b8: 1a59 subs r1, r3, r1
|
|||
|
|
80006ba: 291b cmp r1, #27
|
|||
|
|
80006bc: dd66 ble.n 800078c <__aeabi_fdiv+0x238>
|
|||
|
|
80006be: 9a01 ldr r2, [sp, #4]
|
|||
|
|
80006c0: 4013 ands r3, r2
|
|||
|
|
80006c2: 2100 movs r1, #0
|
|||
|
|
80006c4: 2400 movs r4, #0
|
|||
|
|
80006c6: e7e1 b.n 800068c <__aeabi_fdiv+0x138>
|
|||
|
|
80006c8: 2380 movs r3, #128 ; 0x80
|
|||
|
|
80006ca: 03db lsls r3, r3, #15
|
|||
|
|
80006cc: 421c tst r4, r3
|
|||
|
|
80006ce: d038 beq.n 8000742 <__aeabi_fdiv+0x1ee>
|
|||
|
|
80006d0: 421d tst r5, r3
|
|||
|
|
80006d2: d051 beq.n 8000778 <__aeabi_fdiv+0x224>
|
|||
|
|
80006d4: 431c orrs r4, r3
|
|||
|
|
80006d6: 0264 lsls r4, r4, #9
|
|||
|
|
80006d8: 0a64 lsrs r4, r4, #9
|
|||
|
|
80006da: 0033 movs r3, r6
|
|||
|
|
80006dc: 21ff movs r1, #255 ; 0xff
|
|||
|
|
80006de: e7d5 b.n 800068c <__aeabi_fdiv+0x138>
|
|||
|
|
80006e0: 0163 lsls r3, r4, #5
|
|||
|
|
80006e2: 016c lsls r4, r5, #5
|
|||
|
|
80006e4: 42a3 cmp r3, r4
|
|||
|
|
80006e6: d23b bcs.n 8000760 <__aeabi_fdiv+0x20c>
|
|||
|
|
80006e8: 261b movs r6, #27
|
|||
|
|
80006ea: 2100 movs r1, #0
|
|||
|
|
80006ec: 3801 subs r0, #1
|
|||
|
|
80006ee: 2501 movs r5, #1
|
|||
|
|
80006f0: 001f movs r7, r3
|
|||
|
|
80006f2: 0049 lsls r1, r1, #1
|
|||
|
|
80006f4: 005b lsls r3, r3, #1
|
|||
|
|
80006f6: 2f00 cmp r7, #0
|
|||
|
|
80006f8: db01 blt.n 80006fe <__aeabi_fdiv+0x1aa>
|
|||
|
|
80006fa: 429c cmp r4, r3
|
|||
|
|
80006fc: d801 bhi.n 8000702 <__aeabi_fdiv+0x1ae>
|
|||
|
|
80006fe: 1b1b subs r3, r3, r4
|
|||
|
|
8000700: 4329 orrs r1, r5
|
|||
|
|
8000702: 3e01 subs r6, #1
|
|||
|
|
8000704: 2e00 cmp r6, #0
|
|||
|
|
8000706: d1f3 bne.n 80006f0 <__aeabi_fdiv+0x19c>
|
|||
|
|
8000708: 001c movs r4, r3
|
|||
|
|
800070a: 1e63 subs r3, r4, #1
|
|||
|
|
800070c: 419c sbcs r4, r3
|
|||
|
|
800070e: 430c orrs r4, r1
|
|||
|
|
8000710: 0001 movs r1, r0
|
|||
|
|
8000712: 317f adds r1, #127 ; 0x7f
|
|||
|
|
8000714: 2900 cmp r1, #0
|
|||
|
|
8000716: ddce ble.n 80006b6 <__aeabi_fdiv+0x162>
|
|||
|
|
8000718: 0763 lsls r3, r4, #29
|
|||
|
|
800071a: d004 beq.n 8000726 <__aeabi_fdiv+0x1d2>
|
|||
|
|
800071c: 230f movs r3, #15
|
|||
|
|
800071e: 4023 ands r3, r4
|
|||
|
|
8000720: 2b04 cmp r3, #4
|
|||
|
|
8000722: d000 beq.n 8000726 <__aeabi_fdiv+0x1d2>
|
|||
|
|
8000724: 3404 adds r4, #4
|
|||
|
|
8000726: 0123 lsls r3, r4, #4
|
|||
|
|
8000728: d503 bpl.n 8000732 <__aeabi_fdiv+0x1de>
|
|||
|
|
800072a: 0001 movs r1, r0
|
|||
|
|
800072c: 4b2c ldr r3, [pc, #176] ; (80007e0 <__aeabi_fdiv+0x28c>)
|
|||
|
|
800072e: 3180 adds r1, #128 ; 0x80
|
|||
|
|
8000730: 401c ands r4, r3
|
|||
|
|
8000732: 29fe cmp r1, #254 ; 0xfe
|
|||
|
|
8000734: dd0d ble.n 8000752 <__aeabi_fdiv+0x1fe>
|
|||
|
|
8000736: 2301 movs r3, #1
|
|||
|
|
8000738: 9a01 ldr r2, [sp, #4]
|
|||
|
|
800073a: 21ff movs r1, #255 ; 0xff
|
|||
|
|
800073c: 4013 ands r3, r2
|
|||
|
|
800073e: 2400 movs r4, #0
|
|||
|
|
8000740: e7a4 b.n 800068c <__aeabi_fdiv+0x138>
|
|||
|
|
8000742: 2380 movs r3, #128 ; 0x80
|
|||
|
|
8000744: 03db lsls r3, r3, #15
|
|||
|
|
8000746: 431c orrs r4, r3
|
|||
|
|
8000748: 0264 lsls r4, r4, #9
|
|||
|
|
800074a: 0a64 lsrs r4, r4, #9
|
|||
|
|
800074c: 0033 movs r3, r6
|
|||
|
|
800074e: 21ff movs r1, #255 ; 0xff
|
|||
|
|
8000750: e79c b.n 800068c <__aeabi_fdiv+0x138>
|
|||
|
|
8000752: 2301 movs r3, #1
|
|||
|
|
8000754: 9a01 ldr r2, [sp, #4]
|
|||
|
|
8000756: 01a4 lsls r4, r4, #6
|
|||
|
|
8000758: 0a64 lsrs r4, r4, #9
|
|||
|
|
800075a: b2c9 uxtb r1, r1
|
|||
|
|
800075c: 4013 ands r3, r2
|
|||
|
|
800075e: e795 b.n 800068c <__aeabi_fdiv+0x138>
|
|||
|
|
8000760: 1b1b subs r3, r3, r4
|
|||
|
|
8000762: 261a movs r6, #26
|
|||
|
|
8000764: 2101 movs r1, #1
|
|||
|
|
8000766: e7c2 b.n 80006ee <__aeabi_fdiv+0x19a>
|
|||
|
|
8000768: 9b00 ldr r3, [sp, #0]
|
|||
|
|
800076a: 468b mov fp, r1
|
|||
|
|
800076c: 469a mov sl, r3
|
|||
|
|
800076e: 2400 movs r4, #0
|
|||
|
|
8000770: e74c b.n 800060c <__aeabi_fdiv+0xb8>
|
|||
|
|
8000772: 0263 lsls r3, r4, #9
|
|||
|
|
8000774: d5e5 bpl.n 8000742 <__aeabi_fdiv+0x1ee>
|
|||
|
|
8000776: 2500 movs r5, #0
|
|||
|
|
8000778: 2480 movs r4, #128 ; 0x80
|
|||
|
|
800077a: 03e4 lsls r4, r4, #15
|
|||
|
|
800077c: 432c orrs r4, r5
|
|||
|
|
800077e: 0264 lsls r4, r4, #9
|
|||
|
|
8000780: 0a64 lsrs r4, r4, #9
|
|||
|
|
8000782: 9b00 ldr r3, [sp, #0]
|
|||
|
|
8000784: 21ff movs r1, #255 ; 0xff
|
|||
|
|
8000786: e781 b.n 800068c <__aeabi_fdiv+0x138>
|
|||
|
|
8000788: 9501 str r5, [sp, #4]
|
|||
|
|
800078a: e7c1 b.n 8000710 <__aeabi_fdiv+0x1bc>
|
|||
|
|
800078c: 0023 movs r3, r4
|
|||
|
|
800078e: 2020 movs r0, #32
|
|||
|
|
8000790: 40cb lsrs r3, r1
|
|||
|
|
8000792: 1a41 subs r1, r0, r1
|
|||
|
|
8000794: 408c lsls r4, r1
|
|||
|
|
8000796: 1e61 subs r1, r4, #1
|
|||
|
|
8000798: 418c sbcs r4, r1
|
|||
|
|
800079a: 431c orrs r4, r3
|
|||
|
|
800079c: 0763 lsls r3, r4, #29
|
|||
|
|
800079e: d004 beq.n 80007aa <__aeabi_fdiv+0x256>
|
|||
|
|
80007a0: 230f movs r3, #15
|
|||
|
|
80007a2: 4023 ands r3, r4
|
|||
|
|
80007a4: 2b04 cmp r3, #4
|
|||
|
|
80007a6: d000 beq.n 80007aa <__aeabi_fdiv+0x256>
|
|||
|
|
80007a8: 3404 adds r4, #4
|
|||
|
|
80007aa: 0163 lsls r3, r4, #5
|
|||
|
|
80007ac: d505 bpl.n 80007ba <__aeabi_fdiv+0x266>
|
|||
|
|
80007ae: 2301 movs r3, #1
|
|||
|
|
80007b0: 9a01 ldr r2, [sp, #4]
|
|||
|
|
80007b2: 2101 movs r1, #1
|
|||
|
|
80007b4: 4013 ands r3, r2
|
|||
|
|
80007b6: 2400 movs r4, #0
|
|||
|
|
80007b8: e768 b.n 800068c <__aeabi_fdiv+0x138>
|
|||
|
|
80007ba: 2301 movs r3, #1
|
|||
|
|
80007bc: 9a01 ldr r2, [sp, #4]
|
|||
|
|
80007be: 01a4 lsls r4, r4, #6
|
|||
|
|
80007c0: 0a64 lsrs r4, r4, #9
|
|||
|
|
80007c2: 4013 ands r3, r2
|
|||
|
|
80007c4: 2100 movs r1, #0
|
|||
|
|
80007c6: e761 b.n 800068c <__aeabi_fdiv+0x138>
|
|||
|
|
80007c8: 2380 movs r3, #128 ; 0x80
|
|||
|
|
80007ca: 03db lsls r3, r3, #15
|
|||
|
|
80007cc: 431c orrs r4, r3
|
|||
|
|
80007ce: 0264 lsls r4, r4, #9
|
|||
|
|
80007d0: 0a64 lsrs r4, r4, #9
|
|||
|
|
80007d2: 4653 mov r3, sl
|
|||
|
|
80007d4: 21ff movs r1, #255 ; 0xff
|
|||
|
|
80007d6: e759 b.n 800068c <__aeabi_fdiv+0x138>
|
|||
|
|
80007d8: 08006fe8 .word 0x08006fe8
|
|||
|
|
80007dc: 08007028 .word 0x08007028
|
|||
|
|
80007e0: f7ffffff .word 0xf7ffffff
|
|||
|
|
|
|||
|
|
080007e4 <__eqsf2>:
|
|||
|
|
80007e4: b570 push {r4, r5, r6, lr}
|
|||
|
|
80007e6: 0042 lsls r2, r0, #1
|
|||
|
|
80007e8: 0245 lsls r5, r0, #9
|
|||
|
|
80007ea: 024e lsls r6, r1, #9
|
|||
|
|
80007ec: 004c lsls r4, r1, #1
|
|||
|
|
80007ee: 0fc3 lsrs r3, r0, #31
|
|||
|
|
80007f0: 0a6d lsrs r5, r5, #9
|
|||
|
|
80007f2: 0e12 lsrs r2, r2, #24
|
|||
|
|
80007f4: 0a76 lsrs r6, r6, #9
|
|||
|
|
80007f6: 0e24 lsrs r4, r4, #24
|
|||
|
|
80007f8: 0fc9 lsrs r1, r1, #31
|
|||
|
|
80007fa: 2001 movs r0, #1
|
|||
|
|
80007fc: 2aff cmp r2, #255 ; 0xff
|
|||
|
|
80007fe: d006 beq.n 800080e <__eqsf2+0x2a>
|
|||
|
|
8000800: 2cff cmp r4, #255 ; 0xff
|
|||
|
|
8000802: d003 beq.n 800080c <__eqsf2+0x28>
|
|||
|
|
8000804: 42a2 cmp r2, r4
|
|||
|
|
8000806: d101 bne.n 800080c <__eqsf2+0x28>
|
|||
|
|
8000808: 42b5 cmp r5, r6
|
|||
|
|
800080a: d006 beq.n 800081a <__eqsf2+0x36>
|
|||
|
|
800080c: bd70 pop {r4, r5, r6, pc}
|
|||
|
|
800080e: 2d00 cmp r5, #0
|
|||
|
|
8000810: d1fc bne.n 800080c <__eqsf2+0x28>
|
|||
|
|
8000812: 2cff cmp r4, #255 ; 0xff
|
|||
|
|
8000814: d1fa bne.n 800080c <__eqsf2+0x28>
|
|||
|
|
8000816: 2e00 cmp r6, #0
|
|||
|
|
8000818: d1f8 bne.n 800080c <__eqsf2+0x28>
|
|||
|
|
800081a: 428b cmp r3, r1
|
|||
|
|
800081c: d006 beq.n 800082c <__eqsf2+0x48>
|
|||
|
|
800081e: 2001 movs r0, #1
|
|||
|
|
8000820: 2a00 cmp r2, #0
|
|||
|
|
8000822: d1f3 bne.n 800080c <__eqsf2+0x28>
|
|||
|
|
8000824: 0028 movs r0, r5
|
|||
|
|
8000826: 1e45 subs r5, r0, #1
|
|||
|
|
8000828: 41a8 sbcs r0, r5
|
|||
|
|
800082a: e7ef b.n 800080c <__eqsf2+0x28>
|
|||
|
|
800082c: 2000 movs r0, #0
|
|||
|
|
800082e: e7ed b.n 800080c <__eqsf2+0x28>
|
|||
|
|
|
|||
|
|
08000830 <__gesf2>:
|
|||
|
|
8000830: b5f0 push {r4, r5, r6, r7, lr}
|
|||
|
|
8000832: 0042 lsls r2, r0, #1
|
|||
|
|
8000834: 0245 lsls r5, r0, #9
|
|||
|
|
8000836: 024c lsls r4, r1, #9
|
|||
|
|
8000838: 0fc3 lsrs r3, r0, #31
|
|||
|
|
800083a: 0048 lsls r0, r1, #1
|
|||
|
|
800083c: 0a6d lsrs r5, r5, #9
|
|||
|
|
800083e: 0e12 lsrs r2, r2, #24
|
|||
|
|
8000840: 0a64 lsrs r4, r4, #9
|
|||
|
|
8000842: 0e00 lsrs r0, r0, #24
|
|||
|
|
8000844: 0fc9 lsrs r1, r1, #31
|
|||
|
|
8000846: 2aff cmp r2, #255 ; 0xff
|
|||
|
|
8000848: d01e beq.n 8000888 <__gesf2+0x58>
|
|||
|
|
800084a: 28ff cmp r0, #255 ; 0xff
|
|||
|
|
800084c: d021 beq.n 8000892 <__gesf2+0x62>
|
|||
|
|
800084e: 2a00 cmp r2, #0
|
|||
|
|
8000850: d10a bne.n 8000868 <__gesf2+0x38>
|
|||
|
|
8000852: 426e negs r6, r5
|
|||
|
|
8000854: 416e adcs r6, r5
|
|||
|
|
8000856: b2f6 uxtb r6, r6
|
|||
|
|
8000858: 2800 cmp r0, #0
|
|||
|
|
800085a: d10f bne.n 800087c <__gesf2+0x4c>
|
|||
|
|
800085c: 2c00 cmp r4, #0
|
|||
|
|
800085e: d10d bne.n 800087c <__gesf2+0x4c>
|
|||
|
|
8000860: 2000 movs r0, #0
|
|||
|
|
8000862: 2d00 cmp r5, #0
|
|||
|
|
8000864: d009 beq.n 800087a <__gesf2+0x4a>
|
|||
|
|
8000866: e005 b.n 8000874 <__gesf2+0x44>
|
|||
|
|
8000868: 2800 cmp r0, #0
|
|||
|
|
800086a: d101 bne.n 8000870 <__gesf2+0x40>
|
|||
|
|
800086c: 2c00 cmp r4, #0
|
|||
|
|
800086e: d001 beq.n 8000874 <__gesf2+0x44>
|
|||
|
|
8000870: 428b cmp r3, r1
|
|||
|
|
8000872: d011 beq.n 8000898 <__gesf2+0x68>
|
|||
|
|
8000874: 2101 movs r1, #1
|
|||
|
|
8000876: 4258 negs r0, r3
|
|||
|
|
8000878: 4308 orrs r0, r1
|
|||
|
|
800087a: bdf0 pop {r4, r5, r6, r7, pc}
|
|||
|
|
800087c: 2e00 cmp r6, #0
|
|||
|
|
800087e: d0f7 beq.n 8000870 <__gesf2+0x40>
|
|||
|
|
8000880: 2001 movs r0, #1
|
|||
|
|
8000882: 3901 subs r1, #1
|
|||
|
|
8000884: 4308 orrs r0, r1
|
|||
|
|
8000886: e7f8 b.n 800087a <__gesf2+0x4a>
|
|||
|
|
8000888: 2d00 cmp r5, #0
|
|||
|
|
800088a: d0de beq.n 800084a <__gesf2+0x1a>
|
|||
|
|
800088c: 2002 movs r0, #2
|
|||
|
|
800088e: 4240 negs r0, r0
|
|||
|
|
8000890: e7f3 b.n 800087a <__gesf2+0x4a>
|
|||
|
|
8000892: 2c00 cmp r4, #0
|
|||
|
|
8000894: d0db beq.n 800084e <__gesf2+0x1e>
|
|||
|
|
8000896: e7f9 b.n 800088c <__gesf2+0x5c>
|
|||
|
|
8000898: 4282 cmp r2, r0
|
|||
|
|
800089a: dceb bgt.n 8000874 <__gesf2+0x44>
|
|||
|
|
800089c: db04 blt.n 80008a8 <__gesf2+0x78>
|
|||
|
|
800089e: 42a5 cmp r5, r4
|
|||
|
|
80008a0: d8e8 bhi.n 8000874 <__gesf2+0x44>
|
|||
|
|
80008a2: 2000 movs r0, #0
|
|||
|
|
80008a4: 42a5 cmp r5, r4
|
|||
|
|
80008a6: d2e8 bcs.n 800087a <__gesf2+0x4a>
|
|||
|
|
80008a8: 2101 movs r1, #1
|
|||
|
|
80008aa: 1e58 subs r0, r3, #1
|
|||
|
|
80008ac: 4308 orrs r0, r1
|
|||
|
|
80008ae: e7e4 b.n 800087a <__gesf2+0x4a>
|
|||
|
|
|
|||
|
|
080008b0 <__lesf2>:
|
|||
|
|
80008b0: b5f0 push {r4, r5, r6, r7, lr}
|
|||
|
|
80008b2: 0042 lsls r2, r0, #1
|
|||
|
|
80008b4: 024d lsls r5, r1, #9
|
|||
|
|
80008b6: 004c lsls r4, r1, #1
|
|||
|
|
80008b8: 0246 lsls r6, r0, #9
|
|||
|
|
80008ba: 0a76 lsrs r6, r6, #9
|
|||
|
|
80008bc: 0e12 lsrs r2, r2, #24
|
|||
|
|
80008be: 0fc3 lsrs r3, r0, #31
|
|||
|
|
80008c0: 0a6d lsrs r5, r5, #9
|
|||
|
|
80008c2: 0e24 lsrs r4, r4, #24
|
|||
|
|
80008c4: 0fc9 lsrs r1, r1, #31
|
|||
|
|
80008c6: 2aff cmp r2, #255 ; 0xff
|
|||
|
|
80008c8: d016 beq.n 80008f8 <__lesf2+0x48>
|
|||
|
|
80008ca: 2cff cmp r4, #255 ; 0xff
|
|||
|
|
80008cc: d018 beq.n 8000900 <__lesf2+0x50>
|
|||
|
|
80008ce: 2a00 cmp r2, #0
|
|||
|
|
80008d0: d10a bne.n 80008e8 <__lesf2+0x38>
|
|||
|
|
80008d2: 4270 negs r0, r6
|
|||
|
|
80008d4: 4170 adcs r0, r6
|
|||
|
|
80008d6: b2c0 uxtb r0, r0
|
|||
|
|
80008d8: 2c00 cmp r4, #0
|
|||
|
|
80008da: d015 beq.n 8000908 <__lesf2+0x58>
|
|||
|
|
80008dc: 2800 cmp r0, #0
|
|||
|
|
80008de: d005 beq.n 80008ec <__lesf2+0x3c>
|
|||
|
|
80008e0: 2001 movs r0, #1
|
|||
|
|
80008e2: 3901 subs r1, #1
|
|||
|
|
80008e4: 4308 orrs r0, r1
|
|||
|
|
80008e6: bdf0 pop {r4, r5, r6, r7, pc}
|
|||
|
|
80008e8: 2c00 cmp r4, #0
|
|||
|
|
80008ea: d013 beq.n 8000914 <__lesf2+0x64>
|
|||
|
|
80008ec: 4299 cmp r1, r3
|
|||
|
|
80008ee: d014 beq.n 800091a <__lesf2+0x6a>
|
|||
|
|
80008f0: 2001 movs r0, #1
|
|||
|
|
80008f2: 425b negs r3, r3
|
|||
|
|
80008f4: 4318 orrs r0, r3
|
|||
|
|
80008f6: e7f6 b.n 80008e6 <__lesf2+0x36>
|
|||
|
|
80008f8: 2002 movs r0, #2
|
|||
|
|
80008fa: 2e00 cmp r6, #0
|
|||
|
|
80008fc: d1f3 bne.n 80008e6 <__lesf2+0x36>
|
|||
|
|
80008fe: e7e4 b.n 80008ca <__lesf2+0x1a>
|
|||
|
|
8000900: 2002 movs r0, #2
|
|||
|
|
8000902: 2d00 cmp r5, #0
|
|||
|
|
8000904: d1ef bne.n 80008e6 <__lesf2+0x36>
|
|||
|
|
8000906: e7e2 b.n 80008ce <__lesf2+0x1e>
|
|||
|
|
8000908: 2d00 cmp r5, #0
|
|||
|
|
800090a: d1e7 bne.n 80008dc <__lesf2+0x2c>
|
|||
|
|
800090c: 2000 movs r0, #0
|
|||
|
|
800090e: 2e00 cmp r6, #0
|
|||
|
|
8000910: d0e9 beq.n 80008e6 <__lesf2+0x36>
|
|||
|
|
8000912: e7ed b.n 80008f0 <__lesf2+0x40>
|
|||
|
|
8000914: 2d00 cmp r5, #0
|
|||
|
|
8000916: d1e9 bne.n 80008ec <__lesf2+0x3c>
|
|||
|
|
8000918: e7ea b.n 80008f0 <__lesf2+0x40>
|
|||
|
|
800091a: 42a2 cmp r2, r4
|
|||
|
|
800091c: dc06 bgt.n 800092c <__lesf2+0x7c>
|
|||
|
|
800091e: dbdf blt.n 80008e0 <__lesf2+0x30>
|
|||
|
|
8000920: 42ae cmp r6, r5
|
|||
|
|
8000922: d803 bhi.n 800092c <__lesf2+0x7c>
|
|||
|
|
8000924: 2000 movs r0, #0
|
|||
|
|
8000926: 42ae cmp r6, r5
|
|||
|
|
8000928: d3da bcc.n 80008e0 <__lesf2+0x30>
|
|||
|
|
800092a: e7dc b.n 80008e6 <__lesf2+0x36>
|
|||
|
|
800092c: 2001 movs r0, #1
|
|||
|
|
800092e: 4249 negs r1, r1
|
|||
|
|
8000930: 4308 orrs r0, r1
|
|||
|
|
8000932: e7d8 b.n 80008e6 <__lesf2+0x36>
|
|||
|
|
|
|||
|
|
08000934 <__aeabi_fmul>:
|
|||
|
|
8000934: b5f8 push {r3, r4, r5, r6, r7, lr}
|
|||
|
|
8000936: 4657 mov r7, sl
|
|||
|
|
8000938: 464e mov r6, r9
|
|||
|
|
800093a: 4645 mov r5, r8
|
|||
|
|
800093c: 46de mov lr, fp
|
|||
|
|
800093e: b5e0 push {r5, r6, r7, lr}
|
|||
|
|
8000940: 0247 lsls r7, r0, #9
|
|||
|
|
8000942: 0046 lsls r6, r0, #1
|
|||
|
|
8000944: 4688 mov r8, r1
|
|||
|
|
8000946: 0a7f lsrs r7, r7, #9
|
|||
|
|
8000948: 0e36 lsrs r6, r6, #24
|
|||
|
|
800094a: 0fc4 lsrs r4, r0, #31
|
|||
|
|
800094c: 2e00 cmp r6, #0
|
|||
|
|
800094e: d047 beq.n 80009e0 <__aeabi_fmul+0xac>
|
|||
|
|
8000950: 2eff cmp r6, #255 ; 0xff
|
|||
|
|
8000952: d024 beq.n 800099e <__aeabi_fmul+0x6a>
|
|||
|
|
8000954: 00fb lsls r3, r7, #3
|
|||
|
|
8000956: 2780 movs r7, #128 ; 0x80
|
|||
|
|
8000958: 04ff lsls r7, r7, #19
|
|||
|
|
800095a: 431f orrs r7, r3
|
|||
|
|
800095c: 2300 movs r3, #0
|
|||
|
|
800095e: 4699 mov r9, r3
|
|||
|
|
8000960: 469a mov sl, r3
|
|||
|
|
8000962: 3e7f subs r6, #127 ; 0x7f
|
|||
|
|
8000964: 4643 mov r3, r8
|
|||
|
|
8000966: 025d lsls r5, r3, #9
|
|||
|
|
8000968: 0058 lsls r0, r3, #1
|
|||
|
|
800096a: 0fdb lsrs r3, r3, #31
|
|||
|
|
800096c: 0a6d lsrs r5, r5, #9
|
|||
|
|
800096e: 0e00 lsrs r0, r0, #24
|
|||
|
|
8000970: 4698 mov r8, r3
|
|||
|
|
8000972: d043 beq.n 80009fc <__aeabi_fmul+0xc8>
|
|||
|
|
8000974: 28ff cmp r0, #255 ; 0xff
|
|||
|
|
8000976: d03b beq.n 80009f0 <__aeabi_fmul+0xbc>
|
|||
|
|
8000978: 00eb lsls r3, r5, #3
|
|||
|
|
800097a: 2580 movs r5, #128 ; 0x80
|
|||
|
|
800097c: 2200 movs r2, #0
|
|||
|
|
800097e: 04ed lsls r5, r5, #19
|
|||
|
|
8000980: 431d orrs r5, r3
|
|||
|
|
8000982: 387f subs r0, #127 ; 0x7f
|
|||
|
|
8000984: 1836 adds r6, r6, r0
|
|||
|
|
8000986: 1c73 adds r3, r6, #1
|
|||
|
|
8000988: 4641 mov r1, r8
|
|||
|
|
800098a: 469b mov fp, r3
|
|||
|
|
800098c: 464b mov r3, r9
|
|||
|
|
800098e: 4061 eors r1, r4
|
|||
|
|
8000990: 4313 orrs r3, r2
|
|||
|
|
8000992: 2b0f cmp r3, #15
|
|||
|
|
8000994: d864 bhi.n 8000a60 <__aeabi_fmul+0x12c>
|
|||
|
|
8000996: 4875 ldr r0, [pc, #468] ; (8000b6c <__aeabi_fmul+0x238>)
|
|||
|
|
8000998: 009b lsls r3, r3, #2
|
|||
|
|
800099a: 58c3 ldr r3, [r0, r3]
|
|||
|
|
800099c: 469f mov pc, r3
|
|||
|
|
800099e: 2f00 cmp r7, #0
|
|||
|
|
80009a0: d142 bne.n 8000a28 <__aeabi_fmul+0xf4>
|
|||
|
|
80009a2: 2308 movs r3, #8
|
|||
|
|
80009a4: 4699 mov r9, r3
|
|||
|
|
80009a6: 3b06 subs r3, #6
|
|||
|
|
80009a8: 26ff movs r6, #255 ; 0xff
|
|||
|
|
80009aa: 469a mov sl, r3
|
|||
|
|
80009ac: e7da b.n 8000964 <__aeabi_fmul+0x30>
|
|||
|
|
80009ae: 4641 mov r1, r8
|
|||
|
|
80009b0: 2a02 cmp r2, #2
|
|||
|
|
80009b2: d028 beq.n 8000a06 <__aeabi_fmul+0xd2>
|
|||
|
|
80009b4: 2a03 cmp r2, #3
|
|||
|
|
80009b6: d100 bne.n 80009ba <__aeabi_fmul+0x86>
|
|||
|
|
80009b8: e0ce b.n 8000b58 <__aeabi_fmul+0x224>
|
|||
|
|
80009ba: 2a01 cmp r2, #1
|
|||
|
|
80009bc: d000 beq.n 80009c0 <__aeabi_fmul+0x8c>
|
|||
|
|
80009be: e0ac b.n 8000b1a <__aeabi_fmul+0x1e6>
|
|||
|
|
80009c0: 4011 ands r1, r2
|
|||
|
|
80009c2: 2000 movs r0, #0
|
|||
|
|
80009c4: 2200 movs r2, #0
|
|||
|
|
80009c6: b2cc uxtb r4, r1
|
|||
|
|
80009c8: 0240 lsls r0, r0, #9
|
|||
|
|
80009ca: 05d2 lsls r2, r2, #23
|
|||
|
|
80009cc: 0a40 lsrs r0, r0, #9
|
|||
|
|
80009ce: 07e4 lsls r4, r4, #31
|
|||
|
|
80009d0: 4310 orrs r0, r2
|
|||
|
|
80009d2: 4320 orrs r0, r4
|
|||
|
|
80009d4: bc3c pop {r2, r3, r4, r5}
|
|||
|
|
80009d6: 4690 mov r8, r2
|
|||
|
|
80009d8: 4699 mov r9, r3
|
|||
|
|
80009da: 46a2 mov sl, r4
|
|||
|
|
80009dc: 46ab mov fp, r5
|
|||
|
|
80009de: bdf8 pop {r3, r4, r5, r6, r7, pc}
|
|||
|
|
80009e0: 2f00 cmp r7, #0
|
|||
|
|
80009e2: d115 bne.n 8000a10 <__aeabi_fmul+0xdc>
|
|||
|
|
80009e4: 2304 movs r3, #4
|
|||
|
|
80009e6: 4699 mov r9, r3
|
|||
|
|
80009e8: 3b03 subs r3, #3
|
|||
|
|
80009ea: 2600 movs r6, #0
|
|||
|
|
80009ec: 469a mov sl, r3
|
|||
|
|
80009ee: e7b9 b.n 8000964 <__aeabi_fmul+0x30>
|
|||
|
|
80009f0: 20ff movs r0, #255 ; 0xff
|
|||
|
|
80009f2: 2202 movs r2, #2
|
|||
|
|
80009f4: 2d00 cmp r5, #0
|
|||
|
|
80009f6: d0c5 beq.n 8000984 <__aeabi_fmul+0x50>
|
|||
|
|
80009f8: 2203 movs r2, #3
|
|||
|
|
80009fa: e7c3 b.n 8000984 <__aeabi_fmul+0x50>
|
|||
|
|
80009fc: 2d00 cmp r5, #0
|
|||
|
|
80009fe: d119 bne.n 8000a34 <__aeabi_fmul+0x100>
|
|||
|
|
8000a00: 2000 movs r0, #0
|
|||
|
|
8000a02: 2201 movs r2, #1
|
|||
|
|
8000a04: e7be b.n 8000984 <__aeabi_fmul+0x50>
|
|||
|
|
8000a06: 2401 movs r4, #1
|
|||
|
|
8000a08: 22ff movs r2, #255 ; 0xff
|
|||
|
|
8000a0a: 400c ands r4, r1
|
|||
|
|
8000a0c: 2000 movs r0, #0
|
|||
|
|
8000a0e: e7db b.n 80009c8 <__aeabi_fmul+0x94>
|
|||
|
|
8000a10: 0038 movs r0, r7
|
|||
|
|
8000a12: f000 fc03 bl 800121c <__clzsi2>
|
|||
|
|
8000a16: 2676 movs r6, #118 ; 0x76
|
|||
|
|
8000a18: 1f43 subs r3, r0, #5
|
|||
|
|
8000a1a: 409f lsls r7, r3
|
|||
|
|
8000a1c: 2300 movs r3, #0
|
|||
|
|
8000a1e: 4276 negs r6, r6
|
|||
|
|
8000a20: 1a36 subs r6, r6, r0
|
|||
|
|
8000a22: 4699 mov r9, r3
|
|||
|
|
8000a24: 469a mov sl, r3
|
|||
|
|
8000a26: e79d b.n 8000964 <__aeabi_fmul+0x30>
|
|||
|
|
8000a28: 230c movs r3, #12
|
|||
|
|
8000a2a: 4699 mov r9, r3
|
|||
|
|
8000a2c: 3b09 subs r3, #9
|
|||
|
|
8000a2e: 26ff movs r6, #255 ; 0xff
|
|||
|
|
8000a30: 469a mov sl, r3
|
|||
|
|
8000a32: e797 b.n 8000964 <__aeabi_fmul+0x30>
|
|||
|
|
8000a34: 0028 movs r0, r5
|
|||
|
|
8000a36: f000 fbf1 bl 800121c <__clzsi2>
|
|||
|
|
8000a3a: 1f43 subs r3, r0, #5
|
|||
|
|
8000a3c: 409d lsls r5, r3
|
|||
|
|
8000a3e: 2376 movs r3, #118 ; 0x76
|
|||
|
|
8000a40: 425b negs r3, r3
|
|||
|
|
8000a42: 1a18 subs r0, r3, r0
|
|||
|
|
8000a44: 2200 movs r2, #0
|
|||
|
|
8000a46: e79d b.n 8000984 <__aeabi_fmul+0x50>
|
|||
|
|
8000a48: 2080 movs r0, #128 ; 0x80
|
|||
|
|
8000a4a: 2400 movs r4, #0
|
|||
|
|
8000a4c: 03c0 lsls r0, r0, #15
|
|||
|
|
8000a4e: 22ff movs r2, #255 ; 0xff
|
|||
|
|
8000a50: e7ba b.n 80009c8 <__aeabi_fmul+0x94>
|
|||
|
|
8000a52: 003d movs r5, r7
|
|||
|
|
8000a54: 4652 mov r2, sl
|
|||
|
|
8000a56: e7ab b.n 80009b0 <__aeabi_fmul+0x7c>
|
|||
|
|
8000a58: 003d movs r5, r7
|
|||
|
|
8000a5a: 0021 movs r1, r4
|
|||
|
|
8000a5c: 4652 mov r2, sl
|
|||
|
|
8000a5e: e7a7 b.n 80009b0 <__aeabi_fmul+0x7c>
|
|||
|
|
8000a60: 0c3b lsrs r3, r7, #16
|
|||
|
|
8000a62: 469c mov ip, r3
|
|||
|
|
8000a64: 042a lsls r2, r5, #16
|
|||
|
|
8000a66: 0c12 lsrs r2, r2, #16
|
|||
|
|
8000a68: 0c2b lsrs r3, r5, #16
|
|||
|
|
8000a6a: 0014 movs r4, r2
|
|||
|
|
8000a6c: 4660 mov r0, ip
|
|||
|
|
8000a6e: 4665 mov r5, ip
|
|||
|
|
8000a70: 043f lsls r7, r7, #16
|
|||
|
|
8000a72: 0c3f lsrs r7, r7, #16
|
|||
|
|
8000a74: 437c muls r4, r7
|
|||
|
|
8000a76: 4342 muls r2, r0
|
|||
|
|
8000a78: 435d muls r5, r3
|
|||
|
|
8000a7a: 437b muls r3, r7
|
|||
|
|
8000a7c: 0c27 lsrs r7, r4, #16
|
|||
|
|
8000a7e: 189b adds r3, r3, r2
|
|||
|
|
8000a80: 18ff adds r7, r7, r3
|
|||
|
|
8000a82: 42ba cmp r2, r7
|
|||
|
|
8000a84: d903 bls.n 8000a8e <__aeabi_fmul+0x15a>
|
|||
|
|
8000a86: 2380 movs r3, #128 ; 0x80
|
|||
|
|
8000a88: 025b lsls r3, r3, #9
|
|||
|
|
8000a8a: 469c mov ip, r3
|
|||
|
|
8000a8c: 4465 add r5, ip
|
|||
|
|
8000a8e: 0424 lsls r4, r4, #16
|
|||
|
|
8000a90: 043a lsls r2, r7, #16
|
|||
|
|
8000a92: 0c24 lsrs r4, r4, #16
|
|||
|
|
8000a94: 1912 adds r2, r2, r4
|
|||
|
|
8000a96: 0193 lsls r3, r2, #6
|
|||
|
|
8000a98: 1e5c subs r4, r3, #1
|
|||
|
|
8000a9a: 41a3 sbcs r3, r4
|
|||
|
|
8000a9c: 0c3f lsrs r7, r7, #16
|
|||
|
|
8000a9e: 0e92 lsrs r2, r2, #26
|
|||
|
|
8000aa0: 197d adds r5, r7, r5
|
|||
|
|
8000aa2: 431a orrs r2, r3
|
|||
|
|
8000aa4: 01ad lsls r5, r5, #6
|
|||
|
|
8000aa6: 4315 orrs r5, r2
|
|||
|
|
8000aa8: 012b lsls r3, r5, #4
|
|||
|
|
8000aaa: d504 bpl.n 8000ab6 <__aeabi_fmul+0x182>
|
|||
|
|
8000aac: 2301 movs r3, #1
|
|||
|
|
8000aae: 465e mov r6, fp
|
|||
|
|
8000ab0: 086a lsrs r2, r5, #1
|
|||
|
|
8000ab2: 401d ands r5, r3
|
|||
|
|
8000ab4: 4315 orrs r5, r2
|
|||
|
|
8000ab6: 0032 movs r2, r6
|
|||
|
|
8000ab8: 327f adds r2, #127 ; 0x7f
|
|||
|
|
8000aba: 2a00 cmp r2, #0
|
|||
|
|
8000abc: dd25 ble.n 8000b0a <__aeabi_fmul+0x1d6>
|
|||
|
|
8000abe: 076b lsls r3, r5, #29
|
|||
|
|
8000ac0: d004 beq.n 8000acc <__aeabi_fmul+0x198>
|
|||
|
|
8000ac2: 230f movs r3, #15
|
|||
|
|
8000ac4: 402b ands r3, r5
|
|||
|
|
8000ac6: 2b04 cmp r3, #4
|
|||
|
|
8000ac8: d000 beq.n 8000acc <__aeabi_fmul+0x198>
|
|||
|
|
8000aca: 3504 adds r5, #4
|
|||
|
|
8000acc: 012b lsls r3, r5, #4
|
|||
|
|
8000ace: d503 bpl.n 8000ad8 <__aeabi_fmul+0x1a4>
|
|||
|
|
8000ad0: 0032 movs r2, r6
|
|||
|
|
8000ad2: 4b27 ldr r3, [pc, #156] ; (8000b70 <__aeabi_fmul+0x23c>)
|
|||
|
|
8000ad4: 3280 adds r2, #128 ; 0x80
|
|||
|
|
8000ad6: 401d ands r5, r3
|
|||
|
|
8000ad8: 2afe cmp r2, #254 ; 0xfe
|
|||
|
|
8000ada: dc94 bgt.n 8000a06 <__aeabi_fmul+0xd2>
|
|||
|
|
8000adc: 2401 movs r4, #1
|
|||
|
|
8000ade: 01a8 lsls r0, r5, #6
|
|||
|
|
8000ae0: 0a40 lsrs r0, r0, #9
|
|||
|
|
8000ae2: b2d2 uxtb r2, r2
|
|||
|
|
8000ae4: 400c ands r4, r1
|
|||
|
|
8000ae6: e76f b.n 80009c8 <__aeabi_fmul+0x94>
|
|||
|
|
8000ae8: 2080 movs r0, #128 ; 0x80
|
|||
|
|
8000aea: 03c0 lsls r0, r0, #15
|
|||
|
|
8000aec: 4207 tst r7, r0
|
|||
|
|
8000aee: d007 beq.n 8000b00 <__aeabi_fmul+0x1cc>
|
|||
|
|
8000af0: 4205 tst r5, r0
|
|||
|
|
8000af2: d105 bne.n 8000b00 <__aeabi_fmul+0x1cc>
|
|||
|
|
8000af4: 4328 orrs r0, r5
|
|||
|
|
8000af6: 0240 lsls r0, r0, #9
|
|||
|
|
8000af8: 0a40 lsrs r0, r0, #9
|
|||
|
|
8000afa: 4644 mov r4, r8
|
|||
|
|
8000afc: 22ff movs r2, #255 ; 0xff
|
|||
|
|
8000afe: e763 b.n 80009c8 <__aeabi_fmul+0x94>
|
|||
|
|
8000b00: 4338 orrs r0, r7
|
|||
|
|
8000b02: 0240 lsls r0, r0, #9
|
|||
|
|
8000b04: 0a40 lsrs r0, r0, #9
|
|||
|
|
8000b06: 22ff movs r2, #255 ; 0xff
|
|||
|
|
8000b08: e75e b.n 80009c8 <__aeabi_fmul+0x94>
|
|||
|
|
8000b0a: 2401 movs r4, #1
|
|||
|
|
8000b0c: 1aa3 subs r3, r4, r2
|
|||
|
|
8000b0e: 2b1b cmp r3, #27
|
|||
|
|
8000b10: dd05 ble.n 8000b1e <__aeabi_fmul+0x1ea>
|
|||
|
|
8000b12: 400c ands r4, r1
|
|||
|
|
8000b14: 2200 movs r2, #0
|
|||
|
|
8000b16: 2000 movs r0, #0
|
|||
|
|
8000b18: e756 b.n 80009c8 <__aeabi_fmul+0x94>
|
|||
|
|
8000b1a: 465e mov r6, fp
|
|||
|
|
8000b1c: e7cb b.n 8000ab6 <__aeabi_fmul+0x182>
|
|||
|
|
8000b1e: 002a movs r2, r5
|
|||
|
|
8000b20: 2020 movs r0, #32
|
|||
|
|
8000b22: 40da lsrs r2, r3
|
|||
|
|
8000b24: 1ac3 subs r3, r0, r3
|
|||
|
|
8000b26: 409d lsls r5, r3
|
|||
|
|
8000b28: 002b movs r3, r5
|
|||
|
|
8000b2a: 1e5d subs r5, r3, #1
|
|||
|
|
8000b2c: 41ab sbcs r3, r5
|
|||
|
|
8000b2e: 4313 orrs r3, r2
|
|||
|
|
8000b30: 075a lsls r2, r3, #29
|
|||
|
|
8000b32: d004 beq.n 8000b3e <__aeabi_fmul+0x20a>
|
|||
|
|
8000b34: 220f movs r2, #15
|
|||
|
|
8000b36: 401a ands r2, r3
|
|||
|
|
8000b38: 2a04 cmp r2, #4
|
|||
|
|
8000b3a: d000 beq.n 8000b3e <__aeabi_fmul+0x20a>
|
|||
|
|
8000b3c: 3304 adds r3, #4
|
|||
|
|
8000b3e: 015a lsls r2, r3, #5
|
|||
|
|
8000b40: d504 bpl.n 8000b4c <__aeabi_fmul+0x218>
|
|||
|
|
8000b42: 2401 movs r4, #1
|
|||
|
|
8000b44: 2201 movs r2, #1
|
|||
|
|
8000b46: 400c ands r4, r1
|
|||
|
|
8000b48: 2000 movs r0, #0
|
|||
|
|
8000b4a: e73d b.n 80009c8 <__aeabi_fmul+0x94>
|
|||
|
|
8000b4c: 2401 movs r4, #1
|
|||
|
|
8000b4e: 019b lsls r3, r3, #6
|
|||
|
|
8000b50: 0a58 lsrs r0, r3, #9
|
|||
|
|
8000b52: 400c ands r4, r1
|
|||
|
|
8000b54: 2200 movs r2, #0
|
|||
|
|
8000b56: e737 b.n 80009c8 <__aeabi_fmul+0x94>
|
|||
|
|
8000b58: 2080 movs r0, #128 ; 0x80
|
|||
|
|
8000b5a: 2401 movs r4, #1
|
|||
|
|
8000b5c: 03c0 lsls r0, r0, #15
|
|||
|
|
8000b5e: 4328 orrs r0, r5
|
|||
|
|
8000b60: 0240 lsls r0, r0, #9
|
|||
|
|
8000b62: 0a40 lsrs r0, r0, #9
|
|||
|
|
8000b64: 400c ands r4, r1
|
|||
|
|
8000b66: 22ff movs r2, #255 ; 0xff
|
|||
|
|
8000b68: e72e b.n 80009c8 <__aeabi_fmul+0x94>
|
|||
|
|
8000b6a: 46c0 nop ; (mov r8, r8)
|
|||
|
|
8000b6c: 08007068 .word 0x08007068
|
|||
|
|
8000b70: f7ffffff .word 0xf7ffffff
|
|||
|
|
|
|||
|
|
08000b74 <__aeabi_fsub>:
|
|||
|
|
8000b74: b5f0 push {r4, r5, r6, r7, lr}
|
|||
|
|
8000b76: 464f mov r7, r9
|
|||
|
|
8000b78: 46d6 mov lr, sl
|
|||
|
|
8000b7a: 4646 mov r6, r8
|
|||
|
|
8000b7c: 0044 lsls r4, r0, #1
|
|||
|
|
8000b7e: b5c0 push {r6, r7, lr}
|
|||
|
|
8000b80: 0fc2 lsrs r2, r0, #31
|
|||
|
|
8000b82: 0247 lsls r7, r0, #9
|
|||
|
|
8000b84: 0248 lsls r0, r1, #9
|
|||
|
|
8000b86: 0a40 lsrs r0, r0, #9
|
|||
|
|
8000b88: 4684 mov ip, r0
|
|||
|
|
8000b8a: 4666 mov r6, ip
|
|||
|
|
8000b8c: 0a7b lsrs r3, r7, #9
|
|||
|
|
8000b8e: 0048 lsls r0, r1, #1
|
|||
|
|
8000b90: 0fc9 lsrs r1, r1, #31
|
|||
|
|
8000b92: 469a mov sl, r3
|
|||
|
|
8000b94: 0e24 lsrs r4, r4, #24
|
|||
|
|
8000b96: 0015 movs r5, r2
|
|||
|
|
8000b98: 00db lsls r3, r3, #3
|
|||
|
|
8000b9a: 0e00 lsrs r0, r0, #24
|
|||
|
|
8000b9c: 4689 mov r9, r1
|
|||
|
|
8000b9e: 00f6 lsls r6, r6, #3
|
|||
|
|
8000ba0: 28ff cmp r0, #255 ; 0xff
|
|||
|
|
8000ba2: d100 bne.n 8000ba6 <__aeabi_fsub+0x32>
|
|||
|
|
8000ba4: e08f b.n 8000cc6 <__aeabi_fsub+0x152>
|
|||
|
|
8000ba6: 2101 movs r1, #1
|
|||
|
|
8000ba8: 464f mov r7, r9
|
|||
|
|
8000baa: 404f eors r7, r1
|
|||
|
|
8000bac: 0039 movs r1, r7
|
|||
|
|
8000bae: 4291 cmp r1, r2
|
|||
|
|
8000bb0: d066 beq.n 8000c80 <__aeabi_fsub+0x10c>
|
|||
|
|
8000bb2: 1a22 subs r2, r4, r0
|
|||
|
|
8000bb4: 2a00 cmp r2, #0
|
|||
|
|
8000bb6: dc00 bgt.n 8000bba <__aeabi_fsub+0x46>
|
|||
|
|
8000bb8: e09d b.n 8000cf6 <__aeabi_fsub+0x182>
|
|||
|
|
8000bba: 2800 cmp r0, #0
|
|||
|
|
8000bbc: d13d bne.n 8000c3a <__aeabi_fsub+0xc6>
|
|||
|
|
8000bbe: 2e00 cmp r6, #0
|
|||
|
|
8000bc0: d100 bne.n 8000bc4 <__aeabi_fsub+0x50>
|
|||
|
|
8000bc2: e08b b.n 8000cdc <__aeabi_fsub+0x168>
|
|||
|
|
8000bc4: 1e51 subs r1, r2, #1
|
|||
|
|
8000bc6: 2900 cmp r1, #0
|
|||
|
|
8000bc8: d000 beq.n 8000bcc <__aeabi_fsub+0x58>
|
|||
|
|
8000bca: e0b5 b.n 8000d38 <__aeabi_fsub+0x1c4>
|
|||
|
|
8000bcc: 2401 movs r4, #1
|
|||
|
|
8000bce: 1b9b subs r3, r3, r6
|
|||
|
|
8000bd0: 015a lsls r2, r3, #5
|
|||
|
|
8000bd2: d544 bpl.n 8000c5e <__aeabi_fsub+0xea>
|
|||
|
|
8000bd4: 019b lsls r3, r3, #6
|
|||
|
|
8000bd6: 099f lsrs r7, r3, #6
|
|||
|
|
8000bd8: 0038 movs r0, r7
|
|||
|
|
8000bda: f000 fb1f bl 800121c <__clzsi2>
|
|||
|
|
8000bde: 3805 subs r0, #5
|
|||
|
|
8000be0: 4087 lsls r7, r0
|
|||
|
|
8000be2: 4284 cmp r4, r0
|
|||
|
|
8000be4: dd00 ble.n 8000be8 <__aeabi_fsub+0x74>
|
|||
|
|
8000be6: e096 b.n 8000d16 <__aeabi_fsub+0x1a2>
|
|||
|
|
8000be8: 1b04 subs r4, r0, r4
|
|||
|
|
8000bea: 003a movs r2, r7
|
|||
|
|
8000bec: 2020 movs r0, #32
|
|||
|
|
8000bee: 3401 adds r4, #1
|
|||
|
|
8000bf0: 40e2 lsrs r2, r4
|
|||
|
|
8000bf2: 1b04 subs r4, r0, r4
|
|||
|
|
8000bf4: 40a7 lsls r7, r4
|
|||
|
|
8000bf6: 003b movs r3, r7
|
|||
|
|
8000bf8: 1e5f subs r7, r3, #1
|
|||
|
|
8000bfa: 41bb sbcs r3, r7
|
|||
|
|
8000bfc: 2400 movs r4, #0
|
|||
|
|
8000bfe: 4313 orrs r3, r2
|
|||
|
|
8000c00: 075a lsls r2, r3, #29
|
|||
|
|
8000c02: d004 beq.n 8000c0e <__aeabi_fsub+0x9a>
|
|||
|
|
8000c04: 220f movs r2, #15
|
|||
|
|
8000c06: 401a ands r2, r3
|
|||
|
|
8000c08: 2a04 cmp r2, #4
|
|||
|
|
8000c0a: d000 beq.n 8000c0e <__aeabi_fsub+0x9a>
|
|||
|
|
8000c0c: 3304 adds r3, #4
|
|||
|
|
8000c0e: 015a lsls r2, r3, #5
|
|||
|
|
8000c10: d527 bpl.n 8000c62 <__aeabi_fsub+0xee>
|
|||
|
|
8000c12: 3401 adds r4, #1
|
|||
|
|
8000c14: 2cff cmp r4, #255 ; 0xff
|
|||
|
|
8000c16: d100 bne.n 8000c1a <__aeabi_fsub+0xa6>
|
|||
|
|
8000c18: e079 b.n 8000d0e <__aeabi_fsub+0x19a>
|
|||
|
|
8000c1a: 2201 movs r2, #1
|
|||
|
|
8000c1c: 019b lsls r3, r3, #6
|
|||
|
|
8000c1e: 0a5b lsrs r3, r3, #9
|
|||
|
|
8000c20: b2e4 uxtb r4, r4
|
|||
|
|
8000c22: 402a ands r2, r5
|
|||
|
|
8000c24: 025b lsls r3, r3, #9
|
|||
|
|
8000c26: 05e4 lsls r4, r4, #23
|
|||
|
|
8000c28: 0a58 lsrs r0, r3, #9
|
|||
|
|
8000c2a: 07d2 lsls r2, r2, #31
|
|||
|
|
8000c2c: 4320 orrs r0, r4
|
|||
|
|
8000c2e: 4310 orrs r0, r2
|
|||
|
|
8000c30: bc1c pop {r2, r3, r4}
|
|||
|
|
8000c32: 4690 mov r8, r2
|
|||
|
|
8000c34: 4699 mov r9, r3
|
|||
|
|
8000c36: 46a2 mov sl, r4
|
|||
|
|
8000c38: bdf0 pop {r4, r5, r6, r7, pc}
|
|||
|
|
8000c3a: 2cff cmp r4, #255 ; 0xff
|
|||
|
|
8000c3c: d0e0 beq.n 8000c00 <__aeabi_fsub+0x8c>
|
|||
|
|
8000c3e: 2180 movs r1, #128 ; 0x80
|
|||
|
|
8000c40: 04c9 lsls r1, r1, #19
|
|||
|
|
8000c42: 430e orrs r6, r1
|
|||
|
|
8000c44: 2a1b cmp r2, #27
|
|||
|
|
8000c46: dc7b bgt.n 8000d40 <__aeabi_fsub+0x1cc>
|
|||
|
|
8000c48: 0031 movs r1, r6
|
|||
|
|
8000c4a: 2020 movs r0, #32
|
|||
|
|
8000c4c: 40d1 lsrs r1, r2
|
|||
|
|
8000c4e: 1a82 subs r2, r0, r2
|
|||
|
|
8000c50: 4096 lsls r6, r2
|
|||
|
|
8000c52: 1e72 subs r2, r6, #1
|
|||
|
|
8000c54: 4196 sbcs r6, r2
|
|||
|
|
8000c56: 430e orrs r6, r1
|
|||
|
|
8000c58: 1b9b subs r3, r3, r6
|
|||
|
|
8000c5a: 015a lsls r2, r3, #5
|
|||
|
|
8000c5c: d4ba bmi.n 8000bd4 <__aeabi_fsub+0x60>
|
|||
|
|
8000c5e: 075a lsls r2, r3, #29
|
|||
|
|
8000c60: d1d0 bne.n 8000c04 <__aeabi_fsub+0x90>
|
|||
|
|
8000c62: 2201 movs r2, #1
|
|||
|
|
8000c64: 08df lsrs r7, r3, #3
|
|||
|
|
8000c66: 402a ands r2, r5
|
|||
|
|
8000c68: 2cff cmp r4, #255 ; 0xff
|
|||
|
|
8000c6a: d133 bne.n 8000cd4 <__aeabi_fsub+0x160>
|
|||
|
|
8000c6c: 2f00 cmp r7, #0
|
|||
|
|
8000c6e: d100 bne.n 8000c72 <__aeabi_fsub+0xfe>
|
|||
|
|
8000c70: e0a8 b.n 8000dc4 <__aeabi_fsub+0x250>
|
|||
|
|
8000c72: 2380 movs r3, #128 ; 0x80
|
|||
|
|
8000c74: 03db lsls r3, r3, #15
|
|||
|
|
8000c76: 433b orrs r3, r7
|
|||
|
|
8000c78: 025b lsls r3, r3, #9
|
|||
|
|
8000c7a: 0a5b lsrs r3, r3, #9
|
|||
|
|
8000c7c: 24ff movs r4, #255 ; 0xff
|
|||
|
|
8000c7e: e7d1 b.n 8000c24 <__aeabi_fsub+0xb0>
|
|||
|
|
8000c80: 1a21 subs r1, r4, r0
|
|||
|
|
8000c82: 2900 cmp r1, #0
|
|||
|
|
8000c84: dd4c ble.n 8000d20 <__aeabi_fsub+0x1ac>
|
|||
|
|
8000c86: 2800 cmp r0, #0
|
|||
|
|
8000c88: d02a beq.n 8000ce0 <__aeabi_fsub+0x16c>
|
|||
|
|
8000c8a: 2cff cmp r4, #255 ; 0xff
|
|||
|
|
8000c8c: d0b8 beq.n 8000c00 <__aeabi_fsub+0x8c>
|
|||
|
|
8000c8e: 2080 movs r0, #128 ; 0x80
|
|||
|
|
8000c90: 04c0 lsls r0, r0, #19
|
|||
|
|
8000c92: 4306 orrs r6, r0
|
|||
|
|
8000c94: 291b cmp r1, #27
|
|||
|
|
8000c96: dd00 ble.n 8000c9a <__aeabi_fsub+0x126>
|
|||
|
|
8000c98: e0af b.n 8000dfa <__aeabi_fsub+0x286>
|
|||
|
|
8000c9a: 0030 movs r0, r6
|
|||
|
|
8000c9c: 2720 movs r7, #32
|
|||
|
|
8000c9e: 40c8 lsrs r0, r1
|
|||
|
|
8000ca0: 1a79 subs r1, r7, r1
|
|||
|
|
8000ca2: 408e lsls r6, r1
|
|||
|
|
8000ca4: 1e71 subs r1, r6, #1
|
|||
|
|
8000ca6: 418e sbcs r6, r1
|
|||
|
|
8000ca8: 4306 orrs r6, r0
|
|||
|
|
8000caa: 199b adds r3, r3, r6
|
|||
|
|
8000cac: 0159 lsls r1, r3, #5
|
|||
|
|
8000cae: d5d6 bpl.n 8000c5e <__aeabi_fsub+0xea>
|
|||
|
|
8000cb0: 3401 adds r4, #1
|
|||
|
|
8000cb2: 2cff cmp r4, #255 ; 0xff
|
|||
|
|
8000cb4: d100 bne.n 8000cb8 <__aeabi_fsub+0x144>
|
|||
|
|
8000cb6: e085 b.n 8000dc4 <__aeabi_fsub+0x250>
|
|||
|
|
8000cb8: 2201 movs r2, #1
|
|||
|
|
8000cba: 497a ldr r1, [pc, #488] ; (8000ea4 <__aeabi_fsub+0x330>)
|
|||
|
|
8000cbc: 401a ands r2, r3
|
|||
|
|
8000cbe: 085b lsrs r3, r3, #1
|
|||
|
|
8000cc0: 400b ands r3, r1
|
|||
|
|
8000cc2: 4313 orrs r3, r2
|
|||
|
|
8000cc4: e79c b.n 8000c00 <__aeabi_fsub+0x8c>
|
|||
|
|
8000cc6: 2e00 cmp r6, #0
|
|||
|
|
8000cc8: d000 beq.n 8000ccc <__aeabi_fsub+0x158>
|
|||
|
|
8000cca: e770 b.n 8000bae <__aeabi_fsub+0x3a>
|
|||
|
|
8000ccc: e76b b.n 8000ba6 <__aeabi_fsub+0x32>
|
|||
|
|
8000cce: 1e3b subs r3, r7, #0
|
|||
|
|
8000cd0: d1c5 bne.n 8000c5e <__aeabi_fsub+0xea>
|
|||
|
|
8000cd2: 2200 movs r2, #0
|
|||
|
|
8000cd4: 027b lsls r3, r7, #9
|
|||
|
|
8000cd6: 0a5b lsrs r3, r3, #9
|
|||
|
|
8000cd8: b2e4 uxtb r4, r4
|
|||
|
|
8000cda: e7a3 b.n 8000c24 <__aeabi_fsub+0xb0>
|
|||
|
|
8000cdc: 0014 movs r4, r2
|
|||
|
|
8000cde: e78f b.n 8000c00 <__aeabi_fsub+0x8c>
|
|||
|
|
8000ce0: 2e00 cmp r6, #0
|
|||
|
|
8000ce2: d04d beq.n 8000d80 <__aeabi_fsub+0x20c>
|
|||
|
|
8000ce4: 1e48 subs r0, r1, #1
|
|||
|
|
8000ce6: 2800 cmp r0, #0
|
|||
|
|
8000ce8: d157 bne.n 8000d9a <__aeabi_fsub+0x226>
|
|||
|
|
8000cea: 199b adds r3, r3, r6
|
|||
|
|
8000cec: 2401 movs r4, #1
|
|||
|
|
8000cee: 015a lsls r2, r3, #5
|
|||
|
|
8000cf0: d5b5 bpl.n 8000c5e <__aeabi_fsub+0xea>
|
|||
|
|
8000cf2: 2402 movs r4, #2
|
|||
|
|
8000cf4: e7e0 b.n 8000cb8 <__aeabi_fsub+0x144>
|
|||
|
|
8000cf6: 2a00 cmp r2, #0
|
|||
|
|
8000cf8: d125 bne.n 8000d46 <__aeabi_fsub+0x1d2>
|
|||
|
|
8000cfa: 1c62 adds r2, r4, #1
|
|||
|
|
8000cfc: b2d2 uxtb r2, r2
|
|||
|
|
8000cfe: 2a01 cmp r2, #1
|
|||
|
|
8000d00: dd72 ble.n 8000de8 <__aeabi_fsub+0x274>
|
|||
|
|
8000d02: 1b9f subs r7, r3, r6
|
|||
|
|
8000d04: 017a lsls r2, r7, #5
|
|||
|
|
8000d06: d535 bpl.n 8000d74 <__aeabi_fsub+0x200>
|
|||
|
|
8000d08: 1af7 subs r7, r6, r3
|
|||
|
|
8000d0a: 000d movs r5, r1
|
|||
|
|
8000d0c: e764 b.n 8000bd8 <__aeabi_fsub+0x64>
|
|||
|
|
8000d0e: 2201 movs r2, #1
|
|||
|
|
8000d10: 2300 movs r3, #0
|
|||
|
|
8000d12: 402a ands r2, r5
|
|||
|
|
8000d14: e786 b.n 8000c24 <__aeabi_fsub+0xb0>
|
|||
|
|
8000d16: 003b movs r3, r7
|
|||
|
|
8000d18: 4a63 ldr r2, [pc, #396] ; (8000ea8 <__aeabi_fsub+0x334>)
|
|||
|
|
8000d1a: 1a24 subs r4, r4, r0
|
|||
|
|
8000d1c: 4013 ands r3, r2
|
|||
|
|
8000d1e: e76f b.n 8000c00 <__aeabi_fsub+0x8c>
|
|||
|
|
8000d20: 2900 cmp r1, #0
|
|||
|
|
8000d22: d16c bne.n 8000dfe <__aeabi_fsub+0x28a>
|
|||
|
|
8000d24: 1c61 adds r1, r4, #1
|
|||
|
|
8000d26: b2c8 uxtb r0, r1
|
|||
|
|
8000d28: 2801 cmp r0, #1
|
|||
|
|
8000d2a: dd4e ble.n 8000dca <__aeabi_fsub+0x256>
|
|||
|
|
8000d2c: 29ff cmp r1, #255 ; 0xff
|
|||
|
|
8000d2e: d049 beq.n 8000dc4 <__aeabi_fsub+0x250>
|
|||
|
|
8000d30: 199b adds r3, r3, r6
|
|||
|
|
8000d32: 085b lsrs r3, r3, #1
|
|||
|
|
8000d34: 000c movs r4, r1
|
|||
|
|
8000d36: e763 b.n 8000c00 <__aeabi_fsub+0x8c>
|
|||
|
|
8000d38: 2aff cmp r2, #255 ; 0xff
|
|||
|
|
8000d3a: d041 beq.n 8000dc0 <__aeabi_fsub+0x24c>
|
|||
|
|
8000d3c: 000a movs r2, r1
|
|||
|
|
8000d3e: e781 b.n 8000c44 <__aeabi_fsub+0xd0>
|
|||
|
|
8000d40: 2601 movs r6, #1
|
|||
|
|
8000d42: 1b9b subs r3, r3, r6
|
|||
|
|
8000d44: e789 b.n 8000c5a <__aeabi_fsub+0xe6>
|
|||
|
|
8000d46: 2c00 cmp r4, #0
|
|||
|
|
8000d48: d01c beq.n 8000d84 <__aeabi_fsub+0x210>
|
|||
|
|
8000d4a: 28ff cmp r0, #255 ; 0xff
|
|||
|
|
8000d4c: d021 beq.n 8000d92 <__aeabi_fsub+0x21e>
|
|||
|
|
8000d4e: 2480 movs r4, #128 ; 0x80
|
|||
|
|
8000d50: 04e4 lsls r4, r4, #19
|
|||
|
|
8000d52: 4252 negs r2, r2
|
|||
|
|
8000d54: 4323 orrs r3, r4
|
|||
|
|
8000d56: 2a1b cmp r2, #27
|
|||
|
|
8000d58: dd00 ble.n 8000d5c <__aeabi_fsub+0x1e8>
|
|||
|
|
8000d5a: e096 b.n 8000e8a <__aeabi_fsub+0x316>
|
|||
|
|
8000d5c: 001c movs r4, r3
|
|||
|
|
8000d5e: 2520 movs r5, #32
|
|||
|
|
8000d60: 40d4 lsrs r4, r2
|
|||
|
|
8000d62: 1aaa subs r2, r5, r2
|
|||
|
|
8000d64: 4093 lsls r3, r2
|
|||
|
|
8000d66: 1e5a subs r2, r3, #1
|
|||
|
|
8000d68: 4193 sbcs r3, r2
|
|||
|
|
8000d6a: 4323 orrs r3, r4
|
|||
|
|
8000d6c: 1af3 subs r3, r6, r3
|
|||
|
|
8000d6e: 0004 movs r4, r0
|
|||
|
|
8000d70: 000d movs r5, r1
|
|||
|
|
8000d72: e72d b.n 8000bd0 <__aeabi_fsub+0x5c>
|
|||
|
|
8000d74: 2f00 cmp r7, #0
|
|||
|
|
8000d76: d000 beq.n 8000d7a <__aeabi_fsub+0x206>
|
|||
|
|
8000d78: e72e b.n 8000bd8 <__aeabi_fsub+0x64>
|
|||
|
|
8000d7a: 2200 movs r2, #0
|
|||
|
|
8000d7c: 2400 movs r4, #0
|
|||
|
|
8000d7e: e7a9 b.n 8000cd4 <__aeabi_fsub+0x160>
|
|||
|
|
8000d80: 000c movs r4, r1
|
|||
|
|
8000d82: e73d b.n 8000c00 <__aeabi_fsub+0x8c>
|
|||
|
|
8000d84: 2b00 cmp r3, #0
|
|||
|
|
8000d86: d058 beq.n 8000e3a <__aeabi_fsub+0x2c6>
|
|||
|
|
8000d88: 43d2 mvns r2, r2
|
|||
|
|
8000d8a: 2a00 cmp r2, #0
|
|||
|
|
8000d8c: d0ee beq.n 8000d6c <__aeabi_fsub+0x1f8>
|
|||
|
|
8000d8e: 28ff cmp r0, #255 ; 0xff
|
|||
|
|
8000d90: d1e1 bne.n 8000d56 <__aeabi_fsub+0x1e2>
|
|||
|
|
8000d92: 0033 movs r3, r6
|
|||
|
|
8000d94: 24ff movs r4, #255 ; 0xff
|
|||
|
|
8000d96: 000d movs r5, r1
|
|||
|
|
8000d98: e732 b.n 8000c00 <__aeabi_fsub+0x8c>
|
|||
|
|
8000d9a: 29ff cmp r1, #255 ; 0xff
|
|||
|
|
8000d9c: d010 beq.n 8000dc0 <__aeabi_fsub+0x24c>
|
|||
|
|
8000d9e: 0001 movs r1, r0
|
|||
|
|
8000da0: e778 b.n 8000c94 <__aeabi_fsub+0x120>
|
|||
|
|
8000da2: 2b00 cmp r3, #0
|
|||
|
|
8000da4: d06e beq.n 8000e84 <__aeabi_fsub+0x310>
|
|||
|
|
8000da6: 24ff movs r4, #255 ; 0xff
|
|||
|
|
8000da8: 2e00 cmp r6, #0
|
|||
|
|
8000daa: d100 bne.n 8000dae <__aeabi_fsub+0x23a>
|
|||
|
|
8000dac: e728 b.n 8000c00 <__aeabi_fsub+0x8c>
|
|||
|
|
8000dae: 2280 movs r2, #128 ; 0x80
|
|||
|
|
8000db0: 4651 mov r1, sl
|
|||
|
|
8000db2: 03d2 lsls r2, r2, #15
|
|||
|
|
8000db4: 4211 tst r1, r2
|
|||
|
|
8000db6: d003 beq.n 8000dc0 <__aeabi_fsub+0x24c>
|
|||
|
|
8000db8: 4661 mov r1, ip
|
|||
|
|
8000dba: 4211 tst r1, r2
|
|||
|
|
8000dbc: d100 bne.n 8000dc0 <__aeabi_fsub+0x24c>
|
|||
|
|
8000dbe: 0033 movs r3, r6
|
|||
|
|
8000dc0: 24ff movs r4, #255 ; 0xff
|
|||
|
|
8000dc2: e71d b.n 8000c00 <__aeabi_fsub+0x8c>
|
|||
|
|
8000dc4: 24ff movs r4, #255 ; 0xff
|
|||
|
|
8000dc6: 2300 movs r3, #0
|
|||
|
|
8000dc8: e72c b.n 8000c24 <__aeabi_fsub+0xb0>
|
|||
|
|
8000dca: 2c00 cmp r4, #0
|
|||
|
|
8000dcc: d1e9 bne.n 8000da2 <__aeabi_fsub+0x22e>
|
|||
|
|
8000dce: 2b00 cmp r3, #0
|
|||
|
|
8000dd0: d063 beq.n 8000e9a <__aeabi_fsub+0x326>
|
|||
|
|
8000dd2: 2e00 cmp r6, #0
|
|||
|
|
8000dd4: d100 bne.n 8000dd8 <__aeabi_fsub+0x264>
|
|||
|
|
8000dd6: e713 b.n 8000c00 <__aeabi_fsub+0x8c>
|
|||
|
|
8000dd8: 199b adds r3, r3, r6
|
|||
|
|
8000dda: 015a lsls r2, r3, #5
|
|||
|
|
8000ddc: d400 bmi.n 8000de0 <__aeabi_fsub+0x26c>
|
|||
|
|
8000dde: e73e b.n 8000c5e <__aeabi_fsub+0xea>
|
|||
|
|
8000de0: 4a31 ldr r2, [pc, #196] ; (8000ea8 <__aeabi_fsub+0x334>)
|
|||
|
|
8000de2: 000c movs r4, r1
|
|||
|
|
8000de4: 4013 ands r3, r2
|
|||
|
|
8000de6: e70b b.n 8000c00 <__aeabi_fsub+0x8c>
|
|||
|
|
8000de8: 2c00 cmp r4, #0
|
|||
|
|
8000dea: d11e bne.n 8000e2a <__aeabi_fsub+0x2b6>
|
|||
|
|
8000dec: 2b00 cmp r3, #0
|
|||
|
|
8000dee: d12f bne.n 8000e50 <__aeabi_fsub+0x2dc>
|
|||
|
|
8000df0: 2e00 cmp r6, #0
|
|||
|
|
8000df2: d04f beq.n 8000e94 <__aeabi_fsub+0x320>
|
|||
|
|
8000df4: 0033 movs r3, r6
|
|||
|
|
8000df6: 000d movs r5, r1
|
|||
|
|
8000df8: e702 b.n 8000c00 <__aeabi_fsub+0x8c>
|
|||
|
|
8000dfa: 2601 movs r6, #1
|
|||
|
|
8000dfc: e755 b.n 8000caa <__aeabi_fsub+0x136>
|
|||
|
|
8000dfe: 2c00 cmp r4, #0
|
|||
|
|
8000e00: d11f bne.n 8000e42 <__aeabi_fsub+0x2ce>
|
|||
|
|
8000e02: 2b00 cmp r3, #0
|
|||
|
|
8000e04: d043 beq.n 8000e8e <__aeabi_fsub+0x31a>
|
|||
|
|
8000e06: 43c9 mvns r1, r1
|
|||
|
|
8000e08: 2900 cmp r1, #0
|
|||
|
|
8000e0a: d00b beq.n 8000e24 <__aeabi_fsub+0x2b0>
|
|||
|
|
8000e0c: 28ff cmp r0, #255 ; 0xff
|
|||
|
|
8000e0e: d039 beq.n 8000e84 <__aeabi_fsub+0x310>
|
|||
|
|
8000e10: 291b cmp r1, #27
|
|||
|
|
8000e12: dc44 bgt.n 8000e9e <__aeabi_fsub+0x32a>
|
|||
|
|
8000e14: 001c movs r4, r3
|
|||
|
|
8000e16: 2720 movs r7, #32
|
|||
|
|
8000e18: 40cc lsrs r4, r1
|
|||
|
|
8000e1a: 1a79 subs r1, r7, r1
|
|||
|
|
8000e1c: 408b lsls r3, r1
|
|||
|
|
8000e1e: 1e59 subs r1, r3, #1
|
|||
|
|
8000e20: 418b sbcs r3, r1
|
|||
|
|
8000e22: 4323 orrs r3, r4
|
|||
|
|
8000e24: 199b adds r3, r3, r6
|
|||
|
|
8000e26: 0004 movs r4, r0
|
|||
|
|
8000e28: e740 b.n 8000cac <__aeabi_fsub+0x138>
|
|||
|
|
8000e2a: 2b00 cmp r3, #0
|
|||
|
|
8000e2c: d11a bne.n 8000e64 <__aeabi_fsub+0x2f0>
|
|||
|
|
8000e2e: 2e00 cmp r6, #0
|
|||
|
|
8000e30: d124 bne.n 8000e7c <__aeabi_fsub+0x308>
|
|||
|
|
8000e32: 2780 movs r7, #128 ; 0x80
|
|||
|
|
8000e34: 2200 movs r2, #0
|
|||
|
|
8000e36: 03ff lsls r7, r7, #15
|
|||
|
|
8000e38: e71b b.n 8000c72 <__aeabi_fsub+0xfe>
|
|||
|
|
8000e3a: 0033 movs r3, r6
|
|||
|
|
8000e3c: 0004 movs r4, r0
|
|||
|
|
8000e3e: 000d movs r5, r1
|
|||
|
|
8000e40: e6de b.n 8000c00 <__aeabi_fsub+0x8c>
|
|||
|
|
8000e42: 28ff cmp r0, #255 ; 0xff
|
|||
|
|
8000e44: d01e beq.n 8000e84 <__aeabi_fsub+0x310>
|
|||
|
|
8000e46: 2480 movs r4, #128 ; 0x80
|
|||
|
|
8000e48: 04e4 lsls r4, r4, #19
|
|||
|
|
8000e4a: 4249 negs r1, r1
|
|||
|
|
8000e4c: 4323 orrs r3, r4
|
|||
|
|
8000e4e: e7df b.n 8000e10 <__aeabi_fsub+0x29c>
|
|||
|
|
8000e50: 2e00 cmp r6, #0
|
|||
|
|
8000e52: d100 bne.n 8000e56 <__aeabi_fsub+0x2e2>
|
|||
|
|
8000e54: e6d4 b.n 8000c00 <__aeabi_fsub+0x8c>
|
|||
|
|
8000e56: 1b9f subs r7, r3, r6
|
|||
|
|
8000e58: 017a lsls r2, r7, #5
|
|||
|
|
8000e5a: d400 bmi.n 8000e5e <__aeabi_fsub+0x2ea>
|
|||
|
|
8000e5c: e737 b.n 8000cce <__aeabi_fsub+0x15a>
|
|||
|
|
8000e5e: 1af3 subs r3, r6, r3
|
|||
|
|
8000e60: 000d movs r5, r1
|
|||
|
|
8000e62: e6cd b.n 8000c00 <__aeabi_fsub+0x8c>
|
|||
|
|
8000e64: 24ff movs r4, #255 ; 0xff
|
|||
|
|
8000e66: 2e00 cmp r6, #0
|
|||
|
|
8000e68: d100 bne.n 8000e6c <__aeabi_fsub+0x2f8>
|
|||
|
|
8000e6a: e6c9 b.n 8000c00 <__aeabi_fsub+0x8c>
|
|||
|
|
8000e6c: 2280 movs r2, #128 ; 0x80
|
|||
|
|
8000e6e: 4650 mov r0, sl
|
|||
|
|
8000e70: 03d2 lsls r2, r2, #15
|
|||
|
|
8000e72: 4210 tst r0, r2
|
|||
|
|
8000e74: d0a4 beq.n 8000dc0 <__aeabi_fsub+0x24c>
|
|||
|
|
8000e76: 4660 mov r0, ip
|
|||
|
|
8000e78: 4210 tst r0, r2
|
|||
|
|
8000e7a: d1a1 bne.n 8000dc0 <__aeabi_fsub+0x24c>
|
|||
|
|
8000e7c: 0033 movs r3, r6
|
|||
|
|
8000e7e: 000d movs r5, r1
|
|||
|
|
8000e80: 24ff movs r4, #255 ; 0xff
|
|||
|
|
8000e82: e6bd b.n 8000c00 <__aeabi_fsub+0x8c>
|
|||
|
|
8000e84: 0033 movs r3, r6
|
|||
|
|
8000e86: 24ff movs r4, #255 ; 0xff
|
|||
|
|
8000e88: e6ba b.n 8000c00 <__aeabi_fsub+0x8c>
|
|||
|
|
8000e8a: 2301 movs r3, #1
|
|||
|
|
8000e8c: e76e b.n 8000d6c <__aeabi_fsub+0x1f8>
|
|||
|
|
8000e8e: 0033 movs r3, r6
|
|||
|
|
8000e90: 0004 movs r4, r0
|
|||
|
|
8000e92: e6b5 b.n 8000c00 <__aeabi_fsub+0x8c>
|
|||
|
|
8000e94: 2700 movs r7, #0
|
|||
|
|
8000e96: 2200 movs r2, #0
|
|||
|
|
8000e98: e71c b.n 8000cd4 <__aeabi_fsub+0x160>
|
|||
|
|
8000e9a: 0033 movs r3, r6
|
|||
|
|
8000e9c: e6b0 b.n 8000c00 <__aeabi_fsub+0x8c>
|
|||
|
|
8000e9e: 2301 movs r3, #1
|
|||
|
|
8000ea0: e7c0 b.n 8000e24 <__aeabi_fsub+0x2b0>
|
|||
|
|
8000ea2: 46c0 nop ; (mov r8, r8)
|
|||
|
|
8000ea4: 7dffffff .word 0x7dffffff
|
|||
|
|
8000ea8: fbffffff .word 0xfbffffff
|
|||
|
|
|
|||
|
|
08000eac <__aeabi_f2iz>:
|
|||
|
|
8000eac: 0241 lsls r1, r0, #9
|
|||
|
|
8000eae: 0043 lsls r3, r0, #1
|
|||
|
|
8000eb0: 0fc2 lsrs r2, r0, #31
|
|||
|
|
8000eb2: 0a49 lsrs r1, r1, #9
|
|||
|
|
8000eb4: 0e1b lsrs r3, r3, #24
|
|||
|
|
8000eb6: 2000 movs r0, #0
|
|||
|
|
8000eb8: 2b7e cmp r3, #126 ; 0x7e
|
|||
|
|
8000eba: dd0d ble.n 8000ed8 <__aeabi_f2iz+0x2c>
|
|||
|
|
8000ebc: 2b9d cmp r3, #157 ; 0x9d
|
|||
|
|
8000ebe: dc0c bgt.n 8000eda <__aeabi_f2iz+0x2e>
|
|||
|
|
8000ec0: 2080 movs r0, #128 ; 0x80
|
|||
|
|
8000ec2: 0400 lsls r0, r0, #16
|
|||
|
|
8000ec4: 4301 orrs r1, r0
|
|||
|
|
8000ec6: 2b95 cmp r3, #149 ; 0x95
|
|||
|
|
8000ec8: dc0a bgt.n 8000ee0 <__aeabi_f2iz+0x34>
|
|||
|
|
8000eca: 2096 movs r0, #150 ; 0x96
|
|||
|
|
8000ecc: 1ac3 subs r3, r0, r3
|
|||
|
|
8000ece: 40d9 lsrs r1, r3
|
|||
|
|
8000ed0: 4248 negs r0, r1
|
|||
|
|
8000ed2: 2a00 cmp r2, #0
|
|||
|
|
8000ed4: d100 bne.n 8000ed8 <__aeabi_f2iz+0x2c>
|
|||
|
|
8000ed6: 0008 movs r0, r1
|
|||
|
|
8000ed8: 4770 bx lr
|
|||
|
|
8000eda: 4b03 ldr r3, [pc, #12] ; (8000ee8 <__aeabi_f2iz+0x3c>)
|
|||
|
|
8000edc: 18d0 adds r0, r2, r3
|
|||
|
|
8000ede: e7fb b.n 8000ed8 <__aeabi_f2iz+0x2c>
|
|||
|
|
8000ee0: 3b96 subs r3, #150 ; 0x96
|
|||
|
|
8000ee2: 4099 lsls r1, r3
|
|||
|
|
8000ee4: e7f4 b.n 8000ed0 <__aeabi_f2iz+0x24>
|
|||
|
|
8000ee6: 46c0 nop ; (mov r8, r8)
|
|||
|
|
8000ee8: 7fffffff .word 0x7fffffff
|
|||
|
|
|
|||
|
|
08000eec <__aeabi_ui2f>:
|
|||
|
|
8000eec: b510 push {r4, lr}
|
|||
|
|
8000eee: 1e04 subs r4, r0, #0
|
|||
|
|
8000ef0: d027 beq.n 8000f42 <__aeabi_ui2f+0x56>
|
|||
|
|
8000ef2: f000 f993 bl 800121c <__clzsi2>
|
|||
|
|
8000ef6: 239e movs r3, #158 ; 0x9e
|
|||
|
|
8000ef8: 1a1b subs r3, r3, r0
|
|||
|
|
8000efa: 2b96 cmp r3, #150 ; 0x96
|
|||
|
|
8000efc: dc0a bgt.n 8000f14 <__aeabi_ui2f+0x28>
|
|||
|
|
8000efe: 2296 movs r2, #150 ; 0x96
|
|||
|
|
8000f00: 1ad2 subs r2, r2, r3
|
|||
|
|
8000f02: 4094 lsls r4, r2
|
|||
|
|
8000f04: 0264 lsls r4, r4, #9
|
|||
|
|
8000f06: 0a64 lsrs r4, r4, #9
|
|||
|
|
8000f08: b2db uxtb r3, r3
|
|||
|
|
8000f0a: 0264 lsls r4, r4, #9
|
|||
|
|
8000f0c: 05db lsls r3, r3, #23
|
|||
|
|
8000f0e: 0a60 lsrs r0, r4, #9
|
|||
|
|
8000f10: 4318 orrs r0, r3
|
|||
|
|
8000f12: bd10 pop {r4, pc}
|
|||
|
|
8000f14: 2b99 cmp r3, #153 ; 0x99
|
|||
|
|
8000f16: dc17 bgt.n 8000f48 <__aeabi_ui2f+0x5c>
|
|||
|
|
8000f18: 2299 movs r2, #153 ; 0x99
|
|||
|
|
8000f1a: 1ad2 subs r2, r2, r3
|
|||
|
|
8000f1c: 2a00 cmp r2, #0
|
|||
|
|
8000f1e: dd27 ble.n 8000f70 <__aeabi_ui2f+0x84>
|
|||
|
|
8000f20: 4094 lsls r4, r2
|
|||
|
|
8000f22: 0022 movs r2, r4
|
|||
|
|
8000f24: 4c13 ldr r4, [pc, #76] ; (8000f74 <__aeabi_ui2f+0x88>)
|
|||
|
|
8000f26: 4014 ands r4, r2
|
|||
|
|
8000f28: 0751 lsls r1, r2, #29
|
|||
|
|
8000f2a: d004 beq.n 8000f36 <__aeabi_ui2f+0x4a>
|
|||
|
|
8000f2c: 210f movs r1, #15
|
|||
|
|
8000f2e: 400a ands r2, r1
|
|||
|
|
8000f30: 2a04 cmp r2, #4
|
|||
|
|
8000f32: d000 beq.n 8000f36 <__aeabi_ui2f+0x4a>
|
|||
|
|
8000f34: 3404 adds r4, #4
|
|||
|
|
8000f36: 0162 lsls r2, r4, #5
|
|||
|
|
8000f38: d412 bmi.n 8000f60 <__aeabi_ui2f+0x74>
|
|||
|
|
8000f3a: 01a4 lsls r4, r4, #6
|
|||
|
|
8000f3c: 0a64 lsrs r4, r4, #9
|
|||
|
|
8000f3e: b2db uxtb r3, r3
|
|||
|
|
8000f40: e7e3 b.n 8000f0a <__aeabi_ui2f+0x1e>
|
|||
|
|
8000f42: 2300 movs r3, #0
|
|||
|
|
8000f44: 2400 movs r4, #0
|
|||
|
|
8000f46: e7e0 b.n 8000f0a <__aeabi_ui2f+0x1e>
|
|||
|
|
8000f48: 22b9 movs r2, #185 ; 0xb9
|
|||
|
|
8000f4a: 0021 movs r1, r4
|
|||
|
|
8000f4c: 1ad2 subs r2, r2, r3
|
|||
|
|
8000f4e: 4091 lsls r1, r2
|
|||
|
|
8000f50: 000a movs r2, r1
|
|||
|
|
8000f52: 1e51 subs r1, r2, #1
|
|||
|
|
8000f54: 418a sbcs r2, r1
|
|||
|
|
8000f56: 2105 movs r1, #5
|
|||
|
|
8000f58: 1a09 subs r1, r1, r0
|
|||
|
|
8000f5a: 40cc lsrs r4, r1
|
|||
|
|
8000f5c: 4314 orrs r4, r2
|
|||
|
|
8000f5e: e7db b.n 8000f18 <__aeabi_ui2f+0x2c>
|
|||
|
|
8000f60: 4b04 ldr r3, [pc, #16] ; (8000f74 <__aeabi_ui2f+0x88>)
|
|||
|
|
8000f62: 401c ands r4, r3
|
|||
|
|
8000f64: 239f movs r3, #159 ; 0x9f
|
|||
|
|
8000f66: 01a4 lsls r4, r4, #6
|
|||
|
|
8000f68: 1a1b subs r3, r3, r0
|
|||
|
|
8000f6a: 0a64 lsrs r4, r4, #9
|
|||
|
|
8000f6c: b2db uxtb r3, r3
|
|||
|
|
8000f6e: e7cc b.n 8000f0a <__aeabi_ui2f+0x1e>
|
|||
|
|
8000f70: 0022 movs r2, r4
|
|||
|
|
8000f72: e7d7 b.n 8000f24 <__aeabi_ui2f+0x38>
|
|||
|
|
8000f74: fbffffff .word 0xfbffffff
|
|||
|
|
|
|||
|
|
08000f78 <__eqdf2>:
|
|||
|
|
8000f78: b5f0 push {r4, r5, r6, r7, lr}
|
|||
|
|
8000f7a: 464f mov r7, r9
|
|||
|
|
8000f7c: 4646 mov r6, r8
|
|||
|
|
8000f7e: 46d6 mov lr, sl
|
|||
|
|
8000f80: 005c lsls r4, r3, #1
|
|||
|
|
8000f82: b5c0 push {r6, r7, lr}
|
|||
|
|
8000f84: 031f lsls r7, r3, #12
|
|||
|
|
8000f86: 0fdb lsrs r3, r3, #31
|
|||
|
|
8000f88: 469a mov sl, r3
|
|||
|
|
8000f8a: 4b17 ldr r3, [pc, #92] ; (8000fe8 <__eqdf2+0x70>)
|
|||
|
|
8000f8c: 030e lsls r6, r1, #12
|
|||
|
|
8000f8e: 004d lsls r5, r1, #1
|
|||
|
|
8000f90: 4684 mov ip, r0
|
|||
|
|
8000f92: 4680 mov r8, r0
|
|||
|
|
8000f94: 0b36 lsrs r6, r6, #12
|
|||
|
|
8000f96: 0d6d lsrs r5, r5, #21
|
|||
|
|
8000f98: 0fc9 lsrs r1, r1, #31
|
|||
|
|
8000f9a: 4691 mov r9, r2
|
|||
|
|
8000f9c: 0b3f lsrs r7, r7, #12
|
|||
|
|
8000f9e: 0d64 lsrs r4, r4, #21
|
|||
|
|
8000fa0: 2001 movs r0, #1
|
|||
|
|
8000fa2: 429d cmp r5, r3
|
|||
|
|
8000fa4: d008 beq.n 8000fb8 <__eqdf2+0x40>
|
|||
|
|
8000fa6: 429c cmp r4, r3
|
|||
|
|
8000fa8: d001 beq.n 8000fae <__eqdf2+0x36>
|
|||
|
|
8000faa: 42a5 cmp r5, r4
|
|||
|
|
8000fac: d00b beq.n 8000fc6 <__eqdf2+0x4e>
|
|||
|
|
8000fae: bc1c pop {r2, r3, r4}
|
|||
|
|
8000fb0: 4690 mov r8, r2
|
|||
|
|
8000fb2: 4699 mov r9, r3
|
|||
|
|
8000fb4: 46a2 mov sl, r4
|
|||
|
|
8000fb6: bdf0 pop {r4, r5, r6, r7, pc}
|
|||
|
|
8000fb8: 4663 mov r3, ip
|
|||
|
|
8000fba: 4333 orrs r3, r6
|
|||
|
|
8000fbc: d1f7 bne.n 8000fae <__eqdf2+0x36>
|
|||
|
|
8000fbe: 42ac cmp r4, r5
|
|||
|
|
8000fc0: d1f5 bne.n 8000fae <__eqdf2+0x36>
|
|||
|
|
8000fc2: 433a orrs r2, r7
|
|||
|
|
8000fc4: d1f3 bne.n 8000fae <__eqdf2+0x36>
|
|||
|
|
8000fc6: 2001 movs r0, #1
|
|||
|
|
8000fc8: 42be cmp r6, r7
|
|||
|
|
8000fca: d1f0 bne.n 8000fae <__eqdf2+0x36>
|
|||
|
|
8000fcc: 45c8 cmp r8, r9
|
|||
|
|
8000fce: d1ee bne.n 8000fae <__eqdf2+0x36>
|
|||
|
|
8000fd0: 4551 cmp r1, sl
|
|||
|
|
8000fd2: d007 beq.n 8000fe4 <__eqdf2+0x6c>
|
|||
|
|
8000fd4: 2d00 cmp r5, #0
|
|||
|
|
8000fd6: d1ea bne.n 8000fae <__eqdf2+0x36>
|
|||
|
|
8000fd8: 4663 mov r3, ip
|
|||
|
|
8000fda: 431e orrs r6, r3
|
|||
|
|
8000fdc: 0030 movs r0, r6
|
|||
|
|
8000fde: 1e46 subs r6, r0, #1
|
|||
|
|
8000fe0: 41b0 sbcs r0, r6
|
|||
|
|
8000fe2: e7e4 b.n 8000fae <__eqdf2+0x36>
|
|||
|
|
8000fe4: 2000 movs r0, #0
|
|||
|
|
8000fe6: e7e2 b.n 8000fae <__eqdf2+0x36>
|
|||
|
|
8000fe8: 000007ff .word 0x000007ff
|
|||
|
|
|
|||
|
|
08000fec <__gedf2>:
|
|||
|
|
8000fec: b5f0 push {r4, r5, r6, r7, lr}
|
|||
|
|
8000fee: 4645 mov r5, r8
|
|||
|
|
8000ff0: 46de mov lr, fp
|
|||
|
|
8000ff2: 4657 mov r7, sl
|
|||
|
|
8000ff4: 464e mov r6, r9
|
|||
|
|
8000ff6: b5e0 push {r5, r6, r7, lr}
|
|||
|
|
8000ff8: 031f lsls r7, r3, #12
|
|||
|
|
8000ffa: 0b3d lsrs r5, r7, #12
|
|||
|
|
8000ffc: 4f2c ldr r7, [pc, #176] ; (80010b0 <__gedf2+0xc4>)
|
|||
|
|
8000ffe: 030e lsls r6, r1, #12
|
|||
|
|
8001000: 004c lsls r4, r1, #1
|
|||
|
|
8001002: 46ab mov fp, r5
|
|||
|
|
8001004: 005d lsls r5, r3, #1
|
|||
|
|
8001006: 4684 mov ip, r0
|
|||
|
|
8001008: 0b36 lsrs r6, r6, #12
|
|||
|
|
800100a: 0d64 lsrs r4, r4, #21
|
|||
|
|
800100c: 0fc9 lsrs r1, r1, #31
|
|||
|
|
800100e: 4690 mov r8, r2
|
|||
|
|
8001010: 0d6d lsrs r5, r5, #21
|
|||
|
|
8001012: 0fdb lsrs r3, r3, #31
|
|||
|
|
8001014: 42bc cmp r4, r7
|
|||
|
|
8001016: d02a beq.n 800106e <__gedf2+0x82>
|
|||
|
|
8001018: 4f25 ldr r7, [pc, #148] ; (80010b0 <__gedf2+0xc4>)
|
|||
|
|
800101a: 42bd cmp r5, r7
|
|||
|
|
800101c: d02d beq.n 800107a <__gedf2+0x8e>
|
|||
|
|
800101e: 2c00 cmp r4, #0
|
|||
|
|
8001020: d10f bne.n 8001042 <__gedf2+0x56>
|
|||
|
|
8001022: 4330 orrs r0, r6
|
|||
|
|
8001024: 0007 movs r7, r0
|
|||
|
|
8001026: 4681 mov r9, r0
|
|||
|
|
8001028: 4278 negs r0, r7
|
|||
|
|
800102a: 4178 adcs r0, r7
|
|||
|
|
800102c: b2c0 uxtb r0, r0
|
|||
|
|
800102e: 2d00 cmp r5, #0
|
|||
|
|
8001030: d117 bne.n 8001062 <__gedf2+0x76>
|
|||
|
|
8001032: 465f mov r7, fp
|
|||
|
|
8001034: 433a orrs r2, r7
|
|||
|
|
8001036: d114 bne.n 8001062 <__gedf2+0x76>
|
|||
|
|
8001038: 464b mov r3, r9
|
|||
|
|
800103a: 2000 movs r0, #0
|
|||
|
|
800103c: 2b00 cmp r3, #0
|
|||
|
|
800103e: d00a beq.n 8001056 <__gedf2+0x6a>
|
|||
|
|
8001040: e006 b.n 8001050 <__gedf2+0x64>
|
|||
|
|
8001042: 2d00 cmp r5, #0
|
|||
|
|
8001044: d102 bne.n 800104c <__gedf2+0x60>
|
|||
|
|
8001046: 4658 mov r0, fp
|
|||
|
|
8001048: 4302 orrs r2, r0
|
|||
|
|
800104a: d001 beq.n 8001050 <__gedf2+0x64>
|
|||
|
|
800104c: 4299 cmp r1, r3
|
|||
|
|
800104e: d018 beq.n 8001082 <__gedf2+0x96>
|
|||
|
|
8001050: 4248 negs r0, r1
|
|||
|
|
8001052: 2101 movs r1, #1
|
|||
|
|
8001054: 4308 orrs r0, r1
|
|||
|
|
8001056: bc3c pop {r2, r3, r4, r5}
|
|||
|
|
8001058: 4690 mov r8, r2
|
|||
|
|
800105a: 4699 mov r9, r3
|
|||
|
|
800105c: 46a2 mov sl, r4
|
|||
|
|
800105e: 46ab mov fp, r5
|
|||
|
|
8001060: bdf0 pop {r4, r5, r6, r7, pc}
|
|||
|
|
8001062: 2800 cmp r0, #0
|
|||
|
|
8001064: d0f2 beq.n 800104c <__gedf2+0x60>
|
|||
|
|
8001066: 2001 movs r0, #1
|
|||
|
|
8001068: 3b01 subs r3, #1
|
|||
|
|
800106a: 4318 orrs r0, r3
|
|||
|
|
800106c: e7f3 b.n 8001056 <__gedf2+0x6a>
|
|||
|
|
800106e: 0037 movs r7, r6
|
|||
|
|
8001070: 4307 orrs r7, r0
|
|||
|
|
8001072: d0d1 beq.n 8001018 <__gedf2+0x2c>
|
|||
|
|
8001074: 2002 movs r0, #2
|
|||
|
|
8001076: 4240 negs r0, r0
|
|||
|
|
8001078: e7ed b.n 8001056 <__gedf2+0x6a>
|
|||
|
|
800107a: 465f mov r7, fp
|
|||
|
|
800107c: 4317 orrs r7, r2
|
|||
|
|
800107e: d0ce beq.n 800101e <__gedf2+0x32>
|
|||
|
|
8001080: e7f8 b.n 8001074 <__gedf2+0x88>
|
|||
|
|
8001082: 42ac cmp r4, r5
|
|||
|
|
8001084: dce4 bgt.n 8001050 <__gedf2+0x64>
|
|||
|
|
8001086: da03 bge.n 8001090 <__gedf2+0xa4>
|
|||
|
|
8001088: 1e48 subs r0, r1, #1
|
|||
|
|
800108a: 2101 movs r1, #1
|
|||
|
|
800108c: 4308 orrs r0, r1
|
|||
|
|
800108e: e7e2 b.n 8001056 <__gedf2+0x6a>
|
|||
|
|
8001090: 455e cmp r6, fp
|
|||
|
|
8001092: d8dd bhi.n 8001050 <__gedf2+0x64>
|
|||
|
|
8001094: d006 beq.n 80010a4 <__gedf2+0xb8>
|
|||
|
|
8001096: 2000 movs r0, #0
|
|||
|
|
8001098: 455e cmp r6, fp
|
|||
|
|
800109a: d2dc bcs.n 8001056 <__gedf2+0x6a>
|
|||
|
|
800109c: 2301 movs r3, #1
|
|||
|
|
800109e: 1e48 subs r0, r1, #1
|
|||
|
|
80010a0: 4318 orrs r0, r3
|
|||
|
|
80010a2: e7d8 b.n 8001056 <__gedf2+0x6a>
|
|||
|
|
80010a4: 45c4 cmp ip, r8
|
|||
|
|
80010a6: d8d3 bhi.n 8001050 <__gedf2+0x64>
|
|||
|
|
80010a8: 2000 movs r0, #0
|
|||
|
|
80010aa: 45c4 cmp ip, r8
|
|||
|
|
80010ac: d3f6 bcc.n 800109c <__gedf2+0xb0>
|
|||
|
|
80010ae: e7d2 b.n 8001056 <__gedf2+0x6a>
|
|||
|
|
80010b0: 000007ff .word 0x000007ff
|
|||
|
|
|
|||
|
|
080010b4 <__ledf2>:
|
|||
|
|
80010b4: b5f0 push {r4, r5, r6, r7, lr}
|
|||
|
|
80010b6: 464e mov r6, r9
|
|||
|
|
80010b8: 4645 mov r5, r8
|
|||
|
|
80010ba: 46de mov lr, fp
|
|||
|
|
80010bc: 4657 mov r7, sl
|
|||
|
|
80010be: 005c lsls r4, r3, #1
|
|||
|
|
80010c0: b5e0 push {r5, r6, r7, lr}
|
|||
|
|
80010c2: 031f lsls r7, r3, #12
|
|||
|
|
80010c4: 0fdb lsrs r3, r3, #31
|
|||
|
|
80010c6: 4699 mov r9, r3
|
|||
|
|
80010c8: 4b2a ldr r3, [pc, #168] ; (8001174 <__ledf2+0xc0>)
|
|||
|
|
80010ca: 030e lsls r6, r1, #12
|
|||
|
|
80010cc: 004d lsls r5, r1, #1
|
|||
|
|
80010ce: 0fc9 lsrs r1, r1, #31
|
|||
|
|
80010d0: 4684 mov ip, r0
|
|||
|
|
80010d2: 0b36 lsrs r6, r6, #12
|
|||
|
|
80010d4: 0d6d lsrs r5, r5, #21
|
|||
|
|
80010d6: 468b mov fp, r1
|
|||
|
|
80010d8: 4690 mov r8, r2
|
|||
|
|
80010da: 0b3f lsrs r7, r7, #12
|
|||
|
|
80010dc: 0d64 lsrs r4, r4, #21
|
|||
|
|
80010de: 429d cmp r5, r3
|
|||
|
|
80010e0: d020 beq.n 8001124 <__ledf2+0x70>
|
|||
|
|
80010e2: 4b24 ldr r3, [pc, #144] ; (8001174 <__ledf2+0xc0>)
|
|||
|
|
80010e4: 429c cmp r4, r3
|
|||
|
|
80010e6: d022 beq.n 800112e <__ledf2+0x7a>
|
|||
|
|
80010e8: 2d00 cmp r5, #0
|
|||
|
|
80010ea: d112 bne.n 8001112 <__ledf2+0x5e>
|
|||
|
|
80010ec: 4330 orrs r0, r6
|
|||
|
|
80010ee: 4243 negs r3, r0
|
|||
|
|
80010f0: 4143 adcs r3, r0
|
|||
|
|
80010f2: b2db uxtb r3, r3
|
|||
|
|
80010f4: 2c00 cmp r4, #0
|
|||
|
|
80010f6: d01f beq.n 8001138 <__ledf2+0x84>
|
|||
|
|
80010f8: 2b00 cmp r3, #0
|
|||
|
|
80010fa: d00c beq.n 8001116 <__ledf2+0x62>
|
|||
|
|
80010fc: 464b mov r3, r9
|
|||
|
|
80010fe: 2001 movs r0, #1
|
|||
|
|
8001100: 3b01 subs r3, #1
|
|||
|
|
8001102: 4303 orrs r3, r0
|
|||
|
|
8001104: 0018 movs r0, r3
|
|||
|
|
8001106: bc3c pop {r2, r3, r4, r5}
|
|||
|
|
8001108: 4690 mov r8, r2
|
|||
|
|
800110a: 4699 mov r9, r3
|
|||
|
|
800110c: 46a2 mov sl, r4
|
|||
|
|
800110e: 46ab mov fp, r5
|
|||
|
|
8001110: bdf0 pop {r4, r5, r6, r7, pc}
|
|||
|
|
8001112: 2c00 cmp r4, #0
|
|||
|
|
8001114: d016 beq.n 8001144 <__ledf2+0x90>
|
|||
|
|
8001116: 45cb cmp fp, r9
|
|||
|
|
8001118: d017 beq.n 800114a <__ledf2+0x96>
|
|||
|
|
800111a: 465b mov r3, fp
|
|||
|
|
800111c: 4259 negs r1, r3
|
|||
|
|
800111e: 2301 movs r3, #1
|
|||
|
|
8001120: 430b orrs r3, r1
|
|||
|
|
8001122: e7ef b.n 8001104 <__ledf2+0x50>
|
|||
|
|
8001124: 0031 movs r1, r6
|
|||
|
|
8001126: 2302 movs r3, #2
|
|||
|
|
8001128: 4301 orrs r1, r0
|
|||
|
|
800112a: d1eb bne.n 8001104 <__ledf2+0x50>
|
|||
|
|
800112c: e7d9 b.n 80010e2 <__ledf2+0x2e>
|
|||
|
|
800112e: 0039 movs r1, r7
|
|||
|
|
8001130: 2302 movs r3, #2
|
|||
|
|
8001132: 4311 orrs r1, r2
|
|||
|
|
8001134: d1e6 bne.n 8001104 <__ledf2+0x50>
|
|||
|
|
8001136: e7d7 b.n 80010e8 <__ledf2+0x34>
|
|||
|
|
8001138: 433a orrs r2, r7
|
|||
|
|
800113a: d1dd bne.n 80010f8 <__ledf2+0x44>
|
|||
|
|
800113c: 2300 movs r3, #0
|
|||
|
|
800113e: 2800 cmp r0, #0
|
|||
|
|
8001140: d0e0 beq.n 8001104 <__ledf2+0x50>
|
|||
|
|
8001142: e7ea b.n 800111a <__ledf2+0x66>
|
|||
|
|
8001144: 433a orrs r2, r7
|
|||
|
|
8001146: d1e6 bne.n 8001116 <__ledf2+0x62>
|
|||
|
|
8001148: e7e7 b.n 800111a <__ledf2+0x66>
|
|||
|
|
800114a: 42a5 cmp r5, r4
|
|||
|
|
800114c: dce5 bgt.n 800111a <__ledf2+0x66>
|
|||
|
|
800114e: db05 blt.n 800115c <__ledf2+0xa8>
|
|||
|
|
8001150: 42be cmp r6, r7
|
|||
|
|
8001152: d8e2 bhi.n 800111a <__ledf2+0x66>
|
|||
|
|
8001154: d007 beq.n 8001166 <__ledf2+0xb2>
|
|||
|
|
8001156: 2300 movs r3, #0
|
|||
|
|
8001158: 42be cmp r6, r7
|
|||
|
|
800115a: d2d3 bcs.n 8001104 <__ledf2+0x50>
|
|||
|
|
800115c: 4659 mov r1, fp
|
|||
|
|
800115e: 2301 movs r3, #1
|
|||
|
|
8001160: 3901 subs r1, #1
|
|||
|
|
8001162: 430b orrs r3, r1
|
|||
|
|
8001164: e7ce b.n 8001104 <__ledf2+0x50>
|
|||
|
|
8001166: 45c4 cmp ip, r8
|
|||
|
|
8001168: d8d7 bhi.n 800111a <__ledf2+0x66>
|
|||
|
|
800116a: 2300 movs r3, #0
|
|||
|
|
800116c: 45c4 cmp ip, r8
|
|||
|
|
800116e: d3f5 bcc.n 800115c <__ledf2+0xa8>
|
|||
|
|
8001170: e7c8 b.n 8001104 <__ledf2+0x50>
|
|||
|
|
8001172: 46c0 nop ; (mov r8, r8)
|
|||
|
|
8001174: 000007ff .word 0x000007ff
|
|||
|
|
|
|||
|
|
08001178 <__aeabi_f2d>:
|
|||
|
|
8001178: 0041 lsls r1, r0, #1
|
|||
|
|
800117a: 0e09 lsrs r1, r1, #24
|
|||
|
|
800117c: 1c4b adds r3, r1, #1
|
|||
|
|
800117e: b570 push {r4, r5, r6, lr}
|
|||
|
|
8001180: b2db uxtb r3, r3
|
|||
|
|
8001182: 0246 lsls r6, r0, #9
|
|||
|
|
8001184: 0a75 lsrs r5, r6, #9
|
|||
|
|
8001186: 0fc4 lsrs r4, r0, #31
|
|||
|
|
8001188: 2b01 cmp r3, #1
|
|||
|
|
800118a: dd14 ble.n 80011b6 <__aeabi_f2d+0x3e>
|
|||
|
|
800118c: 23e0 movs r3, #224 ; 0xe0
|
|||
|
|
800118e: 009b lsls r3, r3, #2
|
|||
|
|
8001190: 076d lsls r5, r5, #29
|
|||
|
|
8001192: 0b36 lsrs r6, r6, #12
|
|||
|
|
8001194: 18cb adds r3, r1, r3
|
|||
|
|
8001196: 2100 movs r1, #0
|
|||
|
|
8001198: 0d0a lsrs r2, r1, #20
|
|||
|
|
800119a: 0028 movs r0, r5
|
|||
|
|
800119c: 0512 lsls r2, r2, #20
|
|||
|
|
800119e: 4d1c ldr r5, [pc, #112] ; (8001210 <__aeabi_f2d+0x98>)
|
|||
|
|
80011a0: 4332 orrs r2, r6
|
|||
|
|
80011a2: 055b lsls r3, r3, #21
|
|||
|
|
80011a4: 402a ands r2, r5
|
|||
|
|
80011a6: 085b lsrs r3, r3, #1
|
|||
|
|
80011a8: 4313 orrs r3, r2
|
|||
|
|
80011aa: 005b lsls r3, r3, #1
|
|||
|
|
80011ac: 07e4 lsls r4, r4, #31
|
|||
|
|
80011ae: 085b lsrs r3, r3, #1
|
|||
|
|
80011b0: 4323 orrs r3, r4
|
|||
|
|
80011b2: 0019 movs r1, r3
|
|||
|
|
80011b4: bd70 pop {r4, r5, r6, pc}
|
|||
|
|
80011b6: 2900 cmp r1, #0
|
|||
|
|
80011b8: d114 bne.n 80011e4 <__aeabi_f2d+0x6c>
|
|||
|
|
80011ba: 2d00 cmp r5, #0
|
|||
|
|
80011bc: d01e beq.n 80011fc <__aeabi_f2d+0x84>
|
|||
|
|
80011be: 0028 movs r0, r5
|
|||
|
|
80011c0: f000 f82c bl 800121c <__clzsi2>
|
|||
|
|
80011c4: 280a cmp r0, #10
|
|||
|
|
80011c6: dc1c bgt.n 8001202 <__aeabi_f2d+0x8a>
|
|||
|
|
80011c8: 230b movs r3, #11
|
|||
|
|
80011ca: 002a movs r2, r5
|
|||
|
|
80011cc: 1a1b subs r3, r3, r0
|
|||
|
|
80011ce: 40da lsrs r2, r3
|
|||
|
|
80011d0: 0003 movs r3, r0
|
|||
|
|
80011d2: 3315 adds r3, #21
|
|||
|
|
80011d4: 409d lsls r5, r3
|
|||
|
|
80011d6: 4b0f ldr r3, [pc, #60] ; (8001214 <__aeabi_f2d+0x9c>)
|
|||
|
|
80011d8: 0312 lsls r2, r2, #12
|
|||
|
|
80011da: 1a1b subs r3, r3, r0
|
|||
|
|
80011dc: 055b lsls r3, r3, #21
|
|||
|
|
80011de: 0b16 lsrs r6, r2, #12
|
|||
|
|
80011e0: 0d5b lsrs r3, r3, #21
|
|||
|
|
80011e2: e7d8 b.n 8001196 <__aeabi_f2d+0x1e>
|
|||
|
|
80011e4: 2d00 cmp r5, #0
|
|||
|
|
80011e6: d006 beq.n 80011f6 <__aeabi_f2d+0x7e>
|
|||
|
|
80011e8: 0b32 lsrs r2, r6, #12
|
|||
|
|
80011ea: 2680 movs r6, #128 ; 0x80
|
|||
|
|
80011ec: 0336 lsls r6, r6, #12
|
|||
|
|
80011ee: 076d lsls r5, r5, #29
|
|||
|
|
80011f0: 4316 orrs r6, r2
|
|||
|
|
80011f2: 4b09 ldr r3, [pc, #36] ; (8001218 <__aeabi_f2d+0xa0>)
|
|||
|
|
80011f4: e7cf b.n 8001196 <__aeabi_f2d+0x1e>
|
|||
|
|
80011f6: 4b08 ldr r3, [pc, #32] ; (8001218 <__aeabi_f2d+0xa0>)
|
|||
|
|
80011f8: 2600 movs r6, #0
|
|||
|
|
80011fa: e7cc b.n 8001196 <__aeabi_f2d+0x1e>
|
|||
|
|
80011fc: 2300 movs r3, #0
|
|||
|
|
80011fe: 2600 movs r6, #0
|
|||
|
|
8001200: e7c9 b.n 8001196 <__aeabi_f2d+0x1e>
|
|||
|
|
8001202: 0003 movs r3, r0
|
|||
|
|
8001204: 002a movs r2, r5
|
|||
|
|
8001206: 3b0b subs r3, #11
|
|||
|
|
8001208: 409a lsls r2, r3
|
|||
|
|
800120a: 2500 movs r5, #0
|
|||
|
|
800120c: e7e3 b.n 80011d6 <__aeabi_f2d+0x5e>
|
|||
|
|
800120e: 46c0 nop ; (mov r8, r8)
|
|||
|
|
8001210: 800fffff .word 0x800fffff
|
|||
|
|
8001214: 00000389 .word 0x00000389
|
|||
|
|
8001218: 000007ff .word 0x000007ff
|
|||
|
|
|
|||
|
|
0800121c <__clzsi2>:
|
|||
|
|
800121c: 211c movs r1, #28
|
|||
|
|
800121e: 2301 movs r3, #1
|
|||
|
|
8001220: 041b lsls r3, r3, #16
|
|||
|
|
8001222: 4298 cmp r0, r3
|
|||
|
|
8001224: d301 bcc.n 800122a <__clzsi2+0xe>
|
|||
|
|
8001226: 0c00 lsrs r0, r0, #16
|
|||
|
|
8001228: 3910 subs r1, #16
|
|||
|
|
800122a: 0a1b lsrs r3, r3, #8
|
|||
|
|
800122c: 4298 cmp r0, r3
|
|||
|
|
800122e: d301 bcc.n 8001234 <__clzsi2+0x18>
|
|||
|
|
8001230: 0a00 lsrs r0, r0, #8
|
|||
|
|
8001232: 3908 subs r1, #8
|
|||
|
|
8001234: 091b lsrs r3, r3, #4
|
|||
|
|
8001236: 4298 cmp r0, r3
|
|||
|
|
8001238: d301 bcc.n 800123e <__clzsi2+0x22>
|
|||
|
|
800123a: 0900 lsrs r0, r0, #4
|
|||
|
|
800123c: 3904 subs r1, #4
|
|||
|
|
800123e: a202 add r2, pc, #8 ; (adr r2, 8001248 <__clzsi2+0x2c>)
|
|||
|
|
8001240: 5c10 ldrb r0, [r2, r0]
|
|||
|
|
8001242: 1840 adds r0, r0, r1
|
|||
|
|
8001244: 4770 bx lr
|
|||
|
|
8001246: 46c0 nop ; (mov r8, r8)
|
|||
|
|
8001248: 02020304 .word 0x02020304
|
|||
|
|
800124c: 01010101 .word 0x01010101
|
|||
|
|
...
|
|||
|
|
|
|||
|
|
08001258 <__clzdi2>:
|
|||
|
|
8001258: b510 push {r4, lr}
|
|||
|
|
800125a: 2900 cmp r1, #0
|
|||
|
|
800125c: d103 bne.n 8001266 <__clzdi2+0xe>
|
|||
|
|
800125e: f7ff ffdd bl 800121c <__clzsi2>
|
|||
|
|
8001262: 3020 adds r0, #32
|
|||
|
|
8001264: e002 b.n 800126c <__clzdi2+0x14>
|
|||
|
|
8001266: 1c08 adds r0, r1, #0
|
|||
|
|
8001268: f7ff ffd8 bl 800121c <__clzsi2>
|
|||
|
|
800126c: bd10 pop {r4, pc}
|
|||
|
|
800126e: 46c0 nop ; (mov r8, r8)
|
|||
|
|
|
|||
|
|
08001270 <SetAndCorrect>:
|
|||
|
|
|
|||
|
|
//------------------------------------------------------
|
|||
|
|
// <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
|||
|
|
//------------------------------------------------------
|
|||
|
|
void SetAndCorrect(void)
|
|||
|
|
{
|
|||
|
|
8001270: b580 push {r7, lr}
|
|||
|
|
8001272: b082 sub sp, #8
|
|||
|
|
8001274: af00 add r7, sp, #0
|
|||
|
|
float fKU, sens_f;
|
|||
|
|
uint32_t k;
|
|||
|
|
|
|||
|
|
|
|||
|
|
switch(pardata.IIN)
|
|||
|
|
8001276: 4bd3 ldr r3, [pc, #844] ; (80015c4 <SetAndCorrect+0x354>)
|
|||
|
|
8001278: 88db ldrh r3, [r3, #6]
|
|||
|
|
800127a: b29b uxth r3, r3
|
|||
|
|
800127c: 2b00 cmp r3, #0
|
|||
|
|
800127e: d002 beq.n 8001286 <SetAndCorrect+0x16>
|
|||
|
|
8001280: 2b01 cmp r3, #1
|
|||
|
|
8001282: d037 beq.n 80012f4 <SetAndCorrect+0x84>
|
|||
|
|
8001284: e06f b.n 8001366 <SetAndCorrect+0xf6>
|
|||
|
|
{
|
|||
|
|
case CHARGE: // ZAR
|
|||
|
|
HAL_GPIO_WritePin(GPIOB, (A2_Pin | A3_Pin), GPIO_PIN_RESET);
|
|||
|
|
8001286: 4bd0 ldr r3, [pc, #832] ; (80015c8 <SetAndCorrect+0x358>)
|
|||
|
|
8001288: 2200 movs r2, #0
|
|||
|
|
800128a: 210c movs r1, #12
|
|||
|
|
800128c: 0018 movs r0, r3
|
|||
|
|
800128e: f003 fc3e bl 8004b0e <HAL_GPIO_WritePin>
|
|||
|
|
|
|||
|
|
if(pardata.IKU < Ku1)
|
|||
|
|
8001292: 4bcc ldr r3, [pc, #816] ; (80015c4 <SetAndCorrect+0x354>)
|
|||
|
|
8001294: 899b ldrh r3, [r3, #12]
|
|||
|
|
8001296: b29b uxth r3, r3
|
|||
|
|
8001298: 2b02 cmp r3, #2
|
|||
|
|
800129a: d80c bhi.n 80012b6 <SetAndCorrect+0x46>
|
|||
|
|
{
|
|||
|
|
HAL_GPIO_WritePin(GPIOB, A0_Pin, GPIO_PIN_RESET);
|
|||
|
|
800129c: 4bca ldr r3, [pc, #808] ; (80015c8 <SetAndCorrect+0x358>)
|
|||
|
|
800129e: 2200 movs r2, #0
|
|||
|
|
80012a0: 2101 movs r1, #1
|
|||
|
|
80012a2: 0018 movs r0, r3
|
|||
|
|
80012a4: f003 fc33 bl 8004b0e <HAL_GPIO_WritePin>
|
|||
|
|
HAL_GPIO_WritePin(GPIOB, A1_Pin, GPIO_PIN_SET);
|
|||
|
|
80012a8: 4bc7 ldr r3, [pc, #796] ; (80015c8 <SetAndCorrect+0x358>)
|
|||
|
|
80012aa: 2201 movs r2, #1
|
|||
|
|
80012ac: 2102 movs r1, #2
|
|||
|
|
80012ae: 0018 movs r0, r3
|
|||
|
|
80012b0: f003 fc2d bl 8004b0e <HAL_GPIO_WritePin>
|
|||
|
|
else
|
|||
|
|
{
|
|||
|
|
HAL_GPIO_WritePin(GPIOB, A0_Pin, GPIO_PIN_RESET);
|
|||
|
|
HAL_GPIO_WritePin(GPIOB, A1_Pin, GPIO_PIN_RESET);
|
|||
|
|
}
|
|||
|
|
break;
|
|||
|
|
80012b4: e057 b.n 8001366 <SetAndCorrect+0xf6>
|
|||
|
|
if(pardata.IKU > Ku100) // >= x200
|
|||
|
|
80012b6: 4bc3 ldr r3, [pc, #780] ; (80015c4 <SetAndCorrect+0x354>)
|
|||
|
|
80012b8: 899b ldrh r3, [r3, #12]
|
|||
|
|
80012ba: b29b uxth r3, r3
|
|||
|
|
80012bc: 2b09 cmp r3, #9
|
|||
|
|
80012be: d90c bls.n 80012da <SetAndCorrect+0x6a>
|
|||
|
|
HAL_GPIO_WritePin(GPIOB, A0_Pin, GPIO_PIN_SET);
|
|||
|
|
80012c0: 4bc1 ldr r3, [pc, #772] ; (80015c8 <SetAndCorrect+0x358>)
|
|||
|
|
80012c2: 2201 movs r2, #1
|
|||
|
|
80012c4: 2101 movs r1, #1
|
|||
|
|
80012c6: 0018 movs r0, r3
|
|||
|
|
80012c8: f003 fc21 bl 8004b0e <HAL_GPIO_WritePin>
|
|||
|
|
HAL_GPIO_WritePin(GPIOB, A1_Pin, GPIO_PIN_RESET);
|
|||
|
|
80012cc: 4bbe ldr r3, [pc, #760] ; (80015c8 <SetAndCorrect+0x358>)
|
|||
|
|
80012ce: 2200 movs r2, #0
|
|||
|
|
80012d0: 2102 movs r1, #2
|
|||
|
|
80012d2: 0018 movs r0, r3
|
|||
|
|
80012d4: f003 fc1b bl 8004b0e <HAL_GPIO_WritePin>
|
|||
|
|
break;
|
|||
|
|
80012d8: e045 b.n 8001366 <SetAndCorrect+0xf6>
|
|||
|
|
HAL_GPIO_WritePin(GPIOB, A0_Pin, GPIO_PIN_RESET);
|
|||
|
|
80012da: 4bbb ldr r3, [pc, #748] ; (80015c8 <SetAndCorrect+0x358>)
|
|||
|
|
80012dc: 2200 movs r2, #0
|
|||
|
|
80012de: 2101 movs r1, #1
|
|||
|
|
80012e0: 0018 movs r0, r3
|
|||
|
|
80012e2: f003 fc14 bl 8004b0e <HAL_GPIO_WritePin>
|
|||
|
|
HAL_GPIO_WritePin(GPIOB, A1_Pin, GPIO_PIN_RESET);
|
|||
|
|
80012e6: 4bb8 ldr r3, [pc, #736] ; (80015c8 <SetAndCorrect+0x358>)
|
|||
|
|
80012e8: 2200 movs r2, #0
|
|||
|
|
80012ea: 2102 movs r1, #2
|
|||
|
|
80012ec: 0018 movs r0, r3
|
|||
|
|
80012ee: f003 fc0e bl 8004b0e <HAL_GPIO_WritePin>
|
|||
|
|
break;
|
|||
|
|
80012f2: e038 b.n 8001366 <SetAndCorrect+0xf6>
|
|||
|
|
case ICP: // ICP
|
|||
|
|
|
|||
|
|
if(pardata.IKU<Ku1){
|
|||
|
|
80012f4: 4bb3 ldr r3, [pc, #716] ; (80015c4 <SetAndCorrect+0x354>)
|
|||
|
|
80012f6: 899b ldrh r3, [r3, #12]
|
|||
|
|
80012f8: b29b uxth r3, r3
|
|||
|
|
80012fa: 2b02 cmp r3, #2
|
|||
|
|
80012fc: d802 bhi.n 8001304 <SetAndCorrect+0x94>
|
|||
|
|
pardata.IKU=Ku1;
|
|||
|
|
80012fe: 4bb1 ldr r3, [pc, #708] ; (80015c4 <SetAndCorrect+0x354>)
|
|||
|
|
8001300: 2203 movs r2, #3
|
|||
|
|
8001302: 819a strh r2, [r3, #12]
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
if(pardata.IKU > Ku100) // >= x200
|
|||
|
|
8001304: 4baf ldr r3, [pc, #700] ; (80015c4 <SetAndCorrect+0x354>)
|
|||
|
|
8001306: 899b ldrh r3, [r3, #12]
|
|||
|
|
8001308: b29b uxth r3, r3
|
|||
|
|
800130a: 2b09 cmp r3, #9
|
|||
|
|
800130c: d912 bls.n 8001334 <SetAndCorrect+0xc4>
|
|||
|
|
{
|
|||
|
|
HAL_GPIO_WritePin(GPIOB, A0_Pin, GPIO_PIN_SET);
|
|||
|
|
800130e: 4bae ldr r3, [pc, #696] ; (80015c8 <SetAndCorrect+0x358>)
|
|||
|
|
8001310: 2201 movs r2, #1
|
|||
|
|
8001312: 2101 movs r1, #1
|
|||
|
|
8001314: 0018 movs r0, r3
|
|||
|
|
8001316: f003 fbfa bl 8004b0e <HAL_GPIO_WritePin>
|
|||
|
|
HAL_GPIO_WritePin(GPIOB, A1_Pin, GPIO_PIN_RESET);
|
|||
|
|
800131a: 4bab ldr r3, [pc, #684] ; (80015c8 <SetAndCorrect+0x358>)
|
|||
|
|
800131c: 2200 movs r2, #0
|
|||
|
|
800131e: 2102 movs r1, #2
|
|||
|
|
8001320: 0018 movs r0, r3
|
|||
|
|
8001322: f003 fbf4 bl 8004b0e <HAL_GPIO_WritePin>
|
|||
|
|
HAL_GPIO_WritePin(GPIOB, (A2_Pin | A3_Pin), GPIO_PIN_SET);
|
|||
|
|
8001326: 4ba8 ldr r3, [pc, #672] ; (80015c8 <SetAndCorrect+0x358>)
|
|||
|
|
8001328: 2201 movs r2, #1
|
|||
|
|
800132a: 210c movs r1, #12
|
|||
|
|
800132c: 0018 movs r0, r3
|
|||
|
|
800132e: f003 fbee bl 8004b0e <HAL_GPIO_WritePin>
|
|||
|
|
HAL_GPIO_WritePin(GPIOB, A1_Pin, GPIO_PIN_RESET);
|
|||
|
|
|
|||
|
|
HAL_GPIO_WritePin(GPIOB, A2_Pin, GPIO_PIN_SET);
|
|||
|
|
HAL_GPIO_WritePin(GPIOB, A3_Pin, GPIO_PIN_RESET);
|
|||
|
|
}
|
|||
|
|
break;
|
|||
|
|
8001332: e017 b.n 8001364 <SetAndCorrect+0xf4>
|
|||
|
|
HAL_GPIO_WritePin(GPIOB, A0_Pin, GPIO_PIN_RESET);
|
|||
|
|
8001334: 4ba4 ldr r3, [pc, #656] ; (80015c8 <SetAndCorrect+0x358>)
|
|||
|
|
8001336: 2200 movs r2, #0
|
|||
|
|
8001338: 2101 movs r1, #1
|
|||
|
|
800133a: 0018 movs r0, r3
|
|||
|
|
800133c: f003 fbe7 bl 8004b0e <HAL_GPIO_WritePin>
|
|||
|
|
HAL_GPIO_WritePin(GPIOB, A1_Pin, GPIO_PIN_RESET);
|
|||
|
|
8001340: 4ba1 ldr r3, [pc, #644] ; (80015c8 <SetAndCorrect+0x358>)
|
|||
|
|
8001342: 2200 movs r2, #0
|
|||
|
|
8001344: 2102 movs r1, #2
|
|||
|
|
8001346: 0018 movs r0, r3
|
|||
|
|
8001348: f003 fbe1 bl 8004b0e <HAL_GPIO_WritePin>
|
|||
|
|
HAL_GPIO_WritePin(GPIOB, A2_Pin, GPIO_PIN_SET);
|
|||
|
|
800134c: 4b9e ldr r3, [pc, #632] ; (80015c8 <SetAndCorrect+0x358>)
|
|||
|
|
800134e: 2201 movs r2, #1
|
|||
|
|
8001350: 2104 movs r1, #4
|
|||
|
|
8001352: 0018 movs r0, r3
|
|||
|
|
8001354: f003 fbdb bl 8004b0e <HAL_GPIO_WritePin>
|
|||
|
|
HAL_GPIO_WritePin(GPIOB, A3_Pin, GPIO_PIN_RESET);
|
|||
|
|
8001358: 4b9b ldr r3, [pc, #620] ; (80015c8 <SetAndCorrect+0x358>)
|
|||
|
|
800135a: 2200 movs r2, #0
|
|||
|
|
800135c: 2108 movs r1, #8
|
|||
|
|
800135e: 0018 movs r0, r3
|
|||
|
|
8001360: f003 fbd5 bl 8004b0e <HAL_GPIO_WritePin>
|
|||
|
|
break;
|
|||
|
|
8001364: 46c0 nop ; (mov r8, r8)
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
switch(pardata.IKU)
|
|||
|
|
8001366: 4b97 ldr r3, [pc, #604] ; (80015c4 <SetAndCorrect+0x354>)
|
|||
|
|
8001368: 899b ldrh r3, [r3, #12]
|
|||
|
|
800136a: b29b uxth r3, r3
|
|||
|
|
800136c: 2b0c cmp r3, #12
|
|||
|
|
800136e: d853 bhi.n 8001418 <SetAndCorrect+0x1a8>
|
|||
|
|
8001370: 009a lsls r2, r3, #2
|
|||
|
|
8001372: 4b96 ldr r3, [pc, #600] ; (80015cc <SetAndCorrect+0x35c>)
|
|||
|
|
8001374: 18d3 adds r3, r2, r3
|
|||
|
|
8001376: 681b ldr r3, [r3, #0]
|
|||
|
|
8001378: 469f mov pc, r3
|
|||
|
|
{//todo
|
|||
|
|
case Ku0_1: case Ku1: // 0.1, 1
|
|||
|
|
HAL_GPIO_WritePin(GPIOB, (A4_Pin | A5_Pin | A6_Pin), GPIO_PIN_RESET);
|
|||
|
|
800137a: 4b93 ldr r3, [pc, #588] ; (80015c8 <SetAndCorrect+0x358>)
|
|||
|
|
800137c: 2200 movs r2, #0
|
|||
|
|
800137e: 2170 movs r1, #112 ; 0x70
|
|||
|
|
8001380: 0018 movs r0, r3
|
|||
|
|
8001382: f003 fbc4 bl 8004b0e <HAL_GPIO_WritePin>
|
|||
|
|
break;
|
|||
|
|
8001386: e047 b.n 8001418 <SetAndCorrect+0x1a8>
|
|||
|
|
case Ku0_2: case Ku2: // 0.2, 2
|
|||
|
|
HAL_GPIO_WritePin(GPIOB, A4_Pin, GPIO_PIN_SET);
|
|||
|
|
8001388: 4b8f ldr r3, [pc, #572] ; (80015c8 <SetAndCorrect+0x358>)
|
|||
|
|
800138a: 2201 movs r2, #1
|
|||
|
|
800138c: 2110 movs r1, #16
|
|||
|
|
800138e: 0018 movs r0, r3
|
|||
|
|
8001390: f003 fbbd bl 8004b0e <HAL_GPIO_WritePin>
|
|||
|
|
HAL_GPIO_WritePin(GPIOB, (A5_Pin | A6_Pin), GPIO_PIN_RESET);
|
|||
|
|
8001394: 4b8c ldr r3, [pc, #560] ; (80015c8 <SetAndCorrect+0x358>)
|
|||
|
|
8001396: 2200 movs r2, #0
|
|||
|
|
8001398: 2160 movs r1, #96 ; 0x60
|
|||
|
|
800139a: 0018 movs r0, r3
|
|||
|
|
800139c: f003 fbb7 bl 8004b0e <HAL_GPIO_WritePin>
|
|||
|
|
break;
|
|||
|
|
80013a0: e03a b.n 8001418 <SetAndCorrect+0x1a8>
|
|||
|
|
case Ku0_5: case Ku5: // 0.5, 5
|
|||
|
|
HAL_GPIO_WritePin(GPIOB, A5_Pin, GPIO_PIN_SET);
|
|||
|
|
80013a2: 4b89 ldr r3, [pc, #548] ; (80015c8 <SetAndCorrect+0x358>)
|
|||
|
|
80013a4: 2201 movs r2, #1
|
|||
|
|
80013a6: 2120 movs r1, #32
|
|||
|
|
80013a8: 0018 movs r0, r3
|
|||
|
|
80013aa: f003 fbb0 bl 8004b0e <HAL_GPIO_WritePin>
|
|||
|
|
HAL_GPIO_WritePin(GPIOB, (A4_Pin | A6_Pin), GPIO_PIN_RESET);
|
|||
|
|
80013ae: 4b86 ldr r3, [pc, #536] ; (80015c8 <SetAndCorrect+0x358>)
|
|||
|
|
80013b0: 2200 movs r2, #0
|
|||
|
|
80013b2: 2150 movs r1, #80 ; 0x50
|
|||
|
|
80013b4: 0018 movs r0, r3
|
|||
|
|
80013b6: f003 fbaa bl 8004b0e <HAL_GPIO_WritePin>
|
|||
|
|
break;
|
|||
|
|
80013ba: e02d b.n 8001418 <SetAndCorrect+0x1a8>
|
|||
|
|
|
|||
|
|
case Ku10: // 10
|
|||
|
|
HAL_GPIO_WritePin(GPIOB, A6_Pin, GPIO_PIN_RESET);
|
|||
|
|
80013bc: 4b82 ldr r3, [pc, #520] ; (80015c8 <SetAndCorrect+0x358>)
|
|||
|
|
80013be: 2200 movs r2, #0
|
|||
|
|
80013c0: 2140 movs r1, #64 ; 0x40
|
|||
|
|
80013c2: 0018 movs r0, r3
|
|||
|
|
80013c4: f003 fba3 bl 8004b0e <HAL_GPIO_WritePin>
|
|||
|
|
HAL_GPIO_WritePin(GPIOB, (A4_Pin | A5_Pin), GPIO_PIN_SET);
|
|||
|
|
80013c8: 4b7f ldr r3, [pc, #508] ; (80015c8 <SetAndCorrect+0x358>)
|
|||
|
|
80013ca: 2201 movs r2, #1
|
|||
|
|
80013cc: 2130 movs r1, #48 ; 0x30
|
|||
|
|
80013ce: 0018 movs r0, r3
|
|||
|
|
80013d0: f003 fb9d bl 8004b0e <HAL_GPIO_WritePin>
|
|||
|
|
break;
|
|||
|
|
80013d4: e020 b.n 8001418 <SetAndCorrect+0x1a8>
|
|||
|
|
case Ku20: case Ku200: // 20, 200
|
|||
|
|
HAL_GPIO_WritePin(GPIOB, (A4_Pin | A6_Pin), GPIO_PIN_SET);
|
|||
|
|
80013d6: 4b7c ldr r3, [pc, #496] ; (80015c8 <SetAndCorrect+0x358>)
|
|||
|
|
80013d8: 2201 movs r2, #1
|
|||
|
|
80013da: 2150 movs r1, #80 ; 0x50
|
|||
|
|
80013dc: 0018 movs r0, r3
|
|||
|
|
80013de: f003 fb96 bl 8004b0e <HAL_GPIO_WritePin>
|
|||
|
|
HAL_GPIO_WritePin(GPIOB, A5_Pin, GPIO_PIN_RESET);
|
|||
|
|
80013e2: 4b79 ldr r3, [pc, #484] ; (80015c8 <SetAndCorrect+0x358>)
|
|||
|
|
80013e4: 2200 movs r2, #0
|
|||
|
|
80013e6: 2120 movs r1, #32
|
|||
|
|
80013e8: 0018 movs r0, r3
|
|||
|
|
80013ea: f003 fb90 bl 8004b0e <HAL_GPIO_WritePin>
|
|||
|
|
break;
|
|||
|
|
80013ee: e013 b.n 8001418 <SetAndCorrect+0x1a8>
|
|||
|
|
case Ku50: case Ku500: // 50, 500
|
|||
|
|
HAL_GPIO_WritePin(GPIOB, (A5_Pin | A6_Pin), GPIO_PIN_SET);
|
|||
|
|
80013f0: 4b75 ldr r3, [pc, #468] ; (80015c8 <SetAndCorrect+0x358>)
|
|||
|
|
80013f2: 2201 movs r2, #1
|
|||
|
|
80013f4: 2160 movs r1, #96 ; 0x60
|
|||
|
|
80013f6: 0018 movs r0, r3
|
|||
|
|
80013f8: f003 fb89 bl 8004b0e <HAL_GPIO_WritePin>
|
|||
|
|
HAL_GPIO_WritePin(GPIOB, A4_Pin, GPIO_PIN_RESET);
|
|||
|
|
80013fc: 4b72 ldr r3, [pc, #456] ; (80015c8 <SetAndCorrect+0x358>)
|
|||
|
|
80013fe: 2200 movs r2, #0
|
|||
|
|
8001400: 2110 movs r1, #16
|
|||
|
|
8001402: 0018 movs r0, r3
|
|||
|
|
8001404: f003 fb83 bl 8004b0e <HAL_GPIO_WritePin>
|
|||
|
|
break;
|
|||
|
|
8001408: e006 b.n 8001418 <SetAndCorrect+0x1a8>
|
|||
|
|
case Ku100: case Ku1000: // 100, 1000
|
|||
|
|
HAL_GPIO_WritePin(GPIOB, (A4_Pin | A5_Pin | A6_Pin), GPIO_PIN_SET);
|
|||
|
|
800140a: 4b6f ldr r3, [pc, #444] ; (80015c8 <SetAndCorrect+0x358>)
|
|||
|
|
800140c: 2201 movs r2, #1
|
|||
|
|
800140e: 2170 movs r1, #112 ; 0x70
|
|||
|
|
8001410: 0018 movs r0, r3
|
|||
|
|
8001412: f003 fb7c bl 8004b0e <HAL_GPIO_WritePin>
|
|||
|
|
break;
|
|||
|
|
8001416: 46c0 nop ; (mov r8, r8)
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
if(clbr)
|
|||
|
|
8001418: 4b6d ldr r3, [pc, #436] ; (80015d0 <SetAndCorrect+0x360>)
|
|||
|
|
800141a: 781b ldrb r3, [r3, #0]
|
|||
|
|
800141c: b2db uxtb r3, r3
|
|||
|
|
800141e: 2b00 cmp r3, #0
|
|||
|
|
8001420: d015 beq.n 800144e <SetAndCorrect+0x1de>
|
|||
|
|
{
|
|||
|
|
HAL_GPIO_WritePin(GPIOB, (A7_Pin | A8_Pin), GPIO_PIN_SET); //HP 2HZ
|
|||
|
|
8001422: 23c0 movs r3, #192 ; 0xc0
|
|||
|
|
8001424: 005b lsls r3, r3, #1
|
|||
|
|
8001426: 4868 ldr r0, [pc, #416] ; (80015c8 <SetAndCorrect+0x358>)
|
|||
|
|
8001428: 2201 movs r2, #1
|
|||
|
|
800142a: 0019 movs r1, r3
|
|||
|
|
800142c: f003 fb6f bl 8004b0e <HAL_GPIO_WritePin>
|
|||
|
|
HAL_GPIO_WritePin(GPIOB, A9_Pin, GPIO_PIN_RESET); //HP 2HZ
|
|||
|
|
8001430: 2380 movs r3, #128 ; 0x80
|
|||
|
|
8001432: 009b lsls r3, r3, #2
|
|||
|
|
8001434: 4864 ldr r0, [pc, #400] ; (80015c8 <SetAndCorrect+0x358>)
|
|||
|
|
8001436: 2200 movs r2, #0
|
|||
|
|
8001438: 0019 movs r1, r3
|
|||
|
|
800143a: f003 fb68 bl 8004b0e <HAL_GPIO_WritePin>
|
|||
|
|
HAL_GPIO_WritePin(GPIOB, (A10_Pin | A11_Pin | A12_Pin), GPIO_PIN_SET); //LP 100kHz
|
|||
|
|
800143e: 23e0 movs r3, #224 ; 0xe0
|
|||
|
|
8001440: 015b lsls r3, r3, #5
|
|||
|
|
8001442: 4861 ldr r0, [pc, #388] ; (80015c8 <SetAndCorrect+0x358>)
|
|||
|
|
8001444: 2201 movs r2, #1
|
|||
|
|
8001446: 0019 movs r1, r3
|
|||
|
|
8001448: f003 fb61 bl 8004b0e <HAL_GPIO_WritePin>
|
|||
|
|
800144c: e0ce b.n 80015ec <SetAndCorrect+0x37c>
|
|||
|
|
}
|
|||
|
|
else
|
|||
|
|
{
|
|||
|
|
switch(pardata.IFV) // HPF
|
|||
|
|
800144e: 4b5d ldr r3, [pc, #372] ; (80015c4 <SetAndCorrect+0x354>)
|
|||
|
|
8001450: 891b ldrh r3, [r3, #8]
|
|||
|
|
8001452: b29b uxth r3, r3
|
|||
|
|
8001454: 2b04 cmp r3, #4
|
|||
|
|
8001456: d847 bhi.n 80014e8 <SetAndCorrect+0x278>
|
|||
|
|
8001458: 009a lsls r2, r3, #2
|
|||
|
|
800145a: 4b5e ldr r3, [pc, #376] ; (80015d4 <SetAndCorrect+0x364>)
|
|||
|
|
800145c: 18d3 adds r3, r2, r3
|
|||
|
|
800145e: 681b ldr r3, [r3, #0]
|
|||
|
|
8001460: 469f mov pc, r3
|
|||
|
|
{
|
|||
|
|
case Hp0_2: // 0,2 Hz
|
|||
|
|
HAL_GPIO_WritePin(GPIOB, (A7_Pin | A8_Pin | A9_Pin), GPIO_PIN_RESET);
|
|||
|
|
8001462: 23e0 movs r3, #224 ; 0xe0
|
|||
|
|
8001464: 009b lsls r3, r3, #2
|
|||
|
|
8001466: 4858 ldr r0, [pc, #352] ; (80015c8 <SetAndCorrect+0x358>)
|
|||
|
|
8001468: 2200 movs r2, #0
|
|||
|
|
800146a: 0019 movs r1, r3
|
|||
|
|
800146c: f003 fb4f bl 8004b0e <HAL_GPIO_WritePin>
|
|||
|
|
break;
|
|||
|
|
8001470: e03a b.n 80014e8 <SetAndCorrect+0x278>
|
|||
|
|
case Hp0_3: // 0,3 Hz
|
|||
|
|
HAL_GPIO_WritePin(GPIOB, A7_Pin, GPIO_PIN_SET);
|
|||
|
|
8001472: 4b55 ldr r3, [pc, #340] ; (80015c8 <SetAndCorrect+0x358>)
|
|||
|
|
8001474: 2201 movs r2, #1
|
|||
|
|
8001476: 2180 movs r1, #128 ; 0x80
|
|||
|
|
8001478: 0018 movs r0, r3
|
|||
|
|
800147a: f003 fb48 bl 8004b0e <HAL_GPIO_WritePin>
|
|||
|
|
HAL_GPIO_WritePin(GPIOB, (A8_Pin | A9_Pin), GPIO_PIN_RESET);
|
|||
|
|
800147e: 23c0 movs r3, #192 ; 0xc0
|
|||
|
|
8001480: 009b lsls r3, r3, #2
|
|||
|
|
8001482: 4851 ldr r0, [pc, #324] ; (80015c8 <SetAndCorrect+0x358>)
|
|||
|
|
8001484: 2200 movs r2, #0
|
|||
|
|
8001486: 0019 movs r1, r3
|
|||
|
|
8001488: f003 fb41 bl 8004b0e <HAL_GPIO_WritePin>
|
|||
|
|
break;
|
|||
|
|
800148c: e02c b.n 80014e8 <SetAndCorrect+0x278>
|
|||
|
|
case Hp1: // 1 Hz
|
|||
|
|
HAL_GPIO_WritePin(GPIOB, A8_Pin, GPIO_PIN_SET);
|
|||
|
|
800148e: 2380 movs r3, #128 ; 0x80
|
|||
|
|
8001490: 005b lsls r3, r3, #1
|
|||
|
|
8001492: 484d ldr r0, [pc, #308] ; (80015c8 <SetAndCorrect+0x358>)
|
|||
|
|
8001494: 2201 movs r2, #1
|
|||
|
|
8001496: 0019 movs r1, r3
|
|||
|
|
8001498: f003 fb39 bl 8004b0e <HAL_GPIO_WritePin>
|
|||
|
|
HAL_GPIO_WritePin(GPIOB, (A7_Pin | A9_Pin), GPIO_PIN_RESET);
|
|||
|
|
800149c: 23a0 movs r3, #160 ; 0xa0
|
|||
|
|
800149e: 009b lsls r3, r3, #2
|
|||
|
|
80014a0: 4849 ldr r0, [pc, #292] ; (80015c8 <SetAndCorrect+0x358>)
|
|||
|
|
80014a2: 2200 movs r2, #0
|
|||
|
|
80014a4: 0019 movs r1, r3
|
|||
|
|
80014a6: f003 fb32 bl 8004b0e <HAL_GPIO_WritePin>
|
|||
|
|
break;
|
|||
|
|
80014aa: e01d b.n 80014e8 <SetAndCorrect+0x278>
|
|||
|
|
case Hp2: // 2 Hz
|
|||
|
|
HAL_GPIO_WritePin(GPIOB, (A7_Pin | A8_Pin), GPIO_PIN_SET);
|
|||
|
|
80014ac: 23c0 movs r3, #192 ; 0xc0
|
|||
|
|
80014ae: 005b lsls r3, r3, #1
|
|||
|
|
80014b0: 4845 ldr r0, [pc, #276] ; (80015c8 <SetAndCorrect+0x358>)
|
|||
|
|
80014b2: 2201 movs r2, #1
|
|||
|
|
80014b4: 0019 movs r1, r3
|
|||
|
|
80014b6: f003 fb2a bl 8004b0e <HAL_GPIO_WritePin>
|
|||
|
|
HAL_GPIO_WritePin(GPIOB, A9_Pin, GPIO_PIN_RESET);
|
|||
|
|
80014ba: 2380 movs r3, #128 ; 0x80
|
|||
|
|
80014bc: 009b lsls r3, r3, #2
|
|||
|
|
80014be: 4842 ldr r0, [pc, #264] ; (80015c8 <SetAndCorrect+0x358>)
|
|||
|
|
80014c0: 2200 movs r2, #0
|
|||
|
|
80014c2: 0019 movs r1, r3
|
|||
|
|
80014c4: f003 fb23 bl 8004b0e <HAL_GPIO_WritePin>
|
|||
|
|
break;
|
|||
|
|
80014c8: e00e b.n 80014e8 <SetAndCorrect+0x278>
|
|||
|
|
case Hp10: // 10 Hz
|
|||
|
|
HAL_GPIO_WritePin(GPIOB, A9_Pin, GPIO_PIN_SET);
|
|||
|
|
80014ca: 2380 movs r3, #128 ; 0x80
|
|||
|
|
80014cc: 009b lsls r3, r3, #2
|
|||
|
|
80014ce: 483e ldr r0, [pc, #248] ; (80015c8 <SetAndCorrect+0x358>)
|
|||
|
|
80014d0: 2201 movs r2, #1
|
|||
|
|
80014d2: 0019 movs r1, r3
|
|||
|
|
80014d4: f003 fb1b bl 8004b0e <HAL_GPIO_WritePin>
|
|||
|
|
HAL_GPIO_WritePin(GPIOB, (A7_Pin | A8_Pin), GPIO_PIN_RESET);
|
|||
|
|
80014d8: 23c0 movs r3, #192 ; 0xc0
|
|||
|
|
80014da: 005b lsls r3, r3, #1
|
|||
|
|
80014dc: 483a ldr r0, [pc, #232] ; (80015c8 <SetAndCorrect+0x358>)
|
|||
|
|
80014de: 2200 movs r2, #0
|
|||
|
|
80014e0: 0019 movs r1, r3
|
|||
|
|
80014e2: f003 fb14 bl 8004b0e <HAL_GPIO_WritePin>
|
|||
|
|
break;
|
|||
|
|
80014e6: 46c0 nop ; (mov r8, r8)
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
switch(pardata.IFN) //LPF
|
|||
|
|
80014e8: 4b36 ldr r3, [pc, #216] ; (80015c4 <SetAndCorrect+0x354>)
|
|||
|
|
80014ea: 895b ldrh r3, [r3, #10]
|
|||
|
|
80014ec: b29b uxth r3, r3
|
|||
|
|
80014ee: 2b07 cmp r3, #7
|
|||
|
|
80014f0: d900 bls.n 80014f4 <SetAndCorrect+0x284>
|
|||
|
|
80014f2: e07b b.n 80015ec <SetAndCorrect+0x37c>
|
|||
|
|
80014f4: 009a lsls r2, r3, #2
|
|||
|
|
80014f6: 4b38 ldr r3, [pc, #224] ; (80015d8 <SetAndCorrect+0x368>)
|
|||
|
|
80014f8: 18d3 adds r3, r2, r3
|
|||
|
|
80014fa: 681b ldr r3, [r3, #0]
|
|||
|
|
80014fc: 469f mov pc, r3
|
|||
|
|
{
|
|||
|
|
case Lp200: // 200 Hz
|
|||
|
|
HAL_GPIO_WritePin(GPIOB, (A10_Pin | A11_Pin | A12_Pin), GPIO_PIN_RESET);
|
|||
|
|
80014fe: 23e0 movs r3, #224 ; 0xe0
|
|||
|
|
8001500: 015b lsls r3, r3, #5
|
|||
|
|
8001502: 4831 ldr r0, [pc, #196] ; (80015c8 <SetAndCorrect+0x358>)
|
|||
|
|
8001504: 2200 movs r2, #0
|
|||
|
|
8001506: 0019 movs r1, r3
|
|||
|
|
8001508: f003 fb01 bl 8004b0e <HAL_GPIO_WritePin>
|
|||
|
|
break; // 500 Hz
|
|||
|
|
800150c: e06e b.n 80015ec <SetAndCorrect+0x37c>
|
|||
|
|
case Lp500:
|
|||
|
|
HAL_GPIO_WritePin(GPIOB, A10_Pin, GPIO_PIN_SET);
|
|||
|
|
800150e: 2380 movs r3, #128 ; 0x80
|
|||
|
|
8001510: 00db lsls r3, r3, #3
|
|||
|
|
8001512: 482d ldr r0, [pc, #180] ; (80015c8 <SetAndCorrect+0x358>)
|
|||
|
|
8001514: 2201 movs r2, #1
|
|||
|
|
8001516: 0019 movs r1, r3
|
|||
|
|
8001518: f003 faf9 bl 8004b0e <HAL_GPIO_WritePin>
|
|||
|
|
HAL_GPIO_WritePin(GPIOB, (A11_Pin | A12_Pin), GPIO_PIN_RESET);
|
|||
|
|
800151c: 23c0 movs r3, #192 ; 0xc0
|
|||
|
|
800151e: 015b lsls r3, r3, #5
|
|||
|
|
8001520: 4829 ldr r0, [pc, #164] ; (80015c8 <SetAndCorrect+0x358>)
|
|||
|
|
8001522: 2200 movs r2, #0
|
|||
|
|
8001524: 0019 movs r1, r3
|
|||
|
|
8001526: f003 faf2 bl 8004b0e <HAL_GPIO_WritePin>
|
|||
|
|
break;
|
|||
|
|
800152a: e05f b.n 80015ec <SetAndCorrect+0x37c>
|
|||
|
|
case Lp1000: // 1 kHz
|
|||
|
|
HAL_GPIO_WritePin(GPIOB, A11_Pin, GPIO_PIN_SET);
|
|||
|
|
800152c: 2380 movs r3, #128 ; 0x80
|
|||
|
|
800152e: 011b lsls r3, r3, #4
|
|||
|
|
8001530: 4825 ldr r0, [pc, #148] ; (80015c8 <SetAndCorrect+0x358>)
|
|||
|
|
8001532: 2201 movs r2, #1
|
|||
|
|
8001534: 0019 movs r1, r3
|
|||
|
|
8001536: f003 faea bl 8004b0e <HAL_GPIO_WritePin>
|
|||
|
|
HAL_GPIO_WritePin(GPIOB, (A10_Pin | A12_Pin), GPIO_PIN_RESET);
|
|||
|
|
800153a: 23a0 movs r3, #160 ; 0xa0
|
|||
|
|
800153c: 015b lsls r3, r3, #5
|
|||
|
|
800153e: 4822 ldr r0, [pc, #136] ; (80015c8 <SetAndCorrect+0x358>)
|
|||
|
|
8001540: 2200 movs r2, #0
|
|||
|
|
8001542: 0019 movs r1, r3
|
|||
|
|
8001544: f003 fae3 bl 8004b0e <HAL_GPIO_WritePin>
|
|||
|
|
break;
|
|||
|
|
8001548: e050 b.n 80015ec <SetAndCorrect+0x37c>
|
|||
|
|
case Lp5000: // 5 kHz
|
|||
|
|
HAL_GPIO_WritePin(GPIOB, (A10_Pin | A11_Pin), GPIO_PIN_SET);
|
|||
|
|
800154a: 23c0 movs r3, #192 ; 0xc0
|
|||
|
|
800154c: 011b lsls r3, r3, #4
|
|||
|
|
800154e: 481e ldr r0, [pc, #120] ; (80015c8 <SetAndCorrect+0x358>)
|
|||
|
|
8001550: 2201 movs r2, #1
|
|||
|
|
8001552: 0019 movs r1, r3
|
|||
|
|
8001554: f003 fadb bl 8004b0e <HAL_GPIO_WritePin>
|
|||
|
|
HAL_GPIO_WritePin(GPIOB, A12_Pin, GPIO_PIN_RESET);
|
|||
|
|
8001558: 2380 movs r3, #128 ; 0x80
|
|||
|
|
800155a: 015b lsls r3, r3, #5
|
|||
|
|
800155c: 481a ldr r0, [pc, #104] ; (80015c8 <SetAndCorrect+0x358>)
|
|||
|
|
800155e: 2200 movs r2, #0
|
|||
|
|
8001560: 0019 movs r1, r3
|
|||
|
|
8001562: f003 fad4 bl 8004b0e <HAL_GPIO_WritePin>
|
|||
|
|
break;
|
|||
|
|
8001566: e041 b.n 80015ec <SetAndCorrect+0x37c>
|
|||
|
|
case Lp10000: // 10 kHz
|
|||
|
|
HAL_GPIO_WritePin(GPIOB, A12_Pin, GPIO_PIN_SET);
|
|||
|
|
8001568: 2380 movs r3, #128 ; 0x80
|
|||
|
|
800156a: 015b lsls r3, r3, #5
|
|||
|
|
800156c: 4816 ldr r0, [pc, #88] ; (80015c8 <SetAndCorrect+0x358>)
|
|||
|
|
800156e: 2201 movs r2, #1
|
|||
|
|
8001570: 0019 movs r1, r3
|
|||
|
|
8001572: f003 facc bl 8004b0e <HAL_GPIO_WritePin>
|
|||
|
|
HAL_GPIO_WritePin(GPIOB, (A10_Pin | A11_Pin), GPIO_PIN_RESET);
|
|||
|
|
8001576: 23c0 movs r3, #192 ; 0xc0
|
|||
|
|
8001578: 011b lsls r3, r3, #4
|
|||
|
|
800157a: 4813 ldr r0, [pc, #76] ; (80015c8 <SetAndCorrect+0x358>)
|
|||
|
|
800157c: 2200 movs r2, #0
|
|||
|
|
800157e: 0019 movs r1, r3
|
|||
|
|
8001580: f003 fac5 bl 8004b0e <HAL_GPIO_WritePin>
|
|||
|
|
break;
|
|||
|
|
8001584: e032 b.n 80015ec <SetAndCorrect+0x37c>
|
|||
|
|
case Lp20000: // 20 kHz
|
|||
|
|
HAL_GPIO_WritePin(GPIOB, (A12_Pin | A10_Pin), GPIO_PIN_SET);
|
|||
|
|
8001586: 23a0 movs r3, #160 ; 0xa0
|
|||
|
|
8001588: 015b lsls r3, r3, #5
|
|||
|
|
800158a: 480f ldr r0, [pc, #60] ; (80015c8 <SetAndCorrect+0x358>)
|
|||
|
|
800158c: 2201 movs r2, #1
|
|||
|
|
800158e: 0019 movs r1, r3
|
|||
|
|
8001590: f003 fabd bl 8004b0e <HAL_GPIO_WritePin>
|
|||
|
|
HAL_GPIO_WritePin(GPIOB, A11_Pin, GPIO_PIN_RESET);
|
|||
|
|
8001594: 2380 movs r3, #128 ; 0x80
|
|||
|
|
8001596: 011b lsls r3, r3, #4
|
|||
|
|
8001598: 480b ldr r0, [pc, #44] ; (80015c8 <SetAndCorrect+0x358>)
|
|||
|
|
800159a: 2200 movs r2, #0
|
|||
|
|
800159c: 0019 movs r1, r3
|
|||
|
|
800159e: f003 fab6 bl 8004b0e <HAL_GPIO_WritePin>
|
|||
|
|
break;
|
|||
|
|
80015a2: e023 b.n 80015ec <SetAndCorrect+0x37c>
|
|||
|
|
case Lp50000: // 50 kHz
|
|||
|
|
HAL_GPIO_WritePin(GPIOB, (A12_Pin | A11_Pin), GPIO_PIN_SET);
|
|||
|
|
80015a4: 23c0 movs r3, #192 ; 0xc0
|
|||
|
|
80015a6: 015b lsls r3, r3, #5
|
|||
|
|
80015a8: 4807 ldr r0, [pc, #28] ; (80015c8 <SetAndCorrect+0x358>)
|
|||
|
|
80015aa: 2201 movs r2, #1
|
|||
|
|
80015ac: 0019 movs r1, r3
|
|||
|
|
80015ae: f003 faae bl 8004b0e <HAL_GPIO_WritePin>
|
|||
|
|
HAL_GPIO_WritePin(GPIOB, A10_Pin, GPIO_PIN_RESET);
|
|||
|
|
80015b2: 2380 movs r3, #128 ; 0x80
|
|||
|
|
80015b4: 00db lsls r3, r3, #3
|
|||
|
|
80015b6: 4804 ldr r0, [pc, #16] ; (80015c8 <SetAndCorrect+0x358>)
|
|||
|
|
80015b8: 2200 movs r2, #0
|
|||
|
|
80015ba: 0019 movs r1, r3
|
|||
|
|
80015bc: f003 faa7 bl 8004b0e <HAL_GPIO_WritePin>
|
|||
|
|
break;
|
|||
|
|
80015c0: e014 b.n 80015ec <SetAndCorrect+0x37c>
|
|||
|
|
80015c2: 46c0 nop ; (mov r8, r8)
|
|||
|
|
80015c4: 20000098 .word 0x20000098
|
|||
|
|
80015c8: 50000400 .word 0x50000400
|
|||
|
|
80015cc: 080070a8 .word 0x080070a8
|
|||
|
|
80015d0: 20000034 .word 0x20000034
|
|||
|
|
80015d4: 080070dc .word 0x080070dc
|
|||
|
|
80015d8: 080070f0 .word 0x080070f0
|
|||
|
|
case Lp100000: // 100 kHz
|
|||
|
|
HAL_GPIO_WritePin(GPIOB, (A10_Pin | A11_Pin | A12_Pin), GPIO_PIN_SET);
|
|||
|
|
80015dc: 23e0 movs r3, #224 ; 0xe0
|
|||
|
|
80015de: 015b lsls r3, r3, #5
|
|||
|
|
80015e0: 48a6 ldr r0, [pc, #664] ; (800187c <SetAndCorrect+0x60c>)
|
|||
|
|
80015e2: 2201 movs r2, #1
|
|||
|
|
80015e4: 0019 movs r1, r3
|
|||
|
|
80015e6: f003 fa92 bl 8004b0e <HAL_GPIO_WritePin>
|
|||
|
|
break;
|
|||
|
|
80015ea: 46c0 nop ; (mov r8, r8)
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
|
|||
|
|
fKU = (float) CorrWord[pardata.IIN][pardata.IKU];
|
|||
|
|
80015ec: 4ba4 ldr r3, [pc, #656] ; (8001880 <SetAndCorrect+0x610>)
|
|||
|
|
80015ee: 88db ldrh r3, [r3, #6]
|
|||
|
|
80015f0: b29b uxth r3, r3
|
|||
|
|
80015f2: 0019 movs r1, r3
|
|||
|
|
80015f4: 4ba2 ldr r3, [pc, #648] ; (8001880 <SetAndCorrect+0x610>)
|
|||
|
|
80015f6: 899b ldrh r3, [r3, #12]
|
|||
|
|
80015f8: b29b uxth r3, r3
|
|||
|
|
80015fa: 0018 movs r0, r3
|
|||
|
|
80015fc: 4aa1 ldr r2, [pc, #644] ; (8001884 <SetAndCorrect+0x614>)
|
|||
|
|
80015fe: 000b movs r3, r1
|
|||
|
|
8001600: 009b lsls r3, r3, #2
|
|||
|
|
8001602: 185b adds r3, r3, r1
|
|||
|
|
8001604: 009b lsls r3, r3, #2
|
|||
|
|
8001606: 181b adds r3, r3, r0
|
|||
|
|
8001608: 005b lsls r3, r3, #1
|
|||
|
|
800160a: 5a9b ldrh r3, [r3, r2]
|
|||
|
|
800160c: b29b uxth r3, r3
|
|||
|
|
800160e: 0018 movs r0, r3
|
|||
|
|
8001610: f7ff fc6c bl 8000eec <__aeabi_ui2f>
|
|||
|
|
8001614: 1c03 adds r3, r0, #0
|
|||
|
|
8001616: 607b str r3, [r7, #4]
|
|||
|
|
if(DVD > 0xfff) {
|
|||
|
|
DVD = 0xfff;
|
|||
|
|
}
|
|||
|
|
*/
|
|||
|
|
|
|||
|
|
if (pardata.SENS>=0.0001&&pardata.SENS<0.001) {OffsetKuDisplay=0; kNormToDAC=pardata.SENS*10000;} // <20><><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
|||
|
|
8001618: 4b99 ldr r3, [pc, #612] ; (8001880 <SetAndCorrect+0x610>)
|
|||
|
|
800161a: 6a1b ldr r3, [r3, #32]
|
|||
|
|
800161c: 1c18 adds r0, r3, #0
|
|||
|
|
800161e: f7ff fdab bl 8001178 <__aeabi_f2d>
|
|||
|
|
8001622: 4a99 ldr r2, [pc, #612] ; (8001888 <SetAndCorrect+0x618>)
|
|||
|
|
8001624: 4b99 ldr r3, [pc, #612] ; (800188c <SetAndCorrect+0x61c>)
|
|||
|
|
8001626: f7fe fe2f bl 8000288 <__aeabi_dcmpge>
|
|||
|
|
800162a: 1e03 subs r3, r0, #0
|
|||
|
|
800162c: d018 beq.n 8001660 <SetAndCorrect+0x3f0>
|
|||
|
|
800162e: 4b94 ldr r3, [pc, #592] ; (8001880 <SetAndCorrect+0x610>)
|
|||
|
|
8001630: 6a1b ldr r3, [r3, #32]
|
|||
|
|
8001632: 1c18 adds r0, r3, #0
|
|||
|
|
8001634: f7ff fda0 bl 8001178 <__aeabi_f2d>
|
|||
|
|
8001638: 4a95 ldr r2, [pc, #596] ; (8001890 <SetAndCorrect+0x620>)
|
|||
|
|
800163a: 4b96 ldr r3, [pc, #600] ; (8001894 <SetAndCorrect+0x624>)
|
|||
|
|
800163c: f7fe fe06 bl 800024c <__aeabi_dcmplt>
|
|||
|
|
8001640: 1e03 subs r3, r0, #0
|
|||
|
|
8001642: d00d beq.n 8001660 <SetAndCorrect+0x3f0>
|
|||
|
|
8001644: 4b94 ldr r3, [pc, #592] ; (8001898 <SetAndCorrect+0x628>)
|
|||
|
|
8001646: 2200 movs r2, #0
|
|||
|
|
8001648: 601a str r2, [r3, #0]
|
|||
|
|
800164a: 4b8d ldr r3, [pc, #564] ; (8001880 <SetAndCorrect+0x610>)
|
|||
|
|
800164c: 6a1b ldr r3, [r3, #32]
|
|||
|
|
800164e: 4993 ldr r1, [pc, #588] ; (800189c <SetAndCorrect+0x62c>)
|
|||
|
|
8001650: 1c18 adds r0, r3, #0
|
|||
|
|
8001652: f7ff f96f bl 8000934 <__aeabi_fmul>
|
|||
|
|
8001656: 1c03 adds r3, r0, #0
|
|||
|
|
8001658: 1c1a adds r2, r3, #0
|
|||
|
|
800165a: 4b91 ldr r3, [pc, #580] ; (80018a0 <SetAndCorrect+0x630>)
|
|||
|
|
800165c: 601a str r2, [r3, #0]
|
|||
|
|
800165e: e0f9 b.n 8001854 <SetAndCorrect+0x5e4>
|
|||
|
|
else if (pardata.SENS>=0.001&&pardata.SENS<0.01){OffsetKuDisplay=0; kNormToDAC=pardata.SENS*1000;}
|
|||
|
|
8001660: 4b87 ldr r3, [pc, #540] ; (8001880 <SetAndCorrect+0x610>)
|
|||
|
|
8001662: 6a1b ldr r3, [r3, #32]
|
|||
|
|
8001664: 1c18 adds r0, r3, #0
|
|||
|
|
8001666: f7ff fd87 bl 8001178 <__aeabi_f2d>
|
|||
|
|
800166a: 4a89 ldr r2, [pc, #548] ; (8001890 <SetAndCorrect+0x620>)
|
|||
|
|
800166c: 4b89 ldr r3, [pc, #548] ; (8001894 <SetAndCorrect+0x624>)
|
|||
|
|
800166e: f7fe fe0b bl 8000288 <__aeabi_dcmpge>
|
|||
|
|
8001672: 1e03 subs r3, r0, #0
|
|||
|
|
8001674: d018 beq.n 80016a8 <SetAndCorrect+0x438>
|
|||
|
|
8001676: 4b82 ldr r3, [pc, #520] ; (8001880 <SetAndCorrect+0x610>)
|
|||
|
|
8001678: 6a1b ldr r3, [r3, #32]
|
|||
|
|
800167a: 1c18 adds r0, r3, #0
|
|||
|
|
800167c: f7ff fd7c bl 8001178 <__aeabi_f2d>
|
|||
|
|
8001680: 4a88 ldr r2, [pc, #544] ; (80018a4 <SetAndCorrect+0x634>)
|
|||
|
|
8001682: 4b89 ldr r3, [pc, #548] ; (80018a8 <SetAndCorrect+0x638>)
|
|||
|
|
8001684: f7fe fde2 bl 800024c <__aeabi_dcmplt>
|
|||
|
|
8001688: 1e03 subs r3, r0, #0
|
|||
|
|
800168a: d00d beq.n 80016a8 <SetAndCorrect+0x438>
|
|||
|
|
800168c: 4b82 ldr r3, [pc, #520] ; (8001898 <SetAndCorrect+0x628>)
|
|||
|
|
800168e: 2200 movs r2, #0
|
|||
|
|
8001690: 601a str r2, [r3, #0]
|
|||
|
|
8001692: 4b7b ldr r3, [pc, #492] ; (8001880 <SetAndCorrect+0x610>)
|
|||
|
|
8001694: 6a1b ldr r3, [r3, #32]
|
|||
|
|
8001696: 4985 ldr r1, [pc, #532] ; (80018ac <SetAndCorrect+0x63c>)
|
|||
|
|
8001698: 1c18 adds r0, r3, #0
|
|||
|
|
800169a: f7ff f94b bl 8000934 <__aeabi_fmul>
|
|||
|
|
800169e: 1c03 adds r3, r0, #0
|
|||
|
|
80016a0: 1c1a adds r2, r3, #0
|
|||
|
|
80016a2: 4b7f ldr r3, [pc, #508] ; (80018a0 <SetAndCorrect+0x630>)
|
|||
|
|
80016a4: 601a str r2, [r3, #0]
|
|||
|
|
80016a6: e0d5 b.n 8001854 <SetAndCorrect+0x5e4>
|
|||
|
|
else if (pardata.SENS>=0.01&&pardata.SENS<0.1){OffsetKuDisplay=3; kNormToDAC=pardata.SENS*100;}
|
|||
|
|
80016a8: 4b75 ldr r3, [pc, #468] ; (8001880 <SetAndCorrect+0x610>)
|
|||
|
|
80016aa: 6a1b ldr r3, [r3, #32]
|
|||
|
|
80016ac: 1c18 adds r0, r3, #0
|
|||
|
|
80016ae: f7ff fd63 bl 8001178 <__aeabi_f2d>
|
|||
|
|
80016b2: 4a7c ldr r2, [pc, #496] ; (80018a4 <SetAndCorrect+0x634>)
|
|||
|
|
80016b4: 4b7c ldr r3, [pc, #496] ; (80018a8 <SetAndCorrect+0x638>)
|
|||
|
|
80016b6: f7fe fde7 bl 8000288 <__aeabi_dcmpge>
|
|||
|
|
80016ba: 1e03 subs r3, r0, #0
|
|||
|
|
80016bc: d018 beq.n 80016f0 <SetAndCorrect+0x480>
|
|||
|
|
80016be: 4b70 ldr r3, [pc, #448] ; (8001880 <SetAndCorrect+0x610>)
|
|||
|
|
80016c0: 6a1b ldr r3, [r3, #32]
|
|||
|
|
80016c2: 1c18 adds r0, r3, #0
|
|||
|
|
80016c4: f7ff fd58 bl 8001178 <__aeabi_f2d>
|
|||
|
|
80016c8: 4a79 ldr r2, [pc, #484] ; (80018b0 <SetAndCorrect+0x640>)
|
|||
|
|
80016ca: 4b7a ldr r3, [pc, #488] ; (80018b4 <SetAndCorrect+0x644>)
|
|||
|
|
80016cc: f7fe fdbe bl 800024c <__aeabi_dcmplt>
|
|||
|
|
80016d0: 1e03 subs r3, r0, #0
|
|||
|
|
80016d2: d00d beq.n 80016f0 <SetAndCorrect+0x480>
|
|||
|
|
80016d4: 4b70 ldr r3, [pc, #448] ; (8001898 <SetAndCorrect+0x628>)
|
|||
|
|
80016d6: 2203 movs r2, #3
|
|||
|
|
80016d8: 601a str r2, [r3, #0]
|
|||
|
|
80016da: 4b69 ldr r3, [pc, #420] ; (8001880 <SetAndCorrect+0x610>)
|
|||
|
|
80016dc: 6a1b ldr r3, [r3, #32]
|
|||
|
|
80016de: 4976 ldr r1, [pc, #472] ; (80018b8 <SetAndCorrect+0x648>)
|
|||
|
|
80016e0: 1c18 adds r0, r3, #0
|
|||
|
|
80016e2: f7ff f927 bl 8000934 <__aeabi_fmul>
|
|||
|
|
80016e6: 1c03 adds r3, r0, #0
|
|||
|
|
80016e8: 1c1a adds r2, r3, #0
|
|||
|
|
80016ea: 4b6d ldr r3, [pc, #436] ; (80018a0 <SetAndCorrect+0x630>)
|
|||
|
|
80016ec: 601a str r2, [r3, #0]
|
|||
|
|
80016ee: e0b1 b.n 8001854 <SetAndCorrect+0x5e4>
|
|||
|
|
else if (pardata.SENS>=0.1&&pardata.SENS<1){OffsetKuDisplay=6; kNormToDAC=pardata.SENS*10;}
|
|||
|
|
80016f0: 4b63 ldr r3, [pc, #396] ; (8001880 <SetAndCorrect+0x610>)
|
|||
|
|
80016f2: 6a1b ldr r3, [r3, #32]
|
|||
|
|
80016f4: 1c18 adds r0, r3, #0
|
|||
|
|
80016f6: f7ff fd3f bl 8001178 <__aeabi_f2d>
|
|||
|
|
80016fa: 4a6d ldr r2, [pc, #436] ; (80018b0 <SetAndCorrect+0x640>)
|
|||
|
|
80016fc: 4b6d ldr r3, [pc, #436] ; (80018b4 <SetAndCorrect+0x644>)
|
|||
|
|
80016fe: f7fe fdc3 bl 8000288 <__aeabi_dcmpge>
|
|||
|
|
8001702: 1e03 subs r3, r0, #0
|
|||
|
|
8001704: d016 beq.n 8001734 <SetAndCorrect+0x4c4>
|
|||
|
|
8001706: 4b5e ldr r3, [pc, #376] ; (8001880 <SetAndCorrect+0x610>)
|
|||
|
|
8001708: 6a1b ldr r3, [r3, #32]
|
|||
|
|
800170a: 21fe movs r1, #254 ; 0xfe
|
|||
|
|
800170c: 0589 lsls r1, r1, #22
|
|||
|
|
800170e: 1c18 adds r0, r3, #0
|
|||
|
|
8001710: f7fe fdd6 bl 80002c0 <__aeabi_fcmplt>
|
|||
|
|
8001714: 1e03 subs r3, r0, #0
|
|||
|
|
8001716: d00d beq.n 8001734 <SetAndCorrect+0x4c4>
|
|||
|
|
8001718: 4b5f ldr r3, [pc, #380] ; (8001898 <SetAndCorrect+0x628>)
|
|||
|
|
800171a: 2206 movs r2, #6
|
|||
|
|
800171c: 601a str r2, [r3, #0]
|
|||
|
|
800171e: 4b58 ldr r3, [pc, #352] ; (8001880 <SetAndCorrect+0x610>)
|
|||
|
|
8001720: 6a1b ldr r3, [r3, #32]
|
|||
|
|
8001722: 4966 ldr r1, [pc, #408] ; (80018bc <SetAndCorrect+0x64c>)
|
|||
|
|
8001724: 1c18 adds r0, r3, #0
|
|||
|
|
8001726: f7ff f905 bl 8000934 <__aeabi_fmul>
|
|||
|
|
800172a: 1c03 adds r3, r0, #0
|
|||
|
|
800172c: 1c1a adds r2, r3, #0
|
|||
|
|
800172e: 4b5c ldr r3, [pc, #368] ; (80018a0 <SetAndCorrect+0x630>)
|
|||
|
|
8001730: 601a str r2, [r3, #0]
|
|||
|
|
8001732: e08f b.n 8001854 <SetAndCorrect+0x5e4>
|
|||
|
|
else if (pardata.SENS>=1&&pardata.SENS<10){OffsetKuDisplay=9; kNormToDAC=pardata.SENS/1;}
|
|||
|
|
8001734: 4b52 ldr r3, [pc, #328] ; (8001880 <SetAndCorrect+0x610>)
|
|||
|
|
8001736: 6a1b ldr r3, [r3, #32]
|
|||
|
|
8001738: 21fe movs r1, #254 ; 0xfe
|
|||
|
|
800173a: 0589 lsls r1, r1, #22
|
|||
|
|
800173c: 1c18 adds r0, r3, #0
|
|||
|
|
800173e: f7fe fddd bl 80002fc <__aeabi_fcmpge>
|
|||
|
|
8001742: 1e03 subs r3, r0, #0
|
|||
|
|
8001744: d00f beq.n 8001766 <SetAndCorrect+0x4f6>
|
|||
|
|
8001746: 4b4e ldr r3, [pc, #312] ; (8001880 <SetAndCorrect+0x610>)
|
|||
|
|
8001748: 6a1b ldr r3, [r3, #32]
|
|||
|
|
800174a: 495c ldr r1, [pc, #368] ; (80018bc <SetAndCorrect+0x64c>)
|
|||
|
|
800174c: 1c18 adds r0, r3, #0
|
|||
|
|
800174e: f7fe fdb7 bl 80002c0 <__aeabi_fcmplt>
|
|||
|
|
8001752: 1e03 subs r3, r0, #0
|
|||
|
|
8001754: d007 beq.n 8001766 <SetAndCorrect+0x4f6>
|
|||
|
|
8001756: 4b50 ldr r3, [pc, #320] ; (8001898 <SetAndCorrect+0x628>)
|
|||
|
|
8001758: 2209 movs r2, #9
|
|||
|
|
800175a: 601a str r2, [r3, #0]
|
|||
|
|
800175c: 4b48 ldr r3, [pc, #288] ; (8001880 <SetAndCorrect+0x610>)
|
|||
|
|
800175e: 6a1a ldr r2, [r3, #32]
|
|||
|
|
8001760: 4b4f ldr r3, [pc, #316] ; (80018a0 <SetAndCorrect+0x630>)
|
|||
|
|
8001762: 601a str r2, [r3, #0]
|
|||
|
|
8001764: e076 b.n 8001854 <SetAndCorrect+0x5e4>
|
|||
|
|
else if (pardata.SENS>=10&&pardata.SENS<100){OffsetKuDisplay=12; kNormToDAC=pardata.SENS/10;}
|
|||
|
|
8001766: 4b46 ldr r3, [pc, #280] ; (8001880 <SetAndCorrect+0x610>)
|
|||
|
|
8001768: 6a1b ldr r3, [r3, #32]
|
|||
|
|
800176a: 4954 ldr r1, [pc, #336] ; (80018bc <SetAndCorrect+0x64c>)
|
|||
|
|
800176c: 1c18 adds r0, r3, #0
|
|||
|
|
800176e: f7fe fdc5 bl 80002fc <__aeabi_fcmpge>
|
|||
|
|
8001772: 1e03 subs r3, r0, #0
|
|||
|
|
8001774: d015 beq.n 80017a2 <SetAndCorrect+0x532>
|
|||
|
|
8001776: 4b42 ldr r3, [pc, #264] ; (8001880 <SetAndCorrect+0x610>)
|
|||
|
|
8001778: 6a1b ldr r3, [r3, #32]
|
|||
|
|
800177a: 494f ldr r1, [pc, #316] ; (80018b8 <SetAndCorrect+0x648>)
|
|||
|
|
800177c: 1c18 adds r0, r3, #0
|
|||
|
|
800177e: f7fe fd9f bl 80002c0 <__aeabi_fcmplt>
|
|||
|
|
8001782: 1e03 subs r3, r0, #0
|
|||
|
|
8001784: d00d beq.n 80017a2 <SetAndCorrect+0x532>
|
|||
|
|
8001786: 4b44 ldr r3, [pc, #272] ; (8001898 <SetAndCorrect+0x628>)
|
|||
|
|
8001788: 220c movs r2, #12
|
|||
|
|
800178a: 601a str r2, [r3, #0]
|
|||
|
|
800178c: 4b3c ldr r3, [pc, #240] ; (8001880 <SetAndCorrect+0x610>)
|
|||
|
|
800178e: 6a1b ldr r3, [r3, #32]
|
|||
|
|
8001790: 494a ldr r1, [pc, #296] ; (80018bc <SetAndCorrect+0x64c>)
|
|||
|
|
8001792: 1c18 adds r0, r3, #0
|
|||
|
|
8001794: f7fe fede bl 8000554 <__aeabi_fdiv>
|
|||
|
|
8001798: 1c03 adds r3, r0, #0
|
|||
|
|
800179a: 1c1a adds r2, r3, #0
|
|||
|
|
800179c: 4b40 ldr r3, [pc, #256] ; (80018a0 <SetAndCorrect+0x630>)
|
|||
|
|
800179e: 601a str r2, [r3, #0]
|
|||
|
|
80017a0: e058 b.n 8001854 <SetAndCorrect+0x5e4>
|
|||
|
|
else if (pardata.SENS>=100&&pardata.SENS<1000){OffsetKuDisplay=15; kNormToDAC=pardata.SENS/100;}
|
|||
|
|
80017a2: 4b37 ldr r3, [pc, #220] ; (8001880 <SetAndCorrect+0x610>)
|
|||
|
|
80017a4: 6a1b ldr r3, [r3, #32]
|
|||
|
|
80017a6: 4944 ldr r1, [pc, #272] ; (80018b8 <SetAndCorrect+0x648>)
|
|||
|
|
80017a8: 1c18 adds r0, r3, #0
|
|||
|
|
80017aa: f7fe fda7 bl 80002fc <__aeabi_fcmpge>
|
|||
|
|
80017ae: 1e03 subs r3, r0, #0
|
|||
|
|
80017b0: d015 beq.n 80017de <SetAndCorrect+0x56e>
|
|||
|
|
80017b2: 4b33 ldr r3, [pc, #204] ; (8001880 <SetAndCorrect+0x610>)
|
|||
|
|
80017b4: 6a1b ldr r3, [r3, #32]
|
|||
|
|
80017b6: 493d ldr r1, [pc, #244] ; (80018ac <SetAndCorrect+0x63c>)
|
|||
|
|
80017b8: 1c18 adds r0, r3, #0
|
|||
|
|
80017ba: f7fe fd81 bl 80002c0 <__aeabi_fcmplt>
|
|||
|
|
80017be: 1e03 subs r3, r0, #0
|
|||
|
|
80017c0: d00d beq.n 80017de <SetAndCorrect+0x56e>
|
|||
|
|
80017c2: 4b35 ldr r3, [pc, #212] ; (8001898 <SetAndCorrect+0x628>)
|
|||
|
|
80017c4: 220f movs r2, #15
|
|||
|
|
80017c6: 601a str r2, [r3, #0]
|
|||
|
|
80017c8: 4b2d ldr r3, [pc, #180] ; (8001880 <SetAndCorrect+0x610>)
|
|||
|
|
80017ca: 6a1b ldr r3, [r3, #32]
|
|||
|
|
80017cc: 493a ldr r1, [pc, #232] ; (80018b8 <SetAndCorrect+0x648>)
|
|||
|
|
80017ce: 1c18 adds r0, r3, #0
|
|||
|
|
80017d0: f7fe fec0 bl 8000554 <__aeabi_fdiv>
|
|||
|
|
80017d4: 1c03 adds r3, r0, #0
|
|||
|
|
80017d6: 1c1a adds r2, r3, #0
|
|||
|
|
80017d8: 4b31 ldr r3, [pc, #196] ; (80018a0 <SetAndCorrect+0x630>)
|
|||
|
|
80017da: 601a str r2, [r3, #0]
|
|||
|
|
80017dc: e03a b.n 8001854 <SetAndCorrect+0x5e4>
|
|||
|
|
else if (pardata.SENS>=1000&&pardata.SENS<10000){OffsetKuDisplay=18; kNormToDAC=pardata.SENS/1000;}
|
|||
|
|
80017de: 4b28 ldr r3, [pc, #160] ; (8001880 <SetAndCorrect+0x610>)
|
|||
|
|
80017e0: 6a1b ldr r3, [r3, #32]
|
|||
|
|
80017e2: 4932 ldr r1, [pc, #200] ; (80018ac <SetAndCorrect+0x63c>)
|
|||
|
|
80017e4: 1c18 adds r0, r3, #0
|
|||
|
|
80017e6: f7fe fd89 bl 80002fc <__aeabi_fcmpge>
|
|||
|
|
80017ea: 1e03 subs r3, r0, #0
|
|||
|
|
80017ec: d015 beq.n 800181a <SetAndCorrect+0x5aa>
|
|||
|
|
80017ee: 4b24 ldr r3, [pc, #144] ; (8001880 <SetAndCorrect+0x610>)
|
|||
|
|
80017f0: 6a1b ldr r3, [r3, #32]
|
|||
|
|
80017f2: 492a ldr r1, [pc, #168] ; (800189c <SetAndCorrect+0x62c>)
|
|||
|
|
80017f4: 1c18 adds r0, r3, #0
|
|||
|
|
80017f6: f7fe fd63 bl 80002c0 <__aeabi_fcmplt>
|
|||
|
|
80017fa: 1e03 subs r3, r0, #0
|
|||
|
|
80017fc: d00d beq.n 800181a <SetAndCorrect+0x5aa>
|
|||
|
|
80017fe: 4b26 ldr r3, [pc, #152] ; (8001898 <SetAndCorrect+0x628>)
|
|||
|
|
8001800: 2212 movs r2, #18
|
|||
|
|
8001802: 601a str r2, [r3, #0]
|
|||
|
|
8001804: 4b1e ldr r3, [pc, #120] ; (8001880 <SetAndCorrect+0x610>)
|
|||
|
|
8001806: 6a1b ldr r3, [r3, #32]
|
|||
|
|
8001808: 4928 ldr r1, [pc, #160] ; (80018ac <SetAndCorrect+0x63c>)
|
|||
|
|
800180a: 1c18 adds r0, r3, #0
|
|||
|
|
800180c: f7fe fea2 bl 8000554 <__aeabi_fdiv>
|
|||
|
|
8001810: 1c03 adds r3, r0, #0
|
|||
|
|
8001812: 1c1a adds r2, r3, #0
|
|||
|
|
8001814: 4b22 ldr r3, [pc, #136] ; (80018a0 <SetAndCorrect+0x630>)
|
|||
|
|
8001816: 601a str r2, [r3, #0]
|
|||
|
|
8001818: e01c b.n 8001854 <SetAndCorrect+0x5e4>
|
|||
|
|
else if (pardata.SENS>=10000&&pardata.SENS<100000){OffsetKuDisplay=21; kNormToDAC=pardata.SENS/10000;}
|
|||
|
|
800181a: 4b19 ldr r3, [pc, #100] ; (8001880 <SetAndCorrect+0x610>)
|
|||
|
|
800181c: 6a1b ldr r3, [r3, #32]
|
|||
|
|
800181e: 491f ldr r1, [pc, #124] ; (800189c <SetAndCorrect+0x62c>)
|
|||
|
|
8001820: 1c18 adds r0, r3, #0
|
|||
|
|
8001822: f7fe fd6b bl 80002fc <__aeabi_fcmpge>
|
|||
|
|
8001826: 1e03 subs r3, r0, #0
|
|||
|
|
8001828: d014 beq.n 8001854 <SetAndCorrect+0x5e4>
|
|||
|
|
800182a: 4b15 ldr r3, [pc, #84] ; (8001880 <SetAndCorrect+0x610>)
|
|||
|
|
800182c: 6a1b ldr r3, [r3, #32]
|
|||
|
|
800182e: 4924 ldr r1, [pc, #144] ; (80018c0 <SetAndCorrect+0x650>)
|
|||
|
|
8001830: 1c18 adds r0, r3, #0
|
|||
|
|
8001832: f7fe fd45 bl 80002c0 <__aeabi_fcmplt>
|
|||
|
|
8001836: 1e03 subs r3, r0, #0
|
|||
|
|
8001838: d00c beq.n 8001854 <SetAndCorrect+0x5e4>
|
|||
|
|
800183a: 4b17 ldr r3, [pc, #92] ; (8001898 <SetAndCorrect+0x628>)
|
|||
|
|
800183c: 2215 movs r2, #21
|
|||
|
|
800183e: 601a str r2, [r3, #0]
|
|||
|
|
8001840: 4b0f ldr r3, [pc, #60] ; (8001880 <SetAndCorrect+0x610>)
|
|||
|
|
8001842: 6a1b ldr r3, [r3, #32]
|
|||
|
|
8001844: 4915 ldr r1, [pc, #84] ; (800189c <SetAndCorrect+0x62c>)
|
|||
|
|
8001846: 1c18 adds r0, r3, #0
|
|||
|
|
8001848: f7fe fe84 bl 8000554 <__aeabi_fdiv>
|
|||
|
|
800184c: 1c03 adds r3, r0, #0
|
|||
|
|
800184e: 1c1a adds r2, r3, #0
|
|||
|
|
8001850: 4b13 ldr r3, [pc, #76] ; (80018a0 <SetAndCorrect+0x630>)
|
|||
|
|
8001852: 601a str r2, [r3, #0]
|
|||
|
|
|
|||
|
|
//void setDAC(void) //from 1210
|
|||
|
|
|
|||
|
|
DVD = fKU/kNormToDAC; // <20><><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
|||
|
|
8001854: 4b12 ldr r3, [pc, #72] ; (80018a0 <SetAndCorrect+0x630>)
|
|||
|
|
8001856: 681b ldr r3, [r3, #0]
|
|||
|
|
8001858: 1c19 adds r1, r3, #0
|
|||
|
|
800185a: 6878 ldr r0, [r7, #4]
|
|||
|
|
800185c: f7fe fe7a bl 8000554 <__aeabi_fdiv>
|
|||
|
|
8001860: 1c03 adds r3, r0, #0
|
|||
|
|
8001862: 1c18 adds r0, r3, #0
|
|||
|
|
8001864: f7fe fd9e bl 80003a4 <__aeabi_f2uiz>
|
|||
|
|
8001868: 0003 movs r3, r0
|
|||
|
|
800186a: b29a uxth r2, r3
|
|||
|
|
800186c: 4b15 ldr r3, [pc, #84] ; (80018c4 <SetAndCorrect+0x654>)
|
|||
|
|
800186e: 801a strh r2, [r3, #0]
|
|||
|
|
|
|||
|
|
WRDAC();
|
|||
|
|
8001870: f000 f8f6 bl 8001a60 <WRDAC>
|
|||
|
|
|
|||
|
|
// Load RDAC
|
|||
|
|
}
|
|||
|
|
8001874: 46c0 nop ; (mov r8, r8)
|
|||
|
|
8001876: 46bd mov sp, r7
|
|||
|
|
8001878: b002 add sp, #8
|
|||
|
|
800187a: bd80 pop {r7, pc}
|
|||
|
|
800187c: 50000400 .word 0x50000400
|
|||
|
|
8001880: 20000098 .word 0x20000098
|
|||
|
|
8001884: 20000048 .word 0x20000048
|
|||
|
|
8001888: eb1c432d .word 0xeb1c432d
|
|||
|
|
800188c: 3f1a36e2 .word 0x3f1a36e2
|
|||
|
|
8001890: d2f1a9fc .word 0xd2f1a9fc
|
|||
|
|
8001894: 3f50624d .word 0x3f50624d
|
|||
|
|
8001898: 2000003c .word 0x2000003c
|
|||
|
|
800189c: 461c4000 .word 0x461c4000
|
|||
|
|
80018a0: 20000044 .word 0x20000044
|
|||
|
|
80018a4: 47ae147b .word 0x47ae147b
|
|||
|
|
80018a8: 3f847ae1 .word 0x3f847ae1
|
|||
|
|
80018ac: 447a0000 .word 0x447a0000
|
|||
|
|
80018b0: 9999999a .word 0x9999999a
|
|||
|
|
80018b4: 3fb99999 .word 0x3fb99999
|
|||
|
|
80018b8: 42c80000 .word 0x42c80000
|
|||
|
|
80018bc: 41200000 .word 0x41200000
|
|||
|
|
80018c0: 47c35000 .word 0x47c35000
|
|||
|
|
80018c4: 20000040 .word 0x20000040
|
|||
|
|
|
|||
|
|
080018c8 <initCalibr>:
|
|||
|
|
|
|||
|
|
|
|||
|
|
void initCalibr(void)
|
|||
|
|
{
|
|||
|
|
80018c8: b580 push {r7, lr}
|
|||
|
|
80018ca: af00 add r7, sp, #0
|
|||
|
|
pardata.IKE = 0;
|
|||
|
|
80018cc: 4b60 ldr r3, [pc, #384] ; (8001a50 <initCalibr+0x188>)
|
|||
|
|
80018ce: 2200 movs r2, #0
|
|||
|
|
80018d0: 81da strh r2, [r3, #14]
|
|||
|
|
pardata.IKD = 0;
|
|||
|
|
80018d2: 4b5f ldr r3, [pc, #380] ; (8001a50 <initCalibr+0x188>)
|
|||
|
|
80018d4: 2200 movs r2, #0
|
|||
|
|
80018d6: 821a strh r2, [r3, #16]
|
|||
|
|
pardata.IKS = 1;
|
|||
|
|
80018d8: 4b5d ldr r3, [pc, #372] ; (8001a50 <initCalibr+0x188>)
|
|||
|
|
80018da: 2201 movs r2, #1
|
|||
|
|
80018dc: 825a strh r2, [r3, #18]
|
|||
|
|
pardata.IFV = Hp1;
|
|||
|
|
80018de: 4b5c ldr r3, [pc, #368] ; (8001a50 <initCalibr+0x188>)
|
|||
|
|
80018e0: 2202 movs r2, #2
|
|||
|
|
80018e2: 811a strh r2, [r3, #8]
|
|||
|
|
pardata.IFN = Lp100000;
|
|||
|
|
80018e4: 4b5a ldr r3, [pc, #360] ; (8001a50 <initCalibr+0x188>)
|
|||
|
|
80018e6: 2207 movs r2, #7
|
|||
|
|
80018e8: 815a strh r2, [r3, #10]
|
|||
|
|
|
|||
|
|
switch(faseClbr)
|
|||
|
|
80018ea: 4b5a ldr r3, [pc, #360] ; (8001a54 <initCalibr+0x18c>)
|
|||
|
|
80018ec: 681b ldr r3, [r3, #0]
|
|||
|
|
80018ee: 2b16 cmp r3, #22
|
|||
|
|
80018f0: d900 bls.n 80018f4 <initCalibr+0x2c>
|
|||
|
|
80018f2: e0a5 b.n 8001a40 <initCalibr+0x178>
|
|||
|
|
80018f4: 009a lsls r2, r3, #2
|
|||
|
|
80018f6: 4b58 ldr r3, [pc, #352] ; (8001a58 <initCalibr+0x190>)
|
|||
|
|
80018f8: 18d3 adds r3, r2, r3
|
|||
|
|
80018fa: 681b ldr r3, [r3, #0]
|
|||
|
|
80018fc: 469f mov pc, r3
|
|||
|
|
{
|
|||
|
|
case 0: // CHARGE 0.1
|
|||
|
|
pardata.IIN = CHARGE;
|
|||
|
|
80018fe: 4b54 ldr r3, [pc, #336] ; (8001a50 <initCalibr+0x188>)
|
|||
|
|
8001900: 2200 movs r2, #0
|
|||
|
|
8001902: 80da strh r2, [r3, #6]
|
|||
|
|
pardata.IKU = Ku0_1;
|
|||
|
|
8001904: 4b52 ldr r3, [pc, #328] ; (8001a50 <initCalibr+0x188>)
|
|||
|
|
8001906: 2200 movs r2, #0
|
|||
|
|
8001908: 819a strh r2, [r3, #12]
|
|||
|
|
break;
|
|||
|
|
800190a: e099 b.n 8001a40 <initCalibr+0x178>
|
|||
|
|
case 1: // CHARGE 0.2
|
|||
|
|
pardata.IIN = CHARGE;
|
|||
|
|
800190c: 4b50 ldr r3, [pc, #320] ; (8001a50 <initCalibr+0x188>)
|
|||
|
|
800190e: 2200 movs r2, #0
|
|||
|
|
8001910: 80da strh r2, [r3, #6]
|
|||
|
|
pardata.IKU = Ku0_2;
|
|||
|
|
8001912: 4b4f ldr r3, [pc, #316] ; (8001a50 <initCalibr+0x188>)
|
|||
|
|
8001914: 2201 movs r2, #1
|
|||
|
|
8001916: 819a strh r2, [r3, #12]
|
|||
|
|
break;
|
|||
|
|
8001918: e092 b.n 8001a40 <initCalibr+0x178>
|
|||
|
|
case 2: // CHARGE 0.5
|
|||
|
|
pardata.IIN = CHARGE;
|
|||
|
|
800191a: 4b4d ldr r3, [pc, #308] ; (8001a50 <initCalibr+0x188>)
|
|||
|
|
800191c: 2200 movs r2, #0
|
|||
|
|
800191e: 80da strh r2, [r3, #6]
|
|||
|
|
pardata.IKU = Ku0_5;
|
|||
|
|
8001920: 4b4b ldr r3, [pc, #300] ; (8001a50 <initCalibr+0x188>)
|
|||
|
|
8001922: 2202 movs r2, #2
|
|||
|
|
8001924: 819a strh r2, [r3, #12]
|
|||
|
|
break;
|
|||
|
|
8001926: e08b b.n 8001a40 <initCalibr+0x178>
|
|||
|
|
case 3: // CHARGE 1
|
|||
|
|
pardata.IIN = CHARGE;
|
|||
|
|
8001928: 4b49 ldr r3, [pc, #292] ; (8001a50 <initCalibr+0x188>)
|
|||
|
|
800192a: 2200 movs r2, #0
|
|||
|
|
800192c: 80da strh r2, [r3, #6]
|
|||
|
|
pardata.IKU = Ku1;
|
|||
|
|
800192e: 4b48 ldr r3, [pc, #288] ; (8001a50 <initCalibr+0x188>)
|
|||
|
|
8001930: 2203 movs r2, #3
|
|||
|
|
8001932: 819a strh r2, [r3, #12]
|
|||
|
|
break;
|
|||
|
|
8001934: e084 b.n 8001a40 <initCalibr+0x178>
|
|||
|
|
case 4: // CHARGE 2
|
|||
|
|
pardata.IIN = CHARGE;
|
|||
|
|
8001936: 4b46 ldr r3, [pc, #280] ; (8001a50 <initCalibr+0x188>)
|
|||
|
|
8001938: 2200 movs r2, #0
|
|||
|
|
800193a: 80da strh r2, [r3, #6]
|
|||
|
|
pardata.IKU = Ku2;
|
|||
|
|
800193c: 4b44 ldr r3, [pc, #272] ; (8001a50 <initCalibr+0x188>)
|
|||
|
|
800193e: 2204 movs r2, #4
|
|||
|
|
8001940: 819a strh r2, [r3, #12]
|
|||
|
|
break;
|
|||
|
|
8001942: e07d b.n 8001a40 <initCalibr+0x178>
|
|||
|
|
case 5: // CHARGE 5
|
|||
|
|
pardata.IIN = CHARGE;
|
|||
|
|
8001944: 4b42 ldr r3, [pc, #264] ; (8001a50 <initCalibr+0x188>)
|
|||
|
|
8001946: 2200 movs r2, #0
|
|||
|
|
8001948: 80da strh r2, [r3, #6]
|
|||
|
|
pardata.IKU = Ku5;
|
|||
|
|
800194a: 4b41 ldr r3, [pc, #260] ; (8001a50 <initCalibr+0x188>)
|
|||
|
|
800194c: 2205 movs r2, #5
|
|||
|
|
800194e: 819a strh r2, [r3, #12]
|
|||
|
|
break;
|
|||
|
|
8001950: e076 b.n 8001a40 <initCalibr+0x178>
|
|||
|
|
case 6: // CHARGE 10
|
|||
|
|
pardata.IIN = CHARGE;
|
|||
|
|
8001952: 4b3f ldr r3, [pc, #252] ; (8001a50 <initCalibr+0x188>)
|
|||
|
|
8001954: 2200 movs r2, #0
|
|||
|
|
8001956: 80da strh r2, [r3, #6]
|
|||
|
|
pardata.IKU = Ku10;
|
|||
|
|
8001958: 4b3d ldr r3, [pc, #244] ; (8001a50 <initCalibr+0x188>)
|
|||
|
|
800195a: 2206 movs r2, #6
|
|||
|
|
800195c: 819a strh r2, [r3, #12]
|
|||
|
|
break;
|
|||
|
|
800195e: e06f b.n 8001a40 <initCalibr+0x178>
|
|||
|
|
case 7: // CHARGE 20
|
|||
|
|
pardata.IIN = CHARGE;
|
|||
|
|
8001960: 4b3b ldr r3, [pc, #236] ; (8001a50 <initCalibr+0x188>)
|
|||
|
|
8001962: 2200 movs r2, #0
|
|||
|
|
8001964: 80da strh r2, [r3, #6]
|
|||
|
|
pardata.IKU = Ku20;
|
|||
|
|
8001966: 4b3a ldr r3, [pc, #232] ; (8001a50 <initCalibr+0x188>)
|
|||
|
|
8001968: 2207 movs r2, #7
|
|||
|
|
800196a: 819a strh r2, [r3, #12]
|
|||
|
|
break;
|
|||
|
|
800196c: e068 b.n 8001a40 <initCalibr+0x178>
|
|||
|
|
case 8: // CHARGE 50
|
|||
|
|
pardata.IIN = CHARGE;
|
|||
|
|
800196e: 4b38 ldr r3, [pc, #224] ; (8001a50 <initCalibr+0x188>)
|
|||
|
|
8001970: 2200 movs r2, #0
|
|||
|
|
8001972: 80da strh r2, [r3, #6]
|
|||
|
|
pardata.IKU = Ku50;
|
|||
|
|
8001974: 4b36 ldr r3, [pc, #216] ; (8001a50 <initCalibr+0x188>)
|
|||
|
|
8001976: 2208 movs r2, #8
|
|||
|
|
8001978: 819a strh r2, [r3, #12]
|
|||
|
|
break;
|
|||
|
|
800197a: e061 b.n 8001a40 <initCalibr+0x178>
|
|||
|
|
case 9: // CHARGE 100
|
|||
|
|
pardata.IIN = CHARGE;
|
|||
|
|
800197c: 4b34 ldr r3, [pc, #208] ; (8001a50 <initCalibr+0x188>)
|
|||
|
|
800197e: 2200 movs r2, #0
|
|||
|
|
8001980: 80da strh r2, [r3, #6]
|
|||
|
|
pardata.IKU = Ku100;
|
|||
|
|
8001982: 4b33 ldr r3, [pc, #204] ; (8001a50 <initCalibr+0x188>)
|
|||
|
|
8001984: 2209 movs r2, #9
|
|||
|
|
8001986: 819a strh r2, [r3, #12]
|
|||
|
|
break;
|
|||
|
|
8001988: e05a b.n 8001a40 <initCalibr+0x178>
|
|||
|
|
case 10:// CHARGE 200
|
|||
|
|
pardata.IIN = CHARGE;
|
|||
|
|
800198a: 4b31 ldr r3, [pc, #196] ; (8001a50 <initCalibr+0x188>)
|
|||
|
|
800198c: 2200 movs r2, #0
|
|||
|
|
800198e: 80da strh r2, [r3, #6]
|
|||
|
|
pardata.IKU = Ku200;
|
|||
|
|
8001990: 4b2f ldr r3, [pc, #188] ; (8001a50 <initCalibr+0x188>)
|
|||
|
|
8001992: 220a movs r2, #10
|
|||
|
|
8001994: 819a strh r2, [r3, #12]
|
|||
|
|
break;
|
|||
|
|
8001996: e053 b.n 8001a40 <initCalibr+0x178>
|
|||
|
|
case 11:// CHARGE 500
|
|||
|
|
pardata.IIN = CHARGE;
|
|||
|
|
8001998: 4b2d ldr r3, [pc, #180] ; (8001a50 <initCalibr+0x188>)
|
|||
|
|
800199a: 2200 movs r2, #0
|
|||
|
|
800199c: 80da strh r2, [r3, #6]
|
|||
|
|
pardata.IKU = Ku500;
|
|||
|
|
800199e: 4b2c ldr r3, [pc, #176] ; (8001a50 <initCalibr+0x188>)
|
|||
|
|
80019a0: 220b movs r2, #11
|
|||
|
|
80019a2: 819a strh r2, [r3, #12]
|
|||
|
|
break;
|
|||
|
|
80019a4: e04c b.n 8001a40 <initCalibr+0x178>
|
|||
|
|
case 12:// CHARGE 1000
|
|||
|
|
pardata.IIN = CHARGE;
|
|||
|
|
80019a6: 4b2a ldr r3, [pc, #168] ; (8001a50 <initCalibr+0x188>)
|
|||
|
|
80019a8: 2200 movs r2, #0
|
|||
|
|
80019aa: 80da strh r2, [r3, #6]
|
|||
|
|
pardata.IKU = Ku1000;
|
|||
|
|
80019ac: 4b28 ldr r3, [pc, #160] ; (8001a50 <initCalibr+0x188>)
|
|||
|
|
80019ae: 220c movs r2, #12
|
|||
|
|
80019b0: 819a strh r2, [r3, #12]
|
|||
|
|
break;
|
|||
|
|
80019b2: e045 b.n 8001a40 <initCalibr+0x178>
|
|||
|
|
|
|||
|
|
case 13: // ICP 1
|
|||
|
|
pardata.IIN = ICP;
|
|||
|
|
80019b4: 4b26 ldr r3, [pc, #152] ; (8001a50 <initCalibr+0x188>)
|
|||
|
|
80019b6: 2201 movs r2, #1
|
|||
|
|
80019b8: 80da strh r2, [r3, #6]
|
|||
|
|
pardata.IKU = Ku1;
|
|||
|
|
80019ba: 4b25 ldr r3, [pc, #148] ; (8001a50 <initCalibr+0x188>)
|
|||
|
|
80019bc: 2203 movs r2, #3
|
|||
|
|
80019be: 819a strh r2, [r3, #12]
|
|||
|
|
break;
|
|||
|
|
80019c0: e03e b.n 8001a40 <initCalibr+0x178>
|
|||
|
|
case 14: // ICP 2
|
|||
|
|
pardata.IIN = ICP;
|
|||
|
|
80019c2: 4b23 ldr r3, [pc, #140] ; (8001a50 <initCalibr+0x188>)
|
|||
|
|
80019c4: 2201 movs r2, #1
|
|||
|
|
80019c6: 80da strh r2, [r3, #6]
|
|||
|
|
pardata.IKU = Ku2;
|
|||
|
|
80019c8: 4b21 ldr r3, [pc, #132] ; (8001a50 <initCalibr+0x188>)
|
|||
|
|
80019ca: 2204 movs r2, #4
|
|||
|
|
80019cc: 819a strh r2, [r3, #12]
|
|||
|
|
break;
|
|||
|
|
80019ce: e037 b.n 8001a40 <initCalibr+0x178>
|
|||
|
|
case 15: // ICP 5
|
|||
|
|
pardata.IIN = ICP;
|
|||
|
|
80019d0: 4b1f ldr r3, [pc, #124] ; (8001a50 <initCalibr+0x188>)
|
|||
|
|
80019d2: 2201 movs r2, #1
|
|||
|
|
80019d4: 80da strh r2, [r3, #6]
|
|||
|
|
pardata.IKU = Ku5;
|
|||
|
|
80019d6: 4b1e ldr r3, [pc, #120] ; (8001a50 <initCalibr+0x188>)
|
|||
|
|
80019d8: 2205 movs r2, #5
|
|||
|
|
80019da: 819a strh r2, [r3, #12]
|
|||
|
|
break;
|
|||
|
|
80019dc: e030 b.n 8001a40 <initCalibr+0x178>
|
|||
|
|
case 16: // ICP 10
|
|||
|
|
pardata.IIN = ICP;
|
|||
|
|
80019de: 4b1c ldr r3, [pc, #112] ; (8001a50 <initCalibr+0x188>)
|
|||
|
|
80019e0: 2201 movs r2, #1
|
|||
|
|
80019e2: 80da strh r2, [r3, #6]
|
|||
|
|
pardata.IKU = Ku10;
|
|||
|
|
80019e4: 4b1a ldr r3, [pc, #104] ; (8001a50 <initCalibr+0x188>)
|
|||
|
|
80019e6: 2206 movs r2, #6
|
|||
|
|
80019e8: 819a strh r2, [r3, #12]
|
|||
|
|
break;
|
|||
|
|
80019ea: e029 b.n 8001a40 <initCalibr+0x178>
|
|||
|
|
case 17: // ICP 20
|
|||
|
|
pardata.IIN = ICP;
|
|||
|
|
80019ec: 4b18 ldr r3, [pc, #96] ; (8001a50 <initCalibr+0x188>)
|
|||
|
|
80019ee: 2201 movs r2, #1
|
|||
|
|
80019f0: 80da strh r2, [r3, #6]
|
|||
|
|
pardata.IKU = Ku20;
|
|||
|
|
80019f2: 4b17 ldr r3, [pc, #92] ; (8001a50 <initCalibr+0x188>)
|
|||
|
|
80019f4: 2207 movs r2, #7
|
|||
|
|
80019f6: 819a strh r2, [r3, #12]
|
|||
|
|
break;
|
|||
|
|
80019f8: e022 b.n 8001a40 <initCalibr+0x178>
|
|||
|
|
case 18: // ICP 50
|
|||
|
|
pardata.IIN = ICP;
|
|||
|
|
80019fa: 4b15 ldr r3, [pc, #84] ; (8001a50 <initCalibr+0x188>)
|
|||
|
|
80019fc: 2201 movs r2, #1
|
|||
|
|
80019fe: 80da strh r2, [r3, #6]
|
|||
|
|
pardata.IKU = Ku50;
|
|||
|
|
8001a00: 4b13 ldr r3, [pc, #76] ; (8001a50 <initCalibr+0x188>)
|
|||
|
|
8001a02: 2208 movs r2, #8
|
|||
|
|
8001a04: 819a strh r2, [r3, #12]
|
|||
|
|
break;
|
|||
|
|
8001a06: e01b b.n 8001a40 <initCalibr+0x178>
|
|||
|
|
case 19: // ICP 100
|
|||
|
|
pardata.IIN = ICP;
|
|||
|
|
8001a08: 4b11 ldr r3, [pc, #68] ; (8001a50 <initCalibr+0x188>)
|
|||
|
|
8001a0a: 2201 movs r2, #1
|
|||
|
|
8001a0c: 80da strh r2, [r3, #6]
|
|||
|
|
pardata.IKU = Ku100;
|
|||
|
|
8001a0e: 4b10 ldr r3, [pc, #64] ; (8001a50 <initCalibr+0x188>)
|
|||
|
|
8001a10: 2209 movs r2, #9
|
|||
|
|
8001a12: 819a strh r2, [r3, #12]
|
|||
|
|
break;
|
|||
|
|
8001a14: e014 b.n 8001a40 <initCalibr+0x178>
|
|||
|
|
case 20: // ICP 200
|
|||
|
|
pardata.IIN = ICP;
|
|||
|
|
8001a16: 4b0e ldr r3, [pc, #56] ; (8001a50 <initCalibr+0x188>)
|
|||
|
|
8001a18: 2201 movs r2, #1
|
|||
|
|
8001a1a: 80da strh r2, [r3, #6]
|
|||
|
|
pardata.IKU = Ku200;
|
|||
|
|
8001a1c: 4b0c ldr r3, [pc, #48] ; (8001a50 <initCalibr+0x188>)
|
|||
|
|
8001a1e: 220a movs r2, #10
|
|||
|
|
8001a20: 819a strh r2, [r3, #12]
|
|||
|
|
break;
|
|||
|
|
8001a22: e00d b.n 8001a40 <initCalibr+0x178>
|
|||
|
|
case 21: // ICP 500
|
|||
|
|
pardata.IIN = ICP;
|
|||
|
|
8001a24: 4b0a ldr r3, [pc, #40] ; (8001a50 <initCalibr+0x188>)
|
|||
|
|
8001a26: 2201 movs r2, #1
|
|||
|
|
8001a28: 80da strh r2, [r3, #6]
|
|||
|
|
pardata.IKU = Ku500;
|
|||
|
|
8001a2a: 4b09 ldr r3, [pc, #36] ; (8001a50 <initCalibr+0x188>)
|
|||
|
|
8001a2c: 220b movs r2, #11
|
|||
|
|
8001a2e: 819a strh r2, [r3, #12]
|
|||
|
|
break;
|
|||
|
|
8001a30: e006 b.n 8001a40 <initCalibr+0x178>
|
|||
|
|
case 22: // ICP 1000
|
|||
|
|
pardata.IIN = ICP;
|
|||
|
|
8001a32: 4b07 ldr r3, [pc, #28] ; (8001a50 <initCalibr+0x188>)
|
|||
|
|
8001a34: 2201 movs r2, #1
|
|||
|
|
8001a36: 80da strh r2, [r3, #6]
|
|||
|
|
pardata.IKU = Ku1000;
|
|||
|
|
8001a38: 4b05 ldr r3, [pc, #20] ; (8001a50 <initCalibr+0x188>)
|
|||
|
|
8001a3a: 220c movs r2, #12
|
|||
|
|
8001a3c: 819a strh r2, [r3, #12]
|
|||
|
|
break;
|
|||
|
|
8001a3e: 46c0 nop ; (mov r8, r8)
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
clbr = true;
|
|||
|
|
8001a40: 4b06 ldr r3, [pc, #24] ; (8001a5c <initCalibr+0x194>)
|
|||
|
|
8001a42: 2201 movs r2, #1
|
|||
|
|
8001a44: 701a strb r2, [r3, #0]
|
|||
|
|
SetAndCorrect();
|
|||
|
|
8001a46: f7ff fc13 bl 8001270 <SetAndCorrect>
|
|||
|
|
}
|
|||
|
|
8001a4a: 46c0 nop ; (mov r8, r8)
|
|||
|
|
8001a4c: 46bd mov sp, r7
|
|||
|
|
8001a4e: bd80 pop {r7, pc}
|
|||
|
|
8001a50: 20000098 .word 0x20000098
|
|||
|
|
8001a54: 20000030 .word 0x20000030
|
|||
|
|
8001a58: 08007110 .word 0x08007110
|
|||
|
|
8001a5c: 20000034 .word 0x20000034
|
|||
|
|
|
|||
|
|
08001a60 <WRDAC>:
|
|||
|
|
|
|||
|
|
//******************************************************************************
|
|||
|
|
// <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
|||
|
|
//******************************************************************************
|
|||
|
|
void WRDAC(void)
|
|||
|
|
{
|
|||
|
|
8001a60: b580 push {r7, lr}
|
|||
|
|
8001a62: b082 sub sp, #8
|
|||
|
|
8001a64: af00 add r7, sp, #0
|
|||
|
|
uint8_t i;
|
|||
|
|
uint16_t dvd = DVD;
|
|||
|
|
8001a66: 1d3b adds r3, r7, #4
|
|||
|
|
8001a68: 4a2a ldr r2, [pc, #168] ; (8001b14 <WRDAC+0xb4>)
|
|||
|
|
8001a6a: 8812 ldrh r2, [r2, #0]
|
|||
|
|
8001a6c: 801a strh r2, [r3, #0]
|
|||
|
|
|
|||
|
|
dvd <<= 4;
|
|||
|
|
8001a6e: 1d3b adds r3, r7, #4
|
|||
|
|
8001a70: 1d3a adds r2, r7, #4
|
|||
|
|
8001a72: 8812 ldrh r2, [r2, #0]
|
|||
|
|
8001a74: 0112 lsls r2, r2, #4
|
|||
|
|
8001a76: 801a strh r2, [r3, #0]
|
|||
|
|
for(i = 0; i < 12; i++)
|
|||
|
|
8001a78: 1dfb adds r3, r7, #7
|
|||
|
|
8001a7a: 2200 movs r2, #0
|
|||
|
|
8001a7c: 701a strb r2, [r3, #0]
|
|||
|
|
8001a7e: e02b b.n 8001ad8 <WRDAC+0x78>
|
|||
|
|
{
|
|||
|
|
if(dvd & 0x8000)
|
|||
|
|
8001a80: 1d3b adds r3, r7, #4
|
|||
|
|
8001a82: 2200 movs r2, #0
|
|||
|
|
8001a84: 5e9b ldrsh r3, [r3, r2]
|
|||
|
|
8001a86: 2b00 cmp r3, #0
|
|||
|
|
8001a88: da07 bge.n 8001a9a <WRDAC+0x3a>
|
|||
|
|
HAL_GPIO_WritePin(GPIOB, STD_Pin, GPIO_PIN_SET);
|
|||
|
|
8001a8a: 2380 movs r3, #128 ; 0x80
|
|||
|
|
8001a8c: 01db lsls r3, r3, #7
|
|||
|
|
8001a8e: 4822 ldr r0, [pc, #136] ; (8001b18 <WRDAC+0xb8>)
|
|||
|
|
8001a90: 2201 movs r2, #1
|
|||
|
|
8001a92: 0019 movs r1, r3
|
|||
|
|
8001a94: f003 f83b bl 8004b0e <HAL_GPIO_WritePin>
|
|||
|
|
8001a98: e006 b.n 8001aa8 <WRDAC+0x48>
|
|||
|
|
else HAL_GPIO_WritePin(GPIOB, STD_Pin, GPIO_PIN_RESET);
|
|||
|
|
8001a9a: 2380 movs r3, #128 ; 0x80
|
|||
|
|
8001a9c: 01db lsls r3, r3, #7
|
|||
|
|
8001a9e: 481e ldr r0, [pc, #120] ; (8001b18 <WRDAC+0xb8>)
|
|||
|
|
8001aa0: 2200 movs r2, #0
|
|||
|
|
8001aa2: 0019 movs r1, r3
|
|||
|
|
8001aa4: f003 f833 bl 8004b0e <HAL_GPIO_WritePin>
|
|||
|
|
|
|||
|
|
HAL_GPIO_WritePin(GPIOB, SCK_Pin, GPIO_PIN_RESET);
|
|||
|
|
8001aa8: 2380 movs r3, #128 ; 0x80
|
|||
|
|
8001aaa: 021b lsls r3, r3, #8
|
|||
|
|
8001aac: 481a ldr r0, [pc, #104] ; (8001b18 <WRDAC+0xb8>)
|
|||
|
|
8001aae: 2200 movs r2, #0
|
|||
|
|
8001ab0: 0019 movs r1, r3
|
|||
|
|
8001ab2: f003 f82c bl 8004b0e <HAL_GPIO_WritePin>
|
|||
|
|
HAL_GPIO_WritePin(GPIOB, SCK_Pin, GPIO_PIN_SET);
|
|||
|
|
8001ab6: 2380 movs r3, #128 ; 0x80
|
|||
|
|
8001ab8: 021b lsls r3, r3, #8
|
|||
|
|
8001aba: 4817 ldr r0, [pc, #92] ; (8001b18 <WRDAC+0xb8>)
|
|||
|
|
8001abc: 2201 movs r2, #1
|
|||
|
|
8001abe: 0019 movs r1, r3
|
|||
|
|
8001ac0: f003 f825 bl 8004b0e <HAL_GPIO_WritePin>
|
|||
|
|
dvd <<= 1;
|
|||
|
|
8001ac4: 1d3a adds r2, r7, #4
|
|||
|
|
8001ac6: 1d3b adds r3, r7, #4
|
|||
|
|
8001ac8: 881b ldrh r3, [r3, #0]
|
|||
|
|
8001aca: 18db adds r3, r3, r3
|
|||
|
|
8001acc: 8013 strh r3, [r2, #0]
|
|||
|
|
for(i = 0; i < 12; i++)
|
|||
|
|
8001ace: 1dfb adds r3, r7, #7
|
|||
|
|
8001ad0: 781a ldrb r2, [r3, #0]
|
|||
|
|
8001ad2: 1dfb adds r3, r7, #7
|
|||
|
|
8001ad4: 3201 adds r2, #1
|
|||
|
|
8001ad6: 701a strb r2, [r3, #0]
|
|||
|
|
8001ad8: 1dfb adds r3, r7, #7
|
|||
|
|
8001ada: 781b ldrb r3, [r3, #0]
|
|||
|
|
8001adc: 2b0b cmp r3, #11
|
|||
|
|
8001ade: d9cf bls.n 8001a80 <WRDAC+0x20>
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
HAL_GPIO_WritePin(GPIOB, FL_Pin, GPIO_PIN_RESET);
|
|||
|
|
8001ae0: 2380 movs r3, #128 ; 0x80
|
|||
|
|
8001ae2: 019b lsls r3, r3, #6
|
|||
|
|
8001ae4: 480c ldr r0, [pc, #48] ; (8001b18 <WRDAC+0xb8>)
|
|||
|
|
8001ae6: 2200 movs r2, #0
|
|||
|
|
8001ae8: 0019 movs r1, r3
|
|||
|
|
8001aea: f003 f810 bl 8004b0e <HAL_GPIO_WritePin>
|
|||
|
|
HAL_GPIO_WritePin(GPIOB, FL_Pin, GPIO_PIN_SET);
|
|||
|
|
8001aee: 2380 movs r3, #128 ; 0x80
|
|||
|
|
8001af0: 019b lsls r3, r3, #6
|
|||
|
|
8001af2: 4809 ldr r0, [pc, #36] ; (8001b18 <WRDAC+0xb8>)
|
|||
|
|
8001af4: 2201 movs r2, #1
|
|||
|
|
8001af6: 0019 movs r1, r3
|
|||
|
|
8001af8: f003 f809 bl 8004b0e <HAL_GPIO_WritePin>
|
|||
|
|
HAL_GPIO_WritePin(GPIOB, STD_Pin, GPIO_PIN_SET);
|
|||
|
|
8001afc: 2380 movs r3, #128 ; 0x80
|
|||
|
|
8001afe: 01db lsls r3, r3, #7
|
|||
|
|
8001b00: 4805 ldr r0, [pc, #20] ; (8001b18 <WRDAC+0xb8>)
|
|||
|
|
8001b02: 2201 movs r2, #1
|
|||
|
|
8001b04: 0019 movs r1, r3
|
|||
|
|
8001b06: f003 f802 bl 8004b0e <HAL_GPIO_WritePin>
|
|||
|
|
}
|
|||
|
|
8001b0a: 46c0 nop ; (mov r8, r8)
|
|||
|
|
8001b0c: 46bd mov sp, r7
|
|||
|
|
8001b0e: b002 add sp, #8
|
|||
|
|
8001b10: bd80 pop {r7, pc}
|
|||
|
|
8001b12: 46c0 nop ; (mov r8, r8)
|
|||
|
|
8001b14: 20000040 .word 0x20000040
|
|||
|
|
8001b18: 50000400 .word 0x50000400
|
|||
|
|
|
|||
|
|
08001b1c <MX_FLASH_Init>:
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
void MX_FLASH_Init(void)
|
|||
|
|
{
|
|||
|
|
8001b1c: b580 push {r7, lr}
|
|||
|
|
8001b1e: af00 add r7, sp, #0
|
|||
|
|
__HAL_RCC_SYSCFG_CLK_ENABLE();
|
|||
|
|
8001b20: 4b06 ldr r3, [pc, #24] ; (8001b3c <MX_FLASH_Init+0x20>)
|
|||
|
|
8001b22: 4a06 ldr r2, [pc, #24] ; (8001b3c <MX_FLASH_Init+0x20>)
|
|||
|
|
8001b24: 6b52 ldr r2, [r2, #52] ; 0x34
|
|||
|
|
8001b26: 2101 movs r1, #1
|
|||
|
|
8001b28: 430a orrs r2, r1
|
|||
|
|
8001b2a: 635a str r2, [r3, #52] ; 0x34
|
|||
|
|
|
|||
|
|
rdPar();
|
|||
|
|
8001b2c: f000 f866 bl 8001bfc <rdPar>
|
|||
|
|
rdCorr();
|
|||
|
|
8001b30: f000 f97a bl 8001e28 <rdCorr>
|
|||
|
|
}
|
|||
|
|
8001b34: 46c0 nop ; (mov r8, r8)
|
|||
|
|
8001b36: 46bd mov sp, r7
|
|||
|
|
8001b38: bd80 pop {r7, pc}
|
|||
|
|
8001b3a: 46c0 nop ; (mov r8, r8)
|
|||
|
|
8001b3c: 40021000 .word 0x40021000
|
|||
|
|
|
|||
|
|
08001b40 <wrPar>:
|
|||
|
|
|
|||
|
|
|
|||
|
|
void wrPar(void)
|
|||
|
|
{
|
|||
|
|
8001b40: b580 push {r7, lr}
|
|||
|
|
8001b42: b084 sub sp, #16
|
|||
|
|
8001b44: af00 add r7, sp, #0
|
|||
|
|
uint8_t i, len;
|
|||
|
|
uint32_t *pData, Address;
|
|||
|
|
|
|||
|
|
len = sizeof(UserData_TypeDef);
|
|||
|
|
8001b46: 1cfb adds r3, r7, #3
|
|||
|
|
8001b48: 2228 movs r2, #40 ; 0x28
|
|||
|
|
8001b4a: 701a strb r2, [r3, #0]
|
|||
|
|
len >>= 2;
|
|||
|
|
8001b4c: 1cfb adds r3, r7, #3
|
|||
|
|
8001b4e: 1cfa adds r2, r7, #3
|
|||
|
|
8001b50: 7812 ldrb r2, [r2, #0]
|
|||
|
|
8001b52: 0892 lsrs r2, r2, #2
|
|||
|
|
8001b54: 701a strb r2, [r3, #0]
|
|||
|
|
|
|||
|
|
HAL_FLASH_Unlock();
|
|||
|
|
8001b56: f002 fbc7 bl 80042e8 <HAL_FLASH_Unlock>
|
|||
|
|
FLASH_PageErase(USERPAGE);
|
|||
|
|
8001b5a: 4b24 ldr r3, [pc, #144] ; (8001bec <wrPar+0xac>)
|
|||
|
|
8001b5c: 0018 movs r0, r3
|
|||
|
|
8001b5e: f002 fd35 bl 80045cc <FLASH_PageErase>
|
|||
|
|
CLEAR_BIT(FLASH->PECR, FLASH_PECR_PROG);
|
|||
|
|
8001b62: 4b23 ldr r3, [pc, #140] ; (8001bf0 <wrPar+0xb0>)
|
|||
|
|
8001b64: 4a22 ldr r2, [pc, #136] ; (8001bf0 <wrPar+0xb0>)
|
|||
|
|
8001b66: 6852 ldr r2, [r2, #4]
|
|||
|
|
8001b68: 2108 movs r1, #8
|
|||
|
|
8001b6a: 438a bics r2, r1
|
|||
|
|
8001b6c: 605a str r2, [r3, #4]
|
|||
|
|
CLEAR_BIT(FLASH->PECR, FLASH_PECR_ERASE);
|
|||
|
|
8001b6e: 4b20 ldr r3, [pc, #128] ; (8001bf0 <wrPar+0xb0>)
|
|||
|
|
8001b70: 4a1f ldr r2, [pc, #124] ; (8001bf0 <wrPar+0xb0>)
|
|||
|
|
8001b72: 6852 ldr r2, [r2, #4]
|
|||
|
|
8001b74: 491f ldr r1, [pc, #124] ; (8001bf4 <wrPar+0xb4>)
|
|||
|
|
8001b76: 400a ands r2, r1
|
|||
|
|
8001b78: 605a str r2, [r3, #4]
|
|||
|
|
FLASH_WaitForLastOperation(100);
|
|||
|
|
8001b7a: 2064 movs r0, #100 ; 0x64
|
|||
|
|
8001b7c: f002 fc18 bl 80043b0 <FLASH_WaitForLastOperation>
|
|||
|
|
|
|||
|
|
Address = USERPAGE;
|
|||
|
|
8001b80: 4b1a ldr r3, [pc, #104] ; (8001bec <wrPar+0xac>)
|
|||
|
|
8001b82: 607b str r3, [r7, #4]
|
|||
|
|
pData = (uint32_t *) &pardata;
|
|||
|
|
8001b84: 4b1c ldr r3, [pc, #112] ; (8001bf8 <wrPar+0xb8>)
|
|||
|
|
8001b86: 60bb str r3, [r7, #8]
|
|||
|
|
for(i = 0; i < len; i++)
|
|||
|
|
8001b88: 230f movs r3, #15
|
|||
|
|
8001b8a: 18fb adds r3, r7, r3
|
|||
|
|
8001b8c: 2200 movs r2, #0
|
|||
|
|
8001b8e: 701a strb r2, [r3, #0]
|
|||
|
|
8001b90: e012 b.n 8001bb8 <wrPar+0x78>
|
|||
|
|
{
|
|||
|
|
HAL_FLASH_Program(FLASH_TYPEPROGRAM_WORD, Address, *pData++);
|
|||
|
|
8001b92: 68bb ldr r3, [r7, #8]
|
|||
|
|
8001b94: 1d1a adds r2, r3, #4
|
|||
|
|
8001b96: 60ba str r2, [r7, #8]
|
|||
|
|
8001b98: 681a ldr r2, [r3, #0]
|
|||
|
|
8001b9a: 687b ldr r3, [r7, #4]
|
|||
|
|
8001b9c: 0019 movs r1, r3
|
|||
|
|
8001b9e: 2002 movs r0, #2
|
|||
|
|
8001ba0: f002 fb66 bl 8004270 <HAL_FLASH_Program>
|
|||
|
|
Address += 4;
|
|||
|
|
8001ba4: 687b ldr r3, [r7, #4]
|
|||
|
|
8001ba6: 3304 adds r3, #4
|
|||
|
|
8001ba8: 607b str r3, [r7, #4]
|
|||
|
|
for(i = 0; i < len; i++)
|
|||
|
|
8001baa: 230f movs r3, #15
|
|||
|
|
8001bac: 18fb adds r3, r7, r3
|
|||
|
|
8001bae: 781a ldrb r2, [r3, #0]
|
|||
|
|
8001bb0: 230f movs r3, #15
|
|||
|
|
8001bb2: 18fb adds r3, r7, r3
|
|||
|
|
8001bb4: 3201 adds r2, #1
|
|||
|
|
8001bb6: 701a strb r2, [r3, #0]
|
|||
|
|
8001bb8: 230f movs r3, #15
|
|||
|
|
8001bba: 18fa adds r2, r7, r3
|
|||
|
|
8001bbc: 1cfb adds r3, r7, #3
|
|||
|
|
8001bbe: 7812 ldrb r2, [r2, #0]
|
|||
|
|
8001bc0: 781b ldrb r3, [r3, #0]
|
|||
|
|
8001bc2: 429a cmp r2, r3
|
|||
|
|
8001bc4: d3e5 bcc.n 8001b92 <wrPar+0x52>
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
CLEAR_BIT(FLASH->PECR, FLASH_PECR_PROG);
|
|||
|
|
8001bc6: 4b0a ldr r3, [pc, #40] ; (8001bf0 <wrPar+0xb0>)
|
|||
|
|
8001bc8: 4a09 ldr r2, [pc, #36] ; (8001bf0 <wrPar+0xb0>)
|
|||
|
|
8001bca: 6852 ldr r2, [r2, #4]
|
|||
|
|
8001bcc: 2108 movs r1, #8
|
|||
|
|
8001bce: 438a bics r2, r1
|
|||
|
|
8001bd0: 605a str r2, [r3, #4]
|
|||
|
|
CLEAR_BIT(FLASH->PECR, FLASH_PECR_ERASE);
|
|||
|
|
8001bd2: 4b07 ldr r3, [pc, #28] ; (8001bf0 <wrPar+0xb0>)
|
|||
|
|
8001bd4: 4a06 ldr r2, [pc, #24] ; (8001bf0 <wrPar+0xb0>)
|
|||
|
|
8001bd6: 6852 ldr r2, [r2, #4]
|
|||
|
|
8001bd8: 4906 ldr r1, [pc, #24] ; (8001bf4 <wrPar+0xb4>)
|
|||
|
|
8001bda: 400a ands r2, r1
|
|||
|
|
8001bdc: 605a str r2, [r3, #4]
|
|||
|
|
HAL_FLASH_Lock();
|
|||
|
|
8001bde: f002 fbd3 bl 8004388 <HAL_FLASH_Lock>
|
|||
|
|
}
|
|||
|
|
8001be2: 46c0 nop ; (mov r8, r8)
|
|||
|
|
8001be4: 46bd mov sp, r7
|
|||
|
|
8001be6: b004 add sp, #16
|
|||
|
|
8001be8: bd80 pop {r7, pc}
|
|||
|
|
8001bea: 46c0 nop ; (mov r8, r8)
|
|||
|
|
8001bec: 0801ff00 .word 0x0801ff00
|
|||
|
|
8001bf0: 40022000 .word 0x40022000
|
|||
|
|
8001bf4: fffffdff .word 0xfffffdff
|
|||
|
|
8001bf8: 20000098 .word 0x20000098
|
|||
|
|
|
|||
|
|
08001bfc <rdPar>:
|
|||
|
|
|
|||
|
|
|
|||
|
|
void rdPar(void)
|
|||
|
|
{
|
|||
|
|
8001bfc: b590 push {r4, r7, lr}
|
|||
|
|
8001bfe: b083 sub sp, #12
|
|||
|
|
8001c00: af00 add r7, sp, #0
|
|||
|
|
uint8_t rewrite = 0;
|
|||
|
|
8001c02: 1dfb adds r3, r7, #7
|
|||
|
|
8001c04: 2200 movs r2, #0
|
|||
|
|
8001c06: 701a strb r2, [r3, #0]
|
|||
|
|
|
|||
|
|
memcpy((void *) &pardata, (void *) USERPAGE, sizeof(UserData_TypeDef));
|
|||
|
|
8001c08: 4b54 ldr r3, [pc, #336] ; (8001d5c <rdPar+0x160>)
|
|||
|
|
8001c0a: 4a55 ldr r2, [pc, #340] ; (8001d60 <rdPar+0x164>)
|
|||
|
|
8001c0c: ca13 ldmia r2!, {r0, r1, r4}
|
|||
|
|
8001c0e: c313 stmia r3!, {r0, r1, r4}
|
|||
|
|
8001c10: ca13 ldmia r2!, {r0, r1, r4}
|
|||
|
|
8001c12: c313 stmia r3!, {r0, r1, r4}
|
|||
|
|
8001c14: ca13 ldmia r2!, {r0, r1, r4}
|
|||
|
|
8001c16: c313 stmia r3!, {r0, r1, r4}
|
|||
|
|
8001c18: 6812 ldr r2, [r2, #0]
|
|||
|
|
8001c1a: 601a str r2, [r3, #0]
|
|||
|
|
|
|||
|
|
//pardata.OWN = 0;
|
|||
|
|
if((pardata.OWN != MY_ADDRESS) || (pardata.OWN == 0))
|
|||
|
|
8001c1c: 4b4f ldr r3, [pc, #316] ; (8001d5c <rdPar+0x160>)
|
|||
|
|
8001c1e: 881b ldrh r3, [r3, #0]
|
|||
|
|
8001c20: b29b uxth r3, r3
|
|||
|
|
8001c22: 2b03 cmp r3, #3
|
|||
|
|
8001c24: d104 bne.n 8001c30 <rdPar+0x34>
|
|||
|
|
8001c26: 4b4d ldr r3, [pc, #308] ; (8001d5c <rdPar+0x160>)
|
|||
|
|
8001c28: 881b ldrh r3, [r3, #0]
|
|||
|
|
8001c2a: b29b uxth r3, r3
|
|||
|
|
8001c2c: 2b00 cmp r3, #0
|
|||
|
|
8001c2e: d132 bne.n 8001c96 <rdPar+0x9a>
|
|||
|
|
{
|
|||
|
|
pardata.OWN = MY_ADDRESS;
|
|||
|
|
8001c30: 4b4a ldr r3, [pc, #296] ; (8001d5c <rdPar+0x160>)
|
|||
|
|
8001c32: 2203 movs r2, #3
|
|||
|
|
8001c34: 801a strh r2, [r3, #0]
|
|||
|
|
pardata.BAUD = 7; //115200
|
|||
|
|
8001c36: 4b49 ldr r3, [pc, #292] ; (8001d5c <rdPar+0x160>)
|
|||
|
|
8001c38: 2207 movs r2, #7
|
|||
|
|
8001c3a: 805a strh r2, [r3, #2]
|
|||
|
|
pardata.INFB = 0;
|
|||
|
|
8001c3c: 4b47 ldr r3, [pc, #284] ; (8001d5c <rdPar+0x160>)
|
|||
|
|
8001c3e: 2200 movs r2, #0
|
|||
|
|
8001c40: 809a strh r2, [r3, #4]
|
|||
|
|
|
|||
|
|
pardata.IIN = CHARGE;
|
|||
|
|
8001c42: 4b46 ldr r3, [pc, #280] ; (8001d5c <rdPar+0x160>)
|
|||
|
|
8001c44: 2200 movs r2, #0
|
|||
|
|
8001c46: 80da strh r2, [r3, #6]
|
|||
|
|
pardata.IFV = Hp0_2;
|
|||
|
|
8001c48: 4b44 ldr r3, [pc, #272] ; (8001d5c <rdPar+0x160>)
|
|||
|
|
8001c4a: 2200 movs r2, #0
|
|||
|
|
8001c4c: 811a strh r2, [r3, #8]
|
|||
|
|
pardata.IFN = Lp100000;
|
|||
|
|
8001c4e: 4b43 ldr r3, [pc, #268] ; (8001d5c <rdPar+0x160>)
|
|||
|
|
8001c50: 2207 movs r2, #7
|
|||
|
|
8001c52: 815a strh r2, [r3, #10]
|
|||
|
|
pardata.IKU = Ku1;
|
|||
|
|
8001c54: 4b41 ldr r3, [pc, #260] ; (8001d5c <rdPar+0x160>)
|
|||
|
|
8001c56: 2203 movs r2, #3
|
|||
|
|
8001c58: 819a strh r2, [r3, #12]
|
|||
|
|
pardata.IKE = 0;
|
|||
|
|
8001c5a: 4b40 ldr r3, [pc, #256] ; (8001d5c <rdPar+0x160>)
|
|||
|
|
8001c5c: 2200 movs r2, #0
|
|||
|
|
8001c5e: 81da strh r2, [r3, #14]
|
|||
|
|
pardata.IKD = 0;
|
|||
|
|
8001c60: 4b3e ldr r3, [pc, #248] ; (8001d5c <rdPar+0x160>)
|
|||
|
|
8001c62: 2200 movs r2, #0
|
|||
|
|
8001c64: 821a strh r2, [r3, #16]
|
|||
|
|
pardata.IKS = 1;
|
|||
|
|
8001c66: 4b3d ldr r3, [pc, #244] ; (8001d5c <rdPar+0x160>)
|
|||
|
|
8001c68: 2201 movs r2, #1
|
|||
|
|
8001c6a: 825a strh r2, [r3, #18]
|
|||
|
|
pardata.IPZ = 0;
|
|||
|
|
8001c6c: 4b3b ldr r3, [pc, #236] ; (8001d5c <rdPar+0x160>)
|
|||
|
|
8001c6e: 2200 movs r2, #0
|
|||
|
|
8001c70: 829a strh r2, [r3, #20]
|
|||
|
|
pardata.OPZ = 0;
|
|||
|
|
8001c72: 4b3a ldr r3, [pc, #232] ; (8001d5c <rdPar+0x160>)
|
|||
|
|
8001c74: 2200 movs r2, #0
|
|||
|
|
8001c76: 82da strh r2, [r3, #22]
|
|||
|
|
pardata.VAL = Accel;
|
|||
|
|
8001c78: 4b38 ldr r3, [pc, #224] ; (8001d5c <rdPar+0x160>)
|
|||
|
|
8001c7a: 2200 movs r2, #0
|
|||
|
|
8001c7c: 831a strh r2, [r3, #24]
|
|||
|
|
|
|||
|
|
pardata.KCOND = 1.00001f;
|
|||
|
|
8001c7e: 4b37 ldr r3, [pc, #220] ; (8001d5c <rdPar+0x160>)
|
|||
|
|
8001c80: 4a38 ldr r2, [pc, #224] ; (8001d64 <rdPar+0x168>)
|
|||
|
|
8001c82: 61da str r2, [r3, #28]
|
|||
|
|
pardata.SENS = 1.00001f;
|
|||
|
|
8001c84: 4b35 ldr r3, [pc, #212] ; (8001d5c <rdPar+0x160>)
|
|||
|
|
8001c86: 4a37 ldr r2, [pc, #220] ; (8001d64 <rdPar+0x168>)
|
|||
|
|
8001c88: 621a str r2, [r3, #32]
|
|||
|
|
pardata.ACCEL = 10.00001f;
|
|||
|
|
8001c8a: 4b34 ldr r3, [pc, #208] ; (8001d5c <rdPar+0x160>)
|
|||
|
|
8001c8c: 4a36 ldr r2, [pc, #216] ; (8001d68 <rdPar+0x16c>)
|
|||
|
|
8001c8e: 625a str r2, [r3, #36] ; 0x24
|
|||
|
|
|
|||
|
|
rewrite = 1;
|
|||
|
|
8001c90: 1dfb adds r3, r7, #7
|
|||
|
|
8001c92: 2201 movs r2, #1
|
|||
|
|
8001c94: 701a strb r2, [r3, #0]
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
if((pardata.IKE == 0) && (pardata.IKD == 0) && (pardata.IKS == 0)) {
|
|||
|
|
8001c96: 4b31 ldr r3, [pc, #196] ; (8001d5c <rdPar+0x160>)
|
|||
|
|
8001c98: 89db ldrh r3, [r3, #14]
|
|||
|
|
8001c9a: b29b uxth r3, r3
|
|||
|
|
8001c9c: 2b00 cmp r3, #0
|
|||
|
|
8001c9e: d115 bne.n 8001ccc <rdPar+0xd0>
|
|||
|
|
8001ca0: 4b2e ldr r3, [pc, #184] ; (8001d5c <rdPar+0x160>)
|
|||
|
|
8001ca2: 8a1b ldrh r3, [r3, #16]
|
|||
|
|
8001ca4: b29b uxth r3, r3
|
|||
|
|
8001ca6: 2b00 cmp r3, #0
|
|||
|
|
8001ca8: d110 bne.n 8001ccc <rdPar+0xd0>
|
|||
|
|
8001caa: 4b2c ldr r3, [pc, #176] ; (8001d5c <rdPar+0x160>)
|
|||
|
|
8001cac: 8a5b ldrh r3, [r3, #18]
|
|||
|
|
8001cae: b29b uxth r3, r3
|
|||
|
|
8001cb0: 2b00 cmp r3, #0
|
|||
|
|
8001cb2: d10b bne.n 8001ccc <rdPar+0xd0>
|
|||
|
|
pardata.IKE = 0;
|
|||
|
|
8001cb4: 4b29 ldr r3, [pc, #164] ; (8001d5c <rdPar+0x160>)
|
|||
|
|
8001cb6: 2200 movs r2, #0
|
|||
|
|
8001cb8: 81da strh r2, [r3, #14]
|
|||
|
|
pardata.IKD = 0;
|
|||
|
|
8001cba: 4b28 ldr r3, [pc, #160] ; (8001d5c <rdPar+0x160>)
|
|||
|
|
8001cbc: 2200 movs r2, #0
|
|||
|
|
8001cbe: 821a strh r2, [r3, #16]
|
|||
|
|
pardata.IKS = 1;
|
|||
|
|
8001cc0: 4b26 ldr r3, [pc, #152] ; (8001d5c <rdPar+0x160>)
|
|||
|
|
8001cc2: 2201 movs r2, #1
|
|||
|
|
8001cc4: 825a strh r2, [r3, #18]
|
|||
|
|
rewrite = true;
|
|||
|
|
8001cc6: 1dfb adds r3, r7, #7
|
|||
|
|
8001cc8: 2201 movs r2, #1
|
|||
|
|
8001cca: 701a strb r2, [r3, #0]
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
if(pardata.SENS == 0.0f) {
|
|||
|
|
8001ccc: 4b23 ldr r3, [pc, #140] ; (8001d5c <rdPar+0x160>)
|
|||
|
|
8001cce: 6a1b ldr r3, [r3, #32]
|
|||
|
|
8001cd0: 2100 movs r1, #0
|
|||
|
|
8001cd2: 1c18 adds r0, r3, #0
|
|||
|
|
8001cd4: f7fe faee bl 80002b4 <__aeabi_fcmpeq>
|
|||
|
|
8001cd8: 1e03 subs r3, r0, #0
|
|||
|
|
8001cda: d006 beq.n 8001cea <rdPar+0xee>
|
|||
|
|
pardata.SENS = 1.0f;
|
|||
|
|
8001cdc: 4b1f ldr r3, [pc, #124] ; (8001d5c <rdPar+0x160>)
|
|||
|
|
8001cde: 22fe movs r2, #254 ; 0xfe
|
|||
|
|
8001ce0: 0592 lsls r2, r2, #22
|
|||
|
|
8001ce2: 621a str r2, [r3, #32]
|
|||
|
|
rewrite = true;
|
|||
|
|
8001ce4: 1dfb adds r3, r7, #7
|
|||
|
|
8001ce6: 2201 movs r2, #1
|
|||
|
|
8001ce8: 701a strb r2, [r3, #0]
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
if(pardata.IFN > Lp100000) {
|
|||
|
|
8001cea: 4b1c ldr r3, [pc, #112] ; (8001d5c <rdPar+0x160>)
|
|||
|
|
8001cec: 895b ldrh r3, [r3, #10]
|
|||
|
|
8001cee: b29b uxth r3, r3
|
|||
|
|
8001cf0: 2b07 cmp r3, #7
|
|||
|
|
8001cf2: d905 bls.n 8001d00 <rdPar+0x104>
|
|||
|
|
pardata.IFN = Lp100000;
|
|||
|
|
8001cf4: 4b19 ldr r3, [pc, #100] ; (8001d5c <rdPar+0x160>)
|
|||
|
|
8001cf6: 2207 movs r2, #7
|
|||
|
|
8001cf8: 815a strh r2, [r3, #10]
|
|||
|
|
rewrite = true;
|
|||
|
|
8001cfa: 1dfb adds r3, r7, #7
|
|||
|
|
8001cfc: 2201 movs r2, #1
|
|||
|
|
8001cfe: 701a strb r2, [r3, #0]
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
if(pardata.IFV > Hp10) {
|
|||
|
|
8001d00: 4b16 ldr r3, [pc, #88] ; (8001d5c <rdPar+0x160>)
|
|||
|
|
8001d02: 891b ldrh r3, [r3, #8]
|
|||
|
|
8001d04: b29b uxth r3, r3
|
|||
|
|
8001d06: 2b04 cmp r3, #4
|
|||
|
|
8001d08: d905 bls.n 8001d16 <rdPar+0x11a>
|
|||
|
|
pardata.IFN = Hp10;
|
|||
|
|
8001d0a: 4b14 ldr r3, [pc, #80] ; (8001d5c <rdPar+0x160>)
|
|||
|
|
8001d0c: 2204 movs r2, #4
|
|||
|
|
8001d0e: 815a strh r2, [r3, #10]
|
|||
|
|
rewrite = true;
|
|||
|
|
8001d10: 1dfb adds r3, r7, #7
|
|||
|
|
8001d12: 2201 movs r2, #1
|
|||
|
|
8001d14: 701a strb r2, [r3, #0]
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
if(pardata.IKU > Ku1000) {
|
|||
|
|
8001d16: 4b11 ldr r3, [pc, #68] ; (8001d5c <rdPar+0x160>)
|
|||
|
|
8001d18: 899b ldrh r3, [r3, #12]
|
|||
|
|
8001d1a: b29b uxth r3, r3
|
|||
|
|
8001d1c: 2b0c cmp r3, #12
|
|||
|
|
8001d1e: d905 bls.n 8001d2c <rdPar+0x130>
|
|||
|
|
pardata.IKU = Ku1000;
|
|||
|
|
8001d20: 4b0e ldr r3, [pc, #56] ; (8001d5c <rdPar+0x160>)
|
|||
|
|
8001d22: 220c movs r2, #12
|
|||
|
|
8001d24: 819a strh r2, [r3, #12]
|
|||
|
|
rewrite = true;
|
|||
|
|
8001d26: 1dfb adds r3, r7, #7
|
|||
|
|
8001d28: 2201 movs r2, #1
|
|||
|
|
8001d2a: 701a strb r2, [r3, #0]
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
if(pardata.VAL > Nython) {
|
|||
|
|
8001d2c: 4b0b ldr r3, [pc, #44] ; (8001d5c <rdPar+0x160>)
|
|||
|
|
8001d2e: 8b1b ldrh r3, [r3, #24]
|
|||
|
|
8001d30: b29b uxth r3, r3
|
|||
|
|
8001d32: 2b05 cmp r3, #5
|
|||
|
|
8001d34: d905 bls.n 8001d42 <rdPar+0x146>
|
|||
|
|
pardata.VAL = Accel;
|
|||
|
|
8001d36: 4b09 ldr r3, [pc, #36] ; (8001d5c <rdPar+0x160>)
|
|||
|
|
8001d38: 2200 movs r2, #0
|
|||
|
|
8001d3a: 831a strh r2, [r3, #24]
|
|||
|
|
rewrite = true;
|
|||
|
|
8001d3c: 1dfb adds r3, r7, #7
|
|||
|
|
8001d3e: 2201 movs r2, #1
|
|||
|
|
8001d40: 701a strb r2, [r3, #0]
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
|
|||
|
|
/////////////////////////////
|
|||
|
|
if(rewrite)
|
|||
|
|
8001d42: 1dfb adds r3, r7, #7
|
|||
|
|
8001d44: 781b ldrb r3, [r3, #0]
|
|||
|
|
8001d46: 2b00 cmp r3, #0
|
|||
|
|
8001d48: d004 beq.n 8001d54 <rdPar+0x158>
|
|||
|
|
{
|
|||
|
|
rewrite = 0;
|
|||
|
|
8001d4a: 1dfb adds r3, r7, #7
|
|||
|
|
8001d4c: 2200 movs r2, #0
|
|||
|
|
8001d4e: 701a strb r2, [r3, #0]
|
|||
|
|
wrPar();
|
|||
|
|
8001d50: f7ff fef6 bl 8001b40 <wrPar>
|
|||
|
|
}
|
|||
|
|
/////////////////////////////
|
|||
|
|
}
|
|||
|
|
8001d54: 46c0 nop ; (mov r8, r8)
|
|||
|
|
8001d56: 46bd mov sp, r7
|
|||
|
|
8001d58: b003 add sp, #12
|
|||
|
|
8001d5a: bd90 pop {r4, r7, pc}
|
|||
|
|
8001d5c: 20000098 .word 0x20000098
|
|||
|
|
8001d60: 0801ff00 .word 0x0801ff00
|
|||
|
|
8001d64: 3f800054 .word 0x3f800054
|
|||
|
|
8001d68: 4120000a .word 0x4120000a
|
|||
|
|
|
|||
|
|
08001d6c <wrCorr>:
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
void wrCorr(void)
|
|||
|
|
{
|
|||
|
|
8001d6c: b580 push {r7, lr}
|
|||
|
|
8001d6e: b084 sub sp, #16
|
|||
|
|
8001d70: af00 add r7, sp, #0
|
|||
|
|
uint8_t i, len;
|
|||
|
|
uint32_t *pData, Address;
|
|||
|
|
|
|||
|
|
len = sizeof(CorrWord);
|
|||
|
|
8001d72: 1cfb adds r3, r7, #3
|
|||
|
|
8001d74: 2250 movs r2, #80 ; 0x50
|
|||
|
|
8001d76: 701a strb r2, [r3, #0]
|
|||
|
|
len >>= 2;
|
|||
|
|
8001d78: 1cfb adds r3, r7, #3
|
|||
|
|
8001d7a: 1cfa adds r2, r7, #3
|
|||
|
|
8001d7c: 7812 ldrb r2, [r2, #0]
|
|||
|
|
8001d7e: 0892 lsrs r2, r2, #2
|
|||
|
|
8001d80: 701a strb r2, [r3, #0]
|
|||
|
|
|
|||
|
|
HAL_FLASH_Unlock();
|
|||
|
|
8001d82: f002 fab1 bl 80042e8 <HAL_FLASH_Unlock>
|
|||
|
|
FLASH_PageErase(CORRPAGE);
|
|||
|
|
8001d86: 4b24 ldr r3, [pc, #144] ; (8001e18 <wrCorr+0xac>)
|
|||
|
|
8001d88: 0018 movs r0, r3
|
|||
|
|
8001d8a: f002 fc1f bl 80045cc <FLASH_PageErase>
|
|||
|
|
CLEAR_BIT(FLASH->PECR, FLASH_PECR_PROG);
|
|||
|
|
8001d8e: 4b23 ldr r3, [pc, #140] ; (8001e1c <wrCorr+0xb0>)
|
|||
|
|
8001d90: 4a22 ldr r2, [pc, #136] ; (8001e1c <wrCorr+0xb0>)
|
|||
|
|
8001d92: 6852 ldr r2, [r2, #4]
|
|||
|
|
8001d94: 2108 movs r1, #8
|
|||
|
|
8001d96: 438a bics r2, r1
|
|||
|
|
8001d98: 605a str r2, [r3, #4]
|
|||
|
|
CLEAR_BIT(FLASH->PECR, FLASH_PECR_ERASE);
|
|||
|
|
8001d9a: 4b20 ldr r3, [pc, #128] ; (8001e1c <wrCorr+0xb0>)
|
|||
|
|
8001d9c: 4a1f ldr r2, [pc, #124] ; (8001e1c <wrCorr+0xb0>)
|
|||
|
|
8001d9e: 6852 ldr r2, [r2, #4]
|
|||
|
|
8001da0: 491f ldr r1, [pc, #124] ; (8001e20 <wrCorr+0xb4>)
|
|||
|
|
8001da2: 400a ands r2, r1
|
|||
|
|
8001da4: 605a str r2, [r3, #4]
|
|||
|
|
FLASH_WaitForLastOperation(100);
|
|||
|
|
8001da6: 2064 movs r0, #100 ; 0x64
|
|||
|
|
8001da8: f002 fb02 bl 80043b0 <FLASH_WaitForLastOperation>
|
|||
|
|
|
|||
|
|
Address = CORRPAGE;
|
|||
|
|
8001dac: 4b1a ldr r3, [pc, #104] ; (8001e18 <wrCorr+0xac>)
|
|||
|
|
8001dae: 607b str r3, [r7, #4]
|
|||
|
|
pData = (uint32_t *) &CorrWord;
|
|||
|
|
8001db0: 4b1c ldr r3, [pc, #112] ; (8001e24 <wrCorr+0xb8>)
|
|||
|
|
8001db2: 60bb str r3, [r7, #8]
|
|||
|
|
for(i = 0; i < len; i++)
|
|||
|
|
8001db4: 230f movs r3, #15
|
|||
|
|
8001db6: 18fb adds r3, r7, r3
|
|||
|
|
8001db8: 2200 movs r2, #0
|
|||
|
|
8001dba: 701a strb r2, [r3, #0]
|
|||
|
|
8001dbc: e012 b.n 8001de4 <wrCorr+0x78>
|
|||
|
|
{
|
|||
|
|
HAL_FLASH_Program(FLASH_TYPEPROGRAM_WORD, Address, *pData++);
|
|||
|
|
8001dbe: 68bb ldr r3, [r7, #8]
|
|||
|
|
8001dc0: 1d1a adds r2, r3, #4
|
|||
|
|
8001dc2: 60ba str r2, [r7, #8]
|
|||
|
|
8001dc4: 681a ldr r2, [r3, #0]
|
|||
|
|
8001dc6: 687b ldr r3, [r7, #4]
|
|||
|
|
8001dc8: 0019 movs r1, r3
|
|||
|
|
8001dca: 2002 movs r0, #2
|
|||
|
|
8001dcc: f002 fa50 bl 8004270 <HAL_FLASH_Program>
|
|||
|
|
Address += 4;
|
|||
|
|
8001dd0: 687b ldr r3, [r7, #4]
|
|||
|
|
8001dd2: 3304 adds r3, #4
|
|||
|
|
8001dd4: 607b str r3, [r7, #4]
|
|||
|
|
for(i = 0; i < len; i++)
|
|||
|
|
8001dd6: 230f movs r3, #15
|
|||
|
|
8001dd8: 18fb adds r3, r7, r3
|
|||
|
|
8001dda: 781a ldrb r2, [r3, #0]
|
|||
|
|
8001ddc: 230f movs r3, #15
|
|||
|
|
8001dde: 18fb adds r3, r7, r3
|
|||
|
|
8001de0: 3201 adds r2, #1
|
|||
|
|
8001de2: 701a strb r2, [r3, #0]
|
|||
|
|
8001de4: 230f movs r3, #15
|
|||
|
|
8001de6: 18fa adds r2, r7, r3
|
|||
|
|
8001de8: 1cfb adds r3, r7, #3
|
|||
|
|
8001dea: 7812 ldrb r2, [r2, #0]
|
|||
|
|
8001dec: 781b ldrb r3, [r3, #0]
|
|||
|
|
8001dee: 429a cmp r2, r3
|
|||
|
|
8001df0: d3e5 bcc.n 8001dbe <wrCorr+0x52>
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
CLEAR_BIT(FLASH->PECR, FLASH_PECR_PROG);
|
|||
|
|
8001df2: 4b0a ldr r3, [pc, #40] ; (8001e1c <wrCorr+0xb0>)
|
|||
|
|
8001df4: 4a09 ldr r2, [pc, #36] ; (8001e1c <wrCorr+0xb0>)
|
|||
|
|
8001df6: 6852 ldr r2, [r2, #4]
|
|||
|
|
8001df8: 2108 movs r1, #8
|
|||
|
|
8001dfa: 438a bics r2, r1
|
|||
|
|
8001dfc: 605a str r2, [r3, #4]
|
|||
|
|
CLEAR_BIT(FLASH->PECR, FLASH_PECR_ERASE);
|
|||
|
|
8001dfe: 4b07 ldr r3, [pc, #28] ; (8001e1c <wrCorr+0xb0>)
|
|||
|
|
8001e00: 4a06 ldr r2, [pc, #24] ; (8001e1c <wrCorr+0xb0>)
|
|||
|
|
8001e02: 6852 ldr r2, [r2, #4]
|
|||
|
|
8001e04: 4906 ldr r1, [pc, #24] ; (8001e20 <wrCorr+0xb4>)
|
|||
|
|
8001e06: 400a ands r2, r1
|
|||
|
|
8001e08: 605a str r2, [r3, #4]
|
|||
|
|
HAL_FLASH_Lock();
|
|||
|
|
8001e0a: f002 fabd bl 8004388 <HAL_FLASH_Lock>
|
|||
|
|
}
|
|||
|
|
8001e0e: 46c0 nop ; (mov r8, r8)
|
|||
|
|
8001e10: 46bd mov sp, r7
|
|||
|
|
8001e12: b004 add sp, #16
|
|||
|
|
8001e14: bd80 pop {r7, pc}
|
|||
|
|
8001e16: 46c0 nop ; (mov r8, r8)
|
|||
|
|
8001e18: 0801ff80 .word 0x0801ff80
|
|||
|
|
8001e1c: 40022000 .word 0x40022000
|
|||
|
|
8001e20: fffffdff .word 0xfffffdff
|
|||
|
|
8001e24: 20000048 .word 0x20000048
|
|||
|
|
|
|||
|
|
08001e28 <rdCorr>:
|
|||
|
|
|
|||
|
|
|
|||
|
|
void rdCorr(void)
|
|||
|
|
{
|
|||
|
|
8001e28: b5b0 push {r4, r5, r7, lr}
|
|||
|
|
8001e2a: b082 sub sp, #8
|
|||
|
|
8001e2c: af00 add r7, sp, #0
|
|||
|
|
uint8_t i, j;
|
|||
|
|
|
|||
|
|
memcpy((void *) &CorrWord, (void *) CORRPAGE, sizeof(CorrWord));
|
|||
|
|
8001e2e: 4b2b ldr r3, [pc, #172] ; (8001edc <rdCorr+0xb4>)
|
|||
|
|
8001e30: 4a2b ldr r2, [pc, #172] ; (8001ee0 <rdCorr+0xb8>)
|
|||
|
|
8001e32: 0018 movs r0, r3
|
|||
|
|
8001e34: 0011 movs r1, r2
|
|||
|
|
8001e36: 2350 movs r3, #80 ; 0x50
|
|||
|
|
8001e38: 001a movs r2, r3
|
|||
|
|
8001e3a: f005 f8b7 bl 8006fac <memcpy>
|
|||
|
|
|
|||
|
|
if(((CorrWord[0][0] == 0xffff) || (CorrWord[0][1] == 0xffff)) || ((CorrWord[0][0] == 0) || (CorrWord[0][1] == 0)))
|
|||
|
|
8001e3e: 4b27 ldr r3, [pc, #156] ; (8001edc <rdCorr+0xb4>)
|
|||
|
|
8001e40: 881b ldrh r3, [r3, #0]
|
|||
|
|
8001e42: b29b uxth r3, r3
|
|||
|
|
8001e44: 4a27 ldr r2, [pc, #156] ; (8001ee4 <rdCorr+0xbc>)
|
|||
|
|
8001e46: 4293 cmp r3, r2
|
|||
|
|
8001e48: d00f beq.n 8001e6a <rdCorr+0x42>
|
|||
|
|
8001e4a: 4b24 ldr r3, [pc, #144] ; (8001edc <rdCorr+0xb4>)
|
|||
|
|
8001e4c: 885b ldrh r3, [r3, #2]
|
|||
|
|
8001e4e: b29b uxth r3, r3
|
|||
|
|
8001e50: 4a24 ldr r2, [pc, #144] ; (8001ee4 <rdCorr+0xbc>)
|
|||
|
|
8001e52: 4293 cmp r3, r2
|
|||
|
|
8001e54: d009 beq.n 8001e6a <rdCorr+0x42>
|
|||
|
|
8001e56: 4b21 ldr r3, [pc, #132] ; (8001edc <rdCorr+0xb4>)
|
|||
|
|
8001e58: 881b ldrh r3, [r3, #0]
|
|||
|
|
8001e5a: b29b uxth r3, r3
|
|||
|
|
8001e5c: 2b00 cmp r3, #0
|
|||
|
|
8001e5e: d004 beq.n 8001e6a <rdCorr+0x42>
|
|||
|
|
8001e60: 4b1e ldr r3, [pc, #120] ; (8001edc <rdCorr+0xb4>)
|
|||
|
|
8001e62: 885b ldrh r3, [r3, #2]
|
|||
|
|
8001e64: b29b uxth r3, r3
|
|||
|
|
8001e66: 2b00 cmp r3, #0
|
|||
|
|
8001e68: d134 bne.n 8001ed4 <rdCorr+0xac>
|
|||
|
|
{
|
|||
|
|
for(j = 0; j < 2; j++)
|
|||
|
|
8001e6a: 1dbb adds r3, r7, #6
|
|||
|
|
8001e6c: 2200 movs r2, #0
|
|||
|
|
8001e6e: 701a strb r2, [r3, #0]
|
|||
|
|
8001e70: e02a b.n 8001ec8 <rdCorr+0xa0>
|
|||
|
|
{
|
|||
|
|
for(i = 0; i < 20; i++) {
|
|||
|
|
8001e72: 1dfb adds r3, r7, #7
|
|||
|
|
8001e74: 2200 movs r2, #0
|
|||
|
|
8001e76: 701a strb r2, [r3, #0]
|
|||
|
|
8001e78: e01d b.n 8001eb6 <rdCorr+0x8e>
|
|||
|
|
CorrWord[j][i] = FACTORY_CORR[j][i];
|
|||
|
|
8001e7a: 1dbb adds r3, r7, #6
|
|||
|
|
8001e7c: 781a ldrb r2, [r3, #0]
|
|||
|
|
8001e7e: 1dfb adds r3, r7, #7
|
|||
|
|
8001e80: 7818 ldrb r0, [r3, #0]
|
|||
|
|
8001e82: 1dbb adds r3, r7, #6
|
|||
|
|
8001e84: 7819 ldrb r1, [r3, #0]
|
|||
|
|
8001e86: 1dfb adds r3, r7, #7
|
|||
|
|
8001e88: 781d ldrb r5, [r3, #0]
|
|||
|
|
8001e8a: 4c17 ldr r4, [pc, #92] ; (8001ee8 <rdCorr+0xc0>)
|
|||
|
|
8001e8c: 000b movs r3, r1
|
|||
|
|
8001e8e: 009b lsls r3, r3, #2
|
|||
|
|
8001e90: 185b adds r3, r3, r1
|
|||
|
|
8001e92: 009b lsls r3, r3, #2
|
|||
|
|
8001e94: 195b adds r3, r3, r5
|
|||
|
|
8001e96: 005b lsls r3, r3, #1
|
|||
|
|
8001e98: 5b1c ldrh r4, [r3, r4]
|
|||
|
|
8001e9a: 4910 ldr r1, [pc, #64] ; (8001edc <rdCorr+0xb4>)
|
|||
|
|
8001e9c: 0013 movs r3, r2
|
|||
|
|
8001e9e: 009b lsls r3, r3, #2
|
|||
|
|
8001ea0: 189b adds r3, r3, r2
|
|||
|
|
8001ea2: 009b lsls r3, r3, #2
|
|||
|
|
8001ea4: 181b adds r3, r3, r0
|
|||
|
|
8001ea6: 005b lsls r3, r3, #1
|
|||
|
|
8001ea8: 1c22 adds r2, r4, #0
|
|||
|
|
8001eaa: 525a strh r2, [r3, r1]
|
|||
|
|
for(i = 0; i < 20; i++) {
|
|||
|
|
8001eac: 1dfb adds r3, r7, #7
|
|||
|
|
8001eae: 781a ldrb r2, [r3, #0]
|
|||
|
|
8001eb0: 1dfb adds r3, r7, #7
|
|||
|
|
8001eb2: 3201 adds r2, #1
|
|||
|
|
8001eb4: 701a strb r2, [r3, #0]
|
|||
|
|
8001eb6: 1dfb adds r3, r7, #7
|
|||
|
|
8001eb8: 781b ldrb r3, [r3, #0]
|
|||
|
|
8001eba: 2b13 cmp r3, #19
|
|||
|
|
8001ebc: d9dd bls.n 8001e7a <rdCorr+0x52>
|
|||
|
|
for(j = 0; j < 2; j++)
|
|||
|
|
8001ebe: 1dbb adds r3, r7, #6
|
|||
|
|
8001ec0: 781a ldrb r2, [r3, #0]
|
|||
|
|
8001ec2: 1dbb adds r3, r7, #6
|
|||
|
|
8001ec4: 3201 adds r2, #1
|
|||
|
|
8001ec6: 701a strb r2, [r3, #0]
|
|||
|
|
8001ec8: 1dbb adds r3, r7, #6
|
|||
|
|
8001eca: 781b ldrb r3, [r3, #0]
|
|||
|
|
8001ecc: 2b01 cmp r3, #1
|
|||
|
|
8001ece: d9d0 bls.n 8001e72 <rdCorr+0x4a>
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
wrCorr();
|
|||
|
|
8001ed0: f7ff ff4c bl 8001d6c <wrCorr>
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
8001ed4: 46c0 nop ; (mov r8, r8)
|
|||
|
|
8001ed6: 46bd mov sp, r7
|
|||
|
|
8001ed8: b002 add sp, #8
|
|||
|
|
8001eda: bdb0 pop {r4, r5, r7, pc}
|
|||
|
|
8001edc: 20000048 .word 0x20000048
|
|||
|
|
8001ee0: 0801ff80 .word 0x0801ff80
|
|||
|
|
8001ee4: 0000ffff .word 0x0000ffff
|
|||
|
|
8001ee8: 0800716c .word 0x0800716c
|
|||
|
|
|
|||
|
|
08001eec <MX_GPIO_Init>:
|
|||
|
|
* Output
|
|||
|
|
* EVENT_OUT
|
|||
|
|
* EXTI
|
|||
|
|
*/
|
|||
|
|
void MX_GPIO_Init(void)
|
|||
|
|
{
|
|||
|
|
8001eec: b580 push {r7, lr}
|
|||
|
|
8001eee: b088 sub sp, #32
|
|||
|
|
8001ef0: af00 add r7, sp, #0
|
|||
|
|
|
|||
|
|
GPIO_InitTypeDef GPIO_InitStruct = {0};
|
|||
|
|
8001ef2: 230c movs r3, #12
|
|||
|
|
8001ef4: 18fb adds r3, r7, r3
|
|||
|
|
8001ef6: 0018 movs r0, r3
|
|||
|
|
8001ef8: 2314 movs r3, #20
|
|||
|
|
8001efa: 001a movs r2, r3
|
|||
|
|
8001efc: 2100 movs r1, #0
|
|||
|
|
8001efe: f005 f85e bl 8006fbe <memset>
|
|||
|
|
|
|||
|
|
/* GPIO Ports Clock Enable */
|
|||
|
|
__HAL_RCC_GPIOA_CLK_ENABLE();
|
|||
|
|
8001f02: 4b5a ldr r3, [pc, #360] ; (800206c <MX_GPIO_Init+0x180>)
|
|||
|
|
8001f04: 4a59 ldr r2, [pc, #356] ; (800206c <MX_GPIO_Init+0x180>)
|
|||
|
|
8001f06: 6ad2 ldr r2, [r2, #44] ; 0x2c
|
|||
|
|
8001f08: 2101 movs r1, #1
|
|||
|
|
8001f0a: 430a orrs r2, r1
|
|||
|
|
8001f0c: 62da str r2, [r3, #44] ; 0x2c
|
|||
|
|
8001f0e: 4b57 ldr r3, [pc, #348] ; (800206c <MX_GPIO_Init+0x180>)
|
|||
|
|
8001f10: 6adb ldr r3, [r3, #44] ; 0x2c
|
|||
|
|
8001f12: 2201 movs r2, #1
|
|||
|
|
8001f14: 4013 ands r3, r2
|
|||
|
|
8001f16: 60bb str r3, [r7, #8]
|
|||
|
|
8001f18: 68bb ldr r3, [r7, #8]
|
|||
|
|
__HAL_RCC_GPIOB_CLK_ENABLE();
|
|||
|
|
8001f1a: 4b54 ldr r3, [pc, #336] ; (800206c <MX_GPIO_Init+0x180>)
|
|||
|
|
8001f1c: 4a53 ldr r2, [pc, #332] ; (800206c <MX_GPIO_Init+0x180>)
|
|||
|
|
8001f1e: 6ad2 ldr r2, [r2, #44] ; 0x2c
|
|||
|
|
8001f20: 2102 movs r1, #2
|
|||
|
|
8001f22: 430a orrs r2, r1
|
|||
|
|
8001f24: 62da str r2, [r3, #44] ; 0x2c
|
|||
|
|
8001f26: 4b51 ldr r3, [pc, #324] ; (800206c <MX_GPIO_Init+0x180>)
|
|||
|
|
8001f28: 6adb ldr r3, [r3, #44] ; 0x2c
|
|||
|
|
8001f2a: 2202 movs r2, #2
|
|||
|
|
8001f2c: 4013 ands r3, r2
|
|||
|
|
8001f2e: 607b str r3, [r7, #4]
|
|||
|
|
8001f30: 687b ldr r3, [r7, #4]
|
|||
|
|
|
|||
|
|
/*Configure GPIO pin Output Level */
|
|||
|
|
HAL_GPIO_WritePin(GPIOA, PER_Pin|RE_Pin, GPIO_PIN_RESET);
|
|||
|
|
8001f32: 2388 movs r3, #136 ; 0x88
|
|||
|
|
8001f34: 0059 lsls r1, r3, #1
|
|||
|
|
8001f36: 23a0 movs r3, #160 ; 0xa0
|
|||
|
|
8001f38: 05db lsls r3, r3, #23
|
|||
|
|
8001f3a: 2200 movs r2, #0
|
|||
|
|
8001f3c: 0018 movs r0, r3
|
|||
|
|
8001f3e: f002 fde6 bl 8004b0e <HAL_GPIO_WritePin>
|
|||
|
|
|
|||
|
|
/*Configure GPIO pin Output Level */
|
|||
|
|
HAL_GPIO_WritePin(GPIOB, A0_Pin|A1_Pin|A2_Pin|A10_Pin
|
|||
|
|
8001f42: 494b ldr r1, [pc, #300] ; (8002070 <MX_GPIO_Init+0x184>)
|
|||
|
|
8001f44: 4b4b ldr r3, [pc, #300] ; (8002074 <MX_GPIO_Init+0x188>)
|
|||
|
|
8001f46: 2200 movs r2, #0
|
|||
|
|
8001f48: 0018 movs r0, r3
|
|||
|
|
8001f4a: f002 fde0 bl 8004b0e <HAL_GPIO_WritePin>
|
|||
|
|
|A11_Pin|A12_Pin|A3_Pin|A4_Pin
|
|||
|
|
|A5_Pin|A6_Pin|A7_Pin|A8_Pin
|
|||
|
|
|A9_Pin, GPIO_PIN_RESET);
|
|||
|
|
|
|||
|
|
/*Configure GPIO pin Output Level */
|
|||
|
|
HAL_GPIO_WritePin(GPIOB, FL_Pin|STD_Pin|SCK_Pin, GPIO_PIN_SET);
|
|||
|
|
8001f4e: 23e0 movs r3, #224 ; 0xe0
|
|||
|
|
8001f50: 021b lsls r3, r3, #8
|
|||
|
|
8001f52: 4848 ldr r0, [pc, #288] ; (8002074 <MX_GPIO_Init+0x188>)
|
|||
|
|
8001f54: 2201 movs r2, #1
|
|||
|
|
8001f56: 0019 movs r1, r3
|
|||
|
|
8001f58: f002 fdd9 bl 8004b0e <HAL_GPIO_WritePin>
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
/*Configure GPIO pin : PtPin */
|
|||
|
|
GPIO_InitStruct.Pin = PER_Pin;
|
|||
|
|
8001f5c: 230c movs r3, #12
|
|||
|
|
8001f5e: 18fb adds r3, r7, r3
|
|||
|
|
8001f60: 2210 movs r2, #16
|
|||
|
|
8001f62: 601a str r2, [r3, #0]
|
|||
|
|
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
|
|||
|
|
8001f64: 230c movs r3, #12
|
|||
|
|
8001f66: 18fb adds r3, r7, r3
|
|||
|
|
8001f68: 2201 movs r2, #1
|
|||
|
|
8001f6a: 605a str r2, [r3, #4]
|
|||
|
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|||
|
|
8001f6c: 230c movs r3, #12
|
|||
|
|
8001f6e: 18fb adds r3, r7, r3
|
|||
|
|
8001f70: 2200 movs r2, #0
|
|||
|
|
8001f72: 609a str r2, [r3, #8]
|
|||
|
|
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
|
|||
|
|
8001f74: 230c movs r3, #12
|
|||
|
|
8001f76: 18fb adds r3, r7, r3
|
|||
|
|
8001f78: 2202 movs r2, #2
|
|||
|
|
8001f7a: 60da str r2, [r3, #12]
|
|||
|
|
HAL_GPIO_Init(PER_GPIO_Port, &GPIO_InitStruct);
|
|||
|
|
8001f7c: 230c movs r3, #12
|
|||
|
|
8001f7e: 18fa adds r2, r7, r3
|
|||
|
|
8001f80: 23a0 movs r3, #160 ; 0xa0
|
|||
|
|
8001f82: 05db lsls r3, r3, #23
|
|||
|
|
8001f84: 0011 movs r1, r2
|
|||
|
|
8001f86: 0018 movs r0, r3
|
|||
|
|
8001f88: f002 fb42 bl 8004610 <HAL_GPIO_Init>
|
|||
|
|
|
|||
|
|
/*Configure GPIO pins : PBPin PBPin PBPin PBPin
|
|||
|
|
PBPin PBPin PBPin PBPin
|
|||
|
|
PBPin PBPin PBPin PBPin
|
|||
|
|
PBPin */
|
|||
|
|
GPIO_InitStruct.Pin = A0_Pin|A1_Pin|A2_Pin|A10_Pin
|
|||
|
|
8001f8c: 230c movs r3, #12
|
|||
|
|
8001f8e: 18fb adds r3, r7, r3
|
|||
|
|
8001f90: 4a37 ldr r2, [pc, #220] ; (8002070 <MX_GPIO_Init+0x184>)
|
|||
|
|
8001f92: 601a str r2, [r3, #0]
|
|||
|
|
|A11_Pin|A12_Pin|A3_Pin|A4_Pin
|
|||
|
|
|A5_Pin|A6_Pin|A7_Pin|A8_Pin
|
|||
|
|
|A9_Pin;
|
|||
|
|
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
|
|||
|
|
8001f94: 230c movs r3, #12
|
|||
|
|
8001f96: 18fb adds r3, r7, r3
|
|||
|
|
8001f98: 2201 movs r2, #1
|
|||
|
|
8001f9a: 605a str r2, [r3, #4]
|
|||
|
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|||
|
|
8001f9c: 230c movs r3, #12
|
|||
|
|
8001f9e: 18fb adds r3, r7, r3
|
|||
|
|
8001fa0: 2200 movs r2, #0
|
|||
|
|
8001fa2: 609a str r2, [r3, #8]
|
|||
|
|
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
|
|||
|
|
8001fa4: 230c movs r3, #12
|
|||
|
|
8001fa6: 18fb adds r3, r7, r3
|
|||
|
|
8001fa8: 2200 movs r2, #0
|
|||
|
|
8001faa: 60da str r2, [r3, #12]
|
|||
|
|
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
|
|||
|
|
8001fac: 230c movs r3, #12
|
|||
|
|
8001fae: 18fb adds r3, r7, r3
|
|||
|
|
8001fb0: 4a30 ldr r2, [pc, #192] ; (8002074 <MX_GPIO_Init+0x188>)
|
|||
|
|
8001fb2: 0019 movs r1, r3
|
|||
|
|
8001fb4: 0010 movs r0, r2
|
|||
|
|
8001fb6: f002 fb2b bl 8004610 <HAL_GPIO_Init>
|
|||
|
|
|
|||
|
|
/*Configure GPIO pins : PBPin PBPin PBPin */
|
|||
|
|
GPIO_InitStruct.Pin = FL_Pin|STD_Pin|SCK_Pin;
|
|||
|
|
8001fba: 230c movs r3, #12
|
|||
|
|
8001fbc: 18fb adds r3, r7, r3
|
|||
|
|
8001fbe: 22e0 movs r2, #224 ; 0xe0
|
|||
|
|
8001fc0: 0212 lsls r2, r2, #8
|
|||
|
|
8001fc2: 601a str r2, [r3, #0]
|
|||
|
|
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
|
|||
|
|
8001fc4: 230c movs r3, #12
|
|||
|
|
8001fc6: 18fb adds r3, r7, r3
|
|||
|
|
8001fc8: 2201 movs r2, #1
|
|||
|
|
8001fca: 605a str r2, [r3, #4]
|
|||
|
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|||
|
|
8001fcc: 230c movs r3, #12
|
|||
|
|
8001fce: 18fb adds r3, r7, r3
|
|||
|
|
8001fd0: 2200 movs r2, #0
|
|||
|
|
8001fd2: 609a str r2, [r3, #8]
|
|||
|
|
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
|
|||
|
|
8001fd4: 230c movs r3, #12
|
|||
|
|
8001fd6: 18fb adds r3, r7, r3
|
|||
|
|
8001fd8: 2203 movs r2, #3
|
|||
|
|
8001fda: 60da str r2, [r3, #12]
|
|||
|
|
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
|
|||
|
|
8001fdc: 230c movs r3, #12
|
|||
|
|
8001fde: 18fb adds r3, r7, r3
|
|||
|
|
8001fe0: 4a24 ldr r2, [pc, #144] ; (8002074 <MX_GPIO_Init+0x188>)
|
|||
|
|
8001fe2: 0019 movs r1, r3
|
|||
|
|
8001fe4: 0010 movs r0, r2
|
|||
|
|
8001fe6: f002 fb13 bl 8004610 <HAL_GPIO_Init>
|
|||
|
|
|
|||
|
|
/*Configure GPIO pin : PtPin */
|
|||
|
|
GPIO_InitStruct.Pin = RE_Pin;
|
|||
|
|
8001fea: 230c movs r3, #12
|
|||
|
|
8001fec: 18fb adds r3, r7, r3
|
|||
|
|
8001fee: 2280 movs r2, #128 ; 0x80
|
|||
|
|
8001ff0: 0052 lsls r2, r2, #1
|
|||
|
|
8001ff2: 601a str r2, [r3, #0]
|
|||
|
|
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
|
|||
|
|
8001ff4: 230c movs r3, #12
|
|||
|
|
8001ff6: 18fb adds r3, r7, r3
|
|||
|
|
8001ff8: 2201 movs r2, #1
|
|||
|
|
8001ffa: 605a str r2, [r3, #4]
|
|||
|
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|||
|
|
8001ffc: 230c movs r3, #12
|
|||
|
|
8001ffe: 18fb adds r3, r7, r3
|
|||
|
|
8002000: 2200 movs r2, #0
|
|||
|
|
8002002: 609a str r2, [r3, #8]
|
|||
|
|
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
|
|||
|
|
8002004: 230c movs r3, #12
|
|||
|
|
8002006: 18fb adds r3, r7, r3
|
|||
|
|
8002008: 2203 movs r2, #3
|
|||
|
|
800200a: 60da str r2, [r3, #12]
|
|||
|
|
HAL_GPIO_Init(RE_GPIO_Port, &GPIO_InitStruct);
|
|||
|
|
800200c: 230c movs r3, #12
|
|||
|
|
800200e: 18fa adds r2, r7, r3
|
|||
|
|
8002010: 23a0 movs r3, #160 ; 0xa0
|
|||
|
|
8002012: 05db lsls r3, r3, #23
|
|||
|
|
8002014: 0011 movs r1, r2
|
|||
|
|
8002016: 0018 movs r0, r3
|
|||
|
|
8002018: f002 fafa bl 8004610 <HAL_GPIO_Init>
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
/*Configure GPIO pins : PAPin PAPin PAPin */
|
|||
|
|
GPIO_InitStruct.Pin = UPER_Pin|OP_Pin|KZ_Pin;
|
|||
|
|
800201c: 230c movs r3, #12
|
|||
|
|
800201e: 18fb adds r3, r7, r3
|
|||
|
|
8002020: 2207 movs r2, #7
|
|||
|
|
8002022: 601a str r2, [r3, #0]
|
|||
|
|
GPIO_InitStruct.Mode = GPIO_MODE_IT_RISING_FALLING;
|
|||
|
|
8002024: 230c movs r3, #12
|
|||
|
|
8002026: 18fb adds r3, r7, r3
|
|||
|
|
8002028: 4a13 ldr r2, [pc, #76] ; (8002078 <MX_GPIO_Init+0x18c>)
|
|||
|
|
800202a: 605a str r2, [r3, #4]
|
|||
|
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|||
|
|
800202c: 230c movs r3, #12
|
|||
|
|
800202e: 18fb adds r3, r7, r3
|
|||
|
|
8002030: 2200 movs r2, #0
|
|||
|
|
8002032: 609a str r2, [r3, #8]
|
|||
|
|
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
|
|||
|
|
8002034: 230c movs r3, #12
|
|||
|
|
8002036: 18fa adds r2, r7, r3
|
|||
|
|
8002038: 23a0 movs r3, #160 ; 0xa0
|
|||
|
|
800203a: 05db lsls r3, r3, #23
|
|||
|
|
800203c: 0011 movs r1, r2
|
|||
|
|
800203e: 0018 movs r0, r3
|
|||
|
|
8002040: f002 fae6 bl 8004610 <HAL_GPIO_Init>
|
|||
|
|
|
|||
|
|
/* EXTI interrupt init*/
|
|||
|
|
HAL_NVIC_SetPriority(EXTI0_1_IRQn, 1, 0);
|
|||
|
|
8002044: 2200 movs r2, #0
|
|||
|
|
8002046: 2101 movs r1, #1
|
|||
|
|
8002048: 2005 movs r0, #5
|
|||
|
|
800204a: f002 f845 bl 80040d8 <HAL_NVIC_SetPriority>
|
|||
|
|
HAL_NVIC_EnableIRQ(EXTI0_1_IRQn);
|
|||
|
|
800204e: 2005 movs r0, #5
|
|||
|
|
8002050: f002 f858 bl 8004104 <HAL_NVIC_EnableIRQ>
|
|||
|
|
HAL_NVIC_SetPriority(EXTI2_3_IRQn, 1, 0);
|
|||
|
|
8002054: 2200 movs r2, #0
|
|||
|
|
8002056: 2101 movs r1, #1
|
|||
|
|
8002058: 2006 movs r0, #6
|
|||
|
|
800205a: f002 f83d bl 80040d8 <HAL_NVIC_SetPriority>
|
|||
|
|
HAL_NVIC_EnableIRQ(EXTI2_3_IRQn);
|
|||
|
|
800205e: 2006 movs r0, #6
|
|||
|
|
8002060: f002 f850 bl 8004104 <HAL_NVIC_EnableIRQ>
|
|||
|
|
|
|||
|
|
}
|
|||
|
|
8002064: 46c0 nop ; (mov r8, r8)
|
|||
|
|
8002066: 46bd mov sp, r7
|
|||
|
|
8002068: b008 add sp, #32
|
|||
|
|
800206a: bd80 pop {r7, pc}
|
|||
|
|
800206c: 40021000 .word 0x40021000
|
|||
|
|
8002070: 00001fff .word 0x00001fff
|
|||
|
|
8002074: 50000400 .word 0x50000400
|
|||
|
|
8002078: 10310000 .word 0x10310000
|
|||
|
|
|
|||
|
|
0800207c <main>:
|
|||
|
|
/**
|
|||
|
|
* @brief The application entry point.
|
|||
|
|
* @retval int
|
|||
|
|
*/
|
|||
|
|
int main(void)
|
|||
|
|
{
|
|||
|
|
800207c: b580 push {r7, lr}
|
|||
|
|
800207e: af00 add r7, sp, #0
|
|||
|
|
HAL_Init();
|
|||
|
|
8002080: f001 feee bl 8003e60 <HAL_Init>
|
|||
|
|
|
|||
|
|
SystemClock_Config();
|
|||
|
|
8002084: f000 f834 bl 80020f0 <SystemClock_Config>
|
|||
|
|
|
|||
|
|
MX_GPIO_Init();
|
|||
|
|
8002088: f7ff ff30 bl 8001eec <MX_GPIO_Init>
|
|||
|
|
MX_FLASH_Init();
|
|||
|
|
800208c: f7ff fd46 bl 8001b1c <MX_FLASH_Init>
|
|||
|
|
MX_TIM7_Init();
|
|||
|
|
8002090: f000 f93a bl 8002308 <MX_TIM7_Init>
|
|||
|
|
|
|||
|
|
//pardata.OWN = 1; // was defined in my.h
|
|||
|
|
SetAndCorrect();
|
|||
|
|
8002094: f7ff f8ec bl 8001270 <SetAndCorrect>
|
|||
|
|
|
|||
|
|
MX_USART1_UART_Init();
|
|||
|
|
8002098: f000 f9ac bl 80023f4 <MX_USART1_UART_Init>
|
|||
|
|
|
|||
|
|
|
|||
|
|
while (1)
|
|||
|
|
{
|
|||
|
|
if(needClbr)
|
|||
|
|
800209c: 4b11 ldr r3, [pc, #68] ; (80020e4 <main+0x68>)
|
|||
|
|
800209e: 781b ldrb r3, [r3, #0]
|
|||
|
|
80020a0: b2db uxtb r3, r3
|
|||
|
|
80020a2: 2b00 cmp r3, #0
|
|||
|
|
80020a4: d004 beq.n 80020b0 <main+0x34>
|
|||
|
|
{
|
|||
|
|
needClbr = false;
|
|||
|
|
80020a6: 4b0f ldr r3, [pc, #60] ; (80020e4 <main+0x68>)
|
|||
|
|
80020a8: 2200 movs r2, #0
|
|||
|
|
80020aa: 701a strb r2, [r3, #0]
|
|||
|
|
initCalibr();
|
|||
|
|
80020ac: f7ff fc0c bl 80018c8 <initCalibr>
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
if(needSave)
|
|||
|
|
80020b0: 4b0d ldr r3, [pc, #52] ; (80020e8 <main+0x6c>)
|
|||
|
|
80020b2: 781b ldrb r3, [r3, #0]
|
|||
|
|
80020b4: b2db uxtb r3, r3
|
|||
|
|
80020b6: 2b00 cmp r3, #0
|
|||
|
|
80020b8: d006 beq.n 80020c8 <main+0x4c>
|
|||
|
|
{
|
|||
|
|
needSave = false;
|
|||
|
|
80020ba: 4b0b ldr r3, [pc, #44] ; (80020e8 <main+0x6c>)
|
|||
|
|
80020bc: 2200 movs r2, #0
|
|||
|
|
80020be: 701a strb r2, [r3, #0]
|
|||
|
|
SetAndCorrect();
|
|||
|
|
80020c0: f7ff f8d6 bl 8001270 <SetAndCorrect>
|
|||
|
|
wrPar();
|
|||
|
|
80020c4: f7ff fd3c bl 8001b40 <wrPar>
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
if(needCorr)
|
|||
|
|
80020c8: 4b08 ldr r3, [pc, #32] ; (80020ec <main+0x70>)
|
|||
|
|
80020ca: 781b ldrb r3, [r3, #0]
|
|||
|
|
80020cc: b2db uxtb r3, r3
|
|||
|
|
80020ce: 2b00 cmp r3, #0
|
|||
|
|
80020d0: d0e4 beq.n 800209c <main+0x20>
|
|||
|
|
{
|
|||
|
|
needCorr = false;
|
|||
|
|
80020d2: 4b06 ldr r3, [pc, #24] ; (80020ec <main+0x70>)
|
|||
|
|
80020d4: 2200 movs r2, #0
|
|||
|
|
80020d6: 701a strb r2, [r3, #0]
|
|||
|
|
SetAndCorrect();
|
|||
|
|
80020d8: f7ff f8ca bl 8001270 <SetAndCorrect>
|
|||
|
|
wrCorr();
|
|||
|
|
80020dc: f7ff fe46 bl 8001d6c <wrCorr>
|
|||
|
|
if(needClbr)
|
|||
|
|
80020e0: e7dc b.n 800209c <main+0x20>
|
|||
|
|
80020e2: 46c0 nop ; (mov r8, r8)
|
|||
|
|
80020e4: 2000002e .word 0x2000002e
|
|||
|
|
80020e8: 20000037 .word 0x20000037
|
|||
|
|
80020ec: 20000038 .word 0x20000038
|
|||
|
|
|
|||
|
|
080020f0 <SystemClock_Config>:
|
|||
|
|
/**
|
|||
|
|
* @brief System Clock Configuration
|
|||
|
|
* @retval None
|
|||
|
|
*/
|
|||
|
|
void SystemClock_Config(void)
|
|||
|
|
{
|
|||
|
|
80020f0: b580 push {r7, lr}
|
|||
|
|
80020f2: b09c sub sp, #112 ; 0x70
|
|||
|
|
80020f4: af00 add r7, sp, #0
|
|||
|
|
RCC_OscInitTypeDef RCC_OscInitStruct = {0};
|
|||
|
|
80020f6: 2338 movs r3, #56 ; 0x38
|
|||
|
|
80020f8: 18fb adds r3, r7, r3
|
|||
|
|
80020fa: 0018 movs r0, r3
|
|||
|
|
80020fc: 2338 movs r3, #56 ; 0x38
|
|||
|
|
80020fe: 001a movs r2, r3
|
|||
|
|
8002100: 2100 movs r1, #0
|
|||
|
|
8002102: f004 ff5c bl 8006fbe <memset>
|
|||
|
|
RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
|
|||
|
|
8002106: 2324 movs r3, #36 ; 0x24
|
|||
|
|
8002108: 18fb adds r3, r7, r3
|
|||
|
|
800210a: 0018 movs r0, r3
|
|||
|
|
800210c: 2314 movs r3, #20
|
|||
|
|
800210e: 001a movs r2, r3
|
|||
|
|
8002110: 2100 movs r1, #0
|
|||
|
|
8002112: f004 ff54 bl 8006fbe <memset>
|
|||
|
|
RCC_PeriphCLKInitTypeDef PeriphClkInit = {0};
|
|||
|
|
8002116: 003b movs r3, r7
|
|||
|
|
8002118: 0018 movs r0, r3
|
|||
|
|
800211a: 2324 movs r3, #36 ; 0x24
|
|||
|
|
800211c: 001a movs r2, r3
|
|||
|
|
800211e: 2100 movs r1, #0
|
|||
|
|
8002120: f004 ff4d bl 8006fbe <memset>
|
|||
|
|
|
|||
|
|
/** Configure the main internal regulator output voltage
|
|||
|
|
*/
|
|||
|
|
__HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
|
|||
|
|
8002124: 4b2f ldr r3, [pc, #188] ; (80021e4 <SystemClock_Config+0xf4>)
|
|||
|
|
8002126: 4a2f ldr r2, [pc, #188] ; (80021e4 <SystemClock_Config+0xf4>)
|
|||
|
|
8002128: 6812 ldr r2, [r2, #0]
|
|||
|
|
800212a: 492f ldr r1, [pc, #188] ; (80021e8 <SystemClock_Config+0xf8>)
|
|||
|
|
800212c: 400a ands r2, r1
|
|||
|
|
800212e: 2180 movs r1, #128 ; 0x80
|
|||
|
|
8002130: 0109 lsls r1, r1, #4
|
|||
|
|
8002132: 430a orrs r2, r1
|
|||
|
|
8002134: 601a str r2, [r3, #0]
|
|||
|
|
/** Initializes the RCC Oscillators according to the specified parameters
|
|||
|
|
* in the RCC_OscInitTypeDef structure.
|
|||
|
|
*/
|
|||
|
|
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;
|
|||
|
|
8002136: 2338 movs r3, #56 ; 0x38
|
|||
|
|
8002138: 18fb adds r3, r7, r3
|
|||
|
|
800213a: 2202 movs r2, #2
|
|||
|
|
800213c: 601a str r2, [r3, #0]
|
|||
|
|
RCC_OscInitStruct.HSIState = RCC_HSI_ON;
|
|||
|
|
800213e: 2338 movs r3, #56 ; 0x38
|
|||
|
|
8002140: 18fb adds r3, r7, r3
|
|||
|
|
8002142: 2201 movs r2, #1
|
|||
|
|
8002144: 60da str r2, [r3, #12]
|
|||
|
|
RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
|
|||
|
|
8002146: 2338 movs r3, #56 ; 0x38
|
|||
|
|
8002148: 18fb adds r3, r7, r3
|
|||
|
|
800214a: 2210 movs r2, #16
|
|||
|
|
800214c: 611a str r2, [r3, #16]
|
|||
|
|
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
|
|||
|
|
800214e: 2338 movs r3, #56 ; 0x38
|
|||
|
|
8002150: 18fb adds r3, r7, r3
|
|||
|
|
8002152: 2202 movs r2, #2
|
|||
|
|
8002154: 629a str r2, [r3, #40] ; 0x28
|
|||
|
|
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
|
|||
|
|
8002156: 2338 movs r3, #56 ; 0x38
|
|||
|
|
8002158: 18fb adds r3, r7, r3
|
|||
|
|
800215a: 2200 movs r2, #0
|
|||
|
|
800215c: 62da str r2, [r3, #44] ; 0x2c
|
|||
|
|
RCC_OscInitStruct.PLL.PLLMUL = RCC_PLLMUL_3;
|
|||
|
|
800215e: 2338 movs r3, #56 ; 0x38
|
|||
|
|
8002160: 18fb adds r3, r7, r3
|
|||
|
|
8002162: 2200 movs r2, #0
|
|||
|
|
8002164: 631a str r2, [r3, #48] ; 0x30
|
|||
|
|
RCC_OscInitStruct.PLL.PLLDIV = RCC_PLLDIV_3;
|
|||
|
|
8002166: 2338 movs r3, #56 ; 0x38
|
|||
|
|
8002168: 18fb adds r3, r7, r3
|
|||
|
|
800216a: 2280 movs r2, #128 ; 0x80
|
|||
|
|
800216c: 0412 lsls r2, r2, #16
|
|||
|
|
800216e: 635a str r2, [r3, #52] ; 0x34
|
|||
|
|
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
|
|||
|
|
8002170: 2338 movs r3, #56 ; 0x38
|
|||
|
|
8002172: 18fb adds r3, r7, r3
|
|||
|
|
8002174: 0018 movs r0, r3
|
|||
|
|
8002176: f002 fd03 bl 8004b80 <HAL_RCC_OscConfig>
|
|||
|
|
800217a: 1e03 subs r3, r0, #0
|
|||
|
|
800217c: d001 beq.n 8002182 <SystemClock_Config+0x92>
|
|||
|
|
{
|
|||
|
|
Error_Handler();
|
|||
|
|
800217e: f000 f835 bl 80021ec <Error_Handler>
|
|||
|
|
}
|
|||
|
|
/** Initializes the CPU, AHB and APB buses clocks
|
|||
|
|
*/
|
|||
|
|
RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
|
|||
|
|
8002182: 2324 movs r3, #36 ; 0x24
|
|||
|
|
8002184: 18fb adds r3, r7, r3
|
|||
|
|
8002186: 220f movs r2, #15
|
|||
|
|
8002188: 601a str r2, [r3, #0]
|
|||
|
|
|RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
|
|||
|
|
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
|
|||
|
|
800218a: 2324 movs r3, #36 ; 0x24
|
|||
|
|
800218c: 18fb adds r3, r7, r3
|
|||
|
|
800218e: 2203 movs r2, #3
|
|||
|
|
8002190: 605a str r2, [r3, #4]
|
|||
|
|
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV2;
|
|||
|
|
8002192: 2324 movs r3, #36 ; 0x24
|
|||
|
|
8002194: 18fb adds r3, r7, r3
|
|||
|
|
8002196: 2280 movs r2, #128 ; 0x80
|
|||
|
|
8002198: 609a str r2, [r3, #8]
|
|||
|
|
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
|
|||
|
|
800219a: 2324 movs r3, #36 ; 0x24
|
|||
|
|
800219c: 18fb adds r3, r7, r3
|
|||
|
|
800219e: 2200 movs r2, #0
|
|||
|
|
80021a0: 60da str r2, [r3, #12]
|
|||
|
|
RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
|
|||
|
|
80021a2: 2324 movs r3, #36 ; 0x24
|
|||
|
|
80021a4: 18fb adds r3, r7, r3
|
|||
|
|
80021a6: 2200 movs r2, #0
|
|||
|
|
80021a8: 611a str r2, [r3, #16]
|
|||
|
|
|
|||
|
|
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0) != HAL_OK)
|
|||
|
|
80021aa: 2324 movs r3, #36 ; 0x24
|
|||
|
|
80021ac: 18fb adds r3, r7, r3
|
|||
|
|
80021ae: 2100 movs r1, #0
|
|||
|
|
80021b0: 0018 movs r0, r3
|
|||
|
|
80021b2: f003 f8b7 bl 8005324 <HAL_RCC_ClockConfig>
|
|||
|
|
80021b6: 1e03 subs r3, r0, #0
|
|||
|
|
80021b8: d001 beq.n 80021be <SystemClock_Config+0xce>
|
|||
|
|
{
|
|||
|
|
Error_Handler();
|
|||
|
|
80021ba: f000 f817 bl 80021ec <Error_Handler>
|
|||
|
|
}
|
|||
|
|
PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USART1;
|
|||
|
|
80021be: 003b movs r3, r7
|
|||
|
|
80021c0: 2201 movs r2, #1
|
|||
|
|
80021c2: 601a str r2, [r3, #0]
|
|||
|
|
PeriphClkInit.Usart1ClockSelection = RCC_USART1CLKSOURCE_PCLK2;
|
|||
|
|
80021c4: 003b movs r3, r7
|
|||
|
|
80021c6: 2200 movs r2, #0
|
|||
|
|
80021c8: 609a str r2, [r3, #8]
|
|||
|
|
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK)
|
|||
|
|
80021ca: 003b movs r3, r7
|
|||
|
|
80021cc: 0018 movs r0, r3
|
|||
|
|
80021ce: f003 fac9 bl 8005764 <HAL_RCCEx_PeriphCLKConfig>
|
|||
|
|
80021d2: 1e03 subs r3, r0, #0
|
|||
|
|
80021d4: d001 beq.n 80021da <SystemClock_Config+0xea>
|
|||
|
|
{
|
|||
|
|
Error_Handler();
|
|||
|
|
80021d6: f000 f809 bl 80021ec <Error_Handler>
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
80021da: 46c0 nop ; (mov r8, r8)
|
|||
|
|
80021dc: 46bd mov sp, r7
|
|||
|
|
80021de: b01c add sp, #112 ; 0x70
|
|||
|
|
80021e0: bd80 pop {r7, pc}
|
|||
|
|
80021e2: 46c0 nop ; (mov r8, r8)
|
|||
|
|
80021e4: 40007000 .word 0x40007000
|
|||
|
|
80021e8: ffffe7ff .word 0xffffe7ff
|
|||
|
|
|
|||
|
|
080021ec <Error_Handler>:
|
|||
|
|
/**
|
|||
|
|
* @brief This function is executed in case of error occurrence.
|
|||
|
|
* @retval None
|
|||
|
|
*/
|
|||
|
|
void Error_Handler(void)
|
|||
|
|
{
|
|||
|
|
80021ec: b580 push {r7, lr}
|
|||
|
|
80021ee: af00 add r7, sp, #0
|
|||
|
|
\details Disables IRQ interrupts by setting the I-bit in the CPSR.
|
|||
|
|
Can only be executed in Privileged modes.
|
|||
|
|
*/
|
|||
|
|
__STATIC_FORCEINLINE void __disable_irq(void)
|
|||
|
|
{
|
|||
|
|
__ASM volatile ("cpsid i" : : : "memory");
|
|||
|
|
80021f0: b672 cpsid i
|
|||
|
|
/* USER CODE BEGIN Error_Handler_Debug */
|
|||
|
|
/* User can add his own implementation to report the HAL error return state */
|
|||
|
|
__disable_irq();
|
|||
|
|
while (1)
|
|||
|
|
80021f2: e7fe b.n 80021f2 <Error_Handler+0x6>
|
|||
|
|
|
|||
|
|
080021f4 <HAL_MspInit>:
|
|||
|
|
/* USER CODE END 0 */
|
|||
|
|
/**
|
|||
|
|
* Initializes the Global MSP.
|
|||
|
|
*/
|
|||
|
|
void HAL_MspInit(void)
|
|||
|
|
{
|
|||
|
|
80021f4: b580 push {r7, lr}
|
|||
|
|
80021f6: af00 add r7, sp, #0
|
|||
|
|
/* USER CODE BEGIN MspInit 0 */
|
|||
|
|
|
|||
|
|
/* USER CODE END MspInit 0 */
|
|||
|
|
|
|||
|
|
__HAL_RCC_SYSCFG_CLK_ENABLE();
|
|||
|
|
80021f8: 4b07 ldr r3, [pc, #28] ; (8002218 <HAL_MspInit+0x24>)
|
|||
|
|
80021fa: 4a07 ldr r2, [pc, #28] ; (8002218 <HAL_MspInit+0x24>)
|
|||
|
|
80021fc: 6b52 ldr r2, [r2, #52] ; 0x34
|
|||
|
|
80021fe: 2101 movs r1, #1
|
|||
|
|
8002200: 430a orrs r2, r1
|
|||
|
|
8002202: 635a str r2, [r3, #52] ; 0x34
|
|||
|
|
__HAL_RCC_PWR_CLK_ENABLE();
|
|||
|
|
8002204: 4b04 ldr r3, [pc, #16] ; (8002218 <HAL_MspInit+0x24>)
|
|||
|
|
8002206: 4a04 ldr r2, [pc, #16] ; (8002218 <HAL_MspInit+0x24>)
|
|||
|
|
8002208: 6b92 ldr r2, [r2, #56] ; 0x38
|
|||
|
|
800220a: 2180 movs r1, #128 ; 0x80
|
|||
|
|
800220c: 0549 lsls r1, r1, #21
|
|||
|
|
800220e: 430a orrs r2, r1
|
|||
|
|
8002210: 639a str r2, [r3, #56] ; 0x38
|
|||
|
|
/* System interrupt init*/
|
|||
|
|
|
|||
|
|
/* USER CODE BEGIN MspInit 1 */
|
|||
|
|
|
|||
|
|
/* USER CODE END MspInit 1 */
|
|||
|
|
}
|
|||
|
|
8002212: 46c0 nop ; (mov r8, r8)
|
|||
|
|
8002214: 46bd mov sp, r7
|
|||
|
|
8002216: bd80 pop {r7, pc}
|
|||
|
|
8002218: 40021000 .word 0x40021000
|
|||
|
|
|
|||
|
|
0800221c <NMI_Handler>:
|
|||
|
|
/******************************************************************************/
|
|||
|
|
/**
|
|||
|
|
* @brief This function handles Non maskable Interrupt.
|
|||
|
|
*/
|
|||
|
|
void NMI_Handler(void)
|
|||
|
|
{
|
|||
|
|
800221c: b580 push {r7, lr}
|
|||
|
|
800221e: af00 add r7, sp, #0
|
|||
|
|
/* USER CODE BEGIN NonMaskableInt_IRQn 0 */
|
|||
|
|
|
|||
|
|
/* USER CODE END NonMaskableInt_IRQn 0 */
|
|||
|
|
/* USER CODE BEGIN NonMaskableInt_IRQn 1 */
|
|||
|
|
while (1)
|
|||
|
|
8002220: e7fe b.n 8002220 <NMI_Handler+0x4>
|
|||
|
|
|
|||
|
|
08002222 <HardFault_Handler>:
|
|||
|
|
|
|||
|
|
/**
|
|||
|
|
* @brief This function handles Hard fault interrupt.
|
|||
|
|
*/
|
|||
|
|
void HardFault_Handler(void)
|
|||
|
|
{
|
|||
|
|
8002222: b580 push {r7, lr}
|
|||
|
|
8002224: af00 add r7, sp, #0
|
|||
|
|
/* USER CODE BEGIN HardFault_IRQn 0 */
|
|||
|
|
|
|||
|
|
/* USER CODE END HardFault_IRQn 0 */
|
|||
|
|
while (1)
|
|||
|
|
8002226: e7fe b.n 8002226 <HardFault_Handler+0x4>
|
|||
|
|
|
|||
|
|
08002228 <SVC_Handler>:
|
|||
|
|
|
|||
|
|
/**
|
|||
|
|
* @brief This function handles System service call via SWI instruction.
|
|||
|
|
*/
|
|||
|
|
void SVC_Handler(void)
|
|||
|
|
{
|
|||
|
|
8002228: b580 push {r7, lr}
|
|||
|
|
800222a: af00 add r7, sp, #0
|
|||
|
|
|
|||
|
|
/* USER CODE END SVC_IRQn 0 */
|
|||
|
|
/* USER CODE BEGIN SVC_IRQn 1 */
|
|||
|
|
|
|||
|
|
/* USER CODE END SVC_IRQn 1 */
|
|||
|
|
}
|
|||
|
|
800222c: 46c0 nop ; (mov r8, r8)
|
|||
|
|
800222e: 46bd mov sp, r7
|
|||
|
|
8002230: bd80 pop {r7, pc}
|
|||
|
|
|
|||
|
|
08002232 <PendSV_Handler>:
|
|||
|
|
|
|||
|
|
/**
|
|||
|
|
* @brief This function handles Pendable request for system service.
|
|||
|
|
*/
|
|||
|
|
void PendSV_Handler(void)
|
|||
|
|
{
|
|||
|
|
8002232: b580 push {r7, lr}
|
|||
|
|
8002234: af00 add r7, sp, #0
|
|||
|
|
|
|||
|
|
/* USER CODE END PendSV_IRQn 0 */
|
|||
|
|
/* USER CODE BEGIN PendSV_IRQn 1 */
|
|||
|
|
|
|||
|
|
/* USER CODE END PendSV_IRQn 1 */
|
|||
|
|
}
|
|||
|
|
8002236: 46c0 nop ; (mov r8, r8)
|
|||
|
|
8002238: 46bd mov sp, r7
|
|||
|
|
800223a: bd80 pop {r7, pc}
|
|||
|
|
|
|||
|
|
0800223c <SysTick_Handler>:
|
|||
|
|
|
|||
|
|
/**
|
|||
|
|
* @brief This function handles System tick timer.
|
|||
|
|
*/
|
|||
|
|
void SysTick_Handler(void)
|
|||
|
|
{
|
|||
|
|
800223c: b580 push {r7, lr}
|
|||
|
|
800223e: af00 add r7, sp, #0
|
|||
|
|
/* USER CODE BEGIN SysTick_IRQn 0 */
|
|||
|
|
|
|||
|
|
/* USER CODE END SysTick_IRQn 0 */
|
|||
|
|
HAL_IncTick();
|
|||
|
|
8002240: f001 fe62 bl 8003f08 <HAL_IncTick>
|
|||
|
|
|
|||
|
|
if(timeout)
|
|||
|
|
8002244: 4b17 ldr r3, [pc, #92] ; (80022a4 <SysTick_Handler+0x68>)
|
|||
|
|
8002246: 781b ldrb r3, [r3, #0]
|
|||
|
|
8002248: 2b00 cmp r3, #0
|
|||
|
|
800224a: d006 beq.n 800225a <SysTick_Handler+0x1e>
|
|||
|
|
timeout--;
|
|||
|
|
800224c: 4b15 ldr r3, [pc, #84] ; (80022a4 <SysTick_Handler+0x68>)
|
|||
|
|
800224e: 781b ldrb r3, [r3, #0]
|
|||
|
|
8002250: 3b01 subs r3, #1
|
|||
|
|
8002252: b2da uxtb r2, r3
|
|||
|
|
8002254: 4b13 ldr r3, [pc, #76] ; (80022a4 <SysTick_Handler+0x68>)
|
|||
|
|
8002256: 701a strb r2, [r3, #0]
|
|||
|
|
|
|||
|
|
}
|
|||
|
|
else
|
|||
|
|
send = false;
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
8002258: e020 b.n 800229c <SysTick_Handler+0x60>
|
|||
|
|
if(iolen)
|
|||
|
|
800225a: 4b13 ldr r3, [pc, #76] ; (80022a8 <SysTick_Handler+0x6c>)
|
|||
|
|
800225c: 781b ldrb r3, [r3, #0]
|
|||
|
|
800225e: 2b00 cmp r3, #0
|
|||
|
|
8002260: d002 beq.n 8002268 <SysTick_Handler+0x2c>
|
|||
|
|
iolen = 0;
|
|||
|
|
8002262: 4b11 ldr r3, [pc, #68] ; (80022a8 <SysTick_Handler+0x6c>)
|
|||
|
|
8002264: 2200 movs r2, #0
|
|||
|
|
8002266: 701a strb r2, [r3, #0]
|
|||
|
|
if(sendreq)
|
|||
|
|
8002268: 4b10 ldr r3, [pc, #64] ; (80022ac <SysTick_Handler+0x70>)
|
|||
|
|
800226a: 781b ldrb r3, [r3, #0]
|
|||
|
|
800226c: 2b00 cmp r3, #0
|
|||
|
|
800226e: d012 beq.n 8002296 <SysTick_Handler+0x5a>
|
|||
|
|
sendreq = false;
|
|||
|
|
8002270: 4b0e ldr r3, [pc, #56] ; (80022ac <SysTick_Handler+0x70>)
|
|||
|
|
8002272: 2200 movs r2, #0
|
|||
|
|
8002274: 701a strb r2, [r3, #0]
|
|||
|
|
send = true;
|
|||
|
|
8002276: 4b0e ldr r3, [pc, #56] ; (80022b0 <SysTick_Handler+0x74>)
|
|||
|
|
8002278: 2201 movs r2, #1
|
|||
|
|
800227a: 701a strb r2, [r3, #0]
|
|||
|
|
timeout = time35[pardata.BAUD];
|
|||
|
|
800227c: 4b0d ldr r3, [pc, #52] ; (80022b4 <SysTick_Handler+0x78>)
|
|||
|
|
800227e: 885b ldrh r3, [r3, #2]
|
|||
|
|
8002280: b29b uxth r3, r3
|
|||
|
|
8002282: 001a movs r2, r3
|
|||
|
|
8002284: 4b0c ldr r3, [pc, #48] ; (80022b8 <SysTick_Handler+0x7c>)
|
|||
|
|
8002286: 0052 lsls r2, r2, #1
|
|||
|
|
8002288: 5ad3 ldrh r3, [r2, r3]
|
|||
|
|
800228a: b2da uxtb r2, r3
|
|||
|
|
800228c: 4b05 ldr r3, [pc, #20] ; (80022a4 <SysTick_Handler+0x68>)
|
|||
|
|
800228e: 701a strb r2, [r3, #0]
|
|||
|
|
StartTransfer();
|
|||
|
|
8002290: f001 fd52 bl 8003d38 <StartTransfer>
|
|||
|
|
}
|
|||
|
|
8002294: e002 b.n 800229c <SysTick_Handler+0x60>
|
|||
|
|
send = false;
|
|||
|
|
8002296: 4b06 ldr r3, [pc, #24] ; (80022b0 <SysTick_Handler+0x74>)
|
|||
|
|
8002298: 2200 movs r2, #0
|
|||
|
|
800229a: 701a strb r2, [r3, #0]
|
|||
|
|
}
|
|||
|
|
800229c: 46c0 nop ; (mov r8, r8)
|
|||
|
|
800229e: 46bd mov sp, r7
|
|||
|
|
80022a0: bd80 pop {r7, pc}
|
|||
|
|
80022a2: 46c0 nop ; (mov r8, r8)
|
|||
|
|
80022a4: 20000288 .word 0x20000288
|
|||
|
|
80022a8: 20000035 .word 0x20000035
|
|||
|
|
80022ac: 20000036 .word 0x20000036
|
|||
|
|
80022b0: 20000005 .word 0x20000005
|
|||
|
|
80022b4: 20000098 .word 0x20000098
|
|||
|
|
80022b8: 080071bc .word 0x080071bc
|
|||
|
|
|
|||
|
|
080022bc <EXTI0_1_IRQHandler>:
|
|||
|
|
|
|||
|
|
/**
|
|||
|
|
* @brief This function handles EXTI line 0 and line 1 interrupts.
|
|||
|
|
*/
|
|||
|
|
void EXTI0_1_IRQHandler(void)
|
|||
|
|
{
|
|||
|
|
80022bc: b580 push {r7, lr}
|
|||
|
|
80022be: af00 add r7, sp, #0
|
|||
|
|
/* USER CODE BEGIN EXTI0_1_IRQn 0 */
|
|||
|
|
|
|||
|
|
/* USER CODE END EXTI0_1_IRQn 0 */
|
|||
|
|
HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_0);
|
|||
|
|
80022c0: 2001 movs r0, #1
|
|||
|
|
80022c2: f002 fc41 bl 8004b48 <HAL_GPIO_EXTI_IRQHandler>
|
|||
|
|
HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_1);
|
|||
|
|
80022c6: 2002 movs r0, #2
|
|||
|
|
80022c8: f002 fc3e bl 8004b48 <HAL_GPIO_EXTI_IRQHandler>
|
|||
|
|
/* USER CODE BEGIN EXTI0_1_IRQn 1 */
|
|||
|
|
|
|||
|
|
/* USER CODE END EXTI0_1_IRQn 1 */
|
|||
|
|
}
|
|||
|
|
80022cc: 46c0 nop ; (mov r8, r8)
|
|||
|
|
80022ce: 46bd mov sp, r7
|
|||
|
|
80022d0: bd80 pop {r7, pc}
|
|||
|
|
|
|||
|
|
080022d2 <EXTI2_3_IRQHandler>:
|
|||
|
|
|
|||
|
|
/**
|
|||
|
|
* @brief This function handles EXTI line 2 and line 3 interrupts.
|
|||
|
|
*/
|
|||
|
|
void EXTI2_3_IRQHandler(void)
|
|||
|
|
{
|
|||
|
|
80022d2: b580 push {r7, lr}
|
|||
|
|
80022d4: af00 add r7, sp, #0
|
|||
|
|
/* USER CODE BEGIN EXTI2_3_IRQn 0 */
|
|||
|
|
|
|||
|
|
/* USER CODE END EXTI2_3_IRQn 0 */
|
|||
|
|
HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_2);
|
|||
|
|
80022d6: 2004 movs r0, #4
|
|||
|
|
80022d8: f002 fc36 bl 8004b48 <HAL_GPIO_EXTI_IRQHandler>
|
|||
|
|
/* USER CODE BEGIN EXTI2_3_IRQn 1 */
|
|||
|
|
|
|||
|
|
/* USER CODE END EXTI2_3_IRQn 1 */
|
|||
|
|
}
|
|||
|
|
80022dc: 46c0 nop ; (mov r8, r8)
|
|||
|
|
80022de: 46bd mov sp, r7
|
|||
|
|
80022e0: bd80 pop {r7, pc}
|
|||
|
|
...
|
|||
|
|
|
|||
|
|
080022e4 <TIM7_IRQHandler>:
|
|||
|
|
*/
|
|||
|
|
|
|||
|
|
|
|||
|
|
/* USER CODE BEGIN 1 */
|
|||
|
|
void TIM7_IRQHandler(void)
|
|||
|
|
{
|
|||
|
|
80022e4: b580 push {r7, lr}
|
|||
|
|
80022e6: af00 add r7, sp, #0
|
|||
|
|
HAL_TIM_IRQHandler(&htim7);
|
|||
|
|
80022e8: 4b03 ldr r3, [pc, #12] ; (80022f8 <TIM7_IRQHandler+0x14>)
|
|||
|
|
80022ea: 0018 movs r0, r3
|
|||
|
|
80022ec: f003 fc1e bl 8005b2c <HAL_TIM_IRQHandler>
|
|||
|
|
}
|
|||
|
|
80022f0: 46c0 nop ; (mov r8, r8)
|
|||
|
|
80022f2: 46bd mov sp, r7
|
|||
|
|
80022f4: bd80 pop {r7, pc}
|
|||
|
|
80022f6: 46c0 nop ; (mov r8, r8)
|
|||
|
|
80022f8: 200000c0 .word 0x200000c0
|
|||
|
|
|
|||
|
|
080022fc <SystemInit>:
|
|||
|
|
* @brief Setup the microcontroller system.
|
|||
|
|
* @param None
|
|||
|
|
* @retval None
|
|||
|
|
*/
|
|||
|
|
void SystemInit (void)
|
|||
|
|
{
|
|||
|
|
80022fc: b580 push {r7, lr}
|
|||
|
|
80022fe: af00 add r7, sp, #0
|
|||
|
|
/* Configure the Vector Table location add offset address ------------------*/
|
|||
|
|
#if defined (USER_VECT_TAB_ADDRESS)
|
|||
|
|
SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
|
|||
|
|
#endif /* USER_VECT_TAB_ADDRESS */
|
|||
|
|
}
|
|||
|
|
8002300: 46c0 nop ; (mov r8, r8)
|
|||
|
|
8002302: 46bd mov sp, r7
|
|||
|
|
8002304: bd80 pop {r7, pc}
|
|||
|
|
...
|
|||
|
|
|
|||
|
|
08002308 <MX_TIM7_Init>:
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
/* TIM7 init function */
|
|||
|
|
void MX_TIM7_Init(void)
|
|||
|
|
{
|
|||
|
|
8002308: b580 push {r7, lr}
|
|||
|
|
800230a: b082 sub sp, #8
|
|||
|
|
800230c: af00 add r7, sp, #0
|
|||
|
|
TIM_MasterConfigTypeDef sMasterConfig = {0};
|
|||
|
|
800230e: 003b movs r3, r7
|
|||
|
|
8002310: 0018 movs r0, r3
|
|||
|
|
8002312: 2308 movs r3, #8
|
|||
|
|
8002314: 001a movs r2, r3
|
|||
|
|
8002316: 2100 movs r1, #0
|
|||
|
|
8002318: f004 fe51 bl 8006fbe <memset>
|
|||
|
|
|
|||
|
|
htim7.Instance = TIM7;
|
|||
|
|
800231c: 4b17 ldr r3, [pc, #92] ; (800237c <MX_TIM7_Init+0x74>)
|
|||
|
|
800231e: 4a18 ldr r2, [pc, #96] ; (8002380 <MX_TIM7_Init+0x78>)
|
|||
|
|
8002320: 601a str r2, [r3, #0]
|
|||
|
|
htim7.Init.Prescaler = 0;
|
|||
|
|
8002322: 4b16 ldr r3, [pc, #88] ; (800237c <MX_TIM7_Init+0x74>)
|
|||
|
|
8002324: 2200 movs r2, #0
|
|||
|
|
8002326: 605a str r2, [r3, #4]
|
|||
|
|
htim7.Init.CounterMode = TIM_COUNTERMODE_UP;
|
|||
|
|
8002328: 4b14 ldr r3, [pc, #80] ; (800237c <MX_TIM7_Init+0x74>)
|
|||
|
|
800232a: 2200 movs r2, #0
|
|||
|
|
800232c: 609a str r2, [r3, #8]
|
|||
|
|
htim7.Init.Period = 7999; // Irq's 1ms
|
|||
|
|
800232e: 4b13 ldr r3, [pc, #76] ; (800237c <MX_TIM7_Init+0x74>)
|
|||
|
|
8002330: 4a14 ldr r2, [pc, #80] ; (8002384 <MX_TIM7_Init+0x7c>)
|
|||
|
|
8002332: 60da str r2, [r3, #12]
|
|||
|
|
htim7.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
|
|||
|
|
8002334: 4b11 ldr r3, [pc, #68] ; (800237c <MX_TIM7_Init+0x74>)
|
|||
|
|
8002336: 2200 movs r2, #0
|
|||
|
|
8002338: 615a str r2, [r3, #20]
|
|||
|
|
if (HAL_TIM_Base_Init(&htim7) != HAL_OK)
|
|||
|
|
800233a: 4b10 ldr r3, [pc, #64] ; (800237c <MX_TIM7_Init+0x74>)
|
|||
|
|
800233c: 0018 movs r0, r3
|
|||
|
|
800233e: f003 fb63 bl 8005a08 <HAL_TIM_Base_Init>
|
|||
|
|
8002342: 1e03 subs r3, r0, #0
|
|||
|
|
8002344: d001 beq.n 800234a <MX_TIM7_Init+0x42>
|
|||
|
|
{
|
|||
|
|
Error_Handler();
|
|||
|
|
8002346: f7ff ff51 bl 80021ec <Error_Handler>
|
|||
|
|
}
|
|||
|
|
sMasterConfig.MasterOutputTrigger = TIM_TRGO_UPDATE;
|
|||
|
|
800234a: 003b movs r3, r7
|
|||
|
|
800234c: 2220 movs r2, #32
|
|||
|
|
800234e: 601a str r2, [r3, #0]
|
|||
|
|
sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;
|
|||
|
|
8002350: 003b movs r3, r7
|
|||
|
|
8002352: 2200 movs r2, #0
|
|||
|
|
8002354: 605a str r2, [r3, #4]
|
|||
|
|
if (HAL_TIMEx_MasterConfigSynchronization(&htim7, &sMasterConfig) != HAL_OK)
|
|||
|
|
8002356: 003a movs r2, r7
|
|||
|
|
8002358: 4b08 ldr r3, [pc, #32] ; (800237c <MX_TIM7_Init+0x74>)
|
|||
|
|
800235a: 0011 movs r1, r2
|
|||
|
|
800235c: 0018 movs r0, r3
|
|||
|
|
800235e: f003 fd4b bl 8005df8 <HAL_TIMEx_MasterConfigSynchronization>
|
|||
|
|
8002362: 1e03 subs r3, r0, #0
|
|||
|
|
8002364: d001 beq.n 800236a <MX_TIM7_Init+0x62>
|
|||
|
|
{
|
|||
|
|
Error_Handler();
|
|||
|
|
8002366: f7ff ff41 bl 80021ec <Error_Handler>
|
|||
|
|
}
|
|||
|
|
/* USER CODE BEGIN TIM7_Init 2 */
|
|||
|
|
HAL_TIM_Base_Start_IT(&htim7);
|
|||
|
|
800236a: 4b04 ldr r3, [pc, #16] ; (800237c <MX_TIM7_Init+0x74>)
|
|||
|
|
800236c: 0018 movs r0, r3
|
|||
|
|
800236e: f003 fb8b bl 8005a88 <HAL_TIM_Base_Start_IT>
|
|||
|
|
/* USER CODE END TIM7_Init 2 */
|
|||
|
|
|
|||
|
|
}
|
|||
|
|
8002372: 46c0 nop ; (mov r8, r8)
|
|||
|
|
8002374: 46bd mov sp, r7
|
|||
|
|
8002376: b002 add sp, #8
|
|||
|
|
8002378: bd80 pop {r7, pc}
|
|||
|
|
800237a: 46c0 nop ; (mov r8, r8)
|
|||
|
|
800237c: 200000c0 .word 0x200000c0
|
|||
|
|
8002380: 40001400 .word 0x40001400
|
|||
|
|
8002384: 00001f3f .word 0x00001f3f
|
|||
|
|
|
|||
|
|
08002388 <HAL_TIM_Base_MspInit>:
|
|||
|
|
|
|||
|
|
void HAL_TIM_Base_MspInit(TIM_HandleTypeDef* tim_baseHandle)
|
|||
|
|
{
|
|||
|
|
8002388: b580 push {r7, lr}
|
|||
|
|
800238a: b082 sub sp, #8
|
|||
|
|
800238c: af00 add r7, sp, #0
|
|||
|
|
800238e: 6078 str r0, [r7, #4]
|
|||
|
|
|
|||
|
|
if(tim_baseHandle->Instance==TIM7)
|
|||
|
|
8002390: 687b ldr r3, [r7, #4]
|
|||
|
|
8002392: 681b ldr r3, [r3, #0]
|
|||
|
|
8002394: 4a0a ldr r2, [pc, #40] ; (80023c0 <HAL_TIM_Base_MspInit+0x38>)
|
|||
|
|
8002396: 4293 cmp r3, r2
|
|||
|
|
8002398: d10d bne.n 80023b6 <HAL_TIM_Base_MspInit+0x2e>
|
|||
|
|
{
|
|||
|
|
/* USER CODE BEGIN TIM7_MspInit 0 */
|
|||
|
|
|
|||
|
|
/* USER CODE END TIM7_MspInit 0 */
|
|||
|
|
/* TIM7 clock enable */
|
|||
|
|
__HAL_RCC_TIM7_CLK_ENABLE();
|
|||
|
|
800239a: 4b0a ldr r3, [pc, #40] ; (80023c4 <HAL_TIM_Base_MspInit+0x3c>)
|
|||
|
|
800239c: 4a09 ldr r2, [pc, #36] ; (80023c4 <HAL_TIM_Base_MspInit+0x3c>)
|
|||
|
|
800239e: 6b92 ldr r2, [r2, #56] ; 0x38
|
|||
|
|
80023a0: 2120 movs r1, #32
|
|||
|
|
80023a2: 430a orrs r2, r1
|
|||
|
|
80023a4: 639a str r2, [r3, #56] ; 0x38
|
|||
|
|
|
|||
|
|
/* TIM7 interrupt Init */
|
|||
|
|
HAL_NVIC_SetPriority(TIM7_IRQn, 2, 0);
|
|||
|
|
80023a6: 2200 movs r2, #0
|
|||
|
|
80023a8: 2102 movs r1, #2
|
|||
|
|
80023aa: 2012 movs r0, #18
|
|||
|
|
80023ac: f001 fe94 bl 80040d8 <HAL_NVIC_SetPriority>
|
|||
|
|
HAL_NVIC_EnableIRQ(TIM7_IRQn);
|
|||
|
|
80023b0: 2012 movs r0, #18
|
|||
|
|
80023b2: f001 fea7 bl 8004104 <HAL_NVIC_EnableIRQ>
|
|||
|
|
/* USER CODE BEGIN TIM7_MspInit 1 */
|
|||
|
|
|
|||
|
|
/* USER CODE END TIM7_MspInit 1 */
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
80023b6: 46c0 nop ; (mov r8, r8)
|
|||
|
|
80023b8: 46bd mov sp, r7
|
|||
|
|
80023ba: b002 add sp, #8
|
|||
|
|
80023bc: bd80 pop {r7, pc}
|
|||
|
|
80023be: 46c0 nop ; (mov r8, r8)
|
|||
|
|
80023c0: 40001400 .word 0x40001400
|
|||
|
|
80023c4: 40021000 .word 0x40021000
|
|||
|
|
|
|||
|
|
080023c8 <HAL_TIM_PeriodElapsedCallback>:
|
|||
|
|
|
|||
|
|
|
|||
|
|
/* USER CODE BEGIN 1 */
|
|||
|
|
/* USER CODE BEGIN 1 */
|
|||
|
|
void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim)
|
|||
|
|
{
|
|||
|
|
80023c8: b580 push {r7, lr}
|
|||
|
|
80023ca: b082 sub sp, #8
|
|||
|
|
80023cc: af00 add r7, sp, #0
|
|||
|
|
80023ce: 6078 str r0, [r7, #4]
|
|||
|
|
if((uint32_t) htim->Instance == TIM7_SOURCE) //TIM2_IRQs every 1024 Hz
|
|||
|
|
80023d0: 687b ldr r3, [r7, #4]
|
|||
|
|
80023d2: 681b ldr r3, [r3, #0]
|
|||
|
|
80023d4: 001a movs r2, r3
|
|||
|
|
80023d6: 4b06 ldr r3, [pc, #24] ; (80023f0 <HAL_TIM_PeriodElapsedCallback+0x28>)
|
|||
|
|
80023d8: 429a cmp r2, r3
|
|||
|
|
80023da: d104 bne.n 80023e6 <HAL_TIM_PeriodElapsedCallback+0x1e>
|
|||
|
|
{
|
|||
|
|
__HAL_TIM_CLEAR_IT(htim, TIM_IT_UPDATE);
|
|||
|
|
80023dc: 687b ldr r3, [r7, #4]
|
|||
|
|
80023de: 681b ldr r3, [r3, #0]
|
|||
|
|
80023e0: 2202 movs r2, #2
|
|||
|
|
80023e2: 4252 negs r2, r2
|
|||
|
|
80023e4: 611a str r2, [r3, #16]
|
|||
|
|
timerKZ--;
|
|||
|
|
if(!timerKZ)
|
|||
|
|
AMP_STATUS &= ~KZ_Pin;
|
|||
|
|
}*/
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
80023e6: 46c0 nop ; (mov r8, r8)
|
|||
|
|
80023e8: 46bd mov sp, r7
|
|||
|
|
80023ea: b002 add sp, #8
|
|||
|
|
80023ec: bd80 pop {r7, pc}
|
|||
|
|
80023ee: 46c0 nop ; (mov r8, r8)
|
|||
|
|
80023f0: 40001400 .word 0x40001400
|
|||
|
|
|
|||
|
|
080023f4 <MX_USART1_UART_Init>:
|
|||
|
|
const int8_t inversely[] = {3, 1, -1,-3};
|
|||
|
|
static const uint32_t BAUDRATE[] = {4800, 7200, 9600, 14400, 19200, 38400, 57600, 115200, 128000, 230400};
|
|||
|
|
|
|||
|
|
|
|||
|
|
void MX_USART1_UART_Init(void)
|
|||
|
|
{
|
|||
|
|
80023f4: b580 push {r7, lr}
|
|||
|
|
80023f6: af00 add r7, sp, #0
|
|||
|
|
huart1.Instance = USART1;
|
|||
|
|
80023f8: 4b4a ldr r3, [pc, #296] ; (8002524 <MX_USART1_UART_Init+0x130>)
|
|||
|
|
80023fa: 4a4b ldr r2, [pc, #300] ; (8002528 <MX_USART1_UART_Init+0x134>)
|
|||
|
|
80023fc: 601a str r2, [r3, #0]
|
|||
|
|
huart1.Init.BaudRate = BAUDRATE[pardata.BAUD];
|
|||
|
|
80023fe: 4b4b ldr r3, [pc, #300] ; (800252c <MX_USART1_UART_Init+0x138>)
|
|||
|
|
8002400: 885b ldrh r3, [r3, #2]
|
|||
|
|
8002402: b29b uxth r3, r3
|
|||
|
|
8002404: 001a movs r2, r3
|
|||
|
|
8002406: 4b4a ldr r3, [pc, #296] ; (8002530 <MX_USART1_UART_Init+0x13c>)
|
|||
|
|
8002408: 0092 lsls r2, r2, #2
|
|||
|
|
800240a: 58d2 ldr r2, [r2, r3]
|
|||
|
|
800240c: 4b45 ldr r3, [pc, #276] ; (8002524 <MX_USART1_UART_Init+0x130>)
|
|||
|
|
800240e: 605a str r2, [r3, #4]
|
|||
|
|
huart1.Init.WordLength = UART_WORDLENGTH_8B;
|
|||
|
|
8002410: 4b44 ldr r3, [pc, #272] ; (8002524 <MX_USART1_UART_Init+0x130>)
|
|||
|
|
8002412: 2200 movs r2, #0
|
|||
|
|
8002414: 609a str r2, [r3, #8]
|
|||
|
|
huart1.Init.StopBits = UART_STOPBITS_1;
|
|||
|
|
8002416: 4b43 ldr r3, [pc, #268] ; (8002524 <MX_USART1_UART_Init+0x130>)
|
|||
|
|
8002418: 2200 movs r2, #0
|
|||
|
|
800241a: 60da str r2, [r3, #12]
|
|||
|
|
switch(pardata.INFB)
|
|||
|
|
800241c: 4b43 ldr r3, [pc, #268] ; (800252c <MX_USART1_UART_Init+0x138>)
|
|||
|
|
800241e: 889b ldrh r3, [r3, #4]
|
|||
|
|
8002420: b29b uxth r3, r3
|
|||
|
|
8002422: 2b01 cmp r3, #1
|
|||
|
|
8002424: d00a beq.n 800243c <MX_USART1_UART_Init+0x48>
|
|||
|
|
8002426: 2b02 cmp r3, #2
|
|||
|
|
8002428: d011 beq.n 800244e <MX_USART1_UART_Init+0x5a>
|
|||
|
|
800242a: 2b00 cmp r3, #0
|
|||
|
|
800242c: d118 bne.n 8002460 <MX_USART1_UART_Init+0x6c>
|
|||
|
|
{
|
|||
|
|
case 0: //NONE
|
|||
|
|
huart1.Init.WordLength = UART_WORDLENGTH_8B;
|
|||
|
|
800242e: 4b3d ldr r3, [pc, #244] ; (8002524 <MX_USART1_UART_Init+0x130>)
|
|||
|
|
8002430: 2200 movs r2, #0
|
|||
|
|
8002432: 609a str r2, [r3, #8]
|
|||
|
|
huart1.Init.Parity = UART_PARITY_NONE;
|
|||
|
|
8002434: 4b3b ldr r3, [pc, #236] ; (8002524 <MX_USART1_UART_Init+0x130>)
|
|||
|
|
8002436: 2200 movs r2, #0
|
|||
|
|
8002438: 611a str r2, [r3, #16]
|
|||
|
|
break;
|
|||
|
|
800243a: e011 b.n 8002460 <MX_USART1_UART_Init+0x6c>
|
|||
|
|
case 1: //ODD
|
|||
|
|
huart1.Init.WordLength = UART_WORDLENGTH_9B;
|
|||
|
|
800243c: 4b39 ldr r3, [pc, #228] ; (8002524 <MX_USART1_UART_Init+0x130>)
|
|||
|
|
800243e: 2280 movs r2, #128 ; 0x80
|
|||
|
|
8002440: 0152 lsls r2, r2, #5
|
|||
|
|
8002442: 609a str r2, [r3, #8]
|
|||
|
|
huart1.Init.Parity = UART_PARITY_ODD;
|
|||
|
|
8002444: 4b37 ldr r3, [pc, #220] ; (8002524 <MX_USART1_UART_Init+0x130>)
|
|||
|
|
8002446: 22c0 movs r2, #192 ; 0xc0
|
|||
|
|
8002448: 00d2 lsls r2, r2, #3
|
|||
|
|
800244a: 611a str r2, [r3, #16]
|
|||
|
|
break;
|
|||
|
|
800244c: e008 b.n 8002460 <MX_USART1_UART_Init+0x6c>
|
|||
|
|
case 2: //EVEN
|
|||
|
|
huart1.Init.WordLength = UART_WORDLENGTH_9B;
|
|||
|
|
800244e: 4b35 ldr r3, [pc, #212] ; (8002524 <MX_USART1_UART_Init+0x130>)
|
|||
|
|
8002450: 2280 movs r2, #128 ; 0x80
|
|||
|
|
8002452: 0152 lsls r2, r2, #5
|
|||
|
|
8002454: 609a str r2, [r3, #8]
|
|||
|
|
huart1.Init.Parity = UART_PARITY_EVEN;
|
|||
|
|
8002456: 4b33 ldr r3, [pc, #204] ; (8002524 <MX_USART1_UART_Init+0x130>)
|
|||
|
|
8002458: 2280 movs r2, #128 ; 0x80
|
|||
|
|
800245a: 00d2 lsls r2, r2, #3
|
|||
|
|
800245c: 611a str r2, [r3, #16]
|
|||
|
|
break;
|
|||
|
|
800245e: 46c0 nop ; (mov r8, r8)
|
|||
|
|
}
|
|||
|
|
if(pardata.BAUD < 7)
|
|||
|
|
8002460: 4b32 ldr r3, [pc, #200] ; (800252c <MX_USART1_UART_Init+0x138>)
|
|||
|
|
8002462: 885b ldrh r3, [r3, #2]
|
|||
|
|
8002464: b29b uxth r3, r3
|
|||
|
|
8002466: 2b06 cmp r3, #6
|
|||
|
|
8002468: d804 bhi.n 8002474 <MX_USART1_UART_Init+0x80>
|
|||
|
|
huart1.Init.OverSampling = UART_OVERSAMPLING_8;
|
|||
|
|
800246a: 4b2e ldr r3, [pc, #184] ; (8002524 <MX_USART1_UART_Init+0x130>)
|
|||
|
|
800246c: 2280 movs r2, #128 ; 0x80
|
|||
|
|
800246e: 0212 lsls r2, r2, #8
|
|||
|
|
8002470: 61da str r2, [r3, #28]
|
|||
|
|
8002472: e002 b.n 800247a <MX_USART1_UART_Init+0x86>
|
|||
|
|
else huart1.Init.OverSampling = UART_OVERSAMPLING_16;
|
|||
|
|
8002474: 4b2b ldr r3, [pc, #172] ; (8002524 <MX_USART1_UART_Init+0x130>)
|
|||
|
|
8002476: 2200 movs r2, #0
|
|||
|
|
8002478: 61da str r2, [r3, #28]
|
|||
|
|
|
|||
|
|
|
|||
|
|
huart1.Init.Mode = UART_MODE_TX_RX;
|
|||
|
|
800247a: 4b2a ldr r3, [pc, #168] ; (8002524 <MX_USART1_UART_Init+0x130>)
|
|||
|
|
800247c: 220c movs r2, #12
|
|||
|
|
800247e: 615a str r2, [r3, #20]
|
|||
|
|
huart1.Init.HwFlowCtl = UART_HWCONTROL_NONE;
|
|||
|
|
8002480: 4b28 ldr r3, [pc, #160] ; (8002524 <MX_USART1_UART_Init+0x130>)
|
|||
|
|
8002482: 2200 movs r2, #0
|
|||
|
|
8002484: 619a str r2, [r3, #24]
|
|||
|
|
huart1.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE;
|
|||
|
|
8002486: 4b27 ldr r3, [pc, #156] ; (8002524 <MX_USART1_UART_Init+0x130>)
|
|||
|
|
8002488: 2200 movs r2, #0
|
|||
|
|
800248a: 621a str r2, [r3, #32]
|
|||
|
|
huart1.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT;
|
|||
|
|
800248c: 4b25 ldr r3, [pc, #148] ; (8002524 <MX_USART1_UART_Init+0x130>)
|
|||
|
|
800248e: 2200 movs r2, #0
|
|||
|
|
8002490: 625a str r2, [r3, #36] ; 0x24
|
|||
|
|
if(HAL_UART_Init(&huart1) != HAL_OK) {
|
|||
|
|
8002492: 4b24 ldr r3, [pc, #144] ; (8002524 <MX_USART1_UART_Init+0x130>)
|
|||
|
|
8002494: 0018 movs r0, r3
|
|||
|
|
8002496: f003 fd0d bl 8005eb4 <HAL_UART_Init>
|
|||
|
|
800249a: 1e03 subs r3, r0, #0
|
|||
|
|
800249c: d001 beq.n 80024a2 <MX_USART1_UART_Init+0xae>
|
|||
|
|
Error_Handler();
|
|||
|
|
800249e: f7ff fea5 bl 80021ec <Error_Handler>
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
if(__HAL_UART_GET_FLAG(&huart1, UART_FLAG_ORE))
|
|||
|
|
80024a2: 4b20 ldr r3, [pc, #128] ; (8002524 <MX_USART1_UART_Init+0x130>)
|
|||
|
|
80024a4: 681b ldr r3, [r3, #0]
|
|||
|
|
80024a6: 69db ldr r3, [r3, #28]
|
|||
|
|
80024a8: 2208 movs r2, #8
|
|||
|
|
80024aa: 4013 ands r3, r2
|
|||
|
|
80024ac: 2b08 cmp r3, #8
|
|||
|
|
80024ae: d103 bne.n 80024b8 <MX_USART1_UART_Init+0xc4>
|
|||
|
|
__HAL_UART_CLEAR_FLAG(&huart1, UART_FLAG_ORE);
|
|||
|
|
80024b0: 4b1c ldr r3, [pc, #112] ; (8002524 <MX_USART1_UART_Init+0x130>)
|
|||
|
|
80024b2: 681b ldr r3, [r3, #0]
|
|||
|
|
80024b4: 2208 movs r2, #8
|
|||
|
|
80024b6: 621a str r2, [r3, #32]
|
|||
|
|
|
|||
|
|
if(__HAL_UART_GET_FLAG(&huart1, UART_FLAG_PE))
|
|||
|
|
80024b8: 4b1a ldr r3, [pc, #104] ; (8002524 <MX_USART1_UART_Init+0x130>)
|
|||
|
|
80024ba: 681b ldr r3, [r3, #0]
|
|||
|
|
80024bc: 69db ldr r3, [r3, #28]
|
|||
|
|
80024be: 2201 movs r2, #1
|
|||
|
|
80024c0: 4013 ands r3, r2
|
|||
|
|
80024c2: 2b01 cmp r3, #1
|
|||
|
|
80024c4: d103 bne.n 80024ce <MX_USART1_UART_Init+0xda>
|
|||
|
|
__HAL_UART_CLEAR_FLAG(&huart1, UART_FLAG_PE);
|
|||
|
|
80024c6: 4b17 ldr r3, [pc, #92] ; (8002524 <MX_USART1_UART_Init+0x130>)
|
|||
|
|
80024c8: 681b ldr r3, [r3, #0]
|
|||
|
|
80024ca: 2201 movs r2, #1
|
|||
|
|
80024cc: 621a str r2, [r3, #32]
|
|||
|
|
|
|||
|
|
if(__HAL_UART_GET_FLAG(&huart1, UART_FLAG_FE))
|
|||
|
|
80024ce: 4b15 ldr r3, [pc, #84] ; (8002524 <MX_USART1_UART_Init+0x130>)
|
|||
|
|
80024d0: 681b ldr r3, [r3, #0]
|
|||
|
|
80024d2: 69db ldr r3, [r3, #28]
|
|||
|
|
80024d4: 2202 movs r2, #2
|
|||
|
|
80024d6: 4013 ands r3, r2
|
|||
|
|
80024d8: 2b02 cmp r3, #2
|
|||
|
|
80024da: d103 bne.n 80024e4 <MX_USART1_UART_Init+0xf0>
|
|||
|
|
__HAL_UART_CLEAR_FLAG(&huart1, UART_FLAG_FE);
|
|||
|
|
80024dc: 4b11 ldr r3, [pc, #68] ; (8002524 <MX_USART1_UART_Init+0x130>)
|
|||
|
|
80024de: 681b ldr r3, [r3, #0]
|
|||
|
|
80024e0: 2202 movs r2, #2
|
|||
|
|
80024e2: 621a str r2, [r3, #32]
|
|||
|
|
|
|||
|
|
if(__HAL_UART_GET_FLAG(&huart1, UART_FLAG_NE))
|
|||
|
|
80024e4: 4b0f ldr r3, [pc, #60] ; (8002524 <MX_USART1_UART_Init+0x130>)
|
|||
|
|
80024e6: 681b ldr r3, [r3, #0]
|
|||
|
|
80024e8: 69db ldr r3, [r3, #28]
|
|||
|
|
80024ea: 2204 movs r2, #4
|
|||
|
|
80024ec: 4013 ands r3, r2
|
|||
|
|
80024ee: 2b04 cmp r3, #4
|
|||
|
|
80024f0: d103 bne.n 80024fa <MX_USART1_UART_Init+0x106>
|
|||
|
|
__HAL_UART_CLEAR_FLAG(&huart1, UART_FLAG_NE);
|
|||
|
|
80024f2: 4b0c ldr r3, [pc, #48] ; (8002524 <MX_USART1_UART_Init+0x130>)
|
|||
|
|
80024f4: 681b ldr r3, [r3, #0]
|
|||
|
|
80024f6: 2204 movs r2, #4
|
|||
|
|
80024f8: 621a str r2, [r3, #32]
|
|||
|
|
|
|||
|
|
HAL_GPIO_WritePin(RE_GPIO_Port, RE_Pin, GPIO_PIN_RESET);
|
|||
|
|
80024fa: 2380 movs r3, #128 ; 0x80
|
|||
|
|
80024fc: 0059 lsls r1, r3, #1
|
|||
|
|
80024fe: 23a0 movs r3, #160 ; 0xa0
|
|||
|
|
8002500: 05db lsls r3, r3, #23
|
|||
|
|
8002502: 2200 movs r2, #0
|
|||
|
|
8002504: 0018 movs r0, r3
|
|||
|
|
8002506: f002 fb02 bl 8004b0e <HAL_GPIO_WritePin>
|
|||
|
|
SET_BIT(huart1.Instance->CR1, USART_CR1_RXNEIE | USART_CR1_PEIE);
|
|||
|
|
800250a: 4b06 ldr r3, [pc, #24] ; (8002524 <MX_USART1_UART_Init+0x130>)
|
|||
|
|
800250c: 681b ldr r3, [r3, #0]
|
|||
|
|
800250e: 4a05 ldr r2, [pc, #20] ; (8002524 <MX_USART1_UART_Init+0x130>)
|
|||
|
|
8002510: 6812 ldr r2, [r2, #0]
|
|||
|
|
8002512: 6812 ldr r2, [r2, #0]
|
|||
|
|
8002514: 2190 movs r1, #144 ; 0x90
|
|||
|
|
8002516: 0049 lsls r1, r1, #1
|
|||
|
|
8002518: 430a orrs r2, r1
|
|||
|
|
800251a: 601a str r2, [r3, #0]
|
|||
|
|
}
|
|||
|
|
800251c: 46c0 nop ; (mov r8, r8)
|
|||
|
|
800251e: 46bd mov sp, r7
|
|||
|
|
8002520: bd80 pop {r7, pc}
|
|||
|
|
8002522: 46c0 nop ; (mov r8, r8)
|
|||
|
|
8002524: 20000104 .word 0x20000104
|
|||
|
|
8002528: 40013800 .word 0x40013800
|
|||
|
|
800252c: 20000098 .word 0x20000098
|
|||
|
|
8002530: 0800741c .word 0x0800741c
|
|||
|
|
|
|||
|
|
08002534 <MX_USART1_UART_DeInit>:
|
|||
|
|
|
|||
|
|
void MX_USART1_UART_DeInit(void)
|
|||
|
|
{
|
|||
|
|
8002534: b580 push {r7, lr}
|
|||
|
|
8002536: af00 add r7, sp, #0
|
|||
|
|
if(HAL_UART_DeInit(&huart1) != HAL_OK) {
|
|||
|
|
8002538: 4b06 ldr r3, [pc, #24] ; (8002554 <MX_USART1_UART_DeInit+0x20>)
|
|||
|
|
800253a: 0018 movs r0, r3
|
|||
|
|
800253c: f003 fd0e bl 8005f5c <HAL_UART_DeInit>
|
|||
|
|
8002540: 1e03 subs r3, r0, #0
|
|||
|
|
8002542: d001 beq.n 8002548 <MX_USART1_UART_DeInit+0x14>
|
|||
|
|
Error_Handler();
|
|||
|
|
8002544: f7ff fe52 bl 80021ec <Error_Handler>
|
|||
|
|
}
|
|||
|
|
HAL_NVIC_DisableIRQ(USART1_IRQn);
|
|||
|
|
8002548: 201b movs r0, #27
|
|||
|
|
800254a: f001 fdeb bl 8004124 <HAL_NVIC_DisableIRQ>
|
|||
|
|
}
|
|||
|
|
800254e: 46c0 nop ; (mov r8, r8)
|
|||
|
|
8002550: 46bd mov sp, r7
|
|||
|
|
8002552: bd80 pop {r7, pc}
|
|||
|
|
8002554: 20000104 .word 0x20000104
|
|||
|
|
|
|||
|
|
08002558 <HAL_UART_MspInit>:
|
|||
|
|
|
|||
|
|
|
|||
|
|
void HAL_UART_MspInit(UART_HandleTypeDef* uartHandle)
|
|||
|
|
{
|
|||
|
|
8002558: b580 push {r7, lr}
|
|||
|
|
800255a: b088 sub sp, #32
|
|||
|
|
800255c: af00 add r7, sp, #0
|
|||
|
|
800255e: 6078 str r0, [r7, #4]
|
|||
|
|
GPIO_InitTypeDef GPIO_InitStruct = {0};
|
|||
|
|
8002560: 230c movs r3, #12
|
|||
|
|
8002562: 18fb adds r3, r7, r3
|
|||
|
|
8002564: 0018 movs r0, r3
|
|||
|
|
8002566: 2314 movs r3, #20
|
|||
|
|
8002568: 001a movs r2, r3
|
|||
|
|
800256a: 2100 movs r1, #0
|
|||
|
|
800256c: f004 fd27 bl 8006fbe <memset>
|
|||
|
|
|
|||
|
|
if(uartHandle->Instance==USART1)
|
|||
|
|
8002570: 687b ldr r3, [r7, #4]
|
|||
|
|
8002572: 681b ldr r3, [r3, #0]
|
|||
|
|
8002574: 4a1f ldr r2, [pc, #124] ; (80025f4 <HAL_UART_MspInit+0x9c>)
|
|||
|
|
8002576: 4293 cmp r3, r2
|
|||
|
|
8002578: d137 bne.n 80025ea <HAL_UART_MspInit+0x92>
|
|||
|
|
{
|
|||
|
|
__HAL_RCC_USART1_CLK_ENABLE();
|
|||
|
|
800257a: 4b1f ldr r3, [pc, #124] ; (80025f8 <HAL_UART_MspInit+0xa0>)
|
|||
|
|
800257c: 4a1e ldr r2, [pc, #120] ; (80025f8 <HAL_UART_MspInit+0xa0>)
|
|||
|
|
800257e: 6b52 ldr r2, [r2, #52] ; 0x34
|
|||
|
|
8002580: 2180 movs r1, #128 ; 0x80
|
|||
|
|
8002582: 01c9 lsls r1, r1, #7
|
|||
|
|
8002584: 430a orrs r2, r1
|
|||
|
|
8002586: 635a str r2, [r3, #52] ; 0x34
|
|||
|
|
__HAL_RCC_GPIOA_CLK_ENABLE();
|
|||
|
|
8002588: 4b1b ldr r3, [pc, #108] ; (80025f8 <HAL_UART_MspInit+0xa0>)
|
|||
|
|
800258a: 4a1b ldr r2, [pc, #108] ; (80025f8 <HAL_UART_MspInit+0xa0>)
|
|||
|
|
800258c: 6ad2 ldr r2, [r2, #44] ; 0x2c
|
|||
|
|
800258e: 2101 movs r1, #1
|
|||
|
|
8002590: 430a orrs r2, r1
|
|||
|
|
8002592: 62da str r2, [r3, #44] ; 0x2c
|
|||
|
|
8002594: 4b18 ldr r3, [pc, #96] ; (80025f8 <HAL_UART_MspInit+0xa0>)
|
|||
|
|
8002596: 6adb ldr r3, [r3, #44] ; 0x2c
|
|||
|
|
8002598: 2201 movs r2, #1
|
|||
|
|
800259a: 4013 ands r3, r2
|
|||
|
|
800259c: 60bb str r3, [r7, #8]
|
|||
|
|
800259e: 68bb ldr r3, [r7, #8]
|
|||
|
|
/**USART1 GPIO Configuration
|
|||
|
|
PA9 ------> USART1_TX
|
|||
|
|
PA10 ------> USART1_RX
|
|||
|
|
*/
|
|||
|
|
GPIO_InitStruct.Pin = GPIO_PIN_9|GPIO_PIN_10;
|
|||
|
|
80025a0: 230c movs r3, #12
|
|||
|
|
80025a2: 18fb adds r3, r7, r3
|
|||
|
|
80025a4: 22c0 movs r2, #192 ; 0xc0
|
|||
|
|
80025a6: 00d2 lsls r2, r2, #3
|
|||
|
|
80025a8: 601a str r2, [r3, #0]
|
|||
|
|
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
|
|||
|
|
80025aa: 230c movs r3, #12
|
|||
|
|
80025ac: 18fb adds r3, r7, r3
|
|||
|
|
80025ae: 2202 movs r2, #2
|
|||
|
|
80025b0: 605a str r2, [r3, #4]
|
|||
|
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|||
|
|
80025b2: 230c movs r3, #12
|
|||
|
|
80025b4: 18fb adds r3, r7, r3
|
|||
|
|
80025b6: 2200 movs r2, #0
|
|||
|
|
80025b8: 609a str r2, [r3, #8]
|
|||
|
|
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
|
|||
|
|
80025ba: 230c movs r3, #12
|
|||
|
|
80025bc: 18fb adds r3, r7, r3
|
|||
|
|
80025be: 2203 movs r2, #3
|
|||
|
|
80025c0: 60da str r2, [r3, #12]
|
|||
|
|
GPIO_InitStruct.Alternate = GPIO_AF4_USART1;
|
|||
|
|
80025c2: 230c movs r3, #12
|
|||
|
|
80025c4: 18fb adds r3, r7, r3
|
|||
|
|
80025c6: 2204 movs r2, #4
|
|||
|
|
80025c8: 611a str r2, [r3, #16]
|
|||
|
|
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
|
|||
|
|
80025ca: 230c movs r3, #12
|
|||
|
|
80025cc: 18fa adds r2, r7, r3
|
|||
|
|
80025ce: 23a0 movs r3, #160 ; 0xa0
|
|||
|
|
80025d0: 05db lsls r3, r3, #23
|
|||
|
|
80025d2: 0011 movs r1, r2
|
|||
|
|
80025d4: 0018 movs r0, r3
|
|||
|
|
80025d6: f002 f81b bl 8004610 <HAL_GPIO_Init>
|
|||
|
|
|
|||
|
|
/* USART1 interrupt Init */
|
|||
|
|
HAL_NVIC_SetPriority(USART1_IRQn, 3, 0);
|
|||
|
|
80025da: 2200 movs r2, #0
|
|||
|
|
80025dc: 2103 movs r1, #3
|
|||
|
|
80025de: 201b movs r0, #27
|
|||
|
|
80025e0: f001 fd7a bl 80040d8 <HAL_NVIC_SetPriority>
|
|||
|
|
HAL_NVIC_EnableIRQ(USART1_IRQn);
|
|||
|
|
80025e4: 201b movs r0, #27
|
|||
|
|
80025e6: f001 fd8d bl 8004104 <HAL_NVIC_EnableIRQ>
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
80025ea: 46c0 nop ; (mov r8, r8)
|
|||
|
|
80025ec: 46bd mov sp, r7
|
|||
|
|
80025ee: b008 add sp, #32
|
|||
|
|
80025f0: bd80 pop {r7, pc}
|
|||
|
|
80025f2: 46c0 nop ; (mov r8, r8)
|
|||
|
|
80025f4: 40013800 .word 0x40013800
|
|||
|
|
80025f8: 40021000 .word 0x40021000
|
|||
|
|
|
|||
|
|
080025fc <HAL_UART_MspDeInit>:
|
|||
|
|
|
|||
|
|
|
|||
|
|
void HAL_UART_MspDeInit(UART_HandleTypeDef* uartHandle)
|
|||
|
|
{
|
|||
|
|
80025fc: b580 push {r7, lr}
|
|||
|
|
80025fe: b082 sub sp, #8
|
|||
|
|
8002600: af00 add r7, sp, #0
|
|||
|
|
8002602: 6078 str r0, [r7, #4]
|
|||
|
|
|
|||
|
|
if(uartHandle->Instance==USART1)
|
|||
|
|
8002604: 687b ldr r3, [r7, #4]
|
|||
|
|
8002606: 681b ldr r3, [r3, #0]
|
|||
|
|
8002608: 4a0b ldr r2, [pc, #44] ; (8002638 <HAL_UART_MspDeInit+0x3c>)
|
|||
|
|
800260a: 4293 cmp r3, r2
|
|||
|
|
800260c: d110 bne.n 8002630 <HAL_UART_MspDeInit+0x34>
|
|||
|
|
{
|
|||
|
|
/* USER CODE BEGIN USART1_MspDeInit 0 */
|
|||
|
|
|
|||
|
|
/* USER CODE END USART1_MspDeInit 0 */
|
|||
|
|
/* Peripheral clock disable */
|
|||
|
|
__HAL_RCC_USART1_CLK_DISABLE();
|
|||
|
|
800260e: 4b0b ldr r3, [pc, #44] ; (800263c <HAL_UART_MspDeInit+0x40>)
|
|||
|
|
8002610: 4a0a ldr r2, [pc, #40] ; (800263c <HAL_UART_MspDeInit+0x40>)
|
|||
|
|
8002612: 6b52 ldr r2, [r2, #52] ; 0x34
|
|||
|
|
8002614: 490a ldr r1, [pc, #40] ; (8002640 <HAL_UART_MspDeInit+0x44>)
|
|||
|
|
8002616: 400a ands r2, r1
|
|||
|
|
8002618: 635a str r2, [r3, #52] ; 0x34
|
|||
|
|
|
|||
|
|
/**USART1 GPIO Configuration
|
|||
|
|
PA9 ------> USART1_TX
|
|||
|
|
PA10 ------> USART1_RX
|
|||
|
|
*/
|
|||
|
|
HAL_GPIO_DeInit(GPIOA, GPIO_PIN_9|GPIO_PIN_10);
|
|||
|
|
800261a: 23c0 movs r3, #192 ; 0xc0
|
|||
|
|
800261c: 00da lsls r2, r3, #3
|
|||
|
|
800261e: 23a0 movs r3, #160 ; 0xa0
|
|||
|
|
8002620: 05db lsls r3, r3, #23
|
|||
|
|
8002622: 0011 movs r1, r2
|
|||
|
|
8002624: 0018 movs r0, r3
|
|||
|
|
8002626: f002 f971 bl 800490c <HAL_GPIO_DeInit>
|
|||
|
|
|
|||
|
|
/* USART1 interrupt Deinit */
|
|||
|
|
HAL_NVIC_DisableIRQ(USART1_IRQn);
|
|||
|
|
800262a: 201b movs r0, #27
|
|||
|
|
800262c: f001 fd7a bl 8004124 <HAL_NVIC_DisableIRQ>
|
|||
|
|
/* USER CODE BEGIN USART1_MspDeInit 1 */
|
|||
|
|
|
|||
|
|
/* USER CODE END USART1_MspDeInit 1 */
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
8002630: 46c0 nop ; (mov r8, r8)
|
|||
|
|
8002632: 46bd mov sp, r7
|
|||
|
|
8002634: b002 add sp, #8
|
|||
|
|
8002636: bd80 pop {r7, pc}
|
|||
|
|
8002638: 40013800 .word 0x40013800
|
|||
|
|
800263c: 40021000 .word 0x40021000
|
|||
|
|
8002640: ffffbfff .word 0xffffbfff
|
|||
|
|
|
|||
|
|
08002644 <USART1_IRQHandler>:
|
|||
|
|
|
|||
|
|
|
|||
|
|
/* USER CODE BEGIN 1 */
|
|||
|
|
void USART1_IRQHandler(void)
|
|||
|
|
{
|
|||
|
|
8002644: b580 push {r7, lr}
|
|||
|
|
8002646: af00 add r7, sp, #0
|
|||
|
|
if((__HAL_UART_GET_IT_SOURCE(&huart1, UART_IT_RXNE)) && (__HAL_UART_GET_FLAG(&huart1, UART_FLAG_RXNE)))
|
|||
|
|
8002648: 4b22 ldr r3, [pc, #136] ; (80026d4 <USART1_IRQHandler+0x90>)
|
|||
|
|
800264a: 681b ldr r3, [r3, #0]
|
|||
|
|
800264c: 681b ldr r3, [r3, #0]
|
|||
|
|
800264e: 2220 movs r2, #32
|
|||
|
|
8002650: 4013 ands r3, r2
|
|||
|
|
8002652: d00b beq.n 800266c <USART1_IRQHandler+0x28>
|
|||
|
|
8002654: 4b1f ldr r3, [pc, #124] ; (80026d4 <USART1_IRQHandler+0x90>)
|
|||
|
|
8002656: 681b ldr r3, [r3, #0]
|
|||
|
|
8002658: 69db ldr r3, [r3, #28]
|
|||
|
|
800265a: 2220 movs r2, #32
|
|||
|
|
800265c: 4013 ands r3, r2
|
|||
|
|
800265e: 2b20 cmp r3, #32
|
|||
|
|
8002660: d104 bne.n 800266c <USART1_IRQHandler+0x28>
|
|||
|
|
{
|
|||
|
|
HAL_UART_RxCpltCallback(&huart1);
|
|||
|
|
8002662: 4b1c ldr r3, [pc, #112] ; (80026d4 <USART1_IRQHandler+0x90>)
|
|||
|
|
8002664: 0018 movs r0, r3
|
|||
|
|
8002666: f000 f929 bl 80028bc <HAL_UART_RxCpltCallback>
|
|||
|
|
800266a: e003 b.n 8002674 <USART1_IRQHandler+0x30>
|
|||
|
|
}
|
|||
|
|
else
|
|||
|
|
{
|
|||
|
|
HAL_UART_IRQHandler(&huart1);
|
|||
|
|
800266c: 4b19 ldr r3, [pc, #100] ; (80026d4 <USART1_IRQHandler+0x90>)
|
|||
|
|
800266e: 0018 movs r0, r3
|
|||
|
|
8002670: f003 fd1c bl 80060ac <HAL_UART_IRQHandler>
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
|
|||
|
|
if(__HAL_UART_GET_FLAG(&huart1, UART_FLAG_ORE))
|
|||
|
|
8002674: 4b17 ldr r3, [pc, #92] ; (80026d4 <USART1_IRQHandler+0x90>)
|
|||
|
|
8002676: 681b ldr r3, [r3, #0]
|
|||
|
|
8002678: 69db ldr r3, [r3, #28]
|
|||
|
|
800267a: 2208 movs r2, #8
|
|||
|
|
800267c: 4013 ands r3, r2
|
|||
|
|
800267e: 2b08 cmp r3, #8
|
|||
|
|
8002680: d103 bne.n 800268a <USART1_IRQHandler+0x46>
|
|||
|
|
__HAL_UART_CLEAR_FLAG(&huart1, UART_FLAG_ORE);
|
|||
|
|
8002682: 4b14 ldr r3, [pc, #80] ; (80026d4 <USART1_IRQHandler+0x90>)
|
|||
|
|
8002684: 681b ldr r3, [r3, #0]
|
|||
|
|
8002686: 2208 movs r2, #8
|
|||
|
|
8002688: 621a str r2, [r3, #32]
|
|||
|
|
|
|||
|
|
if(__HAL_UART_GET_FLAG(&huart1, UART_FLAG_PE))
|
|||
|
|
800268a: 4b12 ldr r3, [pc, #72] ; (80026d4 <USART1_IRQHandler+0x90>)
|
|||
|
|
800268c: 681b ldr r3, [r3, #0]
|
|||
|
|
800268e: 69db ldr r3, [r3, #28]
|
|||
|
|
8002690: 2201 movs r2, #1
|
|||
|
|
8002692: 4013 ands r3, r2
|
|||
|
|
8002694: 2b01 cmp r3, #1
|
|||
|
|
8002696: d103 bne.n 80026a0 <USART1_IRQHandler+0x5c>
|
|||
|
|
__HAL_UART_CLEAR_FLAG(&huart1, UART_FLAG_PE);
|
|||
|
|
8002698: 4b0e ldr r3, [pc, #56] ; (80026d4 <USART1_IRQHandler+0x90>)
|
|||
|
|
800269a: 681b ldr r3, [r3, #0]
|
|||
|
|
800269c: 2201 movs r2, #1
|
|||
|
|
800269e: 621a str r2, [r3, #32]
|
|||
|
|
|
|||
|
|
if(__HAL_UART_GET_FLAG(&huart1, UART_FLAG_FE))
|
|||
|
|
80026a0: 4b0c ldr r3, [pc, #48] ; (80026d4 <USART1_IRQHandler+0x90>)
|
|||
|
|
80026a2: 681b ldr r3, [r3, #0]
|
|||
|
|
80026a4: 69db ldr r3, [r3, #28]
|
|||
|
|
80026a6: 2202 movs r2, #2
|
|||
|
|
80026a8: 4013 ands r3, r2
|
|||
|
|
80026aa: 2b02 cmp r3, #2
|
|||
|
|
80026ac: d103 bne.n 80026b6 <USART1_IRQHandler+0x72>
|
|||
|
|
__HAL_UART_CLEAR_FLAG(&huart1, UART_FLAG_FE);
|
|||
|
|
80026ae: 4b09 ldr r3, [pc, #36] ; (80026d4 <USART1_IRQHandler+0x90>)
|
|||
|
|
80026b0: 681b ldr r3, [r3, #0]
|
|||
|
|
80026b2: 2202 movs r2, #2
|
|||
|
|
80026b4: 621a str r2, [r3, #32]
|
|||
|
|
|
|||
|
|
if(__HAL_UART_GET_FLAG(&huart1, UART_FLAG_NE))
|
|||
|
|
80026b6: 4b07 ldr r3, [pc, #28] ; (80026d4 <USART1_IRQHandler+0x90>)
|
|||
|
|
80026b8: 681b ldr r3, [r3, #0]
|
|||
|
|
80026ba: 69db ldr r3, [r3, #28]
|
|||
|
|
80026bc: 2204 movs r2, #4
|
|||
|
|
80026be: 4013 ands r3, r2
|
|||
|
|
80026c0: 2b04 cmp r3, #4
|
|||
|
|
80026c2: d103 bne.n 80026cc <USART1_IRQHandler+0x88>
|
|||
|
|
__HAL_UART_CLEAR_FLAG(&huart1, UART_FLAG_NE);
|
|||
|
|
80026c4: 4b03 ldr r3, [pc, #12] ; (80026d4 <USART1_IRQHandler+0x90>)
|
|||
|
|
80026c6: 681b ldr r3, [r3, #0]
|
|||
|
|
80026c8: 2204 movs r2, #4
|
|||
|
|
80026ca: 621a str r2, [r3, #32]
|
|||
|
|
}
|
|||
|
|
80026cc: 46c0 nop ; (mov r8, r8)
|
|||
|
|
80026ce: 46bd mov sp, r7
|
|||
|
|
80026d0: bd80 pop {r7, pc}
|
|||
|
|
80026d2: 46c0 nop ; (mov r8, r8)
|
|||
|
|
80026d4: 20000104 .word 0x20000104
|
|||
|
|
|
|||
|
|
080026d8 <strtOut>:
|
|||
|
|
/* USER CODE END 1 */
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
void strtOut(uint16_t n)
|
|||
|
|
{
|
|||
|
|
80026d8: b590 push {r4, r7, lr}
|
|||
|
|
80026da: b085 sub sp, #20
|
|||
|
|
80026dc: af00 add r7, sp, #0
|
|||
|
|
80026de: 0002 movs r2, r0
|
|||
|
|
80026e0: 1dbb adds r3, r7, #6
|
|||
|
|
80026e2: 801a strh r2, [r3, #0]
|
|||
|
|
uint16_t crc;
|
|||
|
|
|
|||
|
|
if(tx[0])
|
|||
|
|
80026e4: 4b1d ldr r3, [pc, #116] ; (800275c <strtOut+0x84>)
|
|||
|
|
80026e6: 781b ldrb r3, [r3, #0]
|
|||
|
|
80026e8: 2b00 cmp r3, #0
|
|||
|
|
80026ea: d02f beq.n 800274c <strtOut+0x74>
|
|||
|
|
{
|
|||
|
|
lastbyte = n + 2; //<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
|||
|
|
80026ec: 1dbb adds r3, r7, #6
|
|||
|
|
80026ee: 881b ldrh r3, [r3, #0]
|
|||
|
|
80026f0: 3302 adds r3, #2
|
|||
|
|
80026f2: b29a uxth r2, r3
|
|||
|
|
80026f4: 4b1a ldr r3, [pc, #104] ; (8002760 <strtOut+0x88>)
|
|||
|
|
80026f6: 801a strh r2, [r3, #0]
|
|||
|
|
crc = Crc16_TX(n); //<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> CRC16
|
|||
|
|
80026f8: 230e movs r3, #14
|
|||
|
|
80026fa: 18fc adds r4, r7, r3
|
|||
|
|
80026fc: 1dbb adds r3, r7, #6
|
|||
|
|
80026fe: 881b ldrh r3, [r3, #0]
|
|||
|
|
8002700: 0018 movs r0, r3
|
|||
|
|
8002702: f000 f875 bl 80027f0 <Crc16_TX>
|
|||
|
|
8002706: 0003 movs r3, r0
|
|||
|
|
8002708: 8023 strh r3, [r4, #0]
|
|||
|
|
tx[n] = lo(crc); //<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> CRC16
|
|||
|
|
800270a: 1dbb adds r3, r7, #6
|
|||
|
|
800270c: 881b ldrh r3, [r3, #0]
|
|||
|
|
800270e: 220e movs r2, #14
|
|||
|
|
8002710: 18ba adds r2, r7, r2
|
|||
|
|
8002712: 8812 ldrh r2, [r2, #0]
|
|||
|
|
8002714: b2d1 uxtb r1, r2
|
|||
|
|
8002716: 4a11 ldr r2, [pc, #68] ; (800275c <strtOut+0x84>)
|
|||
|
|
8002718: 54d1 strb r1, [r2, r3]
|
|||
|
|
tx[n + 1] = hi(crc); // <20> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> 2 <20><><EFBFBD><EFBFBD><EFBFBD>
|
|||
|
|
800271a: 1dbb adds r3, r7, #6
|
|||
|
|
800271c: 881b ldrh r3, [r3, #0]
|
|||
|
|
800271e: 3301 adds r3, #1
|
|||
|
|
8002720: 220e movs r2, #14
|
|||
|
|
8002722: 18ba adds r2, r7, r2
|
|||
|
|
8002724: 8812 ldrh r2, [r2, #0]
|
|||
|
|
8002726: 0a12 lsrs r2, r2, #8
|
|||
|
|
8002728: b292 uxth r2, r2
|
|||
|
|
800272a: b2d1 uxtb r1, r2
|
|||
|
|
800272c: 4a0b ldr r2, [pc, #44] ; (800275c <strtOut+0x84>)
|
|||
|
|
800272e: 54d1 strb r1, [r2, r3]
|
|||
|
|
HAL_GPIO_WritePin(RE_GPIO_Port, RE_Pin, GPIO_PIN_SET); //<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> RS485 <20><> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
|||
|
|
8002730: 2380 movs r3, #128 ; 0x80
|
|||
|
|
8002732: 0059 lsls r1, r3, #1
|
|||
|
|
8002734: 23a0 movs r3, #160 ; 0xa0
|
|||
|
|
8002736: 05db lsls r3, r3, #23
|
|||
|
|
8002738: 2201 movs r2, #1
|
|||
|
|
800273a: 0018 movs r0, r3
|
|||
|
|
800273c: f002 f9e7 bl 8004b0e <HAL_GPIO_WritePin>
|
|||
|
|
ioa = 1;
|
|||
|
|
8002740: 4b08 ldr r3, [pc, #32] ; (8002764 <strtOut+0x8c>)
|
|||
|
|
8002742: 2201 movs r2, #1
|
|||
|
|
8002744: 701a strb r2, [r3, #0]
|
|||
|
|
sendreq = true;
|
|||
|
|
8002746: 4b08 ldr r3, [pc, #32] ; (8002768 <strtOut+0x90>)
|
|||
|
|
8002748: 2201 movs r2, #1
|
|||
|
|
800274a: 701a strb r2, [r3, #0]
|
|||
|
|
}
|
|||
|
|
iolen = 0;
|
|||
|
|
800274c: 4b07 ldr r3, [pc, #28] ; (800276c <strtOut+0x94>)
|
|||
|
|
800274e: 2200 movs r2, #0
|
|||
|
|
8002750: 701a strb r2, [r3, #0]
|
|||
|
|
}
|
|||
|
|
8002752: 46c0 nop ; (mov r8, r8)
|
|||
|
|
8002754: 46bd mov sp, r7
|
|||
|
|
8002756: b005 add sp, #20
|
|||
|
|
8002758: bd90 pop {r4, r7, pc}
|
|||
|
|
800275a: 46c0 nop ; (mov r8, r8)
|
|||
|
|
800275c: 20000188 .word 0x20000188
|
|||
|
|
8002760: 2000028a .word 0x2000028a
|
|||
|
|
8002764: 20000100 .word 0x20000100
|
|||
|
|
8002768: 20000036 .word 0x20000036
|
|||
|
|
800276c: 20000035 .word 0x20000035
|
|||
|
|
|
|||
|
|
08002770 <Crc16>:
|
|||
|
|
|
|||
|
|
|
|||
|
|
uint16_t Crc16(uint16_t len)
|
|||
|
|
{
|
|||
|
|
8002770: b580 push {r7, lr}
|
|||
|
|
8002772: b084 sub sp, #16
|
|||
|
|
8002774: af00 add r7, sp, #0
|
|||
|
|
8002776: 0002 movs r2, r0
|
|||
|
|
8002778: 1dbb adds r3, r7, #6
|
|||
|
|
800277a: 801a strh r2, [r3, #0]
|
|||
|
|
uint16_t i;
|
|||
|
|
uint16_t crc = 0xFFFF;
|
|||
|
|
800277c: 230c movs r3, #12
|
|||
|
|
800277e: 18fb adds r3, r7, r3
|
|||
|
|
8002780: 2201 movs r2, #1
|
|||
|
|
8002782: 4252 negs r2, r2
|
|||
|
|
8002784: 801a strh r2, [r3, #0]
|
|||
|
|
|
|||
|
|
for(i = 0; i < len; i++) {
|
|||
|
|
8002786: 230e movs r3, #14
|
|||
|
|
8002788: 18fb adds r3, r7, r3
|
|||
|
|
800278a: 2200 movs r2, #0
|
|||
|
|
800278c: 801a strh r2, [r3, #0]
|
|||
|
|
800278e: e01d b.n 80027cc <Crc16+0x5c>
|
|||
|
|
crc = (crc >> 8) ^ Crc16Table[(crc & 0xFF) ^ iobuf[i]];
|
|||
|
|
8002790: 230c movs r3, #12
|
|||
|
|
8002792: 18fb adds r3, r7, r3
|
|||
|
|
8002794: 881b ldrh r3, [r3, #0]
|
|||
|
|
8002796: 0a1b lsrs r3, r3, #8
|
|||
|
|
8002798: b299 uxth r1, r3
|
|||
|
|
800279a: 230c movs r3, #12
|
|||
|
|
800279c: 18fb adds r3, r7, r3
|
|||
|
|
800279e: 881b ldrh r3, [r3, #0]
|
|||
|
|
80027a0: 22ff movs r2, #255 ; 0xff
|
|||
|
|
80027a2: 4013 ands r3, r2
|
|||
|
|
80027a4: 220e movs r2, #14
|
|||
|
|
80027a6: 18ba adds r2, r7, r2
|
|||
|
|
80027a8: 8812 ldrh r2, [r2, #0]
|
|||
|
|
80027aa: 480f ldr r0, [pc, #60] ; (80027e8 <Crc16+0x78>)
|
|||
|
|
80027ac: 5c82 ldrb r2, [r0, r2]
|
|||
|
|
80027ae: 405a eors r2, r3
|
|||
|
|
80027b0: 4b0e ldr r3, [pc, #56] ; (80027ec <Crc16+0x7c>)
|
|||
|
|
80027b2: 0052 lsls r2, r2, #1
|
|||
|
|
80027b4: 5ad2 ldrh r2, [r2, r3]
|
|||
|
|
80027b6: 230c movs r3, #12
|
|||
|
|
80027b8: 18fb adds r3, r7, r3
|
|||
|
|
80027ba: 404a eors r2, r1
|
|||
|
|
80027bc: 801a strh r2, [r3, #0]
|
|||
|
|
for(i = 0; i < len; i++) {
|
|||
|
|
80027be: 230e movs r3, #14
|
|||
|
|
80027c0: 18fb adds r3, r7, r3
|
|||
|
|
80027c2: 881a ldrh r2, [r3, #0]
|
|||
|
|
80027c4: 230e movs r3, #14
|
|||
|
|
80027c6: 18fb adds r3, r7, r3
|
|||
|
|
80027c8: 3201 adds r2, #1
|
|||
|
|
80027ca: 801a strh r2, [r3, #0]
|
|||
|
|
80027cc: 230e movs r3, #14
|
|||
|
|
80027ce: 18fa adds r2, r7, r3
|
|||
|
|
80027d0: 1dbb adds r3, r7, #6
|
|||
|
|
80027d2: 8812 ldrh r2, [r2, #0]
|
|||
|
|
80027d4: 881b ldrh r3, [r3, #0]
|
|||
|
|
80027d6: 429a cmp r2, r3
|
|||
|
|
80027d8: d3da bcc.n 8002790 <Crc16+0x20>
|
|||
|
|
}
|
|||
|
|
return crc;
|
|||
|
|
80027da: 230c movs r3, #12
|
|||
|
|
80027dc: 18fb adds r3, r7, r3
|
|||
|
|
80027de: 881b ldrh r3, [r3, #0]
|
|||
|
|
}
|
|||
|
|
80027e0: 0018 movs r0, r3
|
|||
|
|
80027e2: 46bd mov sp, r7
|
|||
|
|
80027e4: b004 add sp, #16
|
|||
|
|
80027e6: bd80 pop {r7, pc}
|
|||
|
|
80027e8: 2000028c .word 0x2000028c
|
|||
|
|
80027ec: 080071f4 .word 0x080071f4
|
|||
|
|
|
|||
|
|
080027f0 <Crc16_TX>:
|
|||
|
|
|
|||
|
|
uint16_t Crc16_TX(uint16_t len)
|
|||
|
|
{
|
|||
|
|
80027f0: b580 push {r7, lr}
|
|||
|
|
80027f2: b084 sub sp, #16
|
|||
|
|
80027f4: af00 add r7, sp, #0
|
|||
|
|
80027f6: 0002 movs r2, r0
|
|||
|
|
80027f8: 1dbb adds r3, r7, #6
|
|||
|
|
80027fa: 801a strh r2, [r3, #0]
|
|||
|
|
uint16_t i;
|
|||
|
|
uint16_t crc = 0xFFFF;
|
|||
|
|
80027fc: 230c movs r3, #12
|
|||
|
|
80027fe: 18fb adds r3, r7, r3
|
|||
|
|
8002800: 2201 movs r2, #1
|
|||
|
|
8002802: 4252 negs r2, r2
|
|||
|
|
8002804: 801a strh r2, [r3, #0]
|
|||
|
|
|
|||
|
|
for(i = 0; i < len; i++) {
|
|||
|
|
8002806: 230e movs r3, #14
|
|||
|
|
8002808: 18fb adds r3, r7, r3
|
|||
|
|
800280a: 2200 movs r2, #0
|
|||
|
|
800280c: 801a strh r2, [r3, #0]
|
|||
|
|
800280e: e01d b.n 800284c <Crc16_TX+0x5c>
|
|||
|
|
crc = (crc >> 8) ^ Crc16Table[(crc & 0xFF) ^ tx[i]];
|
|||
|
|
8002810: 230c movs r3, #12
|
|||
|
|
8002812: 18fb adds r3, r7, r3
|
|||
|
|
8002814: 881b ldrh r3, [r3, #0]
|
|||
|
|
8002816: 0a1b lsrs r3, r3, #8
|
|||
|
|
8002818: b299 uxth r1, r3
|
|||
|
|
800281a: 230c movs r3, #12
|
|||
|
|
800281c: 18fb adds r3, r7, r3
|
|||
|
|
800281e: 881b ldrh r3, [r3, #0]
|
|||
|
|
8002820: 22ff movs r2, #255 ; 0xff
|
|||
|
|
8002822: 4013 ands r3, r2
|
|||
|
|
8002824: 220e movs r2, #14
|
|||
|
|
8002826: 18ba adds r2, r7, r2
|
|||
|
|
8002828: 8812 ldrh r2, [r2, #0]
|
|||
|
|
800282a: 480f ldr r0, [pc, #60] ; (8002868 <Crc16_TX+0x78>)
|
|||
|
|
800282c: 5c82 ldrb r2, [r0, r2]
|
|||
|
|
800282e: 405a eors r2, r3
|
|||
|
|
8002830: 4b0e ldr r3, [pc, #56] ; (800286c <Crc16_TX+0x7c>)
|
|||
|
|
8002832: 0052 lsls r2, r2, #1
|
|||
|
|
8002834: 5ad2 ldrh r2, [r2, r3]
|
|||
|
|
8002836: 230c movs r3, #12
|
|||
|
|
8002838: 18fb adds r3, r7, r3
|
|||
|
|
800283a: 404a eors r2, r1
|
|||
|
|
800283c: 801a strh r2, [r3, #0]
|
|||
|
|
for(i = 0; i < len; i++) {
|
|||
|
|
800283e: 230e movs r3, #14
|
|||
|
|
8002840: 18fb adds r3, r7, r3
|
|||
|
|
8002842: 881a ldrh r2, [r3, #0]
|
|||
|
|
8002844: 230e movs r3, #14
|
|||
|
|
8002846: 18fb adds r3, r7, r3
|
|||
|
|
8002848: 3201 adds r2, #1
|
|||
|
|
800284a: 801a strh r2, [r3, #0]
|
|||
|
|
800284c: 230e movs r3, #14
|
|||
|
|
800284e: 18fa adds r2, r7, r3
|
|||
|
|
8002850: 1dbb adds r3, r7, #6
|
|||
|
|
8002852: 8812 ldrh r2, [r2, #0]
|
|||
|
|
8002854: 881b ldrh r3, [r3, #0]
|
|||
|
|
8002856: 429a cmp r2, r3
|
|||
|
|
8002858: d3da bcc.n 8002810 <Crc16_TX+0x20>
|
|||
|
|
}
|
|||
|
|
return crc;
|
|||
|
|
800285a: 230c movs r3, #12
|
|||
|
|
800285c: 18fb adds r3, r7, r3
|
|||
|
|
800285e: 881b ldrh r3, [r3, #0]
|
|||
|
|
}
|
|||
|
|
8002860: 0018 movs r0, r3
|
|||
|
|
8002862: 46bd mov sp, r7
|
|||
|
|
8002864: b004 add sp, #16
|
|||
|
|
8002866: bd80 pop {r7, pc}
|
|||
|
|
8002868: 20000188 .word 0x20000188
|
|||
|
|
800286c: 080071f4 .word 0x080071f4
|
|||
|
|
|
|||
|
|
08002870 <SetBaudRate>:
|
|||
|
|
|
|||
|
|
|
|||
|
|
void SetBaudRate()
|
|||
|
|
{
|
|||
|
|
8002870: b580 push {r7, lr}
|
|||
|
|
8002872: af00 add r7, sp, #0
|
|||
|
|
timeout = time35[pardata.BAUD];
|
|||
|
|
8002874: 4b0c ldr r3, [pc, #48] ; (80028a8 <SetBaudRate+0x38>)
|
|||
|
|
8002876: 885b ldrh r3, [r3, #2]
|
|||
|
|
8002878: b29b uxth r3, r3
|
|||
|
|
800287a: 001a movs r2, r3
|
|||
|
|
800287c: 4b0b ldr r3, [pc, #44] ; (80028ac <SetBaudRate+0x3c>)
|
|||
|
|
800287e: 0052 lsls r2, r2, #1
|
|||
|
|
8002880: 5ad3 ldrh r3, [r2, r3]
|
|||
|
|
8002882: b2da uxtb r2, r3
|
|||
|
|
8002884: 4b0a ldr r3, [pc, #40] ; (80028b0 <SetBaudRate+0x40>)
|
|||
|
|
8002886: 701a strb r2, [r3, #0]
|
|||
|
|
delayREDE = sendtime[pardata.BAUD];
|
|||
|
|
8002888: 4b07 ldr r3, [pc, #28] ; (80028a8 <SetBaudRate+0x38>)
|
|||
|
|
800288a: 885b ldrh r3, [r3, #2]
|
|||
|
|
800288c: b29b uxth r3, r3
|
|||
|
|
800288e: 001a movs r2, r3
|
|||
|
|
8002890: 4b08 ldr r3, [pc, #32] ; (80028b4 <SetBaudRate+0x44>)
|
|||
|
|
8002892: 0052 lsls r2, r2, #1
|
|||
|
|
8002894: 5ad2 ldrh r2, [r2, r3]
|
|||
|
|
8002896: 4b08 ldr r3, [pc, #32] ; (80028b8 <SetBaudRate+0x48>)
|
|||
|
|
8002898: 801a strh r2, [r3, #0]
|
|||
|
|
|
|||
|
|
MX_USART1_UART_DeInit();
|
|||
|
|
800289a: f7ff fe4b bl 8002534 <MX_USART1_UART_DeInit>
|
|||
|
|
MX_USART1_UART_Init();
|
|||
|
|
800289e: f7ff fda9 bl 80023f4 <MX_USART1_UART_Init>
|
|||
|
|
}
|
|||
|
|
80028a2: 46c0 nop ; (mov r8, r8)
|
|||
|
|
80028a4: 46bd mov sp, r7
|
|||
|
|
80028a6: bd80 pop {r7, pc}
|
|||
|
|
80028a8: 20000098 .word 0x20000098
|
|||
|
|
80028ac: 08007408 .word 0x08007408
|
|||
|
|
80028b0: 20000288 .word 0x20000288
|
|||
|
|
80028b4: 080073f4 .word 0x080073f4
|
|||
|
|
80028b8: 20000102 .word 0x20000102
|
|||
|
|
|
|||
|
|
080028bc <HAL_UART_RxCpltCallback>:
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart)
|
|||
|
|
{
|
|||
|
|
80028bc: b5b0 push {r4, r5, r7, lr}
|
|||
|
|
80028be: b088 sub sp, #32
|
|||
|
|
80028c0: af00 add r7, sp, #0
|
|||
|
|
80028c2: 6078 str r0, [r7, #4]
|
|||
|
|
usfloat f;
|
|||
|
|
uint8_t tmp, tmp1;
|
|||
|
|
uint16_t tmp16;
|
|||
|
|
float tmpf;
|
|||
|
|
|
|||
|
|
timeout = time35[pardata.BAUD];
|
|||
|
|
80028c4: 4bd5 ldr r3, [pc, #852] ; (8002c1c <HAL_UART_RxCpltCallback+0x360>)
|
|||
|
|
80028c6: 885b ldrh r3, [r3, #2]
|
|||
|
|
80028c8: b29b uxth r3, r3
|
|||
|
|
80028ca: 001a movs r2, r3
|
|||
|
|
80028cc: 4bd4 ldr r3, [pc, #848] ; (8002c20 <HAL_UART_RxCpltCallback+0x364>)
|
|||
|
|
80028ce: 0052 lsls r2, r2, #1
|
|||
|
|
80028d0: 5ad3 ldrh r3, [r2, r3]
|
|||
|
|
80028d2: b2da uxtb r2, r3
|
|||
|
|
80028d4: 4bd3 ldr r3, [pc, #844] ; (8002c24 <HAL_UART_RxCpltCallback+0x368>)
|
|||
|
|
80028d6: 701a strb r2, [r3, #0]
|
|||
|
|
iobuf[iolen++] = (uint8_t) (USART1->RDR & 0xFF);
|
|||
|
|
80028d8: 4bd3 ldr r3, [pc, #844] ; (8002c28 <HAL_UART_RxCpltCallback+0x36c>)
|
|||
|
|
80028da: 781b ldrb r3, [r3, #0]
|
|||
|
|
80028dc: 1c5a adds r2, r3, #1
|
|||
|
|
80028de: b2d1 uxtb r1, r2
|
|||
|
|
80028e0: 4ad1 ldr r2, [pc, #836] ; (8002c28 <HAL_UART_RxCpltCallback+0x36c>)
|
|||
|
|
80028e2: 7011 strb r1, [r2, #0]
|
|||
|
|
80028e4: 001a movs r2, r3
|
|||
|
|
80028e6: 4bd1 ldr r3, [pc, #836] ; (8002c2c <HAL_UART_RxCpltCallback+0x370>)
|
|||
|
|
80028e8: 6a5b ldr r3, [r3, #36] ; 0x24
|
|||
|
|
80028ea: b2d9 uxtb r1, r3
|
|||
|
|
80028ec: 4bd0 ldr r3, [pc, #832] ; (8002c30 <HAL_UART_RxCpltCallback+0x374>)
|
|||
|
|
80028ee: 5499 strb r1, [r3, r2]
|
|||
|
|
|
|||
|
|
if((iobuf[0] == pardata.OWN) || (!iobuf[0]))
|
|||
|
|
80028f0: 4bcf ldr r3, [pc, #828] ; (8002c30 <HAL_UART_RxCpltCallback+0x374>)
|
|||
|
|
80028f2: 781b ldrb r3, [r3, #0]
|
|||
|
|
80028f4: b29a uxth r2, r3
|
|||
|
|
80028f6: 4bc9 ldr r3, [pc, #804] ; (8002c1c <HAL_UART_RxCpltCallback+0x360>)
|
|||
|
|
80028f8: 881b ldrh r3, [r3, #0]
|
|||
|
|
80028fa: b29b uxth r3, r3
|
|||
|
|
80028fc: 429a cmp r2, r3
|
|||
|
|
80028fe: d005 beq.n 800290c <HAL_UART_RxCpltCallback+0x50>
|
|||
|
|
8002900: 4bcb ldr r3, [pc, #812] ; (8002c30 <HAL_UART_RxCpltCallback+0x374>)
|
|||
|
|
8002902: 781b ldrb r3, [r3, #0]
|
|||
|
|
8002904: 2b00 cmp r3, #0
|
|||
|
|
8002906: d001 beq.n 800290c <HAL_UART_RxCpltCallback+0x50>
|
|||
|
|
8002908: f001 f9a6 bl 8003c58 <HAL_UART_RxCpltCallback+0x139c>
|
|||
|
|
{
|
|||
|
|
if(iolen > 1)
|
|||
|
|
800290c: 4bc6 ldr r3, [pc, #792] ; (8002c28 <HAL_UART_RxCpltCallback+0x36c>)
|
|||
|
|
800290e: 781b ldrb r3, [r3, #0]
|
|||
|
|
8002910: 2b01 cmp r3, #1
|
|||
|
|
8002912: d801 bhi.n 8002918 <HAL_UART_RxCpltCallback+0x5c>
|
|||
|
|
8002914: f001 f9a0 bl 8003c58 <HAL_UART_RxCpltCallback+0x139c>
|
|||
|
|
{
|
|||
|
|
if(iolen == 2)
|
|||
|
|
8002918: 4bc3 ldr r3, [pc, #780] ; (8002c28 <HAL_UART_RxCpltCallback+0x36c>)
|
|||
|
|
800291a: 781b ldrb r3, [r3, #0]
|
|||
|
|
800291c: 2b02 cmp r3, #2
|
|||
|
|
800291e: d124 bne.n 800296a <HAL_UART_RxCpltCallback+0xae>
|
|||
|
|
{
|
|||
|
|
switch(iobuf[1])
|
|||
|
|
8002920: 4bc3 ldr r3, [pc, #780] ; (8002c30 <HAL_UART_RxCpltCallback+0x374>)
|
|||
|
|
8002922: 785b ldrb r3, [r3, #1]
|
|||
|
|
8002924: 2b03 cmp r3, #3
|
|||
|
|
8002926: d002 beq.n 800292e <HAL_UART_RxCpltCallback+0x72>
|
|||
|
|
8002928: 2b10 cmp r3, #16
|
|||
|
|
800292a: d004 beq.n 8002936 <HAL_UART_RxCpltCallback+0x7a>
|
|||
|
|
800292c: e007 b.n 800293e <HAL_UART_RxCpltCallback+0x82>
|
|||
|
|
{
|
|||
|
|
case 0x03:
|
|||
|
|
lastbyte = 7;
|
|||
|
|
800292e: 4bc1 ldr r3, [pc, #772] ; (8002c34 <HAL_UART_RxCpltCallback+0x378>)
|
|||
|
|
8002930: 2207 movs r2, #7
|
|||
|
|
8002932: 801a strh r2, [r3, #0]
|
|||
|
|
break;
|
|||
|
|
8002934: e019 b.n 800296a <HAL_UART_RxCpltCallback+0xae>
|
|||
|
|
case 0x10:
|
|||
|
|
lastbyte = 6;
|
|||
|
|
8002936: 4bbf ldr r3, [pc, #764] ; (8002c34 <HAL_UART_RxCpltCallback+0x378>)
|
|||
|
|
8002938: 2206 movs r2, #6
|
|||
|
|
800293a: 801a strh r2, [r3, #0]
|
|||
|
|
break;
|
|||
|
|
800293c: e015 b.n 800296a <HAL_UART_RxCpltCallback+0xae>
|
|||
|
|
default:
|
|||
|
|
lastbyte = 3;
|
|||
|
|
800293e: 4bbd ldr r3, [pc, #756] ; (8002c34 <HAL_UART_RxCpltCallback+0x378>)
|
|||
|
|
8002940: 2203 movs r2, #3
|
|||
|
|
8002942: 801a strh r2, [r3, #0]
|
|||
|
|
tx[0] = iobuf[0];
|
|||
|
|
8002944: 4bba ldr r3, [pc, #744] ; (8002c30 <HAL_UART_RxCpltCallback+0x374>)
|
|||
|
|
8002946: 781a ldrb r2, [r3, #0]
|
|||
|
|
8002948: 4bbb ldr r3, [pc, #748] ; (8002c38 <HAL_UART_RxCpltCallback+0x37c>)
|
|||
|
|
800294a: 701a strb r2, [r3, #0]
|
|||
|
|
tx[1] = (iobuf[1] | 0x80);
|
|||
|
|
800294c: 4bb8 ldr r3, [pc, #736] ; (8002c30 <HAL_UART_RxCpltCallback+0x374>)
|
|||
|
|
800294e: 785b ldrb r3, [r3, #1]
|
|||
|
|
8002950: 2280 movs r2, #128 ; 0x80
|
|||
|
|
8002952: 4252 negs r2, r2
|
|||
|
|
8002954: 4313 orrs r3, r2
|
|||
|
|
8002956: b2da uxtb r2, r3
|
|||
|
|
8002958: 4bb7 ldr r3, [pc, #732] ; (8002c38 <HAL_UART_RxCpltCallback+0x37c>)
|
|||
|
|
800295a: 705a strb r2, [r3, #1]
|
|||
|
|
tx[2] = 0x03;
|
|||
|
|
800295c: 4bb6 ldr r3, [pc, #728] ; (8002c38 <HAL_UART_RxCpltCallback+0x37c>)
|
|||
|
|
800295e: 2203 movs r2, #3
|
|||
|
|
8002960: 709a strb r2, [r3, #2]
|
|||
|
|
strtOut(3);
|
|||
|
|
8002962: 2003 movs r0, #3
|
|||
|
|
8002964: f7ff feb8 bl 80026d8 <strtOut>
|
|||
|
|
break;
|
|||
|
|
8002968: 46c0 nop ; (mov r8, r8)
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
|
|||
|
|
if(iolen > lastbyte)
|
|||
|
|
800296a: 4baf ldr r3, [pc, #700] ; (8002c28 <HAL_UART_RxCpltCallback+0x36c>)
|
|||
|
|
800296c: 781b ldrb r3, [r3, #0]
|
|||
|
|
800296e: b29a uxth r2, r3
|
|||
|
|
8002970: 4bb0 ldr r3, [pc, #704] ; (8002c34 <HAL_UART_RxCpltCallback+0x378>)
|
|||
|
|
8002972: 881b ldrh r3, [r3, #0]
|
|||
|
|
8002974: 429a cmp r2, r3
|
|||
|
|
8002976: d801 bhi.n 800297c <HAL_UART_RxCpltCallback+0xc0>
|
|||
|
|
8002978: f001 f96e bl 8003c58 <HAL_UART_RxCpltCallback+0x139c>
|
|||
|
|
{
|
|||
|
|
switch(iobuf[1])
|
|||
|
|
800297c: 4bac ldr r3, [pc, #688] ; (8002c30 <HAL_UART_RxCpltCallback+0x374>)
|
|||
|
|
800297e: 785b ldrb r3, [r3, #1]
|
|||
|
|
8002980: 2b03 cmp r3, #3
|
|||
|
|
8002982: d004 beq.n 800298e <HAL_UART_RxCpltCallback+0xd2>
|
|||
|
|
8002984: 2b10 cmp r3, #16
|
|||
|
|
8002986: d100 bne.n 800298a <HAL_UART_RxCpltCallback+0xce>
|
|||
|
|
8002988: e267 b.n 8002e5a <HAL_UART_RxCpltCallback+0x59e>
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
//iolen++;
|
|||
|
|
}
|
|||
|
|
800298a: f001 f965 bl 8003c58 <HAL_UART_RxCpltCallback+0x139c>
|
|||
|
|
iolen = 0;
|
|||
|
|
800298e: 4ba6 ldr r3, [pc, #664] ; (8002c28 <HAL_UART_RxCpltCallback+0x36c>)
|
|||
|
|
8002990: 2200 movs r2, #0
|
|||
|
|
8002992: 701a strb r2, [r3, #0]
|
|||
|
|
crc.ch[0] = iobuf[6];
|
|||
|
|
8002994: 4ba6 ldr r3, [pc, #664] ; (8002c30 <HAL_UART_RxCpltCallback+0x374>)
|
|||
|
|
8002996: 799a ldrb r2, [r3, #6]
|
|||
|
|
8002998: 2314 movs r3, #20
|
|||
|
|
800299a: 18fb adds r3, r7, r3
|
|||
|
|
800299c: 701a strb r2, [r3, #0]
|
|||
|
|
crc.ch[1] = iobuf[7];
|
|||
|
|
800299e: 4ba4 ldr r3, [pc, #656] ; (8002c30 <HAL_UART_RxCpltCallback+0x374>)
|
|||
|
|
80029a0: 79da ldrb r2, [r3, #7]
|
|||
|
|
80029a2: 2314 movs r3, #20
|
|||
|
|
80029a4: 18fb adds r3, r7, r3
|
|||
|
|
80029a6: 705a strb r2, [r3, #1]
|
|||
|
|
if(crc.sh == Crc16(6)) // ïðè êîððåêòíîì çíà÷åíèè CRC
|
|||
|
|
80029a8: 2314 movs r3, #20
|
|||
|
|
80029aa: 18fb adds r3, r7, r3
|
|||
|
|
80029ac: 881c ldrh r4, [r3, #0]
|
|||
|
|
80029ae: 2006 movs r0, #6
|
|||
|
|
80029b0: f7ff fede bl 8002770 <Crc16>
|
|||
|
|
80029b4: 0003 movs r3, r0
|
|||
|
|
80029b6: 429c cmp r4, r3
|
|||
|
|
80029b8: d001 beq.n 80029be <HAL_UART_RxCpltCallback+0x102>
|
|||
|
|
80029ba: f001 f94c bl 8003c56 <HAL_UART_RxCpltCallback+0x139a>
|
|||
|
|
addr.ch[1] = iobuf[2]; //ñò áàéò àäðåñà ðåãèñòðà
|
|||
|
|
80029be: 4b9c ldr r3, [pc, #624] ; (8002c30 <HAL_UART_RxCpltCallback+0x374>)
|
|||
|
|
80029c0: 789a ldrb r2, [r3, #2]
|
|||
|
|
80029c2: 2310 movs r3, #16
|
|||
|
|
80029c4: 18fb adds r3, r7, r3
|
|||
|
|
80029c6: 705a strb r2, [r3, #1]
|
|||
|
|
addr.ch[0] = iobuf[3]; // ìë áàéò àäðåñà ðåãèñòðà
|
|||
|
|
80029c8: 4b99 ldr r3, [pc, #612] ; (8002c30 <HAL_UART_RxCpltCallback+0x374>)
|
|||
|
|
80029ca: 78da ldrb r2, [r3, #3]
|
|||
|
|
80029cc: 2310 movs r3, #16
|
|||
|
|
80029ce: 18fb adds r3, r7, r3
|
|||
|
|
80029d0: 701a strb r2, [r3, #0]
|
|||
|
|
regs.ch[1] = iobuf[4]; // ñò áàéò êîë-âà ðåãèñòðîâ (ñëîâ)
|
|||
|
|
80029d2: 4b97 ldr r3, [pc, #604] ; (8002c30 <HAL_UART_RxCpltCallback+0x374>)
|
|||
|
|
80029d4: 791a ldrb r2, [r3, #4]
|
|||
|
|
80029d6: 230c movs r3, #12
|
|||
|
|
80029d8: 18fb adds r3, r7, r3
|
|||
|
|
80029da: 705a strb r2, [r3, #1]
|
|||
|
|
regs.ch[0] = iobuf[5]; // ìë áàéò êîë-âî ðåãèñòðîâ (ñëîâ)
|
|||
|
|
80029dc: 4b94 ldr r3, [pc, #592] ; (8002c30 <HAL_UART_RxCpltCallback+0x374>)
|
|||
|
|
80029de: 795a ldrb r2, [r3, #5]
|
|||
|
|
80029e0: 230c movs r3, #12
|
|||
|
|
80029e2: 18fb adds r3, r7, r3
|
|||
|
|
80029e4: 701a strb r2, [r3, #0]
|
|||
|
|
if(addr.sh == 1000) // ×òåíèå áàéòà ÏÅÐÅÃÐÓÇÊÈ
|
|||
|
|
80029e6: 2310 movs r3, #16
|
|||
|
|
80029e8: 18fb adds r3, r7, r3
|
|||
|
|
80029ea: 881a ldrh r2, [r3, #0]
|
|||
|
|
80029ec: 23fa movs r3, #250 ; 0xfa
|
|||
|
|
80029ee: 009b lsls r3, r3, #2
|
|||
|
|
80029f0: 429a cmp r2, r3
|
|||
|
|
80029f2: d142 bne.n 8002a7a <HAL_UART_RxCpltCallback+0x1be>
|
|||
|
|
if(regs.ch[0] != 1) // åñëè çàïðîøåí íå ÎÄÈÍ ðåãèñòð
|
|||
|
|
80029f4: 230c movs r3, #12
|
|||
|
|
80029f6: 18fb adds r3, r7, r3
|
|||
|
|
80029f8: 781b ldrb r3, [r3, #0]
|
|||
|
|
80029fa: 2b01 cmp r3, #1
|
|||
|
|
80029fc: d013 beq.n 8002a26 <HAL_UART_RxCpltCallback+0x16a>
|
|||
|
|
tx[0] = iobuf[0];
|
|||
|
|
80029fe: 4b8c ldr r3, [pc, #560] ; (8002c30 <HAL_UART_RxCpltCallback+0x374>)
|
|||
|
|
8002a00: 781a ldrb r2, [r3, #0]
|
|||
|
|
8002a02: 4b8d ldr r3, [pc, #564] ; (8002c38 <HAL_UART_RxCpltCallback+0x37c>)
|
|||
|
|
8002a04: 701a strb r2, [r3, #0]
|
|||
|
|
tx[1] = (iobuf[1] | 0x80);
|
|||
|
|
8002a06: 4b8a ldr r3, [pc, #552] ; (8002c30 <HAL_UART_RxCpltCallback+0x374>)
|
|||
|
|
8002a08: 785b ldrb r3, [r3, #1]
|
|||
|
|
8002a0a: 2280 movs r2, #128 ; 0x80
|
|||
|
|
8002a0c: 4252 negs r2, r2
|
|||
|
|
8002a0e: 4313 orrs r3, r2
|
|||
|
|
8002a10: b2da uxtb r2, r3
|
|||
|
|
8002a12: 4b89 ldr r3, [pc, #548] ; (8002c38 <HAL_UART_RxCpltCallback+0x37c>)
|
|||
|
|
8002a14: 705a strb r2, [r3, #1]
|
|||
|
|
tx[2] = 0x03;
|
|||
|
|
8002a16: 4b88 ldr r3, [pc, #544] ; (8002c38 <HAL_UART_RxCpltCallback+0x37c>)
|
|||
|
|
8002a18: 2203 movs r2, #3
|
|||
|
|
8002a1a: 709a strb r2, [r3, #2]
|
|||
|
|
strtOut(3);
|
|||
|
|
8002a1c: 2003 movs r0, #3
|
|||
|
|
8002a1e: f7ff fe5b bl 80026d8 <strtOut>
|
|||
|
|
break;
|
|||
|
|
8002a22: f001 f918 bl 8003c56 <HAL_UART_RxCpltCallback+0x139a>
|
|||
|
|
tx[0] = iobuf[0];
|
|||
|
|
8002a26: 4b82 ldr r3, [pc, #520] ; (8002c30 <HAL_UART_RxCpltCallback+0x374>)
|
|||
|
|
8002a28: 781a ldrb r2, [r3, #0]
|
|||
|
|
8002a2a: 4b83 ldr r3, [pc, #524] ; (8002c38 <HAL_UART_RxCpltCallback+0x37c>)
|
|||
|
|
8002a2c: 701a strb r2, [r3, #0]
|
|||
|
|
tx[1] = iobuf[1];
|
|||
|
|
8002a2e: 4b80 ldr r3, [pc, #512] ; (8002c30 <HAL_UART_RxCpltCallback+0x374>)
|
|||
|
|
8002a30: 785a ldrb r2, [r3, #1]
|
|||
|
|
8002a32: 4b81 ldr r3, [pc, #516] ; (8002c38 <HAL_UART_RxCpltCallback+0x37c>)
|
|||
|
|
8002a34: 705a strb r2, [r3, #1]
|
|||
|
|
tx[2] = regs.ch[0] << 1; // êîë-âî áàéò
|
|||
|
|
8002a36: 230c movs r3, #12
|
|||
|
|
8002a38: 18fb adds r3, r7, r3
|
|||
|
|
8002a3a: 781b ldrb r3, [r3, #0]
|
|||
|
|
8002a3c: 18db adds r3, r3, r3
|
|||
|
|
8002a3e: b2da uxtb r2, r3
|
|||
|
|
8002a40: 4b7d ldr r3, [pc, #500] ; (8002c38 <HAL_UART_RxCpltCallback+0x37c>)
|
|||
|
|
8002a42: 709a strb r2, [r3, #2]
|
|||
|
|
tx[3] = 0;
|
|||
|
|
8002a44: 4b7c ldr r3, [pc, #496] ; (8002c38 <HAL_UART_RxCpltCallback+0x37c>)
|
|||
|
|
8002a46: 2200 movs r2, #0
|
|||
|
|
8002a48: 70da strb r2, [r3, #3]
|
|||
|
|
tx[4] = lo(AMP_STATUS);
|
|||
|
|
8002a4a: 4b7c ldr r3, [pc, #496] ; (8002c3c <HAL_UART_RxCpltCallback+0x380>)
|
|||
|
|
8002a4c: 881b ldrh r3, [r3, #0]
|
|||
|
|
8002a4e: b29b uxth r3, r3
|
|||
|
|
8002a50: b2da uxtb r2, r3
|
|||
|
|
8002a52: 4b79 ldr r3, [pc, #484] ; (8002c38 <HAL_UART_RxCpltCallback+0x37c>)
|
|||
|
|
8002a54: 711a strb r2, [r3, #4]
|
|||
|
|
tx[5] = hi(AMP_STATUS);
|
|||
|
|
8002a56: 4b79 ldr r3, [pc, #484] ; (8002c3c <HAL_UART_RxCpltCallback+0x380>)
|
|||
|
|
8002a58: 881b ldrh r3, [r3, #0]
|
|||
|
|
8002a5a: b29b uxth r3, r3
|
|||
|
|
8002a5c: 0a1b lsrs r3, r3, #8
|
|||
|
|
8002a5e: b29b uxth r3, r3
|
|||
|
|
8002a60: b2da uxtb r2, r3
|
|||
|
|
8002a62: 4b75 ldr r3, [pc, #468] ; (8002c38 <HAL_UART_RxCpltCallback+0x37c>)
|
|||
|
|
8002a64: 715a strb r2, [r3, #5]
|
|||
|
|
strtOut(3 + tx[2]);
|
|||
|
|
8002a66: 4b74 ldr r3, [pc, #464] ; (8002c38 <HAL_UART_RxCpltCallback+0x37c>)
|
|||
|
|
8002a68: 789b ldrb r3, [r3, #2]
|
|||
|
|
8002a6a: b29b uxth r3, r3
|
|||
|
|
8002a6c: 3303 adds r3, #3
|
|||
|
|
8002a6e: b29b uxth r3, r3
|
|||
|
|
8002a70: 0018 movs r0, r3
|
|||
|
|
8002a72: f7ff fe31 bl 80026d8 <strtOut>
|
|||
|
|
break;
|
|||
|
|
8002a76: f001 f8ee bl 8003c56 <HAL_UART_RxCpltCallback+0x139a>
|
|||
|
|
switch(addr.sh)
|
|||
|
|
8002a7a: 2310 movs r3, #16
|
|||
|
|
8002a7c: 18fb adds r3, r7, r3
|
|||
|
|
8002a7e: 881b ldrh r3, [r3, #0]
|
|||
|
|
8002a80: 4a6f ldr r2, [pc, #444] ; (8002c40 <HAL_UART_RxCpltCallback+0x384>)
|
|||
|
|
8002a82: 4293 cmp r3, r2
|
|||
|
|
8002a84: d100 bne.n 8002a88 <HAL_UART_RxCpltCallback+0x1cc>
|
|||
|
|
8002a86: e111 b.n 8002cac <HAL_UART_RxCpltCallback+0x3f0>
|
|||
|
|
8002a88: 4a6d ldr r2, [pc, #436] ; (8002c40 <HAL_UART_RxCpltCallback+0x384>)
|
|||
|
|
8002a8a: 4293 cmp r3, r2
|
|||
|
|
8002a8c: dc0b bgt.n 8002aa6 <HAL_UART_RxCpltCallback+0x1ea>
|
|||
|
|
8002a8e: 4a6d ldr r2, [pc, #436] ; (8002c44 <HAL_UART_RxCpltCallback+0x388>)
|
|||
|
|
8002a90: 4293 cmp r3, r2
|
|||
|
|
8002a92: da00 bge.n 8002a96 <HAL_UART_RxCpltCallback+0x1da>
|
|||
|
|
8002a94: e1cc b.n 8002e30 <HAL_UART_RxCpltCallback+0x574>
|
|||
|
|
8002a96: 4a6c ldr r2, [pc, #432] ; (8002c48 <HAL_UART_RxCpltCallback+0x38c>)
|
|||
|
|
8002a98: 4293 cmp r3, r2
|
|||
|
|
8002a9a: dd19 ble.n 8002ad0 <HAL_UART_RxCpltCallback+0x214>
|
|||
|
|
8002a9c: 4a6b ldr r2, [pc, #428] ; (8002c4c <HAL_UART_RxCpltCallback+0x390>)
|
|||
|
|
8002a9e: 4293 cmp r3, r2
|
|||
|
|
8002aa0: d100 bne.n 8002aa4 <HAL_UART_RxCpltCallback+0x1e8>
|
|||
|
|
8002aa2: e07a b.n 8002b9a <HAL_UART_RxCpltCallback+0x2de>
|
|||
|
|
8002aa4: e1c4 b.n 8002e30 <HAL_UART_RxCpltCallback+0x574>
|
|||
|
|
8002aa6: 4a6a ldr r2, [pc, #424] ; (8002c50 <HAL_UART_RxCpltCallback+0x394>)
|
|||
|
|
8002aa8: 4293 cmp r3, r2
|
|||
|
|
8002aaa: d100 bne.n 8002aae <HAL_UART_RxCpltCallback+0x1f2>
|
|||
|
|
8002aac: e075 b.n 8002b9a <HAL_UART_RxCpltCallback+0x2de>
|
|||
|
|
8002aae: 4a68 ldr r2, [pc, #416] ; (8002c50 <HAL_UART_RxCpltCallback+0x394>)
|
|||
|
|
8002ab0: 4293 cmp r3, r2
|
|||
|
|
8002ab2: dc04 bgt.n 8002abe <HAL_UART_RxCpltCallback+0x202>
|
|||
|
|
8002ab4: 4a67 ldr r2, [pc, #412] ; (8002c54 <HAL_UART_RxCpltCallback+0x398>)
|
|||
|
|
8002ab6: 4293 cmp r3, r2
|
|||
|
|
8002ab8: d100 bne.n 8002abc <HAL_UART_RxCpltCallback+0x200>
|
|||
|
|
8002aba: e158 b.n 8002d6e <HAL_UART_RxCpltCallback+0x4b2>
|
|||
|
|
8002abc: e1b8 b.n 8002e30 <HAL_UART_RxCpltCallback+0x574>
|
|||
|
|
8002abe: 4a66 ldr r2, [pc, #408] ; (8002c58 <HAL_UART_RxCpltCallback+0x39c>)
|
|||
|
|
8002ac0: 4293 cmp r3, r2
|
|||
|
|
8002ac2: d100 bne.n 8002ac6 <HAL_UART_RxCpltCallback+0x20a>
|
|||
|
|
8002ac4: e0f2 b.n 8002cac <HAL_UART_RxCpltCallback+0x3f0>
|
|||
|
|
8002ac6: 4a65 ldr r2, [pc, #404] ; (8002c5c <HAL_UART_RxCpltCallback+0x3a0>)
|
|||
|
|
8002ac8: 4293 cmp r3, r2
|
|||
|
|
8002aca: d100 bne.n 8002ace <HAL_UART_RxCpltCallback+0x212>
|
|||
|
|
8002acc: e14f b.n 8002d6e <HAL_UART_RxCpltCallback+0x4b2>
|
|||
|
|
8002ace: e1af b.n 8002e30 <HAL_UART_RxCpltCallback+0x574>
|
|||
|
|
if(regs.ch[0] > (5011 - addr.sh))
|
|||
|
|
8002ad0: 230c movs r3, #12
|
|||
|
|
8002ad2: 18fb adds r3, r7, r3
|
|||
|
|
8002ad4: 781b ldrb r3, [r3, #0]
|
|||
|
|
8002ad6: 001a movs r2, r3
|
|||
|
|
8002ad8: 2310 movs r3, #16
|
|||
|
|
8002ada: 18fb adds r3, r7, r3
|
|||
|
|
8002adc: 881b ldrh r3, [r3, #0]
|
|||
|
|
8002ade: 0019 movs r1, r3
|
|||
|
|
8002ae0: 4b5f ldr r3, [pc, #380] ; (8002c60 <HAL_UART_RxCpltCallback+0x3a4>)
|
|||
|
|
8002ae2: 1a5b subs r3, r3, r1
|
|||
|
|
8002ae4: 429a cmp r2, r3
|
|||
|
|
8002ae6: dd12 ble.n 8002b0e <HAL_UART_RxCpltCallback+0x252>
|
|||
|
|
tx[0] = iobuf[0];
|
|||
|
|
8002ae8: 4b51 ldr r3, [pc, #324] ; (8002c30 <HAL_UART_RxCpltCallback+0x374>)
|
|||
|
|
8002aea: 781a ldrb r2, [r3, #0]
|
|||
|
|
8002aec: 4b52 ldr r3, [pc, #328] ; (8002c38 <HAL_UART_RxCpltCallback+0x37c>)
|
|||
|
|
8002aee: 701a strb r2, [r3, #0]
|
|||
|
|
tx[1] = (iobuf[1] | 0x80);
|
|||
|
|
8002af0: 4b4f ldr r3, [pc, #316] ; (8002c30 <HAL_UART_RxCpltCallback+0x374>)
|
|||
|
|
8002af2: 785b ldrb r3, [r3, #1]
|
|||
|
|
8002af4: 2280 movs r2, #128 ; 0x80
|
|||
|
|
8002af6: 4252 negs r2, r2
|
|||
|
|
8002af8: 4313 orrs r3, r2
|
|||
|
|
8002afa: b2da uxtb r2, r3
|
|||
|
|
8002afc: 4b4e ldr r3, [pc, #312] ; (8002c38 <HAL_UART_RxCpltCallback+0x37c>)
|
|||
|
|
8002afe: 705a strb r2, [r3, #1]
|
|||
|
|
tx[2] = 0x03;
|
|||
|
|
8002b00: 4b4d ldr r3, [pc, #308] ; (8002c38 <HAL_UART_RxCpltCallback+0x37c>)
|
|||
|
|
8002b02: 2203 movs r2, #3
|
|||
|
|
8002b04: 709a strb r2, [r3, #2]
|
|||
|
|
strtOut(3);
|
|||
|
|
8002b06: 2003 movs r0, #3
|
|||
|
|
8002b08: f7ff fde6 bl 80026d8 <strtOut>
|
|||
|
|
break;
|
|||
|
|
8002b0c: e1a3 b.n 8002e56 <HAL_UART_RxCpltCallback+0x59a>
|
|||
|
|
tx[0] = iobuf[0];
|
|||
|
|
8002b0e: 4b48 ldr r3, [pc, #288] ; (8002c30 <HAL_UART_RxCpltCallback+0x374>)
|
|||
|
|
8002b10: 781a ldrb r2, [r3, #0]
|
|||
|
|
8002b12: 4b49 ldr r3, [pc, #292] ; (8002c38 <HAL_UART_RxCpltCallback+0x37c>)
|
|||
|
|
8002b14: 701a strb r2, [r3, #0]
|
|||
|
|
tx[1] = iobuf[1];
|
|||
|
|
8002b16: 4b46 ldr r3, [pc, #280] ; (8002c30 <HAL_UART_RxCpltCallback+0x374>)
|
|||
|
|
8002b18: 785a ldrb r2, [r3, #1]
|
|||
|
|
8002b1a: 4b47 ldr r3, [pc, #284] ; (8002c38 <HAL_UART_RxCpltCallback+0x37c>)
|
|||
|
|
8002b1c: 705a strb r2, [r3, #1]
|
|||
|
|
tx[2] = regs.ch[0] << 1;
|
|||
|
|
8002b1e: 230c movs r3, #12
|
|||
|
|
8002b20: 18fb adds r3, r7, r3
|
|||
|
|
8002b22: 781b ldrb r3, [r3, #0]
|
|||
|
|
8002b24: 18db adds r3, r3, r3
|
|||
|
|
8002b26: b2da uxtb r2, r3
|
|||
|
|
8002b28: 4b43 ldr r3, [pc, #268] ; (8002c38 <HAL_UART_RxCpltCallback+0x37c>)
|
|||
|
|
8002b2a: 709a strb r2, [r3, #2]
|
|||
|
|
pch = (uint8_t *) &pardata.IIN + ((addr.sh - 5001) << 1);
|
|||
|
|
8002b2c: 2310 movs r3, #16
|
|||
|
|
8002b2e: 18fb adds r3, r7, r3
|
|||
|
|
8002b30: 881b ldrh r3, [r3, #0]
|
|||
|
|
8002b32: 4a4c ldr r2, [pc, #304] ; (8002c64 <HAL_UART_RxCpltCallback+0x3a8>)
|
|||
|
|
8002b34: 4694 mov ip, r2
|
|||
|
|
8002b36: 4463 add r3, ip
|
|||
|
|
8002b38: 005b lsls r3, r3, #1
|
|||
|
|
8002b3a: 001a movs r2, r3
|
|||
|
|
8002b3c: 4b4a ldr r3, [pc, #296] ; (8002c68 <HAL_UART_RxCpltCallback+0x3ac>)
|
|||
|
|
8002b3e: 18d3 adds r3, r2, r3
|
|||
|
|
8002b40: 61bb str r3, [r7, #24]
|
|||
|
|
for(j = 0; j < tx[2]; j++)
|
|||
|
|
8002b42: 231f movs r3, #31
|
|||
|
|
8002b44: 18fb adds r3, r7, r3
|
|||
|
|
8002b46: 2200 movs r2, #0
|
|||
|
|
8002b48: 701a strb r2, [r3, #0]
|
|||
|
|
8002b4a: e016 b.n 8002b7a <HAL_UART_RxCpltCallback+0x2be>
|
|||
|
|
tx[j + 3] = *(pch + (j ^ 1));
|
|||
|
|
8002b4c: 231f movs r3, #31
|
|||
|
|
8002b4e: 18fb adds r3, r7, r3
|
|||
|
|
8002b50: 781b ldrb r3, [r3, #0]
|
|||
|
|
8002b52: 3303 adds r3, #3
|
|||
|
|
8002b54: 221f movs r2, #31
|
|||
|
|
8002b56: 18ba adds r2, r7, r2
|
|||
|
|
8002b58: 7812 ldrb r2, [r2, #0]
|
|||
|
|
8002b5a: 2101 movs r1, #1
|
|||
|
|
8002b5c: 404a eors r2, r1
|
|||
|
|
8002b5e: b2d2 uxtb r2, r2
|
|||
|
|
8002b60: 0011 movs r1, r2
|
|||
|
|
8002b62: 69ba ldr r2, [r7, #24]
|
|||
|
|
8002b64: 1852 adds r2, r2, r1
|
|||
|
|
8002b66: 7811 ldrb r1, [r2, #0]
|
|||
|
|
8002b68: 4a33 ldr r2, [pc, #204] ; (8002c38 <HAL_UART_RxCpltCallback+0x37c>)
|
|||
|
|
8002b6a: 54d1 strb r1, [r2, r3]
|
|||
|
|
for(j = 0; j < tx[2]; j++)
|
|||
|
|
8002b6c: 231f movs r3, #31
|
|||
|
|
8002b6e: 18fb adds r3, r7, r3
|
|||
|
|
8002b70: 781a ldrb r2, [r3, #0]
|
|||
|
|
8002b72: 231f movs r3, #31
|
|||
|
|
8002b74: 18fb adds r3, r7, r3
|
|||
|
|
8002b76: 3201 adds r2, #1
|
|||
|
|
8002b78: 701a strb r2, [r3, #0]
|
|||
|
|
8002b7a: 4b2f ldr r3, [pc, #188] ; (8002c38 <HAL_UART_RxCpltCallback+0x37c>)
|
|||
|
|
8002b7c: 789b ldrb r3, [r3, #2]
|
|||
|
|
8002b7e: 221f movs r2, #31
|
|||
|
|
8002b80: 18ba adds r2, r7, r2
|
|||
|
|
8002b82: 7812 ldrb r2, [r2, #0]
|
|||
|
|
8002b84: 429a cmp r2, r3
|
|||
|
|
8002b86: d3e1 bcc.n 8002b4c <HAL_UART_RxCpltCallback+0x290>
|
|||
|
|
strtOut(3 + tx[2]);
|
|||
|
|
8002b88: 4b2b ldr r3, [pc, #172] ; (8002c38 <HAL_UART_RxCpltCallback+0x37c>)
|
|||
|
|
8002b8a: 789b ldrb r3, [r3, #2]
|
|||
|
|
8002b8c: b29b uxth r3, r3
|
|||
|
|
8002b8e: 3303 adds r3, #3
|
|||
|
|
8002b90: b29b uxth r3, r3
|
|||
|
|
8002b92: 0018 movs r0, r3
|
|||
|
|
8002b94: f7ff fda0 bl 80026d8 <strtOut>
|
|||
|
|
break;
|
|||
|
|
8002b98: e15d b.n 8002e56 <HAL_UART_RxCpltCallback+0x59a>
|
|||
|
|
tmp = 3;
|
|||
|
|
8002b9a: 231e movs r3, #30
|
|||
|
|
8002b9c: 18fb adds r3, r7, r3
|
|||
|
|
8002b9e: 2203 movs r2, #3
|
|||
|
|
8002ba0: 701a strb r2, [r3, #0]
|
|||
|
|
tx[0] = iobuf[0];
|
|||
|
|
8002ba2: 4b23 ldr r3, [pc, #140] ; (8002c30 <HAL_UART_RxCpltCallback+0x374>)
|
|||
|
|
8002ba4: 781a ldrb r2, [r3, #0]
|
|||
|
|
8002ba6: 4b24 ldr r3, [pc, #144] ; (8002c38 <HAL_UART_RxCpltCallback+0x37c>)
|
|||
|
|
8002ba8: 701a strb r2, [r3, #0]
|
|||
|
|
tx[1] = iobuf[1];
|
|||
|
|
8002baa: 4b21 ldr r3, [pc, #132] ; (8002c30 <HAL_UART_RxCpltCallback+0x374>)
|
|||
|
|
8002bac: 785a ldrb r2, [r3, #1]
|
|||
|
|
8002bae: 4b22 ldr r3, [pc, #136] ; (8002c38 <HAL_UART_RxCpltCallback+0x37c>)
|
|||
|
|
8002bb0: 705a strb r2, [r3, #1]
|
|||
|
|
tx[2] = regs.ch[0] << 2; // êîë-âî áàéò äàííûõ
|
|||
|
|
8002bb2: 230c movs r3, #12
|
|||
|
|
8002bb4: 18fb adds r3, r7, r3
|
|||
|
|
8002bb6: 781b ldrb r3, [r3, #0]
|
|||
|
|
8002bb8: 009b lsls r3, r3, #2
|
|||
|
|
8002bba: b2da uxtb r2, r3
|
|||
|
|
8002bbc: 4b1e ldr r3, [pc, #120] ; (8002c38 <HAL_UART_RxCpltCallback+0x37c>)
|
|||
|
|
8002bbe: 709a strb r2, [r3, #2]
|
|||
|
|
if(addr.sh == 7002)
|
|||
|
|
8002bc0: 2310 movs r3, #16
|
|||
|
|
8002bc2: 18fb adds r3, r7, r3
|
|||
|
|
8002bc4: 881b ldrh r3, [r3, #0]
|
|||
|
|
8002bc6: 4a21 ldr r2, [pc, #132] ; (8002c4c <HAL_UART_RxCpltCallback+0x390>)
|
|||
|
|
8002bc8: 4293 cmp r3, r2
|
|||
|
|
8002bca: d10c bne.n 8002be6 <HAL_UART_RxCpltCallback+0x32a>
|
|||
|
|
tmp <<= 1; //tmp=6
|
|||
|
|
8002bcc: 231e movs r3, #30
|
|||
|
|
8002bce: 18fa adds r2, r7, r3
|
|||
|
|
8002bd0: 231e movs r3, #30
|
|||
|
|
8002bd2: 18fb adds r3, r7, r3
|
|||
|
|
8002bd4: 781b ldrb r3, [r3, #0]
|
|||
|
|
8002bd6: 18db adds r3, r3, r3
|
|||
|
|
8002bd8: 7013 strb r3, [r2, #0]
|
|||
|
|
tx[2] >>= 1; //êîë-âî ñëîâ äàííûõ
|
|||
|
|
8002bda: 4b17 ldr r3, [pc, #92] ; (8002c38 <HAL_UART_RxCpltCallback+0x37c>)
|
|||
|
|
8002bdc: 789b ldrb r3, [r3, #2]
|
|||
|
|
8002bde: 085b lsrs r3, r3, #1
|
|||
|
|
8002be0: b2da uxtb r2, r3
|
|||
|
|
8002be2: 4b15 ldr r3, [pc, #84] ; (8002c38 <HAL_UART_RxCpltCallback+0x37c>)
|
|||
|
|
8002be4: 709a strb r2, [r3, #2]
|
|||
|
|
if(regs.ch[0] > tmp)
|
|||
|
|
8002be6: 230c movs r3, #12
|
|||
|
|
8002be8: 18fb adds r3, r7, r3
|
|||
|
|
8002bea: 781b ldrb r3, [r3, #0]
|
|||
|
|
8002bec: 221e movs r2, #30
|
|||
|
|
8002bee: 18ba adds r2, r7, r2
|
|||
|
|
8002bf0: 7812 ldrb r2, [r2, #0]
|
|||
|
|
8002bf2: 429a cmp r2, r3
|
|||
|
|
8002bf4: d23a bcs.n 8002c6c <HAL_UART_RxCpltCallback+0x3b0>
|
|||
|
|
tx[0] = iobuf[0];
|
|||
|
|
8002bf6: 4b0e ldr r3, [pc, #56] ; (8002c30 <HAL_UART_RxCpltCallback+0x374>)
|
|||
|
|
8002bf8: 781a ldrb r2, [r3, #0]
|
|||
|
|
8002bfa: 4b0f ldr r3, [pc, #60] ; (8002c38 <HAL_UART_RxCpltCallback+0x37c>)
|
|||
|
|
8002bfc: 701a strb r2, [r3, #0]
|
|||
|
|
tx[1] = (iobuf[1] | 0x80);
|
|||
|
|
8002bfe: 4b0c ldr r3, [pc, #48] ; (8002c30 <HAL_UART_RxCpltCallback+0x374>)
|
|||
|
|
8002c00: 785b ldrb r3, [r3, #1]
|
|||
|
|
8002c02: 2280 movs r2, #128 ; 0x80
|
|||
|
|
8002c04: 4252 negs r2, r2
|
|||
|
|
8002c06: 4313 orrs r3, r2
|
|||
|
|
8002c08: b2da uxtb r2, r3
|
|||
|
|
8002c0a: 4b0b ldr r3, [pc, #44] ; (8002c38 <HAL_UART_RxCpltCallback+0x37c>)
|
|||
|
|
8002c0c: 705a strb r2, [r3, #1]
|
|||
|
|
tx[2] = 0x03;
|
|||
|
|
8002c0e: 4b0a ldr r3, [pc, #40] ; (8002c38 <HAL_UART_RxCpltCallback+0x37c>)
|
|||
|
|
8002c10: 2203 movs r2, #3
|
|||
|
|
8002c12: 709a strb r2, [r3, #2]
|
|||
|
|
strtOut(3);
|
|||
|
|
8002c14: 2003 movs r0, #3
|
|||
|
|
8002c16: f7ff fd5f bl 80026d8 <strtOut>
|
|||
|
|
break;
|
|||
|
|
8002c1a: e11c b.n 8002e56 <HAL_UART_RxCpltCallback+0x59a>
|
|||
|
|
8002c1c: 20000098 .word 0x20000098
|
|||
|
|
8002c20: 08007408 .word 0x08007408
|
|||
|
|
8002c24: 20000288 .word 0x20000288
|
|||
|
|
8002c28: 20000035 .word 0x20000035
|
|||
|
|
8002c2c: 40013800 .word 0x40013800
|
|||
|
|
8002c30: 2000028c .word 0x2000028c
|
|||
|
|
8002c34: 2000028a .word 0x2000028a
|
|||
|
|
8002c38: 20000188 .word 0x20000188
|
|||
|
|
8002c3c: 2000002c .word 0x2000002c
|
|||
|
|
8002c40: 00001b5c .word 0x00001b5c
|
|||
|
|
8002c44: 00001389 .word 0x00001389
|
|||
|
|
8002c48: 00001392 .word 0x00001392
|
|||
|
|
8002c4c: 00001b5a .word 0x00001b5a
|
|||
|
|
8002c50: 00001d4d .word 0x00001d4d
|
|||
|
|
8002c54: 00001b5e .word 0x00001b5e
|
|||
|
|
8002c58: 00001d4e .word 0x00001d4e
|
|||
|
|
8002c5c: 00001d4f .word 0x00001d4f
|
|||
|
|
8002c60: 00001393 .word 0x00001393
|
|||
|
|
8002c64: ffffec77 .word 0xffffec77
|
|||
|
|
8002c68: 2000009e .word 0x2000009e
|
|||
|
|
f.fl = pardata.KCOND;
|
|||
|
|
8002c6c: 4be9 ldr r3, [pc, #932] ; (8003014 <HAL_UART_RxCpltCallback+0x758>)
|
|||
|
|
8002c6e: 69db ldr r3, [r3, #28]
|
|||
|
|
8002c70: 60bb str r3, [r7, #8]
|
|||
|
|
tx[3] = f.ch[3];
|
|||
|
|
8002c72: 2308 movs r3, #8
|
|||
|
|
8002c74: 18fb adds r3, r7, r3
|
|||
|
|
8002c76: 78da ldrb r2, [r3, #3]
|
|||
|
|
8002c78: 4be7 ldr r3, [pc, #924] ; (8003018 <HAL_UART_RxCpltCallback+0x75c>)
|
|||
|
|
8002c7a: 70da strb r2, [r3, #3]
|
|||
|
|
tx[4] = f.ch[2];
|
|||
|
|
8002c7c: 2308 movs r3, #8
|
|||
|
|
8002c7e: 18fb adds r3, r7, r3
|
|||
|
|
8002c80: 789a ldrb r2, [r3, #2]
|
|||
|
|
8002c82: 4be5 ldr r3, [pc, #916] ; (8003018 <HAL_UART_RxCpltCallback+0x75c>)
|
|||
|
|
8002c84: 711a strb r2, [r3, #4]
|
|||
|
|
tx[5] = f.ch[1];
|
|||
|
|
8002c86: 2308 movs r3, #8
|
|||
|
|
8002c88: 18fb adds r3, r7, r3
|
|||
|
|
8002c8a: 785a ldrb r2, [r3, #1]
|
|||
|
|
8002c8c: 4be2 ldr r3, [pc, #904] ; (8003018 <HAL_UART_RxCpltCallback+0x75c>)
|
|||
|
|
8002c8e: 715a strb r2, [r3, #5]
|
|||
|
|
tx[6] = f.ch[0];
|
|||
|
|
8002c90: 2308 movs r3, #8
|
|||
|
|
8002c92: 18fb adds r3, r7, r3
|
|||
|
|
8002c94: 781a ldrb r2, [r3, #0]
|
|||
|
|
8002c96: 4be0 ldr r3, [pc, #896] ; (8003018 <HAL_UART_RxCpltCallback+0x75c>)
|
|||
|
|
8002c98: 719a strb r2, [r3, #6]
|
|||
|
|
strtOut(3 + tx[2]);
|
|||
|
|
8002c9a: 4bdf ldr r3, [pc, #892] ; (8003018 <HAL_UART_RxCpltCallback+0x75c>)
|
|||
|
|
8002c9c: 789b ldrb r3, [r3, #2]
|
|||
|
|
8002c9e: b29b uxth r3, r3
|
|||
|
|
8002ca0: 3303 adds r3, #3
|
|||
|
|
8002ca2: b29b uxth r3, r3
|
|||
|
|
8002ca4: 0018 movs r0, r3
|
|||
|
|
8002ca6: f7ff fd17 bl 80026d8 <strtOut>
|
|||
|
|
break;
|
|||
|
|
8002caa: e0d4 b.n 8002e56 <HAL_UART_RxCpltCallback+0x59a>
|
|||
|
|
tmp = 2;
|
|||
|
|
8002cac: 231e movs r3, #30
|
|||
|
|
8002cae: 18fb adds r3, r7, r3
|
|||
|
|
8002cb0: 2202 movs r2, #2
|
|||
|
|
8002cb2: 701a strb r2, [r3, #0]
|
|||
|
|
tx[0] = iobuf[0];
|
|||
|
|
8002cb4: 4bd9 ldr r3, [pc, #868] ; (800301c <HAL_UART_RxCpltCallback+0x760>)
|
|||
|
|
8002cb6: 781a ldrb r2, [r3, #0]
|
|||
|
|
8002cb8: 4bd7 ldr r3, [pc, #860] ; (8003018 <HAL_UART_RxCpltCallback+0x75c>)
|
|||
|
|
8002cba: 701a strb r2, [r3, #0]
|
|||
|
|
tx[1] = iobuf[1];
|
|||
|
|
8002cbc: 4bd7 ldr r3, [pc, #860] ; (800301c <HAL_UART_RxCpltCallback+0x760>)
|
|||
|
|
8002cbe: 785a ldrb r2, [r3, #1]
|
|||
|
|
8002cc0: 4bd5 ldr r3, [pc, #852] ; (8003018 <HAL_UART_RxCpltCallback+0x75c>)
|
|||
|
|
8002cc2: 705a strb r2, [r3, #1]
|
|||
|
|
tx[2] = regs.ch[0] << 2;
|
|||
|
|
8002cc4: 230c movs r3, #12
|
|||
|
|
8002cc6: 18fb adds r3, r7, r3
|
|||
|
|
8002cc8: 781b ldrb r3, [r3, #0]
|
|||
|
|
8002cca: 009b lsls r3, r3, #2
|
|||
|
|
8002ccc: b2da uxtb r2, r3
|
|||
|
|
8002cce: 4bd2 ldr r3, [pc, #840] ; (8003018 <HAL_UART_RxCpltCallback+0x75c>)
|
|||
|
|
8002cd0: 709a strb r2, [r3, #2]
|
|||
|
|
if(addr.sh == 7004)
|
|||
|
|
8002cd2: 2310 movs r3, #16
|
|||
|
|
8002cd4: 18fb adds r3, r7, r3
|
|||
|
|
8002cd6: 881b ldrh r3, [r3, #0]
|
|||
|
|
8002cd8: 4ad1 ldr r2, [pc, #836] ; (8003020 <HAL_UART_RxCpltCallback+0x764>)
|
|||
|
|
8002cda: 4293 cmp r3, r2
|
|||
|
|
8002cdc: d10c bne.n 8002cf8 <HAL_UART_RxCpltCallback+0x43c>
|
|||
|
|
tmp <<= 1;
|
|||
|
|
8002cde: 231e movs r3, #30
|
|||
|
|
8002ce0: 18fa adds r2, r7, r3
|
|||
|
|
8002ce2: 231e movs r3, #30
|
|||
|
|
8002ce4: 18fb adds r3, r7, r3
|
|||
|
|
8002ce6: 781b ldrb r3, [r3, #0]
|
|||
|
|
8002ce8: 18db adds r3, r3, r3
|
|||
|
|
8002cea: 7013 strb r3, [r2, #0]
|
|||
|
|
tx[2] >>= 1;
|
|||
|
|
8002cec: 4bca ldr r3, [pc, #808] ; (8003018 <HAL_UART_RxCpltCallback+0x75c>)
|
|||
|
|
8002cee: 789b ldrb r3, [r3, #2]
|
|||
|
|
8002cf0: 085b lsrs r3, r3, #1
|
|||
|
|
8002cf2: b2da uxtb r2, r3
|
|||
|
|
8002cf4: 4bc8 ldr r3, [pc, #800] ; (8003018 <HAL_UART_RxCpltCallback+0x75c>)
|
|||
|
|
8002cf6: 709a strb r2, [r3, #2]
|
|||
|
|
if(regs.ch[0] > tmp)
|
|||
|
|
8002cf8: 230c movs r3, #12
|
|||
|
|
8002cfa: 18fb adds r3, r7, r3
|
|||
|
|
8002cfc: 781b ldrb r3, [r3, #0]
|
|||
|
|
8002cfe: 221e movs r2, #30
|
|||
|
|
8002d00: 18ba adds r2, r7, r2
|
|||
|
|
8002d02: 7812 ldrb r2, [r2, #0]
|
|||
|
|
8002d04: 429a cmp r2, r3
|
|||
|
|
8002d06: d212 bcs.n 8002d2e <HAL_UART_RxCpltCallback+0x472>
|
|||
|
|
tx[0] = iobuf[0];
|
|||
|
|
8002d08: 4bc4 ldr r3, [pc, #784] ; (800301c <HAL_UART_RxCpltCallback+0x760>)
|
|||
|
|
8002d0a: 781a ldrb r2, [r3, #0]
|
|||
|
|
8002d0c: 4bc2 ldr r3, [pc, #776] ; (8003018 <HAL_UART_RxCpltCallback+0x75c>)
|
|||
|
|
8002d0e: 701a strb r2, [r3, #0]
|
|||
|
|
tx[1] = (iobuf[1] | 0x80);
|
|||
|
|
8002d10: 4bc2 ldr r3, [pc, #776] ; (800301c <HAL_UART_RxCpltCallback+0x760>)
|
|||
|
|
8002d12: 785b ldrb r3, [r3, #1]
|
|||
|
|
8002d14: 2280 movs r2, #128 ; 0x80
|
|||
|
|
8002d16: 4252 negs r2, r2
|
|||
|
|
8002d18: 4313 orrs r3, r2
|
|||
|
|
8002d1a: b2da uxtb r2, r3
|
|||
|
|
8002d1c: 4bbe ldr r3, [pc, #760] ; (8003018 <HAL_UART_RxCpltCallback+0x75c>)
|
|||
|
|
8002d1e: 705a strb r2, [r3, #1]
|
|||
|
|
tx[2] = 0x03;
|
|||
|
|
8002d20: 4bbd ldr r3, [pc, #756] ; (8003018 <HAL_UART_RxCpltCallback+0x75c>)
|
|||
|
|
8002d22: 2203 movs r2, #3
|
|||
|
|
8002d24: 709a strb r2, [r3, #2]
|
|||
|
|
strtOut(3);
|
|||
|
|
8002d26: 2003 movs r0, #3
|
|||
|
|
8002d28: f7ff fcd6 bl 80026d8 <strtOut>
|
|||
|
|
break;
|
|||
|
|
8002d2c: e093 b.n 8002e56 <HAL_UART_RxCpltCallback+0x59a>
|
|||
|
|
f.fl = pardata.SENS;
|
|||
|
|
8002d2e: 4bb9 ldr r3, [pc, #740] ; (8003014 <HAL_UART_RxCpltCallback+0x758>)
|
|||
|
|
8002d30: 6a1b ldr r3, [r3, #32]
|
|||
|
|
8002d32: 60bb str r3, [r7, #8]
|
|||
|
|
tx[3] = f.ch[3];
|
|||
|
|
8002d34: 2308 movs r3, #8
|
|||
|
|
8002d36: 18fb adds r3, r7, r3
|
|||
|
|
8002d38: 78da ldrb r2, [r3, #3]
|
|||
|
|
8002d3a: 4bb7 ldr r3, [pc, #732] ; (8003018 <HAL_UART_RxCpltCallback+0x75c>)
|
|||
|
|
8002d3c: 70da strb r2, [r3, #3]
|
|||
|
|
tx[4] = f.ch[2];
|
|||
|
|
8002d3e: 2308 movs r3, #8
|
|||
|
|
8002d40: 18fb adds r3, r7, r3
|
|||
|
|
8002d42: 789a ldrb r2, [r3, #2]
|
|||
|
|
8002d44: 4bb4 ldr r3, [pc, #720] ; (8003018 <HAL_UART_RxCpltCallback+0x75c>)
|
|||
|
|
8002d46: 711a strb r2, [r3, #4]
|
|||
|
|
tx[5] = f.ch[1];
|
|||
|
|
8002d48: 2308 movs r3, #8
|
|||
|
|
8002d4a: 18fb adds r3, r7, r3
|
|||
|
|
8002d4c: 785a ldrb r2, [r3, #1]
|
|||
|
|
8002d4e: 4bb2 ldr r3, [pc, #712] ; (8003018 <HAL_UART_RxCpltCallback+0x75c>)
|
|||
|
|
8002d50: 715a strb r2, [r3, #5]
|
|||
|
|
tx[6] = f.ch[0];
|
|||
|
|
8002d52: 2308 movs r3, #8
|
|||
|
|
8002d54: 18fb adds r3, r7, r3
|
|||
|
|
8002d56: 781a ldrb r2, [r3, #0]
|
|||
|
|
8002d58: 4baf ldr r3, [pc, #700] ; (8003018 <HAL_UART_RxCpltCallback+0x75c>)
|
|||
|
|
8002d5a: 719a strb r2, [r3, #6]
|
|||
|
|
strtOut(3 + tx[2]);
|
|||
|
|
8002d5c: 4bae ldr r3, [pc, #696] ; (8003018 <HAL_UART_RxCpltCallback+0x75c>)
|
|||
|
|
8002d5e: 789b ldrb r3, [r3, #2]
|
|||
|
|
8002d60: b29b uxth r3, r3
|
|||
|
|
8002d62: 3303 adds r3, #3
|
|||
|
|
8002d64: b29b uxth r3, r3
|
|||
|
|
8002d66: 0018 movs r0, r3
|
|||
|
|
8002d68: f7ff fcb6 bl 80026d8 <strtOut>
|
|||
|
|
break;
|
|||
|
|
8002d6c: e073 b.n 8002e56 <HAL_UART_RxCpltCallback+0x59a>
|
|||
|
|
tmp = 1;
|
|||
|
|
8002d6e: 231e movs r3, #30
|
|||
|
|
8002d70: 18fb adds r3, r7, r3
|
|||
|
|
8002d72: 2201 movs r2, #1
|
|||
|
|
8002d74: 701a strb r2, [r3, #0]
|
|||
|
|
tx[0] = iobuf[0];
|
|||
|
|
8002d76: 4ba9 ldr r3, [pc, #676] ; (800301c <HAL_UART_RxCpltCallback+0x760>)
|
|||
|
|
8002d78: 781a ldrb r2, [r3, #0]
|
|||
|
|
8002d7a: 4ba7 ldr r3, [pc, #668] ; (8003018 <HAL_UART_RxCpltCallback+0x75c>)
|
|||
|
|
8002d7c: 701a strb r2, [r3, #0]
|
|||
|
|
tx[1] = iobuf[1];
|
|||
|
|
8002d7e: 4ba7 ldr r3, [pc, #668] ; (800301c <HAL_UART_RxCpltCallback+0x760>)
|
|||
|
|
8002d80: 785a ldrb r2, [r3, #1]
|
|||
|
|
8002d82: 4ba5 ldr r3, [pc, #660] ; (8003018 <HAL_UART_RxCpltCallback+0x75c>)
|
|||
|
|
8002d84: 705a strb r2, [r3, #1]
|
|||
|
|
tx[2] = regs.ch[0] << 2;
|
|||
|
|
8002d86: 230c movs r3, #12
|
|||
|
|
8002d88: 18fb adds r3, r7, r3
|
|||
|
|
8002d8a: 781b ldrb r3, [r3, #0]
|
|||
|
|
8002d8c: 009b lsls r3, r3, #2
|
|||
|
|
8002d8e: b2da uxtb r2, r3
|
|||
|
|
8002d90: 4ba1 ldr r3, [pc, #644] ; (8003018 <HAL_UART_RxCpltCallback+0x75c>)
|
|||
|
|
8002d92: 709a strb r2, [r3, #2]
|
|||
|
|
if(addr.sh == 7006)
|
|||
|
|
8002d94: 2310 movs r3, #16
|
|||
|
|
8002d96: 18fb adds r3, r7, r3
|
|||
|
|
8002d98: 881b ldrh r3, [r3, #0]
|
|||
|
|
8002d9a: 4aa2 ldr r2, [pc, #648] ; (8003024 <HAL_UART_RxCpltCallback+0x768>)
|
|||
|
|
8002d9c: 4293 cmp r3, r2
|
|||
|
|
8002d9e: d10c bne.n 8002dba <HAL_UART_RxCpltCallback+0x4fe>
|
|||
|
|
tmp <<= 1;
|
|||
|
|
8002da0: 231e movs r3, #30
|
|||
|
|
8002da2: 18fa adds r2, r7, r3
|
|||
|
|
8002da4: 231e movs r3, #30
|
|||
|
|
8002da6: 18fb adds r3, r7, r3
|
|||
|
|
8002da8: 781b ldrb r3, [r3, #0]
|
|||
|
|
8002daa: 18db adds r3, r3, r3
|
|||
|
|
8002dac: 7013 strb r3, [r2, #0]
|
|||
|
|
tx[2] >>= 1;
|
|||
|
|
8002dae: 4b9a ldr r3, [pc, #616] ; (8003018 <HAL_UART_RxCpltCallback+0x75c>)
|
|||
|
|
8002db0: 789b ldrb r3, [r3, #2]
|
|||
|
|
8002db2: 085b lsrs r3, r3, #1
|
|||
|
|
8002db4: b2da uxtb r2, r3
|
|||
|
|
8002db6: 4b98 ldr r3, [pc, #608] ; (8003018 <HAL_UART_RxCpltCallback+0x75c>)
|
|||
|
|
8002db8: 709a strb r2, [r3, #2]
|
|||
|
|
if(regs.ch[0] > tmp)
|
|||
|
|
8002dba: 230c movs r3, #12
|
|||
|
|
8002dbc: 18fb adds r3, r7, r3
|
|||
|
|
8002dbe: 781b ldrb r3, [r3, #0]
|
|||
|
|
8002dc0: 221e movs r2, #30
|
|||
|
|
8002dc2: 18ba adds r2, r7, r2
|
|||
|
|
8002dc4: 7812 ldrb r2, [r2, #0]
|
|||
|
|
8002dc6: 429a cmp r2, r3
|
|||
|
|
8002dc8: d212 bcs.n 8002df0 <HAL_UART_RxCpltCallback+0x534>
|
|||
|
|
tx[0] = iobuf[0];
|
|||
|
|
8002dca: 4b94 ldr r3, [pc, #592] ; (800301c <HAL_UART_RxCpltCallback+0x760>)
|
|||
|
|
8002dcc: 781a ldrb r2, [r3, #0]
|
|||
|
|
8002dce: 4b92 ldr r3, [pc, #584] ; (8003018 <HAL_UART_RxCpltCallback+0x75c>)
|
|||
|
|
8002dd0: 701a strb r2, [r3, #0]
|
|||
|
|
tx[1] = (iobuf[1] | 0x80);
|
|||
|
|
8002dd2: 4b92 ldr r3, [pc, #584] ; (800301c <HAL_UART_RxCpltCallback+0x760>)
|
|||
|
|
8002dd4: 785b ldrb r3, [r3, #1]
|
|||
|
|
8002dd6: 2280 movs r2, #128 ; 0x80
|
|||
|
|
8002dd8: 4252 negs r2, r2
|
|||
|
|
8002dda: 4313 orrs r3, r2
|
|||
|
|
8002ddc: b2da uxtb r2, r3
|
|||
|
|
8002dde: 4b8e ldr r3, [pc, #568] ; (8003018 <HAL_UART_RxCpltCallback+0x75c>)
|
|||
|
|
8002de0: 705a strb r2, [r3, #1]
|
|||
|
|
tx[2] = 0x03;
|
|||
|
|
8002de2: 4b8d ldr r3, [pc, #564] ; (8003018 <HAL_UART_RxCpltCallback+0x75c>)
|
|||
|
|
8002de4: 2203 movs r2, #3
|
|||
|
|
8002de6: 709a strb r2, [r3, #2]
|
|||
|
|
strtOut(3);
|
|||
|
|
8002de8: 2003 movs r0, #3
|
|||
|
|
8002dea: f7ff fc75 bl 80026d8 <strtOut>
|
|||
|
|
break;
|
|||
|
|
8002dee: e032 b.n 8002e56 <HAL_UART_RxCpltCallback+0x59a>
|
|||
|
|
f.fl = pardata.ACCEL;
|
|||
|
|
8002df0: 4b88 ldr r3, [pc, #544] ; (8003014 <HAL_UART_RxCpltCallback+0x758>)
|
|||
|
|
8002df2: 6a5b ldr r3, [r3, #36] ; 0x24
|
|||
|
|
8002df4: 60bb str r3, [r7, #8]
|
|||
|
|
tx[3] = f.ch[3];
|
|||
|
|
8002df6: 2308 movs r3, #8
|
|||
|
|
8002df8: 18fb adds r3, r7, r3
|
|||
|
|
8002dfa: 78da ldrb r2, [r3, #3]
|
|||
|
|
8002dfc: 4b86 ldr r3, [pc, #536] ; (8003018 <HAL_UART_RxCpltCallback+0x75c>)
|
|||
|
|
8002dfe: 70da strb r2, [r3, #3]
|
|||
|
|
tx[4] = f.ch[2];
|
|||
|
|
8002e00: 2308 movs r3, #8
|
|||
|
|
8002e02: 18fb adds r3, r7, r3
|
|||
|
|
8002e04: 789a ldrb r2, [r3, #2]
|
|||
|
|
8002e06: 4b84 ldr r3, [pc, #528] ; (8003018 <HAL_UART_RxCpltCallback+0x75c>)
|
|||
|
|
8002e08: 711a strb r2, [r3, #4]
|
|||
|
|
tx[5] = f.ch[1];
|
|||
|
|
8002e0a: 2308 movs r3, #8
|
|||
|
|
8002e0c: 18fb adds r3, r7, r3
|
|||
|
|
8002e0e: 785a ldrb r2, [r3, #1]
|
|||
|
|
8002e10: 4b81 ldr r3, [pc, #516] ; (8003018 <HAL_UART_RxCpltCallback+0x75c>)
|
|||
|
|
8002e12: 715a strb r2, [r3, #5]
|
|||
|
|
tx[6] = f.ch[0];
|
|||
|
|
8002e14: 2308 movs r3, #8
|
|||
|
|
8002e16: 18fb adds r3, r7, r3
|
|||
|
|
8002e18: 781a ldrb r2, [r3, #0]
|
|||
|
|
8002e1a: 4b7f ldr r3, [pc, #508] ; (8003018 <HAL_UART_RxCpltCallback+0x75c>)
|
|||
|
|
8002e1c: 719a strb r2, [r3, #6]
|
|||
|
|
strtOut(3 + tx[2]);
|
|||
|
|
8002e1e: 4b7e ldr r3, [pc, #504] ; (8003018 <HAL_UART_RxCpltCallback+0x75c>)
|
|||
|
|
8002e20: 789b ldrb r3, [r3, #2]
|
|||
|
|
8002e22: b29b uxth r3, r3
|
|||
|
|
8002e24: 3303 adds r3, #3
|
|||
|
|
8002e26: b29b uxth r3, r3
|
|||
|
|
8002e28: 0018 movs r0, r3
|
|||
|
|
8002e2a: f7ff fc55 bl 80026d8 <strtOut>
|
|||
|
|
break;
|
|||
|
|
8002e2e: e012 b.n 8002e56 <HAL_UART_RxCpltCallback+0x59a>
|
|||
|
|
tx[0] = iobuf[0];
|
|||
|
|
8002e30: 4b7a ldr r3, [pc, #488] ; (800301c <HAL_UART_RxCpltCallback+0x760>)
|
|||
|
|
8002e32: 781a ldrb r2, [r3, #0]
|
|||
|
|
8002e34: 4b78 ldr r3, [pc, #480] ; (8003018 <HAL_UART_RxCpltCallback+0x75c>)
|
|||
|
|
8002e36: 701a strb r2, [r3, #0]
|
|||
|
|
tx[1] = (iobuf[1] | 0x80);
|
|||
|
|
8002e38: 4b78 ldr r3, [pc, #480] ; (800301c <HAL_UART_RxCpltCallback+0x760>)
|
|||
|
|
8002e3a: 785b ldrb r3, [r3, #1]
|
|||
|
|
8002e3c: 2280 movs r2, #128 ; 0x80
|
|||
|
|
8002e3e: 4252 negs r2, r2
|
|||
|
|
8002e40: 4313 orrs r3, r2
|
|||
|
|
8002e42: b2da uxtb r2, r3
|
|||
|
|
8002e44: 4b74 ldr r3, [pc, #464] ; (8003018 <HAL_UART_RxCpltCallback+0x75c>)
|
|||
|
|
8002e46: 705a strb r2, [r3, #1]
|
|||
|
|
tx[2] = 0x02;
|
|||
|
|
8002e48: 4b73 ldr r3, [pc, #460] ; (8003018 <HAL_UART_RxCpltCallback+0x75c>)
|
|||
|
|
8002e4a: 2202 movs r2, #2
|
|||
|
|
8002e4c: 709a strb r2, [r3, #2]
|
|||
|
|
strtOut(3);
|
|||
|
|
8002e4e: 2003 movs r0, #3
|
|||
|
|
8002e50: f7ff fc42 bl 80026d8 <strtOut>
|
|||
|
|
break;
|
|||
|
|
8002e54: 46c0 nop ; (mov r8, r8)
|
|||
|
|
break;
|
|||
|
|
8002e56: f000 fefe bl 8003c56 <HAL_UART_RxCpltCallback+0x139a>
|
|||
|
|
addr.ch[1] = iobuf[2];
|
|||
|
|
8002e5a: 4b70 ldr r3, [pc, #448] ; (800301c <HAL_UART_RxCpltCallback+0x760>)
|
|||
|
|
8002e5c: 789a ldrb r2, [r3, #2]
|
|||
|
|
8002e5e: 2310 movs r3, #16
|
|||
|
|
8002e60: 18fb adds r3, r7, r3
|
|||
|
|
8002e62: 705a strb r2, [r3, #1]
|
|||
|
|
addr.ch[0] = iobuf[3];
|
|||
|
|
8002e64: 4b6d ldr r3, [pc, #436] ; (800301c <HAL_UART_RxCpltCallback+0x760>)
|
|||
|
|
8002e66: 78da ldrb r2, [r3, #3]
|
|||
|
|
8002e68: 2310 movs r3, #16
|
|||
|
|
8002e6a: 18fb adds r3, r7, r3
|
|||
|
|
8002e6c: 701a strb r2, [r3, #0]
|
|||
|
|
regs.ch[1] = iobuf[4];
|
|||
|
|
8002e6e: 4b6b ldr r3, [pc, #428] ; (800301c <HAL_UART_RxCpltCallback+0x760>)
|
|||
|
|
8002e70: 791a ldrb r2, [r3, #4]
|
|||
|
|
8002e72: 230c movs r3, #12
|
|||
|
|
8002e74: 18fb adds r3, r7, r3
|
|||
|
|
8002e76: 705a strb r2, [r3, #1]
|
|||
|
|
regs.ch[0] = iobuf[5];
|
|||
|
|
8002e78: 4b68 ldr r3, [pc, #416] ; (800301c <HAL_UART_RxCpltCallback+0x760>)
|
|||
|
|
8002e7a: 795a ldrb r2, [r3, #5]
|
|||
|
|
8002e7c: 230c movs r3, #12
|
|||
|
|
8002e7e: 18fb adds r3, r7, r3
|
|||
|
|
8002e80: 701a strb r2, [r3, #0]
|
|||
|
|
switch(addr.sh) // Запись pardata
|
|||
|
|
8002e82: 2310 movs r3, #16
|
|||
|
|
8002e84: 18fb adds r3, r7, r3
|
|||
|
|
8002e86: 881b ldrh r3, [r3, #0]
|
|||
|
|
8002e88: 4a67 ldr r2, [pc, #412] ; (8003028 <HAL_UART_RxCpltCallback+0x76c>)
|
|||
|
|
8002e8a: 4293 cmp r3, r2
|
|||
|
|
8002e8c: d101 bne.n 8002e92 <HAL_UART_RxCpltCallback+0x5d6>
|
|||
|
|
8002e8e: f000 fba4 bl 80035da <HAL_UART_RxCpltCallback+0xd1e>
|
|||
|
|
8002e92: 4a65 ldr r2, [pc, #404] ; (8003028 <HAL_UART_RxCpltCallback+0x76c>)
|
|||
|
|
8002e94: 4293 cmp r3, r2
|
|||
|
|
8002e96: dc13 bgt.n 8002ec0 <HAL_UART_RxCpltCallback+0x604>
|
|||
|
|
8002e98: 4a64 ldr r2, [pc, #400] ; (800302c <HAL_UART_RxCpltCallback+0x770>)
|
|||
|
|
8002e9a: 4293 cmp r3, r2
|
|||
|
|
8002e9c: dc08 bgt.n 8002eb0 <HAL_UART_RxCpltCallback+0x5f4>
|
|||
|
|
8002e9e: 4a64 ldr r2, [pc, #400] ; (8003030 <HAL_UART_RxCpltCallback+0x774>)
|
|||
|
|
8002ea0: 4293 cmp r3, r2
|
|||
|
|
8002ea2: db00 blt.n 8002ea6 <HAL_UART_RxCpltCallback+0x5ea>
|
|||
|
|
8002ea4: e0d8 b.n 8003058 <HAL_UART_RxCpltCallback+0x79c>
|
|||
|
|
8002ea6: 4a63 ldr r2, [pc, #396] ; (8003034 <HAL_UART_RxCpltCallback+0x778>)
|
|||
|
|
8002ea8: 4293 cmp r3, r2
|
|||
|
|
8002eaa: d029 beq.n 8002f00 <HAL_UART_RxCpltCallback+0x644>
|
|||
|
|
8002eac: f000 feb4 bl 8003c18 <HAL_UART_RxCpltCallback+0x135c>
|
|||
|
|
8002eb0: 4a61 ldr r2, [pc, #388] ; (8003038 <HAL_UART_RxCpltCallback+0x77c>)
|
|||
|
|
8002eb2: 4694 mov ip, r2
|
|||
|
|
8002eb4: 4463 add r3, ip
|
|||
|
|
8002eb6: 2b09 cmp r3, #9
|
|||
|
|
8002eb8: d901 bls.n 8002ebe <HAL_UART_RxCpltCallback+0x602>
|
|||
|
|
8002eba: f000 fead bl 8003c18 <HAL_UART_RxCpltCallback+0x135c>
|
|||
|
|
8002ebe: e2ac b.n 800341a <HAL_UART_RxCpltCallback+0xb5e>
|
|||
|
|
8002ec0: 4a5e ldr r2, [pc, #376] ; (800303c <HAL_UART_RxCpltCallback+0x780>)
|
|||
|
|
8002ec2: 4293 cmp r3, r2
|
|||
|
|
8002ec4: d101 bne.n 8002eca <HAL_UART_RxCpltCallback+0x60e>
|
|||
|
|
8002ec6: f000 fb88 bl 80035da <HAL_UART_RxCpltCallback+0xd1e>
|
|||
|
|
8002eca: 4a5c ldr r2, [pc, #368] ; (800303c <HAL_UART_RxCpltCallback+0x780>)
|
|||
|
|
8002ecc: 4293 cmp r3, r2
|
|||
|
|
8002ece: dc0b bgt.n 8002ee8 <HAL_UART_RxCpltCallback+0x62c>
|
|||
|
|
8002ed0: 4a53 ldr r2, [pc, #332] ; (8003020 <HAL_UART_RxCpltCallback+0x764>)
|
|||
|
|
8002ed2: 4293 cmp r3, r2
|
|||
|
|
8002ed4: d101 bne.n 8002eda <HAL_UART_RxCpltCallback+0x61e>
|
|||
|
|
8002ed6: f000 fd03 bl 80038e0 <HAL_UART_RxCpltCallback+0x1024>
|
|||
|
|
8002eda: 4a52 ldr r2, [pc, #328] ; (8003024 <HAL_UART_RxCpltCallback+0x768>)
|
|||
|
|
8002edc: 4293 cmp r3, r2
|
|||
|
|
8002ede: d101 bne.n 8002ee4 <HAL_UART_RxCpltCallback+0x628>
|
|||
|
|
8002ee0: f000 fddc bl 8003a9c <HAL_UART_RxCpltCallback+0x11e0>
|
|||
|
|
8002ee4: f000 fe98 bl 8003c18 <HAL_UART_RxCpltCallback+0x135c>
|
|||
|
|
8002ee8: 4a55 ldr r2, [pc, #340] ; (8003040 <HAL_UART_RxCpltCallback+0x784>)
|
|||
|
|
8002eea: 4293 cmp r3, r2
|
|||
|
|
8002eec: d101 bne.n 8002ef2 <HAL_UART_RxCpltCallback+0x636>
|
|||
|
|
8002eee: f000 fcf7 bl 80038e0 <HAL_UART_RxCpltCallback+0x1024>
|
|||
|
|
8002ef2: 4a54 ldr r2, [pc, #336] ; (8003044 <HAL_UART_RxCpltCallback+0x788>)
|
|||
|
|
8002ef4: 4293 cmp r3, r2
|
|||
|
|
8002ef6: d101 bne.n 8002efc <HAL_UART_RxCpltCallback+0x640>
|
|||
|
|
8002ef8: f000 fdd0 bl 8003a9c <HAL_UART_RxCpltCallback+0x11e0>
|
|||
|
|
8002efc: f000 fe8c bl 8003c18 <HAL_UART_RxCpltCallback+0x135c>
|
|||
|
|
if((regs.ch[0] > 1) || (iobuf[6] != (regs.ch[0] << 1)))
|
|||
|
|
8002f00: 230c movs r3, #12
|
|||
|
|
8002f02: 18fb adds r3, r7, r3
|
|||
|
|
8002f04: 781b ldrb r3, [r3, #0]
|
|||
|
|
8002f06: 2b01 cmp r3, #1
|
|||
|
|
8002f08: d808 bhi.n 8002f1c <HAL_UART_RxCpltCallback+0x660>
|
|||
|
|
8002f0a: 4b44 ldr r3, [pc, #272] ; (800301c <HAL_UART_RxCpltCallback+0x760>)
|
|||
|
|
8002f0c: 799b ldrb r3, [r3, #6]
|
|||
|
|
8002f0e: 001a movs r2, r3
|
|||
|
|
8002f10: 230c movs r3, #12
|
|||
|
|
8002f12: 18fb adds r3, r7, r3
|
|||
|
|
8002f14: 781b ldrb r3, [r3, #0]
|
|||
|
|
8002f16: 005b lsls r3, r3, #1
|
|||
|
|
8002f18: 429a cmp r2, r3
|
|||
|
|
8002f1a: d013 beq.n 8002f44 <HAL_UART_RxCpltCallback+0x688>
|
|||
|
|
tx[0] = iobuf[0];
|
|||
|
|
8002f1c: 4b3f ldr r3, [pc, #252] ; (800301c <HAL_UART_RxCpltCallback+0x760>)
|
|||
|
|
8002f1e: 781a ldrb r2, [r3, #0]
|
|||
|
|
8002f20: 4b3d ldr r3, [pc, #244] ; (8003018 <HAL_UART_RxCpltCallback+0x75c>)
|
|||
|
|
8002f22: 701a strb r2, [r3, #0]
|
|||
|
|
tx[1] = (iobuf[1] | 0x80);
|
|||
|
|
8002f24: 4b3d ldr r3, [pc, #244] ; (800301c <HAL_UART_RxCpltCallback+0x760>)
|
|||
|
|
8002f26: 785b ldrb r3, [r3, #1]
|
|||
|
|
8002f28: 2280 movs r2, #128 ; 0x80
|
|||
|
|
8002f2a: 4252 negs r2, r2
|
|||
|
|
8002f2c: 4313 orrs r3, r2
|
|||
|
|
8002f2e: b2da uxtb r2, r3
|
|||
|
|
8002f30: 4b39 ldr r3, [pc, #228] ; (8003018 <HAL_UART_RxCpltCallback+0x75c>)
|
|||
|
|
8002f32: 705a strb r2, [r3, #1]
|
|||
|
|
tx[2] = 0x03;
|
|||
|
|
8002f34: 4b38 ldr r3, [pc, #224] ; (8003018 <HAL_UART_RxCpltCallback+0x75c>)
|
|||
|
|
8002f36: 2203 movs r2, #3
|
|||
|
|
8002f38: 709a strb r2, [r3, #2]
|
|||
|
|
strtOut(3);
|
|||
|
|
8002f3a: 2003 movs r0, #3
|
|||
|
|
8002f3c: f7ff fbcc bl 80026d8 <strtOut>
|
|||
|
|
break;
|
|||
|
|
8002f40: f000 fe7d bl 8003c3e <HAL_UART_RxCpltCallback+0x1382>
|
|||
|
|
j = 8 + iobuf[6];
|
|||
|
|
8002f44: 4b35 ldr r3, [pc, #212] ; (800301c <HAL_UART_RxCpltCallback+0x760>)
|
|||
|
|
8002f46: 799a ldrb r2, [r3, #6]
|
|||
|
|
8002f48: 231f movs r3, #31
|
|||
|
|
8002f4a: 18fb adds r3, r7, r3
|
|||
|
|
8002f4c: 3208 adds r2, #8
|
|||
|
|
8002f4e: 701a strb r2, [r3, #0]
|
|||
|
|
if(iolen > j)
|
|||
|
|
8002f50: 4b3d ldr r3, [pc, #244] ; (8003048 <HAL_UART_RxCpltCallback+0x78c>)
|
|||
|
|
8002f52: 781b ldrb r3, [r3, #0]
|
|||
|
|
8002f54: 221f movs r2, #31
|
|||
|
|
8002f56: 18ba adds r2, r7, r2
|
|||
|
|
8002f58: 7812 ldrb r2, [r2, #0]
|
|||
|
|
8002f5a: 429a cmp r2, r3
|
|||
|
|
8002f5c: d301 bcc.n 8002f62 <HAL_UART_RxCpltCallback+0x6a6>
|
|||
|
|
8002f5e: f000 fe6e bl 8003c3e <HAL_UART_RxCpltCallback+0x1382>
|
|||
|
|
iolen = 0;
|
|||
|
|
8002f62: 4b39 ldr r3, [pc, #228] ; (8003048 <HAL_UART_RxCpltCallback+0x78c>)
|
|||
|
|
8002f64: 2200 movs r2, #0
|
|||
|
|
8002f66: 701a strb r2, [r3, #0]
|
|||
|
|
crc.ch[0] = iobuf[j - 1];
|
|||
|
|
8002f68: 231f movs r3, #31
|
|||
|
|
8002f6a: 18fb adds r3, r7, r3
|
|||
|
|
8002f6c: 781b ldrb r3, [r3, #0]
|
|||
|
|
8002f6e: 3b01 subs r3, #1
|
|||
|
|
8002f70: 4a2a ldr r2, [pc, #168] ; (800301c <HAL_UART_RxCpltCallback+0x760>)
|
|||
|
|
8002f72: 5cd2 ldrb r2, [r2, r3]
|
|||
|
|
8002f74: 2314 movs r3, #20
|
|||
|
|
8002f76: 18fb adds r3, r7, r3
|
|||
|
|
8002f78: 701a strb r2, [r3, #0]
|
|||
|
|
crc.ch[1] = iobuf[j];
|
|||
|
|
8002f7a: 231f movs r3, #31
|
|||
|
|
8002f7c: 18fb adds r3, r7, r3
|
|||
|
|
8002f7e: 781b ldrb r3, [r3, #0]
|
|||
|
|
8002f80: 4a26 ldr r2, [pc, #152] ; (800301c <HAL_UART_RxCpltCallback+0x760>)
|
|||
|
|
8002f82: 5cd2 ldrb r2, [r2, r3]
|
|||
|
|
8002f84: 2314 movs r3, #20
|
|||
|
|
8002f86: 18fb adds r3, r7, r3
|
|||
|
|
8002f88: 705a strb r2, [r3, #1]
|
|||
|
|
if(crc.sh == Crc16(j - 1))
|
|||
|
|
8002f8a: 2314 movs r3, #20
|
|||
|
|
8002f8c: 18fb adds r3, r7, r3
|
|||
|
|
8002f8e: 881c ldrh r4, [r3, #0]
|
|||
|
|
8002f90: 231f movs r3, #31
|
|||
|
|
8002f92: 18fb adds r3, r7, r3
|
|||
|
|
8002f94: 781b ldrb r3, [r3, #0]
|
|||
|
|
8002f96: b29b uxth r3, r3
|
|||
|
|
8002f98: 3b01 subs r3, #1
|
|||
|
|
8002f9a: b29b uxth r3, r3
|
|||
|
|
8002f9c: 0018 movs r0, r3
|
|||
|
|
8002f9e: f7ff fbe7 bl 8002770 <Crc16>
|
|||
|
|
8002fa2: 0003 movs r3, r0
|
|||
|
|
8002fa4: 429c cmp r4, r3
|
|||
|
|
8002fa6: d001 beq.n 8002fac <HAL_UART_RxCpltCallback+0x6f0>
|
|||
|
|
8002fa8: f000 fe49 bl 8003c3e <HAL_UART_RxCpltCallback+0x1382>
|
|||
|
|
if(!iobuf[8])
|
|||
|
|
8002fac: 4b1b ldr r3, [pc, #108] ; (800301c <HAL_UART_RxCpltCallback+0x760>)
|
|||
|
|
8002fae: 7a1b ldrb r3, [r3, #8]
|
|||
|
|
8002fb0: 2b00 cmp r3, #0
|
|||
|
|
8002fb2: d106 bne.n 8002fc2 <HAL_UART_RxCpltCallback+0x706>
|
|||
|
|
faseClbr = 0;
|
|||
|
|
8002fb4: 4b25 ldr r3, [pc, #148] ; (800304c <HAL_UART_RxCpltCallback+0x790>)
|
|||
|
|
8002fb6: 2200 movs r2, #0
|
|||
|
|
8002fb8: 601a str r2, [r3, #0]
|
|||
|
|
clbr = false;
|
|||
|
|
8002fba: 4b25 ldr r3, [pc, #148] ; (8003050 <HAL_UART_RxCpltCallback+0x794>)
|
|||
|
|
8002fbc: 2200 movs r2, #0
|
|||
|
|
8002fbe: 701a strb r2, [r3, #0]
|
|||
|
|
8002fc0: e008 b.n 8002fd4 <HAL_UART_RxCpltCallback+0x718>
|
|||
|
|
needClbr = true;
|
|||
|
|
8002fc2: 4b24 ldr r3, [pc, #144] ; (8003054 <HAL_UART_RxCpltCallback+0x798>)
|
|||
|
|
8002fc4: 2201 movs r2, #1
|
|||
|
|
8002fc6: 701a strb r2, [r3, #0]
|
|||
|
|
faseClbr = iobuf[8] - 1;
|
|||
|
|
8002fc8: 4b14 ldr r3, [pc, #80] ; (800301c <HAL_UART_RxCpltCallback+0x760>)
|
|||
|
|
8002fca: 7a1b ldrb r3, [r3, #8]
|
|||
|
|
8002fcc: 3b01 subs r3, #1
|
|||
|
|
8002fce: 001a movs r2, r3
|
|||
|
|
8002fd0: 4b1e ldr r3, [pc, #120] ; (800304c <HAL_UART_RxCpltCallback+0x790>)
|
|||
|
|
8002fd2: 601a str r2, [r3, #0]
|
|||
|
|
for(j = 0; j < 6; j++) {
|
|||
|
|
8002fd4: 231f movs r3, #31
|
|||
|
|
8002fd6: 18fb adds r3, r7, r3
|
|||
|
|
8002fd8: 2200 movs r2, #0
|
|||
|
|
8002fda: 701a strb r2, [r3, #0]
|
|||
|
|
8002fdc: e010 b.n 8003000 <HAL_UART_RxCpltCallback+0x744>
|
|||
|
|
tx[j] = iobuf[j];
|
|||
|
|
8002fde: 231f movs r3, #31
|
|||
|
|
8002fe0: 18fb adds r3, r7, r3
|
|||
|
|
8002fe2: 781b ldrb r3, [r3, #0]
|
|||
|
|
8002fe4: 221f movs r2, #31
|
|||
|
|
8002fe6: 18ba adds r2, r7, r2
|
|||
|
|
8002fe8: 7812 ldrb r2, [r2, #0]
|
|||
|
|
8002fea: 490c ldr r1, [pc, #48] ; (800301c <HAL_UART_RxCpltCallback+0x760>)
|
|||
|
|
8002fec: 5c89 ldrb r1, [r1, r2]
|
|||
|
|
8002fee: 4a0a ldr r2, [pc, #40] ; (8003018 <HAL_UART_RxCpltCallback+0x75c>)
|
|||
|
|
8002ff0: 54d1 strb r1, [r2, r3]
|
|||
|
|
for(j = 0; j < 6; j++) {
|
|||
|
|
8002ff2: 231f movs r3, #31
|
|||
|
|
8002ff4: 18fb adds r3, r7, r3
|
|||
|
|
8002ff6: 781a ldrb r2, [r3, #0]
|
|||
|
|
8002ff8: 231f movs r3, #31
|
|||
|
|
8002ffa: 18fb adds r3, r7, r3
|
|||
|
|
8002ffc: 3201 adds r2, #1
|
|||
|
|
8002ffe: 701a strb r2, [r3, #0]
|
|||
|
|
8003000: 231f movs r3, #31
|
|||
|
|
8003002: 18fb adds r3, r7, r3
|
|||
|
|
8003004: 781b ldrb r3, [r3, #0]
|
|||
|
|
8003006: 2b05 cmp r3, #5
|
|||
|
|
8003008: d9e9 bls.n 8002fde <HAL_UART_RxCpltCallback+0x722>
|
|||
|
|
strtOut(6);
|
|||
|
|
800300a: 2006 movs r0, #6
|
|||
|
|
800300c: f7ff fb64 bl 80026d8 <strtOut>
|
|||
|
|
break;
|
|||
|
|
8003010: f000 fe15 bl 8003c3e <HAL_UART_RxCpltCallback+0x1382>
|
|||
|
|
8003014: 20000098 .word 0x20000098
|
|||
|
|
8003018: 20000188 .word 0x20000188
|
|||
|
|
800301c: 2000028c .word 0x2000028c
|
|||
|
|
8003020: 00001b5c .word 0x00001b5c
|
|||
|
|
8003024: 00001b5e .word 0x00001b5e
|
|||
|
|
8003028: 00001b5a .word 0x00001b5a
|
|||
|
|
800302c: 00000bcf .word 0x00000bcf
|
|||
|
|
8003030: 00000bb9 .word 0x00000bb9
|
|||
|
|
8003034: 00000bb8 .word 0x00000bb8
|
|||
|
|
8003038: ffffec77 .word 0xffffec77
|
|||
|
|
800303c: 00001d4d .word 0x00001d4d
|
|||
|
|
8003040: 00001d4e .word 0x00001d4e
|
|||
|
|
8003044: 00001d4f .word 0x00001d4f
|
|||
|
|
8003048: 20000035 .word 0x20000035
|
|||
|
|
800304c: 20000030 .word 0x20000030
|
|||
|
|
8003050: 20000034 .word 0x20000034
|
|||
|
|
8003054: 2000002e .word 0x2000002e
|
|||
|
|
if((regs.ch[0] > 1) || (iobuf[6] != (regs.ch[0] << 1)))
|
|||
|
|
8003058: 230c movs r3, #12
|
|||
|
|
800305a: 18fb adds r3, r7, r3
|
|||
|
|
800305c: 781b ldrb r3, [r3, #0]
|
|||
|
|
800305e: 2b01 cmp r3, #1
|
|||
|
|
8003060: d808 bhi.n 8003074 <HAL_UART_RxCpltCallback+0x7b8>
|
|||
|
|
8003062: 4bd7 ldr r3, [pc, #860] ; (80033c0 <HAL_UART_RxCpltCallback+0xb04>)
|
|||
|
|
8003064: 799b ldrb r3, [r3, #6]
|
|||
|
|
8003066: 001a movs r2, r3
|
|||
|
|
8003068: 230c movs r3, #12
|
|||
|
|
800306a: 18fb adds r3, r7, r3
|
|||
|
|
800306c: 781b ldrb r3, [r3, #0]
|
|||
|
|
800306e: 005b lsls r3, r3, #1
|
|||
|
|
8003070: 429a cmp r2, r3
|
|||
|
|
8003072: d013 beq.n 800309c <HAL_UART_RxCpltCallback+0x7e0>
|
|||
|
|
tx[0] = iobuf[0];
|
|||
|
|
8003074: 4bd2 ldr r3, [pc, #840] ; (80033c0 <HAL_UART_RxCpltCallback+0xb04>)
|
|||
|
|
8003076: 781a ldrb r2, [r3, #0]
|
|||
|
|
8003078: 4bd2 ldr r3, [pc, #840] ; (80033c4 <HAL_UART_RxCpltCallback+0xb08>)
|
|||
|
|
800307a: 701a strb r2, [r3, #0]
|
|||
|
|
tx[1] = (iobuf[1] | 0x80);
|
|||
|
|
800307c: 4bd0 ldr r3, [pc, #832] ; (80033c0 <HAL_UART_RxCpltCallback+0xb04>)
|
|||
|
|
800307e: 785b ldrb r3, [r3, #1]
|
|||
|
|
8003080: 2280 movs r2, #128 ; 0x80
|
|||
|
|
8003082: 4252 negs r2, r2
|
|||
|
|
8003084: 4313 orrs r3, r2
|
|||
|
|
8003086: b2da uxtb r2, r3
|
|||
|
|
8003088: 4bce ldr r3, [pc, #824] ; (80033c4 <HAL_UART_RxCpltCallback+0xb08>)
|
|||
|
|
800308a: 705a strb r2, [r3, #1]
|
|||
|
|
tx[2] = 0x03;
|
|||
|
|
800308c: 4bcd ldr r3, [pc, #820] ; (80033c4 <HAL_UART_RxCpltCallback+0xb08>)
|
|||
|
|
800308e: 2203 movs r2, #3
|
|||
|
|
8003090: 709a strb r2, [r3, #2]
|
|||
|
|
strtOut(3);
|
|||
|
|
8003092: 2003 movs r0, #3
|
|||
|
|
8003094: f7ff fb20 bl 80026d8 <strtOut>
|
|||
|
|
break;
|
|||
|
|
8003098: f000 fdd3 bl 8003c42 <HAL_UART_RxCpltCallback+0x1386>
|
|||
|
|
j = 8 + iobuf[6];
|
|||
|
|
800309c: 4bc8 ldr r3, [pc, #800] ; (80033c0 <HAL_UART_RxCpltCallback+0xb04>)
|
|||
|
|
800309e: 799a ldrb r2, [r3, #6]
|
|||
|
|
80030a0: 231f movs r3, #31
|
|||
|
|
80030a2: 18fb adds r3, r7, r3
|
|||
|
|
80030a4: 3208 adds r2, #8
|
|||
|
|
80030a6: 701a strb r2, [r3, #0]
|
|||
|
|
if(iolen > j)
|
|||
|
|
80030a8: 4bc7 ldr r3, [pc, #796] ; (80033c8 <HAL_UART_RxCpltCallback+0xb0c>)
|
|||
|
|
80030aa: 781b ldrb r3, [r3, #0]
|
|||
|
|
80030ac: 221f movs r2, #31
|
|||
|
|
80030ae: 18ba adds r2, r7, r2
|
|||
|
|
80030b0: 7812 ldrb r2, [r2, #0]
|
|||
|
|
80030b2: 429a cmp r2, r3
|
|||
|
|
80030b4: d301 bcc.n 80030ba <HAL_UART_RxCpltCallback+0x7fe>
|
|||
|
|
80030b6: f000 fdc4 bl 8003c42 <HAL_UART_RxCpltCallback+0x1386>
|
|||
|
|
iolen = 0;
|
|||
|
|
80030ba: 4bc3 ldr r3, [pc, #780] ; (80033c8 <HAL_UART_RxCpltCallback+0xb0c>)
|
|||
|
|
80030bc: 2200 movs r2, #0
|
|||
|
|
80030be: 701a strb r2, [r3, #0]
|
|||
|
|
crc.ch[0] = iobuf[j - 1];
|
|||
|
|
80030c0: 231f movs r3, #31
|
|||
|
|
80030c2: 18fb adds r3, r7, r3
|
|||
|
|
80030c4: 781b ldrb r3, [r3, #0]
|
|||
|
|
80030c6: 3b01 subs r3, #1
|
|||
|
|
80030c8: 4abd ldr r2, [pc, #756] ; (80033c0 <HAL_UART_RxCpltCallback+0xb04>)
|
|||
|
|
80030ca: 5cd2 ldrb r2, [r2, r3]
|
|||
|
|
80030cc: 2314 movs r3, #20
|
|||
|
|
80030ce: 18fb adds r3, r7, r3
|
|||
|
|
80030d0: 701a strb r2, [r3, #0]
|
|||
|
|
crc.ch[1] = iobuf[j];
|
|||
|
|
80030d2: 231f movs r3, #31
|
|||
|
|
80030d4: 18fb adds r3, r7, r3
|
|||
|
|
80030d6: 781b ldrb r3, [r3, #0]
|
|||
|
|
80030d8: 4ab9 ldr r2, [pc, #740] ; (80033c0 <HAL_UART_RxCpltCallback+0xb04>)
|
|||
|
|
80030da: 5cd2 ldrb r2, [r2, r3]
|
|||
|
|
80030dc: 2314 movs r3, #20
|
|||
|
|
80030de: 18fb adds r3, r7, r3
|
|||
|
|
80030e0: 705a strb r2, [r3, #1]
|
|||
|
|
if(crc.sh == Crc16(j - 1))
|
|||
|
|
80030e2: 2314 movs r3, #20
|
|||
|
|
80030e4: 18fb adds r3, r7, r3
|
|||
|
|
80030e6: 881c ldrh r4, [r3, #0]
|
|||
|
|
80030e8: 231f movs r3, #31
|
|||
|
|
80030ea: 18fb adds r3, r7, r3
|
|||
|
|
80030ec: 781b ldrb r3, [r3, #0]
|
|||
|
|
80030ee: b29b uxth r3, r3
|
|||
|
|
80030f0: 3b01 subs r3, #1
|
|||
|
|
80030f2: b29b uxth r3, r3
|
|||
|
|
80030f4: 0018 movs r0, r3
|
|||
|
|
80030f6: f7ff fb3b bl 8002770 <Crc16>
|
|||
|
|
80030fa: 0003 movs r3, r0
|
|||
|
|
80030fc: 429c cmp r4, r3
|
|||
|
|
80030fe: d001 beq.n 8003104 <HAL_UART_RxCpltCallback+0x848>
|
|||
|
|
8003100: f000 fd9f bl 8003c42 <HAL_UART_RxCpltCallback+0x1386>
|
|||
|
|
if(clbr)
|
|||
|
|
8003104: 4bb1 ldr r3, [pc, #708] ; (80033cc <HAL_UART_RxCpltCallback+0xb10>)
|
|||
|
|
8003106: 781b ldrb r3, [r3, #0]
|
|||
|
|
8003108: b2db uxtb r3, r3
|
|||
|
|
800310a: 2b00 cmp r3, #0
|
|||
|
|
800310c: d100 bne.n 8003110 <HAL_UART_RxCpltCallback+0x854>
|
|||
|
|
800310e: e152 b.n 80033b6 <HAL_UART_RxCpltCallback+0xafa>
|
|||
|
|
switch(iobuf[8])
|
|||
|
|
8003110: 4bab ldr r3, [pc, #684] ; (80033c0 <HAL_UART_RxCpltCallback+0xb04>)
|
|||
|
|
8003112: 7a1b ldrb r3, [r3, #8]
|
|||
|
|
8003114: 2b64 cmp r3, #100 ; 0x64
|
|||
|
|
8003116: d100 bne.n 800311a <HAL_UART_RxCpltCallback+0x85e>
|
|||
|
|
8003118: e0d9 b.n 80032ce <HAL_UART_RxCpltCallback+0xa12>
|
|||
|
|
800311a: dc05 bgt.n 8003128 <HAL_UART_RxCpltCallback+0x86c>
|
|||
|
|
800311c: 2b01 cmp r3, #1
|
|||
|
|
800311e: d00c beq.n 800313a <HAL_UART_RxCpltCallback+0x87e>
|
|||
|
|
8003120: 2b0a cmp r3, #10
|
|||
|
|
8003122: d100 bne.n 8003126 <HAL_UART_RxCpltCallback+0x86a>
|
|||
|
|
8003124: e06c b.n 8003200 <HAL_UART_RxCpltCallback+0x944>
|
|||
|
|
8003126: e142 b.n 80033ae <HAL_UART_RxCpltCallback+0xaf2>
|
|||
|
|
8003128: 2b8a cmp r3, #138 ; 0x8a
|
|||
|
|
800312a: d100 bne.n 800312e <HAL_UART_RxCpltCallback+0x872>
|
|||
|
|
800312c: e09c b.n 8003268 <HAL_UART_RxCpltCallback+0x9ac>
|
|||
|
|
800312e: 2be4 cmp r3, #228 ; 0xe4
|
|||
|
|
8003130: d100 bne.n 8003134 <HAL_UART_RxCpltCallback+0x878>
|
|||
|
|
8003132: e0ff b.n 8003334 <HAL_UART_RxCpltCallback+0xa78>
|
|||
|
|
8003134: 2b81 cmp r3, #129 ; 0x81
|
|||
|
|
8003136: d032 beq.n 800319e <HAL_UART_RxCpltCallback+0x8e2>
|
|||
|
|
8003138: e139 b.n 80033ae <HAL_UART_RxCpltCallback+0xaf2>
|
|||
|
|
if(CorrWord[pardata.IIN][pardata.IKU] < 4095)
|
|||
|
|
800313a: 4ba5 ldr r3, [pc, #660] ; (80033d0 <HAL_UART_RxCpltCallback+0xb14>)
|
|||
|
|
800313c: 88db ldrh r3, [r3, #6]
|
|||
|
|
800313e: b29b uxth r3, r3
|
|||
|
|
8003140: 0019 movs r1, r3
|
|||
|
|
8003142: 4ba3 ldr r3, [pc, #652] ; (80033d0 <HAL_UART_RxCpltCallback+0xb14>)
|
|||
|
|
8003144: 899b ldrh r3, [r3, #12]
|
|||
|
|
8003146: b29b uxth r3, r3
|
|||
|
|
8003148: 0018 movs r0, r3
|
|||
|
|
800314a: 4aa2 ldr r2, [pc, #648] ; (80033d4 <HAL_UART_RxCpltCallback+0xb18>)
|
|||
|
|
800314c: 000b movs r3, r1
|
|||
|
|
800314e: 009b lsls r3, r3, #2
|
|||
|
|
8003150: 185b adds r3, r3, r1
|
|||
|
|
8003152: 009b lsls r3, r3, #2
|
|||
|
|
8003154: 181b adds r3, r3, r0
|
|||
|
|
8003156: 005b lsls r3, r3, #1
|
|||
|
|
8003158: 5a9b ldrh r3, [r3, r2]
|
|||
|
|
800315a: b29b uxth r3, r3
|
|||
|
|
800315c: 4a9e ldr r2, [pc, #632] ; (80033d8 <HAL_UART_RxCpltCallback+0xb1c>)
|
|||
|
|
800315e: 4293 cmp r3, r2
|
|||
|
|
8003160: d900 bls.n 8003164 <HAL_UART_RxCpltCallback+0x8a8>
|
|||
|
|
8003162: e119 b.n 8003398 <HAL_UART_RxCpltCallback+0xadc>
|
|||
|
|
CorrWord[pardata.IIN][pardata.IKU]++;
|
|||
|
|
8003164: 4b9a ldr r3, [pc, #616] ; (80033d0 <HAL_UART_RxCpltCallback+0xb14>)
|
|||
|
|
8003166: 88db ldrh r3, [r3, #6]
|
|||
|
|
8003168: b29b uxth r3, r3
|
|||
|
|
800316a: 001a movs r2, r3
|
|||
|
|
800316c: 4b98 ldr r3, [pc, #608] ; (80033d0 <HAL_UART_RxCpltCallback+0xb14>)
|
|||
|
|
800316e: 899b ldrh r3, [r3, #12]
|
|||
|
|
8003170: b29b uxth r3, r3
|
|||
|
|
8003172: 0019 movs r1, r3
|
|||
|
|
8003174: 4897 ldr r0, [pc, #604] ; (80033d4 <HAL_UART_RxCpltCallback+0xb18>)
|
|||
|
|
8003176: 0013 movs r3, r2
|
|||
|
|
8003178: 009b lsls r3, r3, #2
|
|||
|
|
800317a: 189b adds r3, r3, r2
|
|||
|
|
800317c: 009b lsls r3, r3, #2
|
|||
|
|
800317e: 185b adds r3, r3, r1
|
|||
|
|
8003180: 005b lsls r3, r3, #1
|
|||
|
|
8003182: 5a1b ldrh r3, [r3, r0]
|
|||
|
|
8003184: b29b uxth r3, r3
|
|||
|
|
8003186: 3301 adds r3, #1
|
|||
|
|
8003188: b29c uxth r4, r3
|
|||
|
|
800318a: 4892 ldr r0, [pc, #584] ; (80033d4 <HAL_UART_RxCpltCallback+0xb18>)
|
|||
|
|
800318c: 0013 movs r3, r2
|
|||
|
|
800318e: 009b lsls r3, r3, #2
|
|||
|
|
8003190: 189b adds r3, r3, r2
|
|||
|
|
8003192: 009b lsls r3, r3, #2
|
|||
|
|
8003194: 185b adds r3, r3, r1
|
|||
|
|
8003196: 005b lsls r3, r3, #1
|
|||
|
|
8003198: 1c22 adds r2, r4, #0
|
|||
|
|
800319a: 521a strh r2, [r3, r0]
|
|||
|
|
break;
|
|||
|
|
800319c: e0fc b.n 8003398 <HAL_UART_RxCpltCallback+0xadc>
|
|||
|
|
if(CorrWord[pardata.IIN][pardata.IKU] > 0)
|
|||
|
|
800319e: 4b8c ldr r3, [pc, #560] ; (80033d0 <HAL_UART_RxCpltCallback+0xb14>)
|
|||
|
|
80031a0: 88db ldrh r3, [r3, #6]
|
|||
|
|
80031a2: b29b uxth r3, r3
|
|||
|
|
80031a4: 0019 movs r1, r3
|
|||
|
|
80031a6: 4b8a ldr r3, [pc, #552] ; (80033d0 <HAL_UART_RxCpltCallback+0xb14>)
|
|||
|
|
80031a8: 899b ldrh r3, [r3, #12]
|
|||
|
|
80031aa: b29b uxth r3, r3
|
|||
|
|
80031ac: 0018 movs r0, r3
|
|||
|
|
80031ae: 4a89 ldr r2, [pc, #548] ; (80033d4 <HAL_UART_RxCpltCallback+0xb18>)
|
|||
|
|
80031b0: 000b movs r3, r1
|
|||
|
|
80031b2: 009b lsls r3, r3, #2
|
|||
|
|
80031b4: 185b adds r3, r3, r1
|
|||
|
|
80031b6: 009b lsls r3, r3, #2
|
|||
|
|
80031b8: 181b adds r3, r3, r0
|
|||
|
|
80031ba: 005b lsls r3, r3, #1
|
|||
|
|
80031bc: 5a9b ldrh r3, [r3, r2]
|
|||
|
|
80031be: b29b uxth r3, r3
|
|||
|
|
80031c0: 2b00 cmp r3, #0
|
|||
|
|
80031c2: d100 bne.n 80031c6 <HAL_UART_RxCpltCallback+0x90a>
|
|||
|
|
80031c4: e0ea b.n 800339c <HAL_UART_RxCpltCallback+0xae0>
|
|||
|
|
CorrWord[pardata.IIN][pardata.IKU]--;
|
|||
|
|
80031c6: 4b82 ldr r3, [pc, #520] ; (80033d0 <HAL_UART_RxCpltCallback+0xb14>)
|
|||
|
|
80031c8: 88db ldrh r3, [r3, #6]
|
|||
|
|
80031ca: b29b uxth r3, r3
|
|||
|
|
80031cc: 001a movs r2, r3
|
|||
|
|
80031ce: 4b80 ldr r3, [pc, #512] ; (80033d0 <HAL_UART_RxCpltCallback+0xb14>)
|
|||
|
|
80031d0: 899b ldrh r3, [r3, #12]
|
|||
|
|
80031d2: b29b uxth r3, r3
|
|||
|
|
80031d4: 0019 movs r1, r3
|
|||
|
|
80031d6: 487f ldr r0, [pc, #508] ; (80033d4 <HAL_UART_RxCpltCallback+0xb18>)
|
|||
|
|
80031d8: 0013 movs r3, r2
|
|||
|
|
80031da: 009b lsls r3, r3, #2
|
|||
|
|
80031dc: 189b adds r3, r3, r2
|
|||
|
|
80031de: 009b lsls r3, r3, #2
|
|||
|
|
80031e0: 185b adds r3, r3, r1
|
|||
|
|
80031e2: 005b lsls r3, r3, #1
|
|||
|
|
80031e4: 5a1b ldrh r3, [r3, r0]
|
|||
|
|
80031e6: b29b uxth r3, r3
|
|||
|
|
80031e8: 3b01 subs r3, #1
|
|||
|
|
80031ea: b29c uxth r4, r3
|
|||
|
|
80031ec: 4879 ldr r0, [pc, #484] ; (80033d4 <HAL_UART_RxCpltCallback+0xb18>)
|
|||
|
|
80031ee: 0013 movs r3, r2
|
|||
|
|
80031f0: 009b lsls r3, r3, #2
|
|||
|
|
80031f2: 189b adds r3, r3, r2
|
|||
|
|
80031f4: 009b lsls r3, r3, #2
|
|||
|
|
80031f6: 185b adds r3, r3, r1
|
|||
|
|
80031f8: 005b lsls r3, r3, #1
|
|||
|
|
80031fa: 1c22 adds r2, r4, #0
|
|||
|
|
80031fc: 521a strh r2, [r3, r0]
|
|||
|
|
break;
|
|||
|
|
80031fe: e0cd b.n 800339c <HAL_UART_RxCpltCallback+0xae0>
|
|||
|
|
if(CorrWord[pardata.IIN][pardata.IKU] < 4085)
|
|||
|
|
8003200: 4b73 ldr r3, [pc, #460] ; (80033d0 <HAL_UART_RxCpltCallback+0xb14>)
|
|||
|
|
8003202: 88db ldrh r3, [r3, #6]
|
|||
|
|
8003204: b29b uxth r3, r3
|
|||
|
|
8003206: 0019 movs r1, r3
|
|||
|
|
8003208: 4b71 ldr r3, [pc, #452] ; (80033d0 <HAL_UART_RxCpltCallback+0xb14>)
|
|||
|
|
800320a: 899b ldrh r3, [r3, #12]
|
|||
|
|
800320c: b29b uxth r3, r3
|
|||
|
|
800320e: 0018 movs r0, r3
|
|||
|
|
8003210: 4a70 ldr r2, [pc, #448] ; (80033d4 <HAL_UART_RxCpltCallback+0xb18>)
|
|||
|
|
8003212: 000b movs r3, r1
|
|||
|
|
8003214: 009b lsls r3, r3, #2
|
|||
|
|
8003216: 185b adds r3, r3, r1
|
|||
|
|
8003218: 009b lsls r3, r3, #2
|
|||
|
|
800321a: 181b adds r3, r3, r0
|
|||
|
|
800321c: 005b lsls r3, r3, #1
|
|||
|
|
800321e: 5a9b ldrh r3, [r3, r2]
|
|||
|
|
8003220: b29b uxth r3, r3
|
|||
|
|
8003222: 4a6e ldr r2, [pc, #440] ; (80033dc <HAL_UART_RxCpltCallback+0xb20>)
|
|||
|
|
8003224: 4293 cmp r3, r2
|
|||
|
|
8003226: d900 bls.n 800322a <HAL_UART_RxCpltCallback+0x96e>
|
|||
|
|
8003228: e0ba b.n 80033a0 <HAL_UART_RxCpltCallback+0xae4>
|
|||
|
|
CorrWord[pardata.IIN][pardata.IKU] += 10;
|
|||
|
|
800322a: 4b69 ldr r3, [pc, #420] ; (80033d0 <HAL_UART_RxCpltCallback+0xb14>)
|
|||
|
|
800322c: 88db ldrh r3, [r3, #6]
|
|||
|
|
800322e: b29a uxth r2, r3
|
|||
|
|
8003230: 0011 movs r1, r2
|
|||
|
|
8003232: 4b67 ldr r3, [pc, #412] ; (80033d0 <HAL_UART_RxCpltCallback+0xb14>)
|
|||
|
|
8003234: 899b ldrh r3, [r3, #12]
|
|||
|
|
8003236: b29b uxth r3, r3
|
|||
|
|
8003238: 001c movs r4, r3
|
|||
|
|
800323a: 0010 movs r0, r2
|
|||
|
|
800323c: 001d movs r5, r3
|
|||
|
|
800323e: 4a65 ldr r2, [pc, #404] ; (80033d4 <HAL_UART_RxCpltCallback+0xb18>)
|
|||
|
|
8003240: 0003 movs r3, r0
|
|||
|
|
8003242: 009b lsls r3, r3, #2
|
|||
|
|
8003244: 181b adds r3, r3, r0
|
|||
|
|
8003246: 009b lsls r3, r3, #2
|
|||
|
|
8003248: 195b adds r3, r3, r5
|
|||
|
|
800324a: 005b lsls r3, r3, #1
|
|||
|
|
800324c: 5a9b ldrh r3, [r3, r2]
|
|||
|
|
800324e: b29b uxth r3, r3
|
|||
|
|
8003250: 330a adds r3, #10
|
|||
|
|
8003252: b298 uxth r0, r3
|
|||
|
|
8003254: 4a5f ldr r2, [pc, #380] ; (80033d4 <HAL_UART_RxCpltCallback+0xb18>)
|
|||
|
|
8003256: 000b movs r3, r1
|
|||
|
|
8003258: 009b lsls r3, r3, #2
|
|||
|
|
800325a: 185b adds r3, r3, r1
|
|||
|
|
800325c: 009b lsls r3, r3, #2
|
|||
|
|
800325e: 191b adds r3, r3, r4
|
|||
|
|
8003260: 005b lsls r3, r3, #1
|
|||
|
|
8003262: 1c01 adds r1, r0, #0
|
|||
|
|
8003264: 5299 strh r1, [r3, r2]
|
|||
|
|
break;
|
|||
|
|
8003266: e09b b.n 80033a0 <HAL_UART_RxCpltCallback+0xae4>
|
|||
|
|
if(CorrWord[pardata.IIN][pardata.IKU] > 10)
|
|||
|
|
8003268: 4b59 ldr r3, [pc, #356] ; (80033d0 <HAL_UART_RxCpltCallback+0xb14>)
|
|||
|
|
800326a: 88db ldrh r3, [r3, #6]
|
|||
|
|
800326c: b29b uxth r3, r3
|
|||
|
|
800326e: 0019 movs r1, r3
|
|||
|
|
8003270: 4b57 ldr r3, [pc, #348] ; (80033d0 <HAL_UART_RxCpltCallback+0xb14>)
|
|||
|
|
8003272: 899b ldrh r3, [r3, #12]
|
|||
|
|
8003274: b29b uxth r3, r3
|
|||
|
|
8003276: 0018 movs r0, r3
|
|||
|
|
8003278: 4a56 ldr r2, [pc, #344] ; (80033d4 <HAL_UART_RxCpltCallback+0xb18>)
|
|||
|
|
800327a: 000b movs r3, r1
|
|||
|
|
800327c: 009b lsls r3, r3, #2
|
|||
|
|
800327e: 185b adds r3, r3, r1
|
|||
|
|
8003280: 009b lsls r3, r3, #2
|
|||
|
|
8003282: 181b adds r3, r3, r0
|
|||
|
|
8003284: 005b lsls r3, r3, #1
|
|||
|
|
8003286: 5a9b ldrh r3, [r3, r2]
|
|||
|
|
8003288: b29b uxth r3, r3
|
|||
|
|
800328a: 2b0a cmp r3, #10
|
|||
|
|
800328c: d800 bhi.n 8003290 <HAL_UART_RxCpltCallback+0x9d4>
|
|||
|
|
800328e: e089 b.n 80033a4 <HAL_UART_RxCpltCallback+0xae8>
|
|||
|
|
CorrWord[pardata.IIN][pardata.IKU] -= 10;
|
|||
|
|
8003290: 4b4f ldr r3, [pc, #316] ; (80033d0 <HAL_UART_RxCpltCallback+0xb14>)
|
|||
|
|
8003292: 88db ldrh r3, [r3, #6]
|
|||
|
|
8003294: b29a uxth r2, r3
|
|||
|
|
8003296: 0011 movs r1, r2
|
|||
|
|
8003298: 4b4d ldr r3, [pc, #308] ; (80033d0 <HAL_UART_RxCpltCallback+0xb14>)
|
|||
|
|
800329a: 899b ldrh r3, [r3, #12]
|
|||
|
|
800329c: b29b uxth r3, r3
|
|||
|
|
800329e: 001c movs r4, r3
|
|||
|
|
80032a0: 0010 movs r0, r2
|
|||
|
|
80032a2: 001d movs r5, r3
|
|||
|
|
80032a4: 4a4b ldr r2, [pc, #300] ; (80033d4 <HAL_UART_RxCpltCallback+0xb18>)
|
|||
|
|
80032a6: 0003 movs r3, r0
|
|||
|
|
80032a8: 009b lsls r3, r3, #2
|
|||
|
|
80032aa: 181b adds r3, r3, r0
|
|||
|
|
80032ac: 009b lsls r3, r3, #2
|
|||
|
|
80032ae: 195b adds r3, r3, r5
|
|||
|
|
80032b0: 005b lsls r3, r3, #1
|
|||
|
|
80032b2: 5a9b ldrh r3, [r3, r2]
|
|||
|
|
80032b4: b29b uxth r3, r3
|
|||
|
|
80032b6: 3b0a subs r3, #10
|
|||
|
|
80032b8: b298 uxth r0, r3
|
|||
|
|
80032ba: 4a46 ldr r2, [pc, #280] ; (80033d4 <HAL_UART_RxCpltCallback+0xb18>)
|
|||
|
|
80032bc: 000b movs r3, r1
|
|||
|
|
80032be: 009b lsls r3, r3, #2
|
|||
|
|
80032c0: 185b adds r3, r3, r1
|
|||
|
|
80032c2: 009b lsls r3, r3, #2
|
|||
|
|
80032c4: 191b adds r3, r3, r4
|
|||
|
|
80032c6: 005b lsls r3, r3, #1
|
|||
|
|
80032c8: 1c01 adds r1, r0, #0
|
|||
|
|
80032ca: 5299 strh r1, [r3, r2]
|
|||
|
|
break;
|
|||
|
|
80032cc: e06a b.n 80033a4 <HAL_UART_RxCpltCallback+0xae8>
|
|||
|
|
if(CorrWord[pardata.IIN][pardata.IKU] < 3995)
|
|||
|
|
80032ce: 4b40 ldr r3, [pc, #256] ; (80033d0 <HAL_UART_RxCpltCallback+0xb14>)
|
|||
|
|
80032d0: 88db ldrh r3, [r3, #6]
|
|||
|
|
80032d2: b29b uxth r3, r3
|
|||
|
|
80032d4: 0019 movs r1, r3
|
|||
|
|
80032d6: 4b3e ldr r3, [pc, #248] ; (80033d0 <HAL_UART_RxCpltCallback+0xb14>)
|
|||
|
|
80032d8: 899b ldrh r3, [r3, #12]
|
|||
|
|
80032da: b29b uxth r3, r3
|
|||
|
|
80032dc: 0018 movs r0, r3
|
|||
|
|
80032de: 4a3d ldr r2, [pc, #244] ; (80033d4 <HAL_UART_RxCpltCallback+0xb18>)
|
|||
|
|
80032e0: 000b movs r3, r1
|
|||
|
|
80032e2: 009b lsls r3, r3, #2
|
|||
|
|
80032e4: 185b adds r3, r3, r1
|
|||
|
|
80032e6: 009b lsls r3, r3, #2
|
|||
|
|
80032e8: 181b adds r3, r3, r0
|
|||
|
|
80032ea: 005b lsls r3, r3, #1
|
|||
|
|
80032ec: 5a9b ldrh r3, [r3, r2]
|
|||
|
|
80032ee: b29b uxth r3, r3
|
|||
|
|
80032f0: 4a3b ldr r2, [pc, #236] ; (80033e0 <HAL_UART_RxCpltCallback+0xb24>)
|
|||
|
|
80032f2: 4293 cmp r3, r2
|
|||
|
|
80032f4: d858 bhi.n 80033a8 <HAL_UART_RxCpltCallback+0xaec>
|
|||
|
|
CorrWord[pardata.IIN][pardata.IKU] += 100;
|
|||
|
|
80032f6: 4b36 ldr r3, [pc, #216] ; (80033d0 <HAL_UART_RxCpltCallback+0xb14>)
|
|||
|
|
80032f8: 88db ldrh r3, [r3, #6]
|
|||
|
|
80032fa: b29a uxth r2, r3
|
|||
|
|
80032fc: 0011 movs r1, r2
|
|||
|
|
80032fe: 4b34 ldr r3, [pc, #208] ; (80033d0 <HAL_UART_RxCpltCallback+0xb14>)
|
|||
|
|
8003300: 899b ldrh r3, [r3, #12]
|
|||
|
|
8003302: b29b uxth r3, r3
|
|||
|
|
8003304: 001c movs r4, r3
|
|||
|
|
8003306: 0010 movs r0, r2
|
|||
|
|
8003308: 001d movs r5, r3
|
|||
|
|
800330a: 4a32 ldr r2, [pc, #200] ; (80033d4 <HAL_UART_RxCpltCallback+0xb18>)
|
|||
|
|
800330c: 0003 movs r3, r0
|
|||
|
|
800330e: 009b lsls r3, r3, #2
|
|||
|
|
8003310: 181b adds r3, r3, r0
|
|||
|
|
8003312: 009b lsls r3, r3, #2
|
|||
|
|
8003314: 195b adds r3, r3, r5
|
|||
|
|
8003316: 005b lsls r3, r3, #1
|
|||
|
|
8003318: 5a9b ldrh r3, [r3, r2]
|
|||
|
|
800331a: b29b uxth r3, r3
|
|||
|
|
800331c: 3364 adds r3, #100 ; 0x64
|
|||
|
|
800331e: b298 uxth r0, r3
|
|||
|
|
8003320: 4a2c ldr r2, [pc, #176] ; (80033d4 <HAL_UART_RxCpltCallback+0xb18>)
|
|||
|
|
8003322: 000b movs r3, r1
|
|||
|
|
8003324: 009b lsls r3, r3, #2
|
|||
|
|
8003326: 185b adds r3, r3, r1
|
|||
|
|
8003328: 009b lsls r3, r3, #2
|
|||
|
|
800332a: 191b adds r3, r3, r4
|
|||
|
|
800332c: 005b lsls r3, r3, #1
|
|||
|
|
800332e: 1c01 adds r1, r0, #0
|
|||
|
|
8003330: 5299 strh r1, [r3, r2]
|
|||
|
|
break;
|
|||
|
|
8003332: e039 b.n 80033a8 <HAL_UART_RxCpltCallback+0xaec>
|
|||
|
|
if(CorrWord[pardata.IIN][pardata.IKU] > 100)
|
|||
|
|
8003334: 4b26 ldr r3, [pc, #152] ; (80033d0 <HAL_UART_RxCpltCallback+0xb14>)
|
|||
|
|
8003336: 88db ldrh r3, [r3, #6]
|
|||
|
|
8003338: b29b uxth r3, r3
|
|||
|
|
800333a: 0019 movs r1, r3
|
|||
|
|
800333c: 4b24 ldr r3, [pc, #144] ; (80033d0 <HAL_UART_RxCpltCallback+0xb14>)
|
|||
|
|
800333e: 899b ldrh r3, [r3, #12]
|
|||
|
|
8003340: b29b uxth r3, r3
|
|||
|
|
8003342: 0018 movs r0, r3
|
|||
|
|
8003344: 4a23 ldr r2, [pc, #140] ; (80033d4 <HAL_UART_RxCpltCallback+0xb18>)
|
|||
|
|
8003346: 000b movs r3, r1
|
|||
|
|
8003348: 009b lsls r3, r3, #2
|
|||
|
|
800334a: 185b adds r3, r3, r1
|
|||
|
|
800334c: 009b lsls r3, r3, #2
|
|||
|
|
800334e: 181b adds r3, r3, r0
|
|||
|
|
8003350: 005b lsls r3, r3, #1
|
|||
|
|
8003352: 5a9b ldrh r3, [r3, r2]
|
|||
|
|
8003354: b29b uxth r3, r3
|
|||
|
|
8003356: 2b64 cmp r3, #100 ; 0x64
|
|||
|
|
8003358: d928 bls.n 80033ac <HAL_UART_RxCpltCallback+0xaf0>
|
|||
|
|
CorrWord[pardata.IIN][pardata.IKU] -= 100;
|
|||
|
|
800335a: 4b1d ldr r3, [pc, #116] ; (80033d0 <HAL_UART_RxCpltCallback+0xb14>)
|
|||
|
|
800335c: 88db ldrh r3, [r3, #6]
|
|||
|
|
800335e: b29a uxth r2, r3
|
|||
|
|
8003360: 0011 movs r1, r2
|
|||
|
|
8003362: 4b1b ldr r3, [pc, #108] ; (80033d0 <HAL_UART_RxCpltCallback+0xb14>)
|
|||
|
|
8003364: 899b ldrh r3, [r3, #12]
|
|||
|
|
8003366: b29b uxth r3, r3
|
|||
|
|
8003368: 001c movs r4, r3
|
|||
|
|
800336a: 0010 movs r0, r2
|
|||
|
|
800336c: 001d movs r5, r3
|
|||
|
|
800336e: 4a19 ldr r2, [pc, #100] ; (80033d4 <HAL_UART_RxCpltCallback+0xb18>)
|
|||
|
|
8003370: 0003 movs r3, r0
|
|||
|
|
8003372: 009b lsls r3, r3, #2
|
|||
|
|
8003374: 181b adds r3, r3, r0
|
|||
|
|
8003376: 009b lsls r3, r3, #2
|
|||
|
|
8003378: 195b adds r3, r3, r5
|
|||
|
|
800337a: 005b lsls r3, r3, #1
|
|||
|
|
800337c: 5a9b ldrh r3, [r3, r2]
|
|||
|
|
800337e: b29b uxth r3, r3
|
|||
|
|
8003380: 3b64 subs r3, #100 ; 0x64
|
|||
|
|
8003382: b298 uxth r0, r3
|
|||
|
|
8003384: 4a13 ldr r2, [pc, #76] ; (80033d4 <HAL_UART_RxCpltCallback+0xb18>)
|
|||
|
|
8003386: 000b movs r3, r1
|
|||
|
|
8003388: 009b lsls r3, r3, #2
|
|||
|
|
800338a: 185b adds r3, r3, r1
|
|||
|
|
800338c: 009b lsls r3, r3, #2
|
|||
|
|
800338e: 191b adds r3, r3, r4
|
|||
|
|
8003390: 005b lsls r3, r3, #1
|
|||
|
|
8003392: 1c01 adds r1, r0, #0
|
|||
|
|
8003394: 5299 strh r1, [r3, r2]
|
|||
|
|
break;
|
|||
|
|
8003396: e009 b.n 80033ac <HAL_UART_RxCpltCallback+0xaf0>
|
|||
|
|
break;
|
|||
|
|
8003398: 46c0 nop ; (mov r8, r8)
|
|||
|
|
800339a: e008 b.n 80033ae <HAL_UART_RxCpltCallback+0xaf2>
|
|||
|
|
break;
|
|||
|
|
800339c: 46c0 nop ; (mov r8, r8)
|
|||
|
|
800339e: e006 b.n 80033ae <HAL_UART_RxCpltCallback+0xaf2>
|
|||
|
|
break;
|
|||
|
|
80033a0: 46c0 nop ; (mov r8, r8)
|
|||
|
|
80033a2: e004 b.n 80033ae <HAL_UART_RxCpltCallback+0xaf2>
|
|||
|
|
break;
|
|||
|
|
80033a4: 46c0 nop ; (mov r8, r8)
|
|||
|
|
80033a6: e002 b.n 80033ae <HAL_UART_RxCpltCallback+0xaf2>
|
|||
|
|
break;
|
|||
|
|
80033a8: 46c0 nop ; (mov r8, r8)
|
|||
|
|
80033aa: e000 b.n 80033ae <HAL_UART_RxCpltCallback+0xaf2>
|
|||
|
|
break;
|
|||
|
|
80033ac: 46c0 nop ; (mov r8, r8)
|
|||
|
|
SetAndCorrect();
|
|||
|
|
80033ae: f7fd ff5f bl 8001270 <SetAndCorrect>
|
|||
|
|
wrCorr();
|
|||
|
|
80033b2: f7fe fcdb bl 8001d6c <wrCorr>
|
|||
|
|
for(j = 0; j < 6; j++) {
|
|||
|
|
80033b6: 231f movs r3, #31
|
|||
|
|
80033b8: 18fb adds r3, r7, r3
|
|||
|
|
80033ba: 2200 movs r2, #0
|
|||
|
|
80033bc: 701a strb r2, [r3, #0]
|
|||
|
|
80033be: e022 b.n 8003406 <HAL_UART_RxCpltCallback+0xb4a>
|
|||
|
|
80033c0: 2000028c .word 0x2000028c
|
|||
|
|
80033c4: 20000188 .word 0x20000188
|
|||
|
|
80033c8: 20000035 .word 0x20000035
|
|||
|
|
80033cc: 20000034 .word 0x20000034
|
|||
|
|
80033d0: 20000098 .word 0x20000098
|
|||
|
|
80033d4: 20000048 .word 0x20000048
|
|||
|
|
80033d8: 00000ffe .word 0x00000ffe
|
|||
|
|
80033dc: 00000ff4 .word 0x00000ff4
|
|||
|
|
80033e0: 00000f9a .word 0x00000f9a
|
|||
|
|
tx[j] = iobuf[j];
|
|||
|
|
80033e4: 231f movs r3, #31
|
|||
|
|
80033e6: 18fb adds r3, r7, r3
|
|||
|
|
80033e8: 781b ldrb r3, [r3, #0]
|
|||
|
|
80033ea: 221f movs r2, #31
|
|||
|
|
80033ec: 18ba adds r2, r7, r2
|
|||
|
|
80033ee: 7812 ldrb r2, [r2, #0]
|
|||
|
|
80033f0: 49de ldr r1, [pc, #888] ; (800376c <HAL_UART_RxCpltCallback+0xeb0>)
|
|||
|
|
80033f2: 5c89 ldrb r1, [r1, r2]
|
|||
|
|
80033f4: 4ade ldr r2, [pc, #888] ; (8003770 <HAL_UART_RxCpltCallback+0xeb4>)
|
|||
|
|
80033f6: 54d1 strb r1, [r2, r3]
|
|||
|
|
for(j = 0; j < 6; j++) {
|
|||
|
|
80033f8: 231f movs r3, #31
|
|||
|
|
80033fa: 18fb adds r3, r7, r3
|
|||
|
|
80033fc: 781a ldrb r2, [r3, #0]
|
|||
|
|
80033fe: 231f movs r3, #31
|
|||
|
|
8003400: 18fb adds r3, r7, r3
|
|||
|
|
8003402: 3201 adds r2, #1
|
|||
|
|
8003404: 701a strb r2, [r3, #0]
|
|||
|
|
8003406: 231f movs r3, #31
|
|||
|
|
8003408: 18fb adds r3, r7, r3
|
|||
|
|
800340a: 781b ldrb r3, [r3, #0]
|
|||
|
|
800340c: 2b05 cmp r3, #5
|
|||
|
|
800340e: d9e9 bls.n 80033e4 <HAL_UART_RxCpltCallback+0xb28>
|
|||
|
|
strtOut(6);
|
|||
|
|
8003410: 2006 movs r0, #6
|
|||
|
|
8003412: f7ff f961 bl 80026d8 <strtOut>
|
|||
|
|
break;
|
|||
|
|
8003416: f000 fc14 bl 8003c42 <HAL_UART_RxCpltCallback+0x1386>
|
|||
|
|
if((regs.ch[0] > (5011 - addr.sh)) || (iobuf[6] != (regs.ch[0] << 1)))
|
|||
|
|
800341a: 230c movs r3, #12
|
|||
|
|
800341c: 18fb adds r3, r7, r3
|
|||
|
|
800341e: 781b ldrb r3, [r3, #0]
|
|||
|
|
8003420: 001a movs r2, r3
|
|||
|
|
8003422: 2310 movs r3, #16
|
|||
|
|
8003424: 18fb adds r3, r7, r3
|
|||
|
|
8003426: 881b ldrh r3, [r3, #0]
|
|||
|
|
8003428: 0019 movs r1, r3
|
|||
|
|
800342a: 4bd2 ldr r3, [pc, #840] ; (8003774 <HAL_UART_RxCpltCallback+0xeb8>)
|
|||
|
|
800342c: 1a5b subs r3, r3, r1
|
|||
|
|
800342e: 429a cmp r2, r3
|
|||
|
|
8003430: dc08 bgt.n 8003444 <HAL_UART_RxCpltCallback+0xb88>
|
|||
|
|
8003432: 4bce ldr r3, [pc, #824] ; (800376c <HAL_UART_RxCpltCallback+0xeb0>)
|
|||
|
|
8003434: 799b ldrb r3, [r3, #6]
|
|||
|
|
8003436: 001a movs r2, r3
|
|||
|
|
8003438: 230c movs r3, #12
|
|||
|
|
800343a: 18fb adds r3, r7, r3
|
|||
|
|
800343c: 781b ldrb r3, [r3, #0]
|
|||
|
|
800343e: 005b lsls r3, r3, #1
|
|||
|
|
8003440: 429a cmp r2, r3
|
|||
|
|
8003442: d012 beq.n 800346a <HAL_UART_RxCpltCallback+0xbae>
|
|||
|
|
tx[0] = iobuf[0];
|
|||
|
|
8003444: 4bc9 ldr r3, [pc, #804] ; (800376c <HAL_UART_RxCpltCallback+0xeb0>)
|
|||
|
|
8003446: 781a ldrb r2, [r3, #0]
|
|||
|
|
8003448: 4bc9 ldr r3, [pc, #804] ; (8003770 <HAL_UART_RxCpltCallback+0xeb4>)
|
|||
|
|
800344a: 701a strb r2, [r3, #0]
|
|||
|
|
tx[1] = (iobuf[1] | 0x80);
|
|||
|
|
800344c: 4bc7 ldr r3, [pc, #796] ; (800376c <HAL_UART_RxCpltCallback+0xeb0>)
|
|||
|
|
800344e: 785b ldrb r3, [r3, #1]
|
|||
|
|
8003450: 2280 movs r2, #128 ; 0x80
|
|||
|
|
8003452: 4252 negs r2, r2
|
|||
|
|
8003454: 4313 orrs r3, r2
|
|||
|
|
8003456: b2da uxtb r2, r3
|
|||
|
|
8003458: 4bc5 ldr r3, [pc, #788] ; (8003770 <HAL_UART_RxCpltCallback+0xeb4>)
|
|||
|
|
800345a: 705a strb r2, [r3, #1]
|
|||
|
|
tx[2] = 0x03;
|
|||
|
|
800345c: 4bc4 ldr r3, [pc, #784] ; (8003770 <HAL_UART_RxCpltCallback+0xeb4>)
|
|||
|
|
800345e: 2203 movs r2, #3
|
|||
|
|
8003460: 709a strb r2, [r3, #2]
|
|||
|
|
strtOut(3);
|
|||
|
|
8003462: 2003 movs r0, #3
|
|||
|
|
8003464: f7ff f938 bl 80026d8 <strtOut>
|
|||
|
|
8003468: e0b6 b.n 80035d8 <HAL_UART_RxCpltCallback+0xd1c>
|
|||
|
|
j = 8 + iobuf[6];
|
|||
|
|
800346a: 4bc0 ldr r3, [pc, #768] ; (800376c <HAL_UART_RxCpltCallback+0xeb0>)
|
|||
|
|
800346c: 799a ldrb r2, [r3, #6]
|
|||
|
|
800346e: 231f movs r3, #31
|
|||
|
|
8003470: 18fb adds r3, r7, r3
|
|||
|
|
8003472: 3208 adds r2, #8
|
|||
|
|
8003474: 701a strb r2, [r3, #0]
|
|||
|
|
if(iolen > j)
|
|||
|
|
8003476: 4bc0 ldr r3, [pc, #768] ; (8003778 <HAL_UART_RxCpltCallback+0xebc>)
|
|||
|
|
8003478: 781b ldrb r3, [r3, #0]
|
|||
|
|
800347a: 221f movs r2, #31
|
|||
|
|
800347c: 18ba adds r2, r7, r2
|
|||
|
|
800347e: 7812 ldrb r2, [r2, #0]
|
|||
|
|
8003480: 429a cmp r2, r3
|
|||
|
|
8003482: d301 bcc.n 8003488 <HAL_UART_RxCpltCallback+0xbcc>
|
|||
|
|
8003484: f000 fbdf bl 8003c46 <HAL_UART_RxCpltCallback+0x138a>
|
|||
|
|
iolen = 0;
|
|||
|
|
8003488: 4bbb ldr r3, [pc, #748] ; (8003778 <HAL_UART_RxCpltCallback+0xebc>)
|
|||
|
|
800348a: 2200 movs r2, #0
|
|||
|
|
800348c: 701a strb r2, [r3, #0]
|
|||
|
|
crc.ch[0] = iobuf[j - 1];
|
|||
|
|
800348e: 231f movs r3, #31
|
|||
|
|
8003490: 18fb adds r3, r7, r3
|
|||
|
|
8003492: 781b ldrb r3, [r3, #0]
|
|||
|
|
8003494: 3b01 subs r3, #1
|
|||
|
|
8003496: 4ab5 ldr r2, [pc, #724] ; (800376c <HAL_UART_RxCpltCallback+0xeb0>)
|
|||
|
|
8003498: 5cd2 ldrb r2, [r2, r3]
|
|||
|
|
800349a: 2314 movs r3, #20
|
|||
|
|
800349c: 18fb adds r3, r7, r3
|
|||
|
|
800349e: 701a strb r2, [r3, #0]
|
|||
|
|
crc.ch[1] = iobuf[j];
|
|||
|
|
80034a0: 231f movs r3, #31
|
|||
|
|
80034a2: 18fb adds r3, r7, r3
|
|||
|
|
80034a4: 781b ldrb r3, [r3, #0]
|
|||
|
|
80034a6: 4ab1 ldr r2, [pc, #708] ; (800376c <HAL_UART_RxCpltCallback+0xeb0>)
|
|||
|
|
80034a8: 5cd2 ldrb r2, [r2, r3]
|
|||
|
|
80034aa: 2314 movs r3, #20
|
|||
|
|
80034ac: 18fb adds r3, r7, r3
|
|||
|
|
80034ae: 705a strb r2, [r3, #1]
|
|||
|
|
if(crc.sh == Crc16(j - 1))
|
|||
|
|
80034b0: 2314 movs r3, #20
|
|||
|
|
80034b2: 18fb adds r3, r7, r3
|
|||
|
|
80034b4: 881c ldrh r4, [r3, #0]
|
|||
|
|
80034b6: 231f movs r3, #31
|
|||
|
|
80034b8: 18fb adds r3, r7, r3
|
|||
|
|
80034ba: 781b ldrb r3, [r3, #0]
|
|||
|
|
80034bc: b29b uxth r3, r3
|
|||
|
|
80034be: 3b01 subs r3, #1
|
|||
|
|
80034c0: b29b uxth r3, r3
|
|||
|
|
80034c2: 0018 movs r0, r3
|
|||
|
|
80034c4: f7ff f954 bl 8002770 <Crc16>
|
|||
|
|
80034c8: 0003 movs r3, r0
|
|||
|
|
80034ca: 429c cmp r4, r3
|
|||
|
|
80034cc: d001 beq.n 80034d2 <HAL_UART_RxCpltCallback+0xc16>
|
|||
|
|
80034ce: f000 fbba bl 8003c46 <HAL_UART_RxCpltCallback+0x138a>
|
|||
|
|
pch = (uint8_t *) &pardata.IIN + ((addr.sh - 5001) << 1);
|
|||
|
|
80034d2: 2310 movs r3, #16
|
|||
|
|
80034d4: 18fb adds r3, r7, r3
|
|||
|
|
80034d6: 881b ldrh r3, [r3, #0]
|
|||
|
|
80034d8: 4aa8 ldr r2, [pc, #672] ; (800377c <HAL_UART_RxCpltCallback+0xec0>)
|
|||
|
|
80034da: 4694 mov ip, r2
|
|||
|
|
80034dc: 4463 add r3, ip
|
|||
|
|
80034de: 005b lsls r3, r3, #1
|
|||
|
|
80034e0: 001a movs r2, r3
|
|||
|
|
80034e2: 4ba7 ldr r3, [pc, #668] ; (8003780 <HAL_UART_RxCpltCallback+0xec4>)
|
|||
|
|
80034e4: 18d3 adds r3, r2, r3
|
|||
|
|
80034e6: 61bb str r3, [r7, #24]
|
|||
|
|
for(j = 0; j < iobuf[6]; j++)
|
|||
|
|
80034e8: 231f movs r3, #31
|
|||
|
|
80034ea: 18fb adds r3, r7, r3
|
|||
|
|
80034ec: 2200 movs r2, #0
|
|||
|
|
80034ee: 701a strb r2, [r3, #0]
|
|||
|
|
80034f0: e016 b.n 8003520 <HAL_UART_RxCpltCallback+0xc64>
|
|||
|
|
*(pch + (j ^ 1)) = iobuf[j + 7];
|
|||
|
|
80034f2: 231f movs r3, #31
|
|||
|
|
80034f4: 18fb adds r3, r7, r3
|
|||
|
|
80034f6: 781b ldrb r3, [r3, #0]
|
|||
|
|
80034f8: 2201 movs r2, #1
|
|||
|
|
80034fa: 4053 eors r3, r2
|
|||
|
|
80034fc: b2db uxtb r3, r3
|
|||
|
|
80034fe: 001a movs r2, r3
|
|||
|
|
8003500: 69bb ldr r3, [r7, #24]
|
|||
|
|
8003502: 189b adds r3, r3, r2
|
|||
|
|
8003504: 221f movs r2, #31
|
|||
|
|
8003506: 18ba adds r2, r7, r2
|
|||
|
|
8003508: 7812 ldrb r2, [r2, #0]
|
|||
|
|
800350a: 3207 adds r2, #7
|
|||
|
|
800350c: 4997 ldr r1, [pc, #604] ; (800376c <HAL_UART_RxCpltCallback+0xeb0>)
|
|||
|
|
800350e: 5c8a ldrb r2, [r1, r2]
|
|||
|
|
8003510: 701a strb r2, [r3, #0]
|
|||
|
|
for(j = 0; j < iobuf[6]; j++)
|
|||
|
|
8003512: 231f movs r3, #31
|
|||
|
|
8003514: 18fb adds r3, r7, r3
|
|||
|
|
8003516: 781a ldrb r2, [r3, #0]
|
|||
|
|
8003518: 231f movs r3, #31
|
|||
|
|
800351a: 18fb adds r3, r7, r3
|
|||
|
|
800351c: 3201 adds r2, #1
|
|||
|
|
800351e: 701a strb r2, [r3, #0]
|
|||
|
|
8003520: 4b92 ldr r3, [pc, #584] ; (800376c <HAL_UART_RxCpltCallback+0xeb0>)
|
|||
|
|
8003522: 799b ldrb r3, [r3, #6]
|
|||
|
|
8003524: 221f movs r2, #31
|
|||
|
|
8003526: 18ba adds r2, r7, r2
|
|||
|
|
8003528: 7812 ldrb r2, [r2, #0]
|
|||
|
|
800352a: 429a cmp r2, r3
|
|||
|
|
800352c: d3e1 bcc.n 80034f2 <HAL_UART_RxCpltCallback+0xc36>
|
|||
|
|
if((pardata.IIN > ICP) || (pardata.IKU > Ku1000) || (pardata.IFV > Hp10) || (pardata.IFN > Lp100000) || (pardata.VAL > mV))
|
|||
|
|
800352e: 4b95 ldr r3, [pc, #596] ; (8003784 <HAL_UART_RxCpltCallback+0xec8>)
|
|||
|
|
8003530: 88db ldrh r3, [r3, #6]
|
|||
|
|
8003532: b29b uxth r3, r3
|
|||
|
|
8003534: 2b01 cmp r3, #1
|
|||
|
|
8003536: d813 bhi.n 8003560 <HAL_UART_RxCpltCallback+0xca4>
|
|||
|
|
8003538: 4b92 ldr r3, [pc, #584] ; (8003784 <HAL_UART_RxCpltCallback+0xec8>)
|
|||
|
|
800353a: 899b ldrh r3, [r3, #12]
|
|||
|
|
800353c: b29b uxth r3, r3
|
|||
|
|
800353e: 2b0c cmp r3, #12
|
|||
|
|
8003540: d80e bhi.n 8003560 <HAL_UART_RxCpltCallback+0xca4>
|
|||
|
|
8003542: 4b90 ldr r3, [pc, #576] ; (8003784 <HAL_UART_RxCpltCallback+0xec8>)
|
|||
|
|
8003544: 891b ldrh r3, [r3, #8]
|
|||
|
|
8003546: b29b uxth r3, r3
|
|||
|
|
8003548: 2b04 cmp r3, #4
|
|||
|
|
800354a: d809 bhi.n 8003560 <HAL_UART_RxCpltCallback+0xca4>
|
|||
|
|
800354c: 4b8d ldr r3, [pc, #564] ; (8003784 <HAL_UART_RxCpltCallback+0xec8>)
|
|||
|
|
800354e: 895b ldrh r3, [r3, #10]
|
|||
|
|
8003550: b29b uxth r3, r3
|
|||
|
|
8003552: 2b07 cmp r3, #7
|
|||
|
|
8003554: d804 bhi.n 8003560 <HAL_UART_RxCpltCallback+0xca4>
|
|||
|
|
8003556: 4b8b ldr r3, [pc, #556] ; (8003784 <HAL_UART_RxCpltCallback+0xec8>)
|
|||
|
|
8003558: 8b1b ldrh r3, [r3, #24]
|
|||
|
|
800355a: b29b uxth r3, r3
|
|||
|
|
800355c: 2b08 cmp r3, #8
|
|||
|
|
800355e: d914 bls.n 800358a <HAL_UART_RxCpltCallback+0xcce>
|
|||
|
|
rdCorr();
|
|||
|
|
8003560: f7fe fc62 bl 8001e28 <rdCorr>
|
|||
|
|
tx[0] = iobuf[0];
|
|||
|
|
8003564: 4b81 ldr r3, [pc, #516] ; (800376c <HAL_UART_RxCpltCallback+0xeb0>)
|
|||
|
|
8003566: 781a ldrb r2, [r3, #0]
|
|||
|
|
8003568: 4b81 ldr r3, [pc, #516] ; (8003770 <HAL_UART_RxCpltCallback+0xeb4>)
|
|||
|
|
800356a: 701a strb r2, [r3, #0]
|
|||
|
|
tx[1] = (iobuf[1] | 0x80);
|
|||
|
|
800356c: 4b7f ldr r3, [pc, #508] ; (800376c <HAL_UART_RxCpltCallback+0xeb0>)
|
|||
|
|
800356e: 785b ldrb r3, [r3, #1]
|
|||
|
|
8003570: 2280 movs r2, #128 ; 0x80
|
|||
|
|
8003572: 4252 negs r2, r2
|
|||
|
|
8003574: 4313 orrs r3, r2
|
|||
|
|
8003576: b2da uxtb r2, r3
|
|||
|
|
8003578: 4b7d ldr r3, [pc, #500] ; (8003770 <HAL_UART_RxCpltCallback+0xeb4>)
|
|||
|
|
800357a: 705a strb r2, [r3, #1]
|
|||
|
|
tx[2] = 0x03;
|
|||
|
|
800357c: 4b7c ldr r3, [pc, #496] ; (8003770 <HAL_UART_RxCpltCallback+0xeb4>)
|
|||
|
|
800357e: 2203 movs r2, #3
|
|||
|
|
8003580: 709a strb r2, [r3, #2]
|
|||
|
|
strtOut(3);
|
|||
|
|
8003582: 2003 movs r0, #3
|
|||
|
|
8003584: f7ff f8a8 bl 80026d8 <strtOut>
|
|||
|
|
8003588: e026 b.n 80035d8 <HAL_UART_RxCpltCallback+0xd1c>
|
|||
|
|
needSave = true;
|
|||
|
|
800358a: 4b7f ldr r3, [pc, #508] ; (8003788 <HAL_UART_RxCpltCallback+0xecc>)
|
|||
|
|
800358c: 2201 movs r2, #1
|
|||
|
|
800358e: 701a strb r2, [r3, #0]
|
|||
|
|
if(iobuf[0])
|
|||
|
|
8003590: 4b76 ldr r3, [pc, #472] ; (800376c <HAL_UART_RxCpltCallback+0xeb0>)
|
|||
|
|
8003592: 781b ldrb r3, [r3, #0]
|
|||
|
|
8003594: 2b00 cmp r3, #0
|
|||
|
|
8003596: d100 bne.n 800359a <HAL_UART_RxCpltCallback+0xcde>
|
|||
|
|
8003598: e355 b.n 8003c46 <HAL_UART_RxCpltCallback+0x138a>
|
|||
|
|
for(j = 0; j < 6; j++) {
|
|||
|
|
800359a: 231f movs r3, #31
|
|||
|
|
800359c: 18fb adds r3, r7, r3
|
|||
|
|
800359e: 2200 movs r2, #0
|
|||
|
|
80035a0: 701a strb r2, [r3, #0]
|
|||
|
|
80035a2: e010 b.n 80035c6 <HAL_UART_RxCpltCallback+0xd0a>
|
|||
|
|
tx[j] = iobuf[j];
|
|||
|
|
80035a4: 231f movs r3, #31
|
|||
|
|
80035a6: 18fb adds r3, r7, r3
|
|||
|
|
80035a8: 781b ldrb r3, [r3, #0]
|
|||
|
|
80035aa: 221f movs r2, #31
|
|||
|
|
80035ac: 18ba adds r2, r7, r2
|
|||
|
|
80035ae: 7812 ldrb r2, [r2, #0]
|
|||
|
|
80035b0: 496e ldr r1, [pc, #440] ; (800376c <HAL_UART_RxCpltCallback+0xeb0>)
|
|||
|
|
80035b2: 5c89 ldrb r1, [r1, r2]
|
|||
|
|
80035b4: 4a6e ldr r2, [pc, #440] ; (8003770 <HAL_UART_RxCpltCallback+0xeb4>)
|
|||
|
|
80035b6: 54d1 strb r1, [r2, r3]
|
|||
|
|
for(j = 0; j < 6; j++) {
|
|||
|
|
80035b8: 231f movs r3, #31
|
|||
|
|
80035ba: 18fb adds r3, r7, r3
|
|||
|
|
80035bc: 781a ldrb r2, [r3, #0]
|
|||
|
|
80035be: 231f movs r3, #31
|
|||
|
|
80035c0: 18fb adds r3, r7, r3
|
|||
|
|
80035c2: 3201 adds r2, #1
|
|||
|
|
80035c4: 701a strb r2, [r3, #0]
|
|||
|
|
80035c6: 231f movs r3, #31
|
|||
|
|
80035c8: 18fb adds r3, r7, r3
|
|||
|
|
80035ca: 781b ldrb r3, [r3, #0]
|
|||
|
|
80035cc: 2b05 cmp r3, #5
|
|||
|
|
80035ce: d9e9 bls.n 80035a4 <HAL_UART_RxCpltCallback+0xce8>
|
|||
|
|
strtOut(6);
|
|||
|
|
80035d0: 2006 movs r0, #6
|
|||
|
|
80035d2: f7ff f881 bl 80026d8 <strtOut>
|
|||
|
|
break;
|
|||
|
|
80035d6: e336 b.n 8003c46 <HAL_UART_RxCpltCallback+0x138a>
|
|||
|
|
80035d8: e335 b.n 8003c46 <HAL_UART_RxCpltCallback+0x138a>
|
|||
|
|
tmp = 3;
|
|||
|
|
80035da: 231e movs r3, #30
|
|||
|
|
80035dc: 18fb adds r3, r7, r3
|
|||
|
|
80035de: 2203 movs r2, #3
|
|||
|
|
80035e0: 701a strb r2, [r3, #0]
|
|||
|
|
tmp1 = 2;
|
|||
|
|
80035e2: 231d movs r3, #29
|
|||
|
|
80035e4: 18fb adds r3, r7, r3
|
|||
|
|
80035e6: 2202 movs r2, #2
|
|||
|
|
80035e8: 701a strb r2, [r3, #0]
|
|||
|
|
if(addr.sh == 7002)
|
|||
|
|
80035ea: 2310 movs r3, #16
|
|||
|
|
80035ec: 18fb adds r3, r7, r3
|
|||
|
|
80035ee: 881b ldrh r3, [r3, #0]
|
|||
|
|
80035f0: 4a66 ldr r2, [pc, #408] ; (800378c <HAL_UART_RxCpltCallback+0xed0>)
|
|||
|
|
80035f2: 4293 cmp r3, r2
|
|||
|
|
80035f4: d10a bne.n 800360c <HAL_UART_RxCpltCallback+0xd50>
|
|||
|
|
tmp <<= 1;
|
|||
|
|
80035f6: 231e movs r3, #30
|
|||
|
|
80035f8: 18fa adds r2, r7, r3
|
|||
|
|
80035fa: 231e movs r3, #30
|
|||
|
|
80035fc: 18fb adds r3, r7, r3
|
|||
|
|
80035fe: 781b ldrb r3, [r3, #0]
|
|||
|
|
8003600: 18db adds r3, r3, r3
|
|||
|
|
8003602: 7013 strb r3, [r2, #0]
|
|||
|
|
tmp1 = 1;
|
|||
|
|
8003604: 231d movs r3, #29
|
|||
|
|
8003606: 18fb adds r3, r7, r3
|
|||
|
|
8003608: 2201 movs r2, #1
|
|||
|
|
800360a: 701a strb r2, [r3, #0]
|
|||
|
|
if((regs.ch[0] > tmp) || (iobuf[6] != (regs.ch[0] << tmp1)))
|
|||
|
|
800360c: 230c movs r3, #12
|
|||
|
|
800360e: 18fb adds r3, r7, r3
|
|||
|
|
8003610: 781b ldrb r3, [r3, #0]
|
|||
|
|
8003612: 221e movs r2, #30
|
|||
|
|
8003614: 18ba adds r2, r7, r2
|
|||
|
|
8003616: 7812 ldrb r2, [r2, #0]
|
|||
|
|
8003618: 429a cmp r2, r3
|
|||
|
|
800361a: d30d bcc.n 8003638 <HAL_UART_RxCpltCallback+0xd7c>
|
|||
|
|
800361c: 4b53 ldr r3, [pc, #332] ; (800376c <HAL_UART_RxCpltCallback+0xeb0>)
|
|||
|
|
800361e: 799b ldrb r3, [r3, #6]
|
|||
|
|
8003620: 001a movs r2, r3
|
|||
|
|
8003622: 230c movs r3, #12
|
|||
|
|
8003624: 18fb adds r3, r7, r3
|
|||
|
|
8003626: 781b ldrb r3, [r3, #0]
|
|||
|
|
8003628: 0019 movs r1, r3
|
|||
|
|
800362a: 231d movs r3, #29
|
|||
|
|
800362c: 18fb adds r3, r7, r3
|
|||
|
|
800362e: 781b ldrb r3, [r3, #0]
|
|||
|
|
8003630: 4099 lsls r1, r3
|
|||
|
|
8003632: 000b movs r3, r1
|
|||
|
|
8003634: 429a cmp r2, r3
|
|||
|
|
8003636: d012 beq.n 800365e <HAL_UART_RxCpltCallback+0xda2>
|
|||
|
|
tx[0] = iobuf[0];
|
|||
|
|
8003638: 4b4c ldr r3, [pc, #304] ; (800376c <HAL_UART_RxCpltCallback+0xeb0>)
|
|||
|
|
800363a: 781a ldrb r2, [r3, #0]
|
|||
|
|
800363c: 4b4c ldr r3, [pc, #304] ; (8003770 <HAL_UART_RxCpltCallback+0xeb4>)
|
|||
|
|
800363e: 701a strb r2, [r3, #0]
|
|||
|
|
tx[1] |= 0x80; //модификация кода функции на ошибку
|
|||
|
|
8003640: 4b4b ldr r3, [pc, #300] ; (8003770 <HAL_UART_RxCpltCallback+0xeb4>)
|
|||
|
|
8003642: 785b ldrb r3, [r3, #1]
|
|||
|
|
8003644: 2280 movs r2, #128 ; 0x80
|
|||
|
|
8003646: 4252 negs r2, r2
|
|||
|
|
8003648: 4313 orrs r3, r2
|
|||
|
|
800364a: b2da uxtb r2, r3
|
|||
|
|
800364c: 4b48 ldr r3, [pc, #288] ; (8003770 <HAL_UART_RxCpltCallback+0xeb4>)
|
|||
|
|
800364e: 705a strb r2, [r3, #1]
|
|||
|
|
tx[2] = 0x03; //Адрес данных указанный в запросе не доступен
|
|||
|
|
8003650: 4b47 ldr r3, [pc, #284] ; (8003770 <HAL_UART_RxCpltCallback+0xeb4>)
|
|||
|
|
8003652: 2203 movs r2, #3
|
|||
|
|
8003654: 709a strb r2, [r3, #2]
|
|||
|
|
strtOut(3);
|
|||
|
|
8003656: 2003 movs r0, #3
|
|||
|
|
8003658: f7ff f83e bl 80026d8 <strtOut>
|
|||
|
|
break;
|
|||
|
|
800365c: e2f5 b.n 8003c4a <HAL_UART_RxCpltCallback+0x138e>
|
|||
|
|
j = 8 + iobuf[6];
|
|||
|
|
800365e: 4b43 ldr r3, [pc, #268] ; (800376c <HAL_UART_RxCpltCallback+0xeb0>)
|
|||
|
|
8003660: 799a ldrb r2, [r3, #6]
|
|||
|
|
8003662: 231f movs r3, #31
|
|||
|
|
8003664: 18fb adds r3, r7, r3
|
|||
|
|
8003666: 3208 adds r2, #8
|
|||
|
|
8003668: 701a strb r2, [r3, #0]
|
|||
|
|
if(iolen > j)
|
|||
|
|
800366a: 4b43 ldr r3, [pc, #268] ; (8003778 <HAL_UART_RxCpltCallback+0xebc>)
|
|||
|
|
800366c: 781b ldrb r3, [r3, #0]
|
|||
|
|
800366e: 221f movs r2, #31
|
|||
|
|
8003670: 18ba adds r2, r7, r2
|
|||
|
|
8003672: 7812 ldrb r2, [r2, #0]
|
|||
|
|
8003674: 429a cmp r2, r3
|
|||
|
|
8003676: d300 bcc.n 800367a <HAL_UART_RxCpltCallback+0xdbe>
|
|||
|
|
8003678: e2e7 b.n 8003c4a <HAL_UART_RxCpltCallback+0x138e>
|
|||
|
|
crc.ch[0] = iobuf[j - 1];
|
|||
|
|
800367a: 231f movs r3, #31
|
|||
|
|
800367c: 18fb adds r3, r7, r3
|
|||
|
|
800367e: 781b ldrb r3, [r3, #0]
|
|||
|
|
8003680: 3b01 subs r3, #1
|
|||
|
|
8003682: 4a3a ldr r2, [pc, #232] ; (800376c <HAL_UART_RxCpltCallback+0xeb0>)
|
|||
|
|
8003684: 5cd2 ldrb r2, [r2, r3]
|
|||
|
|
8003686: 2314 movs r3, #20
|
|||
|
|
8003688: 18fb adds r3, r7, r3
|
|||
|
|
800368a: 701a strb r2, [r3, #0]
|
|||
|
|
crc.ch[1] = iobuf[j];
|
|||
|
|
800368c: 231f movs r3, #31
|
|||
|
|
800368e: 18fb adds r3, r7, r3
|
|||
|
|
8003690: 781b ldrb r3, [r3, #0]
|
|||
|
|
8003692: 4a36 ldr r2, [pc, #216] ; (800376c <HAL_UART_RxCpltCallback+0xeb0>)
|
|||
|
|
8003694: 5cd2 ldrb r2, [r2, r3]
|
|||
|
|
8003696: 2314 movs r3, #20
|
|||
|
|
8003698: 18fb adds r3, r7, r3
|
|||
|
|
800369a: 705a strb r2, [r3, #1]
|
|||
|
|
if(crc.sh == Crc16(j - 1))
|
|||
|
|
800369c: 2314 movs r3, #20
|
|||
|
|
800369e: 18fb adds r3, r7, r3
|
|||
|
|
80036a0: 881c ldrh r4, [r3, #0]
|
|||
|
|
80036a2: 231f movs r3, #31
|
|||
|
|
80036a4: 18fb adds r3, r7, r3
|
|||
|
|
80036a6: 781b ldrb r3, [r3, #0]
|
|||
|
|
80036a8: b29b uxth r3, r3
|
|||
|
|
80036aa: 3b01 subs r3, #1
|
|||
|
|
80036ac: b29b uxth r3, r3
|
|||
|
|
80036ae: 0018 movs r0, r3
|
|||
|
|
80036b0: f7ff f85e bl 8002770 <Crc16>
|
|||
|
|
80036b4: 0003 movs r3, r0
|
|||
|
|
80036b6: 429c cmp r4, r3
|
|||
|
|
80036b8: d000 beq.n 80036bc <HAL_UART_RxCpltCallback+0xe00>
|
|||
|
|
80036ba: e2c6 b.n 8003c4a <HAL_UART_RxCpltCallback+0x138e>
|
|||
|
|
if(iobuf[6] == 4)
|
|||
|
|
80036bc: 4b2b ldr r3, [pc, #172] ; (800376c <HAL_UART_RxCpltCallback+0xeb0>)
|
|||
|
|
80036be: 799b ldrb r3, [r3, #6]
|
|||
|
|
80036c0: 2b04 cmp r3, #4
|
|||
|
|
80036c2: d128 bne.n 8003716 <HAL_UART_RxCpltCallback+0xe5a>
|
|||
|
|
for(j = 0; j < 4; j++)
|
|||
|
|
80036c4: 231f movs r3, #31
|
|||
|
|
80036c6: 18fb adds r3, r7, r3
|
|||
|
|
80036c8: 2200 movs r2, #0
|
|||
|
|
80036ca: 701a strb r2, [r3, #0]
|
|||
|
|
80036cc: e014 b.n 80036f8 <HAL_UART_RxCpltCallback+0xe3c>
|
|||
|
|
f.ch[3 - j] = iobuf[7 + j];
|
|||
|
|
80036ce: 231f movs r3, #31
|
|||
|
|
80036d0: 18fb adds r3, r7, r3
|
|||
|
|
80036d2: 781b ldrb r3, [r3, #0]
|
|||
|
|
80036d4: 2203 movs r2, #3
|
|||
|
|
80036d6: 1ad3 subs r3, r2, r3
|
|||
|
|
80036d8: 221f movs r2, #31
|
|||
|
|
80036da: 18ba adds r2, r7, r2
|
|||
|
|
80036dc: 7812 ldrb r2, [r2, #0]
|
|||
|
|
80036de: 3207 adds r2, #7
|
|||
|
|
80036e0: 4922 ldr r1, [pc, #136] ; (800376c <HAL_UART_RxCpltCallback+0xeb0>)
|
|||
|
|
80036e2: 5c89 ldrb r1, [r1, r2]
|
|||
|
|
80036e4: 2208 movs r2, #8
|
|||
|
|
80036e6: 18ba adds r2, r7, r2
|
|||
|
|
80036e8: 54d1 strb r1, [r2, r3]
|
|||
|
|
for(j = 0; j < 4; j++)
|
|||
|
|
80036ea: 231f movs r3, #31
|
|||
|
|
80036ec: 18fb adds r3, r7, r3
|
|||
|
|
80036ee: 781a ldrb r2, [r3, #0]
|
|||
|
|
80036f0: 231f movs r3, #31
|
|||
|
|
80036f2: 18fb adds r3, r7, r3
|
|||
|
|
80036f4: 3201 adds r2, #1
|
|||
|
|
80036f6: 701a strb r2, [r3, #0]
|
|||
|
|
80036f8: 231f movs r3, #31
|
|||
|
|
80036fa: 18fb adds r3, r7, r3
|
|||
|
|
80036fc: 781b ldrb r3, [r3, #0]
|
|||
|
|
80036fe: 2b03 cmp r3, #3
|
|||
|
|
8003700: d9e5 bls.n 80036ce <HAL_UART_RxCpltCallback+0xe12>
|
|||
|
|
pardata.KCOND = f.fl;
|
|||
|
|
8003702: 68ba ldr r2, [r7, #8]
|
|||
|
|
8003704: 4b1f ldr r3, [pc, #124] ; (8003784 <HAL_UART_RxCpltCallback+0xec8>)
|
|||
|
|
8003706: 61da str r2, [r3, #28]
|
|||
|
|
needSave = true;
|
|||
|
|
8003708: 4b1f ldr r3, [pc, #124] ; (8003788 <HAL_UART_RxCpltCallback+0xecc>)
|
|||
|
|
800370a: 2201 movs r2, #1
|
|||
|
|
800370c: 701a strb r2, [r3, #0]
|
|||
|
|
strtOut(6);
|
|||
|
|
800370e: 2006 movs r0, #6
|
|||
|
|
8003710: f7fe ffe2 bl 80026d8 <strtOut>
|
|||
|
|
break;
|
|||
|
|
8003714: e299 b.n 8003c4a <HAL_UART_RxCpltCallback+0x138e>
|
|||
|
|
if(iobuf[6] == 8)
|
|||
|
|
8003716: 4b15 ldr r3, [pc, #84] ; (800376c <HAL_UART_RxCpltCallback+0xeb0>)
|
|||
|
|
8003718: 799b ldrb r3, [r3, #6]
|
|||
|
|
800371a: 2b08 cmp r3, #8
|
|||
|
|
800371c: d15c bne.n 80037d8 <HAL_UART_RxCpltCallback+0xf1c>
|
|||
|
|
for(j = 0; j < 4; j++)
|
|||
|
|
800371e: 231f movs r3, #31
|
|||
|
|
8003720: 18fb adds r3, r7, r3
|
|||
|
|
8003722: 2200 movs r2, #0
|
|||
|
|
8003724: 701a strb r2, [r3, #0]
|
|||
|
|
8003726: e014 b.n 8003752 <HAL_UART_RxCpltCallback+0xe96>
|
|||
|
|
f.ch[3 - j] = iobuf[7 + j];
|
|||
|
|
8003728: 231f movs r3, #31
|
|||
|
|
800372a: 18fb adds r3, r7, r3
|
|||
|
|
800372c: 781b ldrb r3, [r3, #0]
|
|||
|
|
800372e: 2203 movs r2, #3
|
|||
|
|
8003730: 1ad3 subs r3, r2, r3
|
|||
|
|
8003732: 221f movs r2, #31
|
|||
|
|
8003734: 18ba adds r2, r7, r2
|
|||
|
|
8003736: 7812 ldrb r2, [r2, #0]
|
|||
|
|
8003738: 3207 adds r2, #7
|
|||
|
|
800373a: 490c ldr r1, [pc, #48] ; (800376c <HAL_UART_RxCpltCallback+0xeb0>)
|
|||
|
|
800373c: 5c89 ldrb r1, [r1, r2]
|
|||
|
|
800373e: 2208 movs r2, #8
|
|||
|
|
8003740: 18ba adds r2, r7, r2
|
|||
|
|
8003742: 54d1 strb r1, [r2, r3]
|
|||
|
|
for(j = 0; j < 4; j++)
|
|||
|
|
8003744: 231f movs r3, #31
|
|||
|
|
8003746: 18fb adds r3, r7, r3
|
|||
|
|
8003748: 781a ldrb r2, [r3, #0]
|
|||
|
|
800374a: 231f movs r3, #31
|
|||
|
|
800374c: 18fb adds r3, r7, r3
|
|||
|
|
800374e: 3201 adds r2, #1
|
|||
|
|
8003750: 701a strb r2, [r3, #0]
|
|||
|
|
8003752: 231f movs r3, #31
|
|||
|
|
8003754: 18fb adds r3, r7, r3
|
|||
|
|
8003756: 781b ldrb r3, [r3, #0]
|
|||
|
|
8003758: 2b03 cmp r3, #3
|
|||
|
|
800375a: d9e5 bls.n 8003728 <HAL_UART_RxCpltCallback+0xe6c>
|
|||
|
|
pardata.KCOND = f.fl;
|
|||
|
|
800375c: 68ba ldr r2, [r7, #8]
|
|||
|
|
800375e: 4b09 ldr r3, [pc, #36] ; (8003784 <HAL_UART_RxCpltCallback+0xec8>)
|
|||
|
|
8003760: 61da str r2, [r3, #28]
|
|||
|
|
for(j = 0; j < 4; j++)
|
|||
|
|
8003762: 231f movs r3, #31
|
|||
|
|
8003764: 18fb adds r3, r7, r3
|
|||
|
|
8003766: 2200 movs r2, #0
|
|||
|
|
8003768: 701a strb r2, [r3, #0]
|
|||
|
|
800376a: e026 b.n 80037ba <HAL_UART_RxCpltCallback+0xefe>
|
|||
|
|
800376c: 2000028c .word 0x2000028c
|
|||
|
|
8003770: 20000188 .word 0x20000188
|
|||
|
|
8003774: 00001393 .word 0x00001393
|
|||
|
|
8003778: 20000035 .word 0x20000035
|
|||
|
|
800377c: ffffec77 .word 0xffffec77
|
|||
|
|
8003780: 2000009e .word 0x2000009e
|
|||
|
|
8003784: 20000098 .word 0x20000098
|
|||
|
|
8003788: 20000037 .word 0x20000037
|
|||
|
|
800378c: 00001b5a .word 0x00001b5a
|
|||
|
|
f.ch[3 - j] = iobuf[11 + j];
|
|||
|
|
8003790: 231f movs r3, #31
|
|||
|
|
8003792: 18fb adds r3, r7, r3
|
|||
|
|
8003794: 781b ldrb r3, [r3, #0]
|
|||
|
|
8003796: 2203 movs r2, #3
|
|||
|
|
8003798: 1ad3 subs r3, r2, r3
|
|||
|
|
800379a: 221f movs r2, #31
|
|||
|
|
800379c: 18ba adds r2, r7, r2
|
|||
|
|
800379e: 7812 ldrb r2, [r2, #0]
|
|||
|
|
80037a0: 320b adds r2, #11
|
|||
|
|
80037a2: 49df ldr r1, [pc, #892] ; (8003b20 <HAL_UART_RxCpltCallback+0x1264>)
|
|||
|
|
80037a4: 5c89 ldrb r1, [r1, r2]
|
|||
|
|
80037a6: 2208 movs r2, #8
|
|||
|
|
80037a8: 18ba adds r2, r7, r2
|
|||
|
|
80037aa: 54d1 strb r1, [r2, r3]
|
|||
|
|
for(j = 0; j < 4; j++)
|
|||
|
|
80037ac: 231f movs r3, #31
|
|||
|
|
80037ae: 18fb adds r3, r7, r3
|
|||
|
|
80037b0: 781a ldrb r2, [r3, #0]
|
|||
|
|
80037b2: 231f movs r3, #31
|
|||
|
|
80037b4: 18fb adds r3, r7, r3
|
|||
|
|
80037b6: 3201 adds r2, #1
|
|||
|
|
80037b8: 701a strb r2, [r3, #0]
|
|||
|
|
80037ba: 231f movs r3, #31
|
|||
|
|
80037bc: 18fb adds r3, r7, r3
|
|||
|
|
80037be: 781b ldrb r3, [r3, #0]
|
|||
|
|
80037c0: 2b03 cmp r3, #3
|
|||
|
|
80037c2: d9e5 bls.n 8003790 <HAL_UART_RxCpltCallback+0xed4>
|
|||
|
|
pardata.SENS = f.fl;
|
|||
|
|
80037c4: 68ba ldr r2, [r7, #8]
|
|||
|
|
80037c6: 4bd7 ldr r3, [pc, #860] ; (8003b24 <HAL_UART_RxCpltCallback+0x1268>)
|
|||
|
|
80037c8: 621a str r2, [r3, #32]
|
|||
|
|
needSave = true;
|
|||
|
|
80037ca: 4bd7 ldr r3, [pc, #860] ; (8003b28 <HAL_UART_RxCpltCallback+0x126c>)
|
|||
|
|
80037cc: 2201 movs r2, #1
|
|||
|
|
80037ce: 701a strb r2, [r3, #0]
|
|||
|
|
strtOut(6);
|
|||
|
|
80037d0: 2006 movs r0, #6
|
|||
|
|
80037d2: f7fe ff81 bl 80026d8 <strtOut>
|
|||
|
|
break;
|
|||
|
|
80037d6: e238 b.n 8003c4a <HAL_UART_RxCpltCallback+0x138e>
|
|||
|
|
if(iobuf[6] == 12)
|
|||
|
|
80037d8: 4bd1 ldr r3, [pc, #836] ; (8003b20 <HAL_UART_RxCpltCallback+0x1264>)
|
|||
|
|
80037da: 799b ldrb r3, [r3, #6]
|
|||
|
|
80037dc: 2b0c cmp r3, #12
|
|||
|
|
80037de: d16c bne.n 80038ba <HAL_UART_RxCpltCallback+0xffe>
|
|||
|
|
for(j = 0; j < 4; j++)
|
|||
|
|
80037e0: 231f movs r3, #31
|
|||
|
|
80037e2: 18fb adds r3, r7, r3
|
|||
|
|
80037e4: 2200 movs r2, #0
|
|||
|
|
80037e6: 701a strb r2, [r3, #0]
|
|||
|
|
80037e8: e014 b.n 8003814 <HAL_UART_RxCpltCallback+0xf58>
|
|||
|
|
f.ch[3 - j] = iobuf[7 + j];
|
|||
|
|
80037ea: 231f movs r3, #31
|
|||
|
|
80037ec: 18fb adds r3, r7, r3
|
|||
|
|
80037ee: 781b ldrb r3, [r3, #0]
|
|||
|
|
80037f0: 2203 movs r2, #3
|
|||
|
|
80037f2: 1ad3 subs r3, r2, r3
|
|||
|
|
80037f4: 221f movs r2, #31
|
|||
|
|
80037f6: 18ba adds r2, r7, r2
|
|||
|
|
80037f8: 7812 ldrb r2, [r2, #0]
|
|||
|
|
80037fa: 3207 adds r2, #7
|
|||
|
|
80037fc: 49c8 ldr r1, [pc, #800] ; (8003b20 <HAL_UART_RxCpltCallback+0x1264>)
|
|||
|
|
80037fe: 5c89 ldrb r1, [r1, r2]
|
|||
|
|
8003800: 2208 movs r2, #8
|
|||
|
|
8003802: 18ba adds r2, r7, r2
|
|||
|
|
8003804: 54d1 strb r1, [r2, r3]
|
|||
|
|
for(j = 0; j < 4; j++)
|
|||
|
|
8003806: 231f movs r3, #31
|
|||
|
|
8003808: 18fb adds r3, r7, r3
|
|||
|
|
800380a: 781a ldrb r2, [r3, #0]
|
|||
|
|
800380c: 231f movs r3, #31
|
|||
|
|
800380e: 18fb adds r3, r7, r3
|
|||
|
|
8003810: 3201 adds r2, #1
|
|||
|
|
8003812: 701a strb r2, [r3, #0]
|
|||
|
|
8003814: 231f movs r3, #31
|
|||
|
|
8003816: 18fb adds r3, r7, r3
|
|||
|
|
8003818: 781b ldrb r3, [r3, #0]
|
|||
|
|
800381a: 2b03 cmp r3, #3
|
|||
|
|
800381c: d9e5 bls.n 80037ea <HAL_UART_RxCpltCallback+0xf2e>
|
|||
|
|
pardata.KCOND = f.fl;
|
|||
|
|
800381e: 68ba ldr r2, [r7, #8]
|
|||
|
|
8003820: 4bc0 ldr r3, [pc, #768] ; (8003b24 <HAL_UART_RxCpltCallback+0x1268>)
|
|||
|
|
8003822: 61da str r2, [r3, #28]
|
|||
|
|
for(j = 0; j < 4; j++)
|
|||
|
|
8003824: 231f movs r3, #31
|
|||
|
|
8003826: 18fb adds r3, r7, r3
|
|||
|
|
8003828: 2200 movs r2, #0
|
|||
|
|
800382a: 701a strb r2, [r3, #0]
|
|||
|
|
800382c: e014 b.n 8003858 <HAL_UART_RxCpltCallback+0xf9c>
|
|||
|
|
f.ch[3 - j] = iobuf[11 + j];
|
|||
|
|
800382e: 231f movs r3, #31
|
|||
|
|
8003830: 18fb adds r3, r7, r3
|
|||
|
|
8003832: 781b ldrb r3, [r3, #0]
|
|||
|
|
8003834: 2203 movs r2, #3
|
|||
|
|
8003836: 1ad3 subs r3, r2, r3
|
|||
|
|
8003838: 221f movs r2, #31
|
|||
|
|
800383a: 18ba adds r2, r7, r2
|
|||
|
|
800383c: 7812 ldrb r2, [r2, #0]
|
|||
|
|
800383e: 320b adds r2, #11
|
|||
|
|
8003840: 49b7 ldr r1, [pc, #732] ; (8003b20 <HAL_UART_RxCpltCallback+0x1264>)
|
|||
|
|
8003842: 5c89 ldrb r1, [r1, r2]
|
|||
|
|
8003844: 2208 movs r2, #8
|
|||
|
|
8003846: 18ba adds r2, r7, r2
|
|||
|
|
8003848: 54d1 strb r1, [r2, r3]
|
|||
|
|
for(j = 0; j < 4; j++)
|
|||
|
|
800384a: 231f movs r3, #31
|
|||
|
|
800384c: 18fb adds r3, r7, r3
|
|||
|
|
800384e: 781a ldrb r2, [r3, #0]
|
|||
|
|
8003850: 231f movs r3, #31
|
|||
|
|
8003852: 18fb adds r3, r7, r3
|
|||
|
|
8003854: 3201 adds r2, #1
|
|||
|
|
8003856: 701a strb r2, [r3, #0]
|
|||
|
|
8003858: 231f movs r3, #31
|
|||
|
|
800385a: 18fb adds r3, r7, r3
|
|||
|
|
800385c: 781b ldrb r3, [r3, #0]
|
|||
|
|
800385e: 2b03 cmp r3, #3
|
|||
|
|
8003860: d9e5 bls.n 800382e <HAL_UART_RxCpltCallback+0xf72>
|
|||
|
|
pardata.SENS = f.fl;
|
|||
|
|
8003862: 68ba ldr r2, [r7, #8]
|
|||
|
|
8003864: 4baf ldr r3, [pc, #700] ; (8003b24 <HAL_UART_RxCpltCallback+0x1268>)
|
|||
|
|
8003866: 621a str r2, [r3, #32]
|
|||
|
|
for(j = 0; j < 4; j++)
|
|||
|
|
8003868: 231f movs r3, #31
|
|||
|
|
800386a: 18fb adds r3, r7, r3
|
|||
|
|
800386c: 2200 movs r2, #0
|
|||
|
|
800386e: 701a strb r2, [r3, #0]
|
|||
|
|
8003870: e014 b.n 800389c <HAL_UART_RxCpltCallback+0xfe0>
|
|||
|
|
f.ch[3 - j] = iobuf[15 + j];
|
|||
|
|
8003872: 231f movs r3, #31
|
|||
|
|
8003874: 18fb adds r3, r7, r3
|
|||
|
|
8003876: 781b ldrb r3, [r3, #0]
|
|||
|
|
8003878: 2203 movs r2, #3
|
|||
|
|
800387a: 1ad3 subs r3, r2, r3
|
|||
|
|
800387c: 221f movs r2, #31
|
|||
|
|
800387e: 18ba adds r2, r7, r2
|
|||
|
|
8003880: 7812 ldrb r2, [r2, #0]
|
|||
|
|
8003882: 320f adds r2, #15
|
|||
|
|
8003884: 49a6 ldr r1, [pc, #664] ; (8003b20 <HAL_UART_RxCpltCallback+0x1264>)
|
|||
|
|
8003886: 5c89 ldrb r1, [r1, r2]
|
|||
|
|
8003888: 2208 movs r2, #8
|
|||
|
|
800388a: 18ba adds r2, r7, r2
|
|||
|
|
800388c: 54d1 strb r1, [r2, r3]
|
|||
|
|
for(j = 0; j < 4; j++)
|
|||
|
|
800388e: 231f movs r3, #31
|
|||
|
|
8003890: 18fb adds r3, r7, r3
|
|||
|
|
8003892: 781a ldrb r2, [r3, #0]
|
|||
|
|
8003894: 231f movs r3, #31
|
|||
|
|
8003896: 18fb adds r3, r7, r3
|
|||
|
|
8003898: 3201 adds r2, #1
|
|||
|
|
800389a: 701a strb r2, [r3, #0]
|
|||
|
|
800389c: 231f movs r3, #31
|
|||
|
|
800389e: 18fb adds r3, r7, r3
|
|||
|
|
80038a0: 781b ldrb r3, [r3, #0]
|
|||
|
|
80038a2: 2b03 cmp r3, #3
|
|||
|
|
80038a4: d9e5 bls.n 8003872 <HAL_UART_RxCpltCallback+0xfb6>
|
|||
|
|
pardata.ACCEL = f.fl;
|
|||
|
|
80038a6: 68ba ldr r2, [r7, #8]
|
|||
|
|
80038a8: 4b9e ldr r3, [pc, #632] ; (8003b24 <HAL_UART_RxCpltCallback+0x1268>)
|
|||
|
|
80038aa: 625a str r2, [r3, #36] ; 0x24
|
|||
|
|
needSave = true;
|
|||
|
|
80038ac: 4b9e ldr r3, [pc, #632] ; (8003b28 <HAL_UART_RxCpltCallback+0x126c>)
|
|||
|
|
80038ae: 2201 movs r2, #1
|
|||
|
|
80038b0: 701a strb r2, [r3, #0]
|
|||
|
|
strtOut(6);
|
|||
|
|
80038b2: 2006 movs r0, #6
|
|||
|
|
80038b4: f7fe ff10 bl 80026d8 <strtOut>
|
|||
|
|
break;
|
|||
|
|
80038b8: e1c7 b.n 8003c4a <HAL_UART_RxCpltCallback+0x138e>
|
|||
|
|
tx[0] = iobuf[0];
|
|||
|
|
80038ba: 4b99 ldr r3, [pc, #612] ; (8003b20 <HAL_UART_RxCpltCallback+0x1264>)
|
|||
|
|
80038bc: 781a ldrb r2, [r3, #0]
|
|||
|
|
80038be: 4b9b ldr r3, [pc, #620] ; (8003b2c <HAL_UART_RxCpltCallback+0x1270>)
|
|||
|
|
80038c0: 701a strb r2, [r3, #0]
|
|||
|
|
tx[1] |= 0x80; //модификация кода функции на ошибку
|
|||
|
|
80038c2: 4b9a ldr r3, [pc, #616] ; (8003b2c <HAL_UART_RxCpltCallback+0x1270>)
|
|||
|
|
80038c4: 785b ldrb r3, [r3, #1]
|
|||
|
|
80038c6: 2280 movs r2, #128 ; 0x80
|
|||
|
|
80038c8: 4252 negs r2, r2
|
|||
|
|
80038ca: 4313 orrs r3, r2
|
|||
|
|
80038cc: b2da uxtb r2, r3
|
|||
|
|
80038ce: 4b97 ldr r3, [pc, #604] ; (8003b2c <HAL_UART_RxCpltCallback+0x1270>)
|
|||
|
|
80038d0: 705a strb r2, [r3, #1]
|
|||
|
|
tx[2] = 0x03; //Адрес данных указанный в запросе не доступен
|
|||
|
|
80038d2: 4b96 ldr r3, [pc, #600] ; (8003b2c <HAL_UART_RxCpltCallback+0x1270>)
|
|||
|
|
80038d4: 2203 movs r2, #3
|
|||
|
|
80038d6: 709a strb r2, [r3, #2]
|
|||
|
|
strtOut(3);
|
|||
|
|
80038d8: 2003 movs r0, #3
|
|||
|
|
80038da: f7fe fefd bl 80026d8 <strtOut>
|
|||
|
|
break;
|
|||
|
|
80038de: e1b4 b.n 8003c4a <HAL_UART_RxCpltCallback+0x138e>
|
|||
|
|
tmp = 2;
|
|||
|
|
80038e0: 231e movs r3, #30
|
|||
|
|
80038e2: 18fb adds r3, r7, r3
|
|||
|
|
80038e4: 2202 movs r2, #2
|
|||
|
|
80038e6: 701a strb r2, [r3, #0]
|
|||
|
|
tmp1 = 2;
|
|||
|
|
80038e8: 231d movs r3, #29
|
|||
|
|
80038ea: 18fb adds r3, r7, r3
|
|||
|
|
80038ec: 2202 movs r2, #2
|
|||
|
|
80038ee: 701a strb r2, [r3, #0]
|
|||
|
|
if(addr.sh == 7004)
|
|||
|
|
80038f0: 2310 movs r3, #16
|
|||
|
|
80038f2: 18fb adds r3, r7, r3
|
|||
|
|
80038f4: 881b ldrh r3, [r3, #0]
|
|||
|
|
80038f6: 4a8e ldr r2, [pc, #568] ; (8003b30 <HAL_UART_RxCpltCallback+0x1274>)
|
|||
|
|
80038f8: 4293 cmp r3, r2
|
|||
|
|
80038fa: d10a bne.n 8003912 <HAL_UART_RxCpltCallback+0x1056>
|
|||
|
|
tmp <<= 1;
|
|||
|
|
80038fc: 231e movs r3, #30
|
|||
|
|
80038fe: 18fa adds r2, r7, r3
|
|||
|
|
8003900: 231e movs r3, #30
|
|||
|
|
8003902: 18fb adds r3, r7, r3
|
|||
|
|
8003904: 781b ldrb r3, [r3, #0]
|
|||
|
|
8003906: 18db adds r3, r3, r3
|
|||
|
|
8003908: 7013 strb r3, [r2, #0]
|
|||
|
|
tmp1 = 1;
|
|||
|
|
800390a: 231d movs r3, #29
|
|||
|
|
800390c: 18fb adds r3, r7, r3
|
|||
|
|
800390e: 2201 movs r2, #1
|
|||
|
|
8003910: 701a strb r2, [r3, #0]
|
|||
|
|
if((regs.ch[0] > tmp) || (iobuf[6] != (regs.ch[0] << tmp1)))
|
|||
|
|
8003912: 230c movs r3, #12
|
|||
|
|
8003914: 18fb adds r3, r7, r3
|
|||
|
|
8003916: 781b ldrb r3, [r3, #0]
|
|||
|
|
8003918: 221e movs r2, #30
|
|||
|
|
800391a: 18ba adds r2, r7, r2
|
|||
|
|
800391c: 7812 ldrb r2, [r2, #0]
|
|||
|
|
800391e: 429a cmp r2, r3
|
|||
|
|
8003920: d30d bcc.n 800393e <HAL_UART_RxCpltCallback+0x1082>
|
|||
|
|
8003922: 4b7f ldr r3, [pc, #508] ; (8003b20 <HAL_UART_RxCpltCallback+0x1264>)
|
|||
|
|
8003924: 799b ldrb r3, [r3, #6]
|
|||
|
|
8003926: 001a movs r2, r3
|
|||
|
|
8003928: 230c movs r3, #12
|
|||
|
|
800392a: 18fb adds r3, r7, r3
|
|||
|
|
800392c: 781b ldrb r3, [r3, #0]
|
|||
|
|
800392e: 0019 movs r1, r3
|
|||
|
|
8003930: 231d movs r3, #29
|
|||
|
|
8003932: 18fb adds r3, r7, r3
|
|||
|
|
8003934: 781b ldrb r3, [r3, #0]
|
|||
|
|
8003936: 4099 lsls r1, r3
|
|||
|
|
8003938: 000b movs r3, r1
|
|||
|
|
800393a: 429a cmp r2, r3
|
|||
|
|
800393c: d012 beq.n 8003964 <HAL_UART_RxCpltCallback+0x10a8>
|
|||
|
|
tx[0] = iobuf[0];
|
|||
|
|
800393e: 4b78 ldr r3, [pc, #480] ; (8003b20 <HAL_UART_RxCpltCallback+0x1264>)
|
|||
|
|
8003940: 781a ldrb r2, [r3, #0]
|
|||
|
|
8003942: 4b7a ldr r3, [pc, #488] ; (8003b2c <HAL_UART_RxCpltCallback+0x1270>)
|
|||
|
|
8003944: 701a strb r2, [r3, #0]
|
|||
|
|
tx[1] |= 0x80; //модификация кода функции на ошибку
|
|||
|
|
8003946: 4b79 ldr r3, [pc, #484] ; (8003b2c <HAL_UART_RxCpltCallback+0x1270>)
|
|||
|
|
8003948: 785b ldrb r3, [r3, #1]
|
|||
|
|
800394a: 2280 movs r2, #128 ; 0x80
|
|||
|
|
800394c: 4252 negs r2, r2
|
|||
|
|
800394e: 4313 orrs r3, r2
|
|||
|
|
8003950: b2da uxtb r2, r3
|
|||
|
|
8003952: 4b76 ldr r3, [pc, #472] ; (8003b2c <HAL_UART_RxCpltCallback+0x1270>)
|
|||
|
|
8003954: 705a strb r2, [r3, #1]
|
|||
|
|
tx[2] = 0x03; //Адрес данных указанный в запросе не доступен
|
|||
|
|
8003956: 4b75 ldr r3, [pc, #468] ; (8003b2c <HAL_UART_RxCpltCallback+0x1270>)
|
|||
|
|
8003958: 2203 movs r2, #3
|
|||
|
|
800395a: 709a strb r2, [r3, #2]
|
|||
|
|
strtOut(3);
|
|||
|
|
800395c: 2003 movs r0, #3
|
|||
|
|
800395e: f7fe febb bl 80026d8 <strtOut>
|
|||
|
|
break;
|
|||
|
|
8003962: e174 b.n 8003c4e <HAL_UART_RxCpltCallback+0x1392>
|
|||
|
|
j = 8 + iobuf[6];
|
|||
|
|
8003964: 4b6e ldr r3, [pc, #440] ; (8003b20 <HAL_UART_RxCpltCallback+0x1264>)
|
|||
|
|
8003966: 799a ldrb r2, [r3, #6]
|
|||
|
|
8003968: 231f movs r3, #31
|
|||
|
|
800396a: 18fb adds r3, r7, r3
|
|||
|
|
800396c: 3208 adds r2, #8
|
|||
|
|
800396e: 701a strb r2, [r3, #0]
|
|||
|
|
if(iolen > j)
|
|||
|
|
8003970: 4b70 ldr r3, [pc, #448] ; (8003b34 <HAL_UART_RxCpltCallback+0x1278>)
|
|||
|
|
8003972: 781b ldrb r3, [r3, #0]
|
|||
|
|
8003974: 221f movs r2, #31
|
|||
|
|
8003976: 18ba adds r2, r7, r2
|
|||
|
|
8003978: 7812 ldrb r2, [r2, #0]
|
|||
|
|
800397a: 429a cmp r2, r3
|
|||
|
|
800397c: d300 bcc.n 8003980 <HAL_UART_RxCpltCallback+0x10c4>
|
|||
|
|
800397e: e166 b.n 8003c4e <HAL_UART_RxCpltCallback+0x1392>
|
|||
|
|
crc.ch[0] = iobuf[j - 1];
|
|||
|
|
8003980: 231f movs r3, #31
|
|||
|
|
8003982: 18fb adds r3, r7, r3
|
|||
|
|
8003984: 781b ldrb r3, [r3, #0]
|
|||
|
|
8003986: 3b01 subs r3, #1
|
|||
|
|
8003988: 4a65 ldr r2, [pc, #404] ; (8003b20 <HAL_UART_RxCpltCallback+0x1264>)
|
|||
|
|
800398a: 5cd2 ldrb r2, [r2, r3]
|
|||
|
|
800398c: 2314 movs r3, #20
|
|||
|
|
800398e: 18fb adds r3, r7, r3
|
|||
|
|
8003990: 701a strb r2, [r3, #0]
|
|||
|
|
crc.ch[1] = iobuf[j];
|
|||
|
|
8003992: 231f movs r3, #31
|
|||
|
|
8003994: 18fb adds r3, r7, r3
|
|||
|
|
8003996: 781b ldrb r3, [r3, #0]
|
|||
|
|
8003998: 4a61 ldr r2, [pc, #388] ; (8003b20 <HAL_UART_RxCpltCallback+0x1264>)
|
|||
|
|
800399a: 5cd2 ldrb r2, [r2, r3]
|
|||
|
|
800399c: 2314 movs r3, #20
|
|||
|
|
800399e: 18fb adds r3, r7, r3
|
|||
|
|
80039a0: 705a strb r2, [r3, #1]
|
|||
|
|
if(crc.sh == Crc16(j - 1))
|
|||
|
|
80039a2: 2314 movs r3, #20
|
|||
|
|
80039a4: 18fb adds r3, r7, r3
|
|||
|
|
80039a6: 881c ldrh r4, [r3, #0]
|
|||
|
|
80039a8: 231f movs r3, #31
|
|||
|
|
80039aa: 18fb adds r3, r7, r3
|
|||
|
|
80039ac: 781b ldrb r3, [r3, #0]
|
|||
|
|
80039ae: b29b uxth r3, r3
|
|||
|
|
80039b0: 3b01 subs r3, #1
|
|||
|
|
80039b2: b29b uxth r3, r3
|
|||
|
|
80039b4: 0018 movs r0, r3
|
|||
|
|
80039b6: f7fe fedb bl 8002770 <Crc16>
|
|||
|
|
80039ba: 0003 movs r3, r0
|
|||
|
|
80039bc: 429c cmp r4, r3
|
|||
|
|
80039be: d000 beq.n 80039c2 <HAL_UART_RxCpltCallback+0x1106>
|
|||
|
|
80039c0: e145 b.n 8003c4e <HAL_UART_RxCpltCallback+0x1392>
|
|||
|
|
if(iobuf[6] == 4)
|
|||
|
|
80039c2: 4b57 ldr r3, [pc, #348] ; (8003b20 <HAL_UART_RxCpltCallback+0x1264>)
|
|||
|
|
80039c4: 799b ldrb r3, [r3, #6]
|
|||
|
|
80039c6: 2b04 cmp r3, #4
|
|||
|
|
80039c8: d128 bne.n 8003a1c <HAL_UART_RxCpltCallback+0x1160>
|
|||
|
|
for(j = 0; j < 4; j++)
|
|||
|
|
80039ca: 231f movs r3, #31
|
|||
|
|
80039cc: 18fb adds r3, r7, r3
|
|||
|
|
80039ce: 2200 movs r2, #0
|
|||
|
|
80039d0: 701a strb r2, [r3, #0]
|
|||
|
|
80039d2: e014 b.n 80039fe <HAL_UART_RxCpltCallback+0x1142>
|
|||
|
|
f.ch[3 - j] = iobuf[7 + j];
|
|||
|
|
80039d4: 231f movs r3, #31
|
|||
|
|
80039d6: 18fb adds r3, r7, r3
|
|||
|
|
80039d8: 781b ldrb r3, [r3, #0]
|
|||
|
|
80039da: 2203 movs r2, #3
|
|||
|
|
80039dc: 1ad3 subs r3, r2, r3
|
|||
|
|
80039de: 221f movs r2, #31
|
|||
|
|
80039e0: 18ba adds r2, r7, r2
|
|||
|
|
80039e2: 7812 ldrb r2, [r2, #0]
|
|||
|
|
80039e4: 3207 adds r2, #7
|
|||
|
|
80039e6: 494e ldr r1, [pc, #312] ; (8003b20 <HAL_UART_RxCpltCallback+0x1264>)
|
|||
|
|
80039e8: 5c89 ldrb r1, [r1, r2]
|
|||
|
|
80039ea: 2208 movs r2, #8
|
|||
|
|
80039ec: 18ba adds r2, r7, r2
|
|||
|
|
80039ee: 54d1 strb r1, [r2, r3]
|
|||
|
|
for(j = 0; j < 4; j++)
|
|||
|
|
80039f0: 231f movs r3, #31
|
|||
|
|
80039f2: 18fb adds r3, r7, r3
|
|||
|
|
80039f4: 781a ldrb r2, [r3, #0]
|
|||
|
|
80039f6: 231f movs r3, #31
|
|||
|
|
80039f8: 18fb adds r3, r7, r3
|
|||
|
|
80039fa: 3201 adds r2, #1
|
|||
|
|
80039fc: 701a strb r2, [r3, #0]
|
|||
|
|
80039fe: 231f movs r3, #31
|
|||
|
|
8003a00: 18fb adds r3, r7, r3
|
|||
|
|
8003a02: 781b ldrb r3, [r3, #0]
|
|||
|
|
8003a04: 2b03 cmp r3, #3
|
|||
|
|
8003a06: d9e5 bls.n 80039d4 <HAL_UART_RxCpltCallback+0x1118>
|
|||
|
|
pardata.SENS = f.fl;
|
|||
|
|
8003a08: 68ba ldr r2, [r7, #8]
|
|||
|
|
8003a0a: 4b46 ldr r3, [pc, #280] ; (8003b24 <HAL_UART_RxCpltCallback+0x1268>)
|
|||
|
|
8003a0c: 621a str r2, [r3, #32]
|
|||
|
|
needSave = true;
|
|||
|
|
8003a0e: 4b46 ldr r3, [pc, #280] ; (8003b28 <HAL_UART_RxCpltCallback+0x126c>)
|
|||
|
|
8003a10: 2201 movs r2, #1
|
|||
|
|
8003a12: 701a strb r2, [r3, #0]
|
|||
|
|
strtOut(6);
|
|||
|
|
8003a14: 2006 movs r0, #6
|
|||
|
|
8003a16: f7fe fe5f bl 80026d8 <strtOut>
|
|||
|
|
break;
|
|||
|
|
8003a1a: e118 b.n 8003c4e <HAL_UART_RxCpltCallback+0x1392>
|
|||
|
|
if(iobuf[6] == 8)
|
|||
|
|
8003a1c: 4b40 ldr r3, [pc, #256] ; (8003b20 <HAL_UART_RxCpltCallback+0x1264>)
|
|||
|
|
8003a1e: 799b ldrb r3, [r3, #6]
|
|||
|
|
8003a20: 2b08 cmp r3, #8
|
|||
|
|
8003a22: d128 bne.n 8003a76 <HAL_UART_RxCpltCallback+0x11ba>
|
|||
|
|
for(j = 0; j < 4; j++)
|
|||
|
|
8003a24: 231f movs r3, #31
|
|||
|
|
8003a26: 18fb adds r3, r7, r3
|
|||
|
|
8003a28: 2200 movs r2, #0
|
|||
|
|
8003a2a: 701a strb r2, [r3, #0]
|
|||
|
|
8003a2c: e014 b.n 8003a58 <HAL_UART_RxCpltCallback+0x119c>
|
|||
|
|
f.ch[3 - j] = iobuf[7 + j];
|
|||
|
|
8003a2e: 231f movs r3, #31
|
|||
|
|
8003a30: 18fb adds r3, r7, r3
|
|||
|
|
8003a32: 781b ldrb r3, [r3, #0]
|
|||
|
|
8003a34: 2203 movs r2, #3
|
|||
|
|
8003a36: 1ad3 subs r3, r2, r3
|
|||
|
|
8003a38: 221f movs r2, #31
|
|||
|
|
8003a3a: 18ba adds r2, r7, r2
|
|||
|
|
8003a3c: 7812 ldrb r2, [r2, #0]
|
|||
|
|
8003a3e: 3207 adds r2, #7
|
|||
|
|
8003a40: 4937 ldr r1, [pc, #220] ; (8003b20 <HAL_UART_RxCpltCallback+0x1264>)
|
|||
|
|
8003a42: 5c89 ldrb r1, [r1, r2]
|
|||
|
|
8003a44: 2208 movs r2, #8
|
|||
|
|
8003a46: 18ba adds r2, r7, r2
|
|||
|
|
8003a48: 54d1 strb r1, [r2, r3]
|
|||
|
|
for(j = 0; j < 4; j++)
|
|||
|
|
8003a4a: 231f movs r3, #31
|
|||
|
|
8003a4c: 18fb adds r3, r7, r3
|
|||
|
|
8003a4e: 781a ldrb r2, [r3, #0]
|
|||
|
|
8003a50: 231f movs r3, #31
|
|||
|
|
8003a52: 18fb adds r3, r7, r3
|
|||
|
|
8003a54: 3201 adds r2, #1
|
|||
|
|
8003a56: 701a strb r2, [r3, #0]
|
|||
|
|
8003a58: 231f movs r3, #31
|
|||
|
|
8003a5a: 18fb adds r3, r7, r3
|
|||
|
|
8003a5c: 781b ldrb r3, [r3, #0]
|
|||
|
|
8003a5e: 2b03 cmp r3, #3
|
|||
|
|
8003a60: d9e5 bls.n 8003a2e <HAL_UART_RxCpltCallback+0x1172>
|
|||
|
|
pardata.ACCEL = f.fl;
|
|||
|
|
8003a62: 68ba ldr r2, [r7, #8]
|
|||
|
|
8003a64: 4b2f ldr r3, [pc, #188] ; (8003b24 <HAL_UART_RxCpltCallback+0x1268>)
|
|||
|
|
8003a66: 625a str r2, [r3, #36] ; 0x24
|
|||
|
|
needSave = true;
|
|||
|
|
8003a68: 4b2f ldr r3, [pc, #188] ; (8003b28 <HAL_UART_RxCpltCallback+0x126c>)
|
|||
|
|
8003a6a: 2201 movs r2, #1
|
|||
|
|
8003a6c: 701a strb r2, [r3, #0]
|
|||
|
|
strtOut(6);
|
|||
|
|
8003a6e: 2006 movs r0, #6
|
|||
|
|
8003a70: f7fe fe32 bl 80026d8 <strtOut>
|
|||
|
|
break;
|
|||
|
|
8003a74: e0eb b.n 8003c4e <HAL_UART_RxCpltCallback+0x1392>
|
|||
|
|
tx[0] = iobuf[0];
|
|||
|
|
8003a76: 4b2a ldr r3, [pc, #168] ; (8003b20 <HAL_UART_RxCpltCallback+0x1264>)
|
|||
|
|
8003a78: 781a ldrb r2, [r3, #0]
|
|||
|
|
8003a7a: 4b2c ldr r3, [pc, #176] ; (8003b2c <HAL_UART_RxCpltCallback+0x1270>)
|
|||
|
|
8003a7c: 701a strb r2, [r3, #0]
|
|||
|
|
tx[1] |= 0x80; //модификация кода функции на ошибку
|
|||
|
|
8003a7e: 4b2b ldr r3, [pc, #172] ; (8003b2c <HAL_UART_RxCpltCallback+0x1270>)
|
|||
|
|
8003a80: 785b ldrb r3, [r3, #1]
|
|||
|
|
8003a82: 2280 movs r2, #128 ; 0x80
|
|||
|
|
8003a84: 4252 negs r2, r2
|
|||
|
|
8003a86: 4313 orrs r3, r2
|
|||
|
|
8003a88: b2da uxtb r2, r3
|
|||
|
|
8003a8a: 4b28 ldr r3, [pc, #160] ; (8003b2c <HAL_UART_RxCpltCallback+0x1270>)
|
|||
|
|
8003a8c: 705a strb r2, [r3, #1]
|
|||
|
|
tx[2] = 0x03; //Адрес данных указанный в запросе не доступен
|
|||
|
|
8003a8e: 4b27 ldr r3, [pc, #156] ; (8003b2c <HAL_UART_RxCpltCallback+0x1270>)
|
|||
|
|
8003a90: 2203 movs r2, #3
|
|||
|
|
8003a92: 709a strb r2, [r3, #2]
|
|||
|
|
strtOut(3);
|
|||
|
|
8003a94: 2003 movs r0, #3
|
|||
|
|
8003a96: f7fe fe1f bl 80026d8 <strtOut>
|
|||
|
|
break;
|
|||
|
|
8003a9a: e0d8 b.n 8003c4e <HAL_UART_RxCpltCallback+0x1392>
|
|||
|
|
tmp = 1;
|
|||
|
|
8003a9c: 231e movs r3, #30
|
|||
|
|
8003a9e: 18fb adds r3, r7, r3
|
|||
|
|
8003aa0: 2201 movs r2, #1
|
|||
|
|
8003aa2: 701a strb r2, [r3, #0]
|
|||
|
|
tmp1 = 2;
|
|||
|
|
8003aa4: 231d movs r3, #29
|
|||
|
|
8003aa6: 18fb adds r3, r7, r3
|
|||
|
|
8003aa8: 2202 movs r2, #2
|
|||
|
|
8003aaa: 701a strb r2, [r3, #0]
|
|||
|
|
if(addr.sh == 7006)
|
|||
|
|
8003aac: 2310 movs r3, #16
|
|||
|
|
8003aae: 18fb adds r3, r7, r3
|
|||
|
|
8003ab0: 881b ldrh r3, [r3, #0]
|
|||
|
|
8003ab2: 4a21 ldr r2, [pc, #132] ; (8003b38 <HAL_UART_RxCpltCallback+0x127c>)
|
|||
|
|
8003ab4: 4293 cmp r3, r2
|
|||
|
|
8003ab6: d10a bne.n 8003ace <HAL_UART_RxCpltCallback+0x1212>
|
|||
|
|
tmp <<= 1;
|
|||
|
|
8003ab8: 231e movs r3, #30
|
|||
|
|
8003aba: 18fa adds r2, r7, r3
|
|||
|
|
8003abc: 231e movs r3, #30
|
|||
|
|
8003abe: 18fb adds r3, r7, r3
|
|||
|
|
8003ac0: 781b ldrb r3, [r3, #0]
|
|||
|
|
8003ac2: 18db adds r3, r3, r3
|
|||
|
|
8003ac4: 7013 strb r3, [r2, #0]
|
|||
|
|
tmp1 = 1;
|
|||
|
|
8003ac6: 231d movs r3, #29
|
|||
|
|
8003ac8: 18fb adds r3, r7, r3
|
|||
|
|
8003aca: 2201 movs r2, #1
|
|||
|
|
8003acc: 701a strb r2, [r3, #0]
|
|||
|
|
if((regs.ch[0] > tmp) || (iobuf[6] != (regs.ch[0] << tmp1)))
|
|||
|
|
8003ace: 230c movs r3, #12
|
|||
|
|
8003ad0: 18fb adds r3, r7, r3
|
|||
|
|
8003ad2: 781b ldrb r3, [r3, #0]
|
|||
|
|
8003ad4: 221e movs r2, #30
|
|||
|
|
8003ad6: 18ba adds r2, r7, r2
|
|||
|
|
8003ad8: 7812 ldrb r2, [r2, #0]
|
|||
|
|
8003ada: 429a cmp r2, r3
|
|||
|
|
8003adc: d30d bcc.n 8003afa <HAL_UART_RxCpltCallback+0x123e>
|
|||
|
|
8003ade: 4b10 ldr r3, [pc, #64] ; (8003b20 <HAL_UART_RxCpltCallback+0x1264>)
|
|||
|
|
8003ae0: 799b ldrb r3, [r3, #6]
|
|||
|
|
8003ae2: 001a movs r2, r3
|
|||
|
|
8003ae4: 230c movs r3, #12
|
|||
|
|
8003ae6: 18fb adds r3, r7, r3
|
|||
|
|
8003ae8: 781b ldrb r3, [r3, #0]
|
|||
|
|
8003aea: 0019 movs r1, r3
|
|||
|
|
8003aec: 231d movs r3, #29
|
|||
|
|
8003aee: 18fb adds r3, r7, r3
|
|||
|
|
8003af0: 781b ldrb r3, [r3, #0]
|
|||
|
|
8003af2: 4099 lsls r1, r3
|
|||
|
|
8003af4: 000b movs r3, r1
|
|||
|
|
8003af6: 429a cmp r2, r3
|
|||
|
|
8003af8: d020 beq.n 8003b3c <HAL_UART_RxCpltCallback+0x1280>
|
|||
|
|
tx[0] = iobuf[0];
|
|||
|
|
8003afa: 4b09 ldr r3, [pc, #36] ; (8003b20 <HAL_UART_RxCpltCallback+0x1264>)
|
|||
|
|
8003afc: 781a ldrb r2, [r3, #0]
|
|||
|
|
8003afe: 4b0b ldr r3, [pc, #44] ; (8003b2c <HAL_UART_RxCpltCallback+0x1270>)
|
|||
|
|
8003b00: 701a strb r2, [r3, #0]
|
|||
|
|
tx[1] |= 0x80; //модификация кода функции на ошибку
|
|||
|
|
8003b02: 4b0a ldr r3, [pc, #40] ; (8003b2c <HAL_UART_RxCpltCallback+0x1270>)
|
|||
|
|
8003b04: 785b ldrb r3, [r3, #1]
|
|||
|
|
8003b06: 2280 movs r2, #128 ; 0x80
|
|||
|
|
8003b08: 4252 negs r2, r2
|
|||
|
|
8003b0a: 4313 orrs r3, r2
|
|||
|
|
8003b0c: b2da uxtb r2, r3
|
|||
|
|
8003b0e: 4b07 ldr r3, [pc, #28] ; (8003b2c <HAL_UART_RxCpltCallback+0x1270>)
|
|||
|
|
8003b10: 705a strb r2, [r3, #1]
|
|||
|
|
tx[2] = 0x03; //Адрес данных указанный в запросе не доступен
|
|||
|
|
8003b12: 4b06 ldr r3, [pc, #24] ; (8003b2c <HAL_UART_RxCpltCallback+0x1270>)
|
|||
|
|
8003b14: 2203 movs r2, #3
|
|||
|
|
8003b16: 709a strb r2, [r3, #2]
|
|||
|
|
strtOut(3);
|
|||
|
|
8003b18: 2003 movs r0, #3
|
|||
|
|
8003b1a: f7fe fddd bl 80026d8 <strtOut>
|
|||
|
|
break;
|
|||
|
|
8003b1e: e098 b.n 8003c52 <HAL_UART_RxCpltCallback+0x1396>
|
|||
|
|
8003b20: 2000028c .word 0x2000028c
|
|||
|
|
8003b24: 20000098 .word 0x20000098
|
|||
|
|
8003b28: 20000037 .word 0x20000037
|
|||
|
|
8003b2c: 20000188 .word 0x20000188
|
|||
|
|
8003b30: 00001b5c .word 0x00001b5c
|
|||
|
|
8003b34: 20000035 .word 0x20000035
|
|||
|
|
8003b38: 00001b5e .word 0x00001b5e
|
|||
|
|
j = 8 + iobuf[6];
|
|||
|
|
8003b3c: 4b48 ldr r3, [pc, #288] ; (8003c60 <HAL_UART_RxCpltCallback+0x13a4>)
|
|||
|
|
8003b3e: 799a ldrb r2, [r3, #6]
|
|||
|
|
8003b40: 231f movs r3, #31
|
|||
|
|
8003b42: 18fb adds r3, r7, r3
|
|||
|
|
8003b44: 3208 adds r2, #8
|
|||
|
|
8003b46: 701a strb r2, [r3, #0]
|
|||
|
|
if(iolen > j)
|
|||
|
|
8003b48: 4b46 ldr r3, [pc, #280] ; (8003c64 <HAL_UART_RxCpltCallback+0x13a8>)
|
|||
|
|
8003b4a: 781b ldrb r3, [r3, #0]
|
|||
|
|
8003b4c: 221f movs r2, #31
|
|||
|
|
8003b4e: 18ba adds r2, r7, r2
|
|||
|
|
8003b50: 7812 ldrb r2, [r2, #0]
|
|||
|
|
8003b52: 429a cmp r2, r3
|
|||
|
|
8003b54: d300 bcc.n 8003b58 <HAL_UART_RxCpltCallback+0x129c>
|
|||
|
|
8003b56: e07c b.n 8003c52 <HAL_UART_RxCpltCallback+0x1396>
|
|||
|
|
crc.ch[0] = iobuf[j - 1];
|
|||
|
|
8003b58: 231f movs r3, #31
|
|||
|
|
8003b5a: 18fb adds r3, r7, r3
|
|||
|
|
8003b5c: 781b ldrb r3, [r3, #0]
|
|||
|
|
8003b5e: 3b01 subs r3, #1
|
|||
|
|
8003b60: 4a3f ldr r2, [pc, #252] ; (8003c60 <HAL_UART_RxCpltCallback+0x13a4>)
|
|||
|
|
8003b62: 5cd2 ldrb r2, [r2, r3]
|
|||
|
|
8003b64: 2314 movs r3, #20
|
|||
|
|
8003b66: 18fb adds r3, r7, r3
|
|||
|
|
8003b68: 701a strb r2, [r3, #0]
|
|||
|
|
crc.ch[1] = iobuf[j];
|
|||
|
|
8003b6a: 231f movs r3, #31
|
|||
|
|
8003b6c: 18fb adds r3, r7, r3
|
|||
|
|
8003b6e: 781b ldrb r3, [r3, #0]
|
|||
|
|
8003b70: 4a3b ldr r2, [pc, #236] ; (8003c60 <HAL_UART_RxCpltCallback+0x13a4>)
|
|||
|
|
8003b72: 5cd2 ldrb r2, [r2, r3]
|
|||
|
|
8003b74: 2314 movs r3, #20
|
|||
|
|
8003b76: 18fb adds r3, r7, r3
|
|||
|
|
8003b78: 705a strb r2, [r3, #1]
|
|||
|
|
if(crc.sh == Crc16(j - 1))
|
|||
|
|
8003b7a: 2314 movs r3, #20
|
|||
|
|
8003b7c: 18fb adds r3, r7, r3
|
|||
|
|
8003b7e: 881c ldrh r4, [r3, #0]
|
|||
|
|
8003b80: 231f movs r3, #31
|
|||
|
|
8003b82: 18fb adds r3, r7, r3
|
|||
|
|
8003b84: 781b ldrb r3, [r3, #0]
|
|||
|
|
8003b86: b29b uxth r3, r3
|
|||
|
|
8003b88: 3b01 subs r3, #1
|
|||
|
|
8003b8a: b29b uxth r3, r3
|
|||
|
|
8003b8c: 0018 movs r0, r3
|
|||
|
|
8003b8e: f7fe fdef bl 8002770 <Crc16>
|
|||
|
|
8003b92: 0003 movs r3, r0
|
|||
|
|
8003b94: 429c cmp r4, r3
|
|||
|
|
8003b96: d15c bne.n 8003c52 <HAL_UART_RxCpltCallback+0x1396>
|
|||
|
|
if(iobuf[6] == 4)
|
|||
|
|
8003b98: 4b31 ldr r3, [pc, #196] ; (8003c60 <HAL_UART_RxCpltCallback+0x13a4>)
|
|||
|
|
8003b9a: 799b ldrb r3, [r3, #6]
|
|||
|
|
8003b9c: 2b04 cmp r3, #4
|
|||
|
|
8003b9e: d128 bne.n 8003bf2 <HAL_UART_RxCpltCallback+0x1336>
|
|||
|
|
for(j = 0; j < 4; j++)
|
|||
|
|
8003ba0: 231f movs r3, #31
|
|||
|
|
8003ba2: 18fb adds r3, r7, r3
|
|||
|
|
8003ba4: 2200 movs r2, #0
|
|||
|
|
8003ba6: 701a strb r2, [r3, #0]
|
|||
|
|
8003ba8: e014 b.n 8003bd4 <HAL_UART_RxCpltCallback+0x1318>
|
|||
|
|
f.ch[3 - j] = iobuf[3 + j];
|
|||
|
|
8003baa: 231f movs r3, #31
|
|||
|
|
8003bac: 18fb adds r3, r7, r3
|
|||
|
|
8003bae: 781b ldrb r3, [r3, #0]
|
|||
|
|
8003bb0: 2203 movs r2, #3
|
|||
|
|
8003bb2: 1ad3 subs r3, r2, r3
|
|||
|
|
8003bb4: 221f movs r2, #31
|
|||
|
|
8003bb6: 18ba adds r2, r7, r2
|
|||
|
|
8003bb8: 7812 ldrb r2, [r2, #0]
|
|||
|
|
8003bba: 3203 adds r2, #3
|
|||
|
|
8003bbc: 4928 ldr r1, [pc, #160] ; (8003c60 <HAL_UART_RxCpltCallback+0x13a4>)
|
|||
|
|
8003bbe: 5c89 ldrb r1, [r1, r2]
|
|||
|
|
8003bc0: 2208 movs r2, #8
|
|||
|
|
8003bc2: 18ba adds r2, r7, r2
|
|||
|
|
8003bc4: 54d1 strb r1, [r2, r3]
|
|||
|
|
for(j = 0; j < 4; j++)
|
|||
|
|
8003bc6: 231f movs r3, #31
|
|||
|
|
8003bc8: 18fb adds r3, r7, r3
|
|||
|
|
8003bca: 781a ldrb r2, [r3, #0]
|
|||
|
|
8003bcc: 231f movs r3, #31
|
|||
|
|
8003bce: 18fb adds r3, r7, r3
|
|||
|
|
8003bd0: 3201 adds r2, #1
|
|||
|
|
8003bd2: 701a strb r2, [r3, #0]
|
|||
|
|
8003bd4: 231f movs r3, #31
|
|||
|
|
8003bd6: 18fb adds r3, r7, r3
|
|||
|
|
8003bd8: 781b ldrb r3, [r3, #0]
|
|||
|
|
8003bda: 2b03 cmp r3, #3
|
|||
|
|
8003bdc: d9e5 bls.n 8003baa <HAL_UART_RxCpltCallback+0x12ee>
|
|||
|
|
pardata.ACCEL = f.fl;
|
|||
|
|
8003bde: 68ba ldr r2, [r7, #8]
|
|||
|
|
8003be0: 4b21 ldr r3, [pc, #132] ; (8003c68 <HAL_UART_RxCpltCallback+0x13ac>)
|
|||
|
|
8003be2: 625a str r2, [r3, #36] ; 0x24
|
|||
|
|
needSave = true;
|
|||
|
|
8003be4: 4b21 ldr r3, [pc, #132] ; (8003c6c <HAL_UART_RxCpltCallback+0x13b0>)
|
|||
|
|
8003be6: 2201 movs r2, #1
|
|||
|
|
8003be8: 701a strb r2, [r3, #0]
|
|||
|
|
strtOut(6);
|
|||
|
|
8003bea: 2006 movs r0, #6
|
|||
|
|
8003bec: f7fe fd74 bl 80026d8 <strtOut>
|
|||
|
|
break;
|
|||
|
|
8003bf0: e02f b.n 8003c52 <HAL_UART_RxCpltCallback+0x1396>
|
|||
|
|
tx[0] = iobuf[0];
|
|||
|
|
8003bf2: 4b1b ldr r3, [pc, #108] ; (8003c60 <HAL_UART_RxCpltCallback+0x13a4>)
|
|||
|
|
8003bf4: 781a ldrb r2, [r3, #0]
|
|||
|
|
8003bf6: 4b1e ldr r3, [pc, #120] ; (8003c70 <HAL_UART_RxCpltCallback+0x13b4>)
|
|||
|
|
8003bf8: 701a strb r2, [r3, #0]
|
|||
|
|
tx[1] |= 0x80; //модификация кода функции на ошибку
|
|||
|
|
8003bfa: 4b1d ldr r3, [pc, #116] ; (8003c70 <HAL_UART_RxCpltCallback+0x13b4>)
|
|||
|
|
8003bfc: 785b ldrb r3, [r3, #1]
|
|||
|
|
8003bfe: 2280 movs r2, #128 ; 0x80
|
|||
|
|
8003c00: 4252 negs r2, r2
|
|||
|
|
8003c02: 4313 orrs r3, r2
|
|||
|
|
8003c04: b2da uxtb r2, r3
|
|||
|
|
8003c06: 4b1a ldr r3, [pc, #104] ; (8003c70 <HAL_UART_RxCpltCallback+0x13b4>)
|
|||
|
|
8003c08: 705a strb r2, [r3, #1]
|
|||
|
|
tx[2] = 0x03; //Адрес данных указанный в запросе не доступен
|
|||
|
|
8003c0a: 4b19 ldr r3, [pc, #100] ; (8003c70 <HAL_UART_RxCpltCallback+0x13b4>)
|
|||
|
|
8003c0c: 2203 movs r2, #3
|
|||
|
|
8003c0e: 709a strb r2, [r3, #2]
|
|||
|
|
strtOut(3);
|
|||
|
|
8003c10: 2003 movs r0, #3
|
|||
|
|
8003c12: f7fe fd61 bl 80026d8 <strtOut>
|
|||
|
|
break;
|
|||
|
|
8003c16: e01c b.n 8003c52 <HAL_UART_RxCpltCallback+0x1396>
|
|||
|
|
tx[0] = iobuf[0];
|
|||
|
|
8003c18: 4b11 ldr r3, [pc, #68] ; (8003c60 <HAL_UART_RxCpltCallback+0x13a4>)
|
|||
|
|
8003c1a: 781a ldrb r2, [r3, #0]
|
|||
|
|
8003c1c: 4b14 ldr r3, [pc, #80] ; (8003c70 <HAL_UART_RxCpltCallback+0x13b4>)
|
|||
|
|
8003c1e: 701a strb r2, [r3, #0]
|
|||
|
|
tx[1] |= 0x80; //модификация кода функции на ошибку
|
|||
|
|
8003c20: 4b13 ldr r3, [pc, #76] ; (8003c70 <HAL_UART_RxCpltCallback+0x13b4>)
|
|||
|
|
8003c22: 785b ldrb r3, [r3, #1]
|
|||
|
|
8003c24: 2280 movs r2, #128 ; 0x80
|
|||
|
|
8003c26: 4252 negs r2, r2
|
|||
|
|
8003c28: 4313 orrs r3, r2
|
|||
|
|
8003c2a: b2da uxtb r2, r3
|
|||
|
|
8003c2c: 4b10 ldr r3, [pc, #64] ; (8003c70 <HAL_UART_RxCpltCallback+0x13b4>)
|
|||
|
|
8003c2e: 705a strb r2, [r3, #1]
|
|||
|
|
tx[2] = 0x02; //Адрес данных указанный в запросе не доступен
|
|||
|
|
8003c30: 4b0f ldr r3, [pc, #60] ; (8003c70 <HAL_UART_RxCpltCallback+0x13b4>)
|
|||
|
|
8003c32: 2202 movs r2, #2
|
|||
|
|
8003c34: 709a strb r2, [r3, #2]
|
|||
|
|
strtOut(3);
|
|||
|
|
8003c36: 2003 movs r0, #3
|
|||
|
|
8003c38: f7fe fd4e bl 80026d8 <strtOut>
|
|||
|
|
break;
|
|||
|
|
8003c3c: e00a b.n 8003c54 <HAL_UART_RxCpltCallback+0x1398>
|
|||
|
|
break;
|
|||
|
|
8003c3e: 46c0 nop ; (mov r8, r8)
|
|||
|
|
8003c40: e00a b.n 8003c58 <HAL_UART_RxCpltCallback+0x139c>
|
|||
|
|
break;
|
|||
|
|
8003c42: 46c0 nop ; (mov r8, r8)
|
|||
|
|
8003c44: e008 b.n 8003c58 <HAL_UART_RxCpltCallback+0x139c>
|
|||
|
|
break;
|
|||
|
|
8003c46: 46c0 nop ; (mov r8, r8)
|
|||
|
|
8003c48: e006 b.n 8003c58 <HAL_UART_RxCpltCallback+0x139c>
|
|||
|
|
break;
|
|||
|
|
8003c4a: 46c0 nop ; (mov r8, r8)
|
|||
|
|
8003c4c: e004 b.n 8003c58 <HAL_UART_RxCpltCallback+0x139c>
|
|||
|
|
break;
|
|||
|
|
8003c4e: 46c0 nop ; (mov r8, r8)
|
|||
|
|
8003c50: e002 b.n 8003c58 <HAL_UART_RxCpltCallback+0x139c>
|
|||
|
|
break;
|
|||
|
|
8003c52: 46c0 nop ; (mov r8, r8)
|
|||
|
|
break;
|
|||
|
|
8003c54: e000 b.n 8003c58 <HAL_UART_RxCpltCallback+0x139c>
|
|||
|
|
break;
|
|||
|
|
8003c56: 46c0 nop ; (mov r8, r8)
|
|||
|
|
}
|
|||
|
|
8003c58: 46c0 nop ; (mov r8, r8)
|
|||
|
|
8003c5a: 46bd mov sp, r7
|
|||
|
|
8003c5c: b008 add sp, #32
|
|||
|
|
8003c5e: bdb0 pop {r4, r5, r7, pc}
|
|||
|
|
8003c60: 2000028c .word 0x2000028c
|
|||
|
|
8003c64: 20000035 .word 0x20000035
|
|||
|
|
8003c68: 20000098 .word 0x20000098
|
|||
|
|
8003c6c: 20000037 .word 0x20000037
|
|||
|
|
8003c70: 20000188 .word 0x20000188
|
|||
|
|
|
|||
|
|
08003c74 <HAL_UART_TxCpltCallback>:
|
|||
|
|
|
|||
|
|
|
|||
|
|
void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart)
|
|||
|
|
{
|
|||
|
|
8003c74: b580 push {r7, lr}
|
|||
|
|
8003c76: b084 sub sp, #16
|
|||
|
|
8003c78: af00 add r7, sp, #0
|
|||
|
|
8003c7a: 6078 str r0, [r7, #4]
|
|||
|
|
__IO uint16_t a;
|
|||
|
|
|
|||
|
|
a = delayREDE;
|
|||
|
|
8003c7c: 4b2a ldr r3, [pc, #168] ; (8003d28 <HAL_UART_TxCpltCallback+0xb4>)
|
|||
|
|
8003c7e: 881b ldrh r3, [r3, #0]
|
|||
|
|
8003c80: b29a uxth r2, r3
|
|||
|
|
8003c82: 230e movs r3, #14
|
|||
|
|
8003c84: 18fb adds r3, r7, r3
|
|||
|
|
8003c86: 801a strh r2, [r3, #0]
|
|||
|
|
while(a)
|
|||
|
|
8003c88: e02c b.n 8003ce4 <HAL_UART_TxCpltCallback+0x70>
|
|||
|
|
{
|
|||
|
|
a--; a++; a--; a++; a--;
|
|||
|
|
8003c8a: 230e movs r3, #14
|
|||
|
|
8003c8c: 18fb adds r3, r7, r3
|
|||
|
|
8003c8e: 881b ldrh r3, [r3, #0]
|
|||
|
|
8003c90: b29b uxth r3, r3
|
|||
|
|
8003c92: 3b01 subs r3, #1
|
|||
|
|
8003c94: b29a uxth r2, r3
|
|||
|
|
8003c96: 230e movs r3, #14
|
|||
|
|
8003c98: 18fb adds r3, r7, r3
|
|||
|
|
8003c9a: 801a strh r2, [r3, #0]
|
|||
|
|
8003c9c: 230e movs r3, #14
|
|||
|
|
8003c9e: 18fb adds r3, r7, r3
|
|||
|
|
8003ca0: 881b ldrh r3, [r3, #0]
|
|||
|
|
8003ca2: b29b uxth r3, r3
|
|||
|
|
8003ca4: 3301 adds r3, #1
|
|||
|
|
8003ca6: b29a uxth r2, r3
|
|||
|
|
8003ca8: 230e movs r3, #14
|
|||
|
|
8003caa: 18fb adds r3, r7, r3
|
|||
|
|
8003cac: 801a strh r2, [r3, #0]
|
|||
|
|
8003cae: 230e movs r3, #14
|
|||
|
|
8003cb0: 18fb adds r3, r7, r3
|
|||
|
|
8003cb2: 881b ldrh r3, [r3, #0]
|
|||
|
|
8003cb4: b29b uxth r3, r3
|
|||
|
|
8003cb6: 3b01 subs r3, #1
|
|||
|
|
8003cb8: b29a uxth r2, r3
|
|||
|
|
8003cba: 230e movs r3, #14
|
|||
|
|
8003cbc: 18fb adds r3, r7, r3
|
|||
|
|
8003cbe: 801a strh r2, [r3, #0]
|
|||
|
|
8003cc0: 230e movs r3, #14
|
|||
|
|
8003cc2: 18fb adds r3, r7, r3
|
|||
|
|
8003cc4: 881b ldrh r3, [r3, #0]
|
|||
|
|
8003cc6: b29b uxth r3, r3
|
|||
|
|
8003cc8: 3301 adds r3, #1
|
|||
|
|
8003cca: b29a uxth r2, r3
|
|||
|
|
8003ccc: 230e movs r3, #14
|
|||
|
|
8003cce: 18fb adds r3, r7, r3
|
|||
|
|
8003cd0: 801a strh r2, [r3, #0]
|
|||
|
|
8003cd2: 230e movs r3, #14
|
|||
|
|
8003cd4: 18fb adds r3, r7, r3
|
|||
|
|
8003cd6: 881b ldrh r3, [r3, #0]
|
|||
|
|
8003cd8: b29b uxth r3, r3
|
|||
|
|
8003cda: 3b01 subs r3, #1
|
|||
|
|
8003cdc: b29a uxth r2, r3
|
|||
|
|
8003cde: 230e movs r3, #14
|
|||
|
|
8003ce0: 18fb adds r3, r7, r3
|
|||
|
|
8003ce2: 801a strh r2, [r3, #0]
|
|||
|
|
while(a)
|
|||
|
|
8003ce4: 230e movs r3, #14
|
|||
|
|
8003ce6: 18fb adds r3, r7, r3
|
|||
|
|
8003ce8: 881b ldrh r3, [r3, #0]
|
|||
|
|
8003cea: b29b uxth r3, r3
|
|||
|
|
8003cec: 2b00 cmp r3, #0
|
|||
|
|
8003cee: d1cc bne.n 8003c8a <HAL_UART_TxCpltCallback+0x16>
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
if(setbaud)
|
|||
|
|
8003cf0: 4b0e ldr r3, [pc, #56] ; (8003d2c <HAL_UART_TxCpltCallback+0xb8>)
|
|||
|
|
8003cf2: 781b ldrb r3, [r3, #0]
|
|||
|
|
8003cf4: 2b00 cmp r3, #0
|
|||
|
|
8003cf6: d007 beq.n 8003d08 <HAL_UART_TxCpltCallback+0x94>
|
|||
|
|
{
|
|||
|
|
setbaud = false;
|
|||
|
|
8003cf8: 4b0c ldr r3, [pc, #48] ; (8003d2c <HAL_UART_TxCpltCallback+0xb8>)
|
|||
|
|
8003cfa: 2200 movs r2, #0
|
|||
|
|
8003cfc: 701a strb r2, [r3, #0]
|
|||
|
|
needSave = true;
|
|||
|
|
8003cfe: 4b0c ldr r3, [pc, #48] ; (8003d30 <HAL_UART_TxCpltCallback+0xbc>)
|
|||
|
|
8003d00: 2201 movs r2, #1
|
|||
|
|
8003d02: 701a strb r2, [r3, #0]
|
|||
|
|
SetBaudRate();
|
|||
|
|
8003d04: f7fe fdb4 bl 8002870 <SetBaudRate>
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
__HAL_UART_CLEAR_FLAG(&huart1, UART_FLAG_TC);
|
|||
|
|
8003d08: 4b0a ldr r3, [pc, #40] ; (8003d34 <HAL_UART_TxCpltCallback+0xc0>)
|
|||
|
|
8003d0a: 681b ldr r3, [r3, #0]
|
|||
|
|
8003d0c: 2240 movs r2, #64 ; 0x40
|
|||
|
|
8003d0e: 621a str r2, [r3, #32]
|
|||
|
|
HAL_GPIO_WritePin(RE_GPIO_Port, RE_Pin, GPIO_PIN_RESET);
|
|||
|
|
8003d10: 2380 movs r3, #128 ; 0x80
|
|||
|
|
8003d12: 0059 lsls r1, r3, #1
|
|||
|
|
8003d14: 23a0 movs r3, #160 ; 0xa0
|
|||
|
|
8003d16: 05db lsls r3, r3, #23
|
|||
|
|
8003d18: 2200 movs r2, #0
|
|||
|
|
8003d1a: 0018 movs r0, r3
|
|||
|
|
8003d1c: f000 fef7 bl 8004b0e <HAL_GPIO_WritePin>
|
|||
|
|
}
|
|||
|
|
8003d20: 46c0 nop ; (mov r8, r8)
|
|||
|
|
8003d22: 46bd mov sp, r7
|
|||
|
|
8003d24: b004 add sp, #16
|
|||
|
|
8003d26: bd80 pop {r7, pc}
|
|||
|
|
8003d28: 20000102 .word 0x20000102
|
|||
|
|
8003d2c: 20000004 .word 0x20000004
|
|||
|
|
8003d30: 20000037 .word 0x20000037
|
|||
|
|
8003d34: 20000104 .word 0x20000104
|
|||
|
|
|
|||
|
|
08003d38 <StartTransfer>:
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
void StartTransfer(void)
|
|||
|
|
{
|
|||
|
|
8003d38: b580 push {r7, lr}
|
|||
|
|
8003d3a: b082 sub sp, #8
|
|||
|
|
8003d3c: af00 add r7, sp, #0
|
|||
|
|
while(a)
|
|||
|
|
{
|
|||
|
|
a--; a++; a--; a++; a--;
|
|||
|
|
}*/
|
|||
|
|
|
|||
|
|
HAL_UART_Transmit_IT(&huart1, tx, lastbyte);
|
|||
|
|
8003d3e: 4b05 ldr r3, [pc, #20] ; (8003d54 <StartTransfer+0x1c>)
|
|||
|
|
8003d40: 881a ldrh r2, [r3, #0]
|
|||
|
|
8003d42: 4905 ldr r1, [pc, #20] ; (8003d58 <StartTransfer+0x20>)
|
|||
|
|
8003d44: 4b05 ldr r3, [pc, #20] ; (8003d5c <StartTransfer+0x24>)
|
|||
|
|
8003d46: 0018 movs r0, r3
|
|||
|
|
8003d48: f002 f942 bl 8005fd0 <HAL_UART_Transmit_IT>
|
|||
|
|
}
|
|||
|
|
8003d4c: 46c0 nop ; (mov r8, r8)
|
|||
|
|
8003d4e: 46bd mov sp, r7
|
|||
|
|
8003d50: b002 add sp, #8
|
|||
|
|
8003d52: bd80 pop {r7, pc}
|
|||
|
|
8003d54: 2000028a .word 0x2000028a
|
|||
|
|
8003d58: 20000188 .word 0x20000188
|
|||
|
|
8003d5c: 20000104 .word 0x20000104
|
|||
|
|
|
|||
|
|
08003d60 <HAL_GPIO_EXTI_Callback>:
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin)
|
|||
|
|
{
|
|||
|
|
8003d60: b580 push {r7, lr}
|
|||
|
|
8003d62: b082 sub sp, #8
|
|||
|
|
8003d64: af00 add r7, sp, #0
|
|||
|
|
8003d66: 0002 movs r2, r0
|
|||
|
|
8003d68: 1dbb adds r3, r7, #6
|
|||
|
|
8003d6a: 801a strh r2, [r3, #0]
|
|||
|
|
|
|||
|
|
if(GPIO_Pin == UPER_Pin) // Overdrive
|
|||
|
|
8003d6c: 1dbb adds r3, r7, #6
|
|||
|
|
8003d6e: 881b ldrh r3, [r3, #0]
|
|||
|
|
8003d70: 2b01 cmp r3, #1
|
|||
|
|
8003d72: d12a bne.n 8003dca <HAL_GPIO_EXTI_Callback+0x6a>
|
|||
|
|
{
|
|||
|
|
__HAL_GPIO_EXTI_CLEAR_FLAG(UPER_Pin);
|
|||
|
|
8003d74: 4b38 ldr r3, [pc, #224] ; (8003e58 <HAL_GPIO_EXTI_Callback+0xf8>)
|
|||
|
|
8003d76: 2201 movs r2, #1
|
|||
|
|
8003d78: 615a str r2, [r3, #20]
|
|||
|
|
|
|||
|
|
if(HAL_GPIO_ReadPin(GPIOA, UPER_Pin) == GPIO_PIN_SET)
|
|||
|
|
8003d7a: 23a0 movs r3, #160 ; 0xa0
|
|||
|
|
8003d7c: 05db lsls r3, r3, #23
|
|||
|
|
8003d7e: 2101 movs r1, #1
|
|||
|
|
8003d80: 0018 movs r0, r3
|
|||
|
|
8003d82: f000 fea7 bl 8004ad4 <HAL_GPIO_ReadPin>
|
|||
|
|
8003d86: 0003 movs r3, r0
|
|||
|
|
8003d88: 2b01 cmp r3, #1
|
|||
|
|
8003d8a: d10f bne.n 8003dac <HAL_GPIO_EXTI_Callback+0x4c>
|
|||
|
|
{
|
|||
|
|
//timerUPER = 1000;
|
|||
|
|
HAL_GPIO_WritePin(GPIOA, PER_Pin, GPIO_PIN_SET);
|
|||
|
|
8003d8c: 23a0 movs r3, #160 ; 0xa0
|
|||
|
|
8003d8e: 05db lsls r3, r3, #23
|
|||
|
|
8003d90: 2201 movs r2, #1
|
|||
|
|
8003d92: 2110 movs r1, #16
|
|||
|
|
8003d94: 0018 movs r0, r3
|
|||
|
|
8003d96: f000 feba bl 8004b0e <HAL_GPIO_WritePin>
|
|||
|
|
AMP_STATUS |= UPER_Pin;
|
|||
|
|
8003d9a: 4b30 ldr r3, [pc, #192] ; (8003e5c <HAL_GPIO_EXTI_Callback+0xfc>)
|
|||
|
|
8003d9c: 881b ldrh r3, [r3, #0]
|
|||
|
|
8003d9e: b29b uxth r3, r3
|
|||
|
|
8003da0: 2201 movs r2, #1
|
|||
|
|
8003da2: 4313 orrs r3, r2
|
|||
|
|
8003da4: b29a uxth r2, r3
|
|||
|
|
8003da6: 4b2d ldr r3, [pc, #180] ; (8003e5c <HAL_GPIO_EXTI_Callback+0xfc>)
|
|||
|
|
8003da8: 801a strh r2, [r3, #0]
|
|||
|
|
8003daa: e00e b.n 8003dca <HAL_GPIO_EXTI_Callback+0x6a>
|
|||
|
|
}
|
|||
|
|
else
|
|||
|
|
{
|
|||
|
|
AMP_STATUS &= ~UPER_Pin;
|
|||
|
|
8003dac: 4b2b ldr r3, [pc, #172] ; (8003e5c <HAL_GPIO_EXTI_Callback+0xfc>)
|
|||
|
|
8003dae: 881b ldrh r3, [r3, #0]
|
|||
|
|
8003db0: b29b uxth r3, r3
|
|||
|
|
8003db2: 2201 movs r2, #1
|
|||
|
|
8003db4: 4393 bics r3, r2
|
|||
|
|
8003db6: b29a uxth r2, r3
|
|||
|
|
8003db8: 4b28 ldr r3, [pc, #160] ; (8003e5c <HAL_GPIO_EXTI_Callback+0xfc>)
|
|||
|
|
8003dba: 801a strh r2, [r3, #0]
|
|||
|
|
HAL_GPIO_WritePin(GPIOA, PER_Pin, GPIO_PIN_RESET);
|
|||
|
|
8003dbc: 23a0 movs r3, #160 ; 0xa0
|
|||
|
|
8003dbe: 05db lsls r3, r3, #23
|
|||
|
|
8003dc0: 2200 movs r2, #0
|
|||
|
|
8003dc2: 2110 movs r1, #16
|
|||
|
|
8003dc4: 0018 movs r0, r3
|
|||
|
|
8003dc6: f000 fea2 bl 8004b0e <HAL_GPIO_WritePin>
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
if(GPIO_Pin == OP_Pin) // OP
|
|||
|
|
8003dca: 1dbb adds r3, r7, #6
|
|||
|
|
8003dcc: 881b ldrh r3, [r3, #0]
|
|||
|
|
8003dce: 2b02 cmp r3, #2
|
|||
|
|
8003dd0: d11c bne.n 8003e0c <HAL_GPIO_EXTI_Callback+0xac>
|
|||
|
|
{
|
|||
|
|
__HAL_GPIO_EXTI_CLEAR_FLAG(OP_Pin);
|
|||
|
|
8003dd2: 4b21 ldr r3, [pc, #132] ; (8003e58 <HAL_GPIO_EXTI_Callback+0xf8>)
|
|||
|
|
8003dd4: 2202 movs r2, #2
|
|||
|
|
8003dd6: 615a str r2, [r3, #20]
|
|||
|
|
|
|||
|
|
if(HAL_GPIO_ReadPin(GPIOA, OP_Pin) == GPIO_PIN_SET)
|
|||
|
|
8003dd8: 23a0 movs r3, #160 ; 0xa0
|
|||
|
|
8003dda: 05db lsls r3, r3, #23
|
|||
|
|
8003ddc: 2102 movs r1, #2
|
|||
|
|
8003dde: 0018 movs r0, r3
|
|||
|
|
8003de0: f000 fe78 bl 8004ad4 <HAL_GPIO_ReadPin>
|
|||
|
|
8003de4: 0003 movs r3, r0
|
|||
|
|
8003de6: 2b01 cmp r3, #1
|
|||
|
|
8003de8: d108 bne.n 8003dfc <HAL_GPIO_EXTI_Callback+0x9c>
|
|||
|
|
{
|
|||
|
|
//timerOP = 1000;
|
|||
|
|
AMP_STATUS |= OP_Pin;
|
|||
|
|
8003dea: 4b1c ldr r3, [pc, #112] ; (8003e5c <HAL_GPIO_EXTI_Callback+0xfc>)
|
|||
|
|
8003dec: 881b ldrh r3, [r3, #0]
|
|||
|
|
8003dee: b29b uxth r3, r3
|
|||
|
|
8003df0: 2202 movs r2, #2
|
|||
|
|
8003df2: 4313 orrs r3, r2
|
|||
|
|
8003df4: b29a uxth r2, r3
|
|||
|
|
8003df6: 4b19 ldr r3, [pc, #100] ; (8003e5c <HAL_GPIO_EXTI_Callback+0xfc>)
|
|||
|
|
8003df8: 801a strh r2, [r3, #0]
|
|||
|
|
8003dfa: e007 b.n 8003e0c <HAL_GPIO_EXTI_Callback+0xac>
|
|||
|
|
}
|
|||
|
|
else
|
|||
|
|
{
|
|||
|
|
AMP_STATUS &= ~OP_Pin;
|
|||
|
|
8003dfc: 4b17 ldr r3, [pc, #92] ; (8003e5c <HAL_GPIO_EXTI_Callback+0xfc>)
|
|||
|
|
8003dfe: 881b ldrh r3, [r3, #0]
|
|||
|
|
8003e00: b29b uxth r3, r3
|
|||
|
|
8003e02: 2202 movs r2, #2
|
|||
|
|
8003e04: 4393 bics r3, r2
|
|||
|
|
8003e06: b29a uxth r2, r3
|
|||
|
|
8003e08: 4b14 ldr r3, [pc, #80] ; (8003e5c <HAL_GPIO_EXTI_Callback+0xfc>)
|
|||
|
|
8003e0a: 801a strh r2, [r3, #0]
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
if(GPIO_Pin == KZ_Pin) // KZ
|
|||
|
|
8003e0c: 1dbb adds r3, r7, #6
|
|||
|
|
8003e0e: 881b ldrh r3, [r3, #0]
|
|||
|
|
8003e10: 2b04 cmp r3, #4
|
|||
|
|
8003e12: d11c bne.n 8003e4e <HAL_GPIO_EXTI_Callback+0xee>
|
|||
|
|
{
|
|||
|
|
__HAL_GPIO_EXTI_CLEAR_FLAG(KZ_Pin);
|
|||
|
|
8003e14: 4b10 ldr r3, [pc, #64] ; (8003e58 <HAL_GPIO_EXTI_Callback+0xf8>)
|
|||
|
|
8003e16: 2204 movs r2, #4
|
|||
|
|
8003e18: 615a str r2, [r3, #20]
|
|||
|
|
|
|||
|
|
if(HAL_GPIO_ReadPin(GPIOA, KZ_Pin) == GPIO_PIN_SET)
|
|||
|
|
8003e1a: 23a0 movs r3, #160 ; 0xa0
|
|||
|
|
8003e1c: 05db lsls r3, r3, #23
|
|||
|
|
8003e1e: 2104 movs r1, #4
|
|||
|
|
8003e20: 0018 movs r0, r3
|
|||
|
|
8003e22: f000 fe57 bl 8004ad4 <HAL_GPIO_ReadPin>
|
|||
|
|
8003e26: 0003 movs r3, r0
|
|||
|
|
8003e28: 2b01 cmp r3, #1
|
|||
|
|
8003e2a: d108 bne.n 8003e3e <HAL_GPIO_EXTI_Callback+0xde>
|
|||
|
|
{
|
|||
|
|
//timerKZ = 1000;
|
|||
|
|
AMP_STATUS |= KZ_Pin;
|
|||
|
|
8003e2c: 4b0b ldr r3, [pc, #44] ; (8003e5c <HAL_GPIO_EXTI_Callback+0xfc>)
|
|||
|
|
8003e2e: 881b ldrh r3, [r3, #0]
|
|||
|
|
8003e30: b29b uxth r3, r3
|
|||
|
|
8003e32: 2204 movs r2, #4
|
|||
|
|
8003e34: 4313 orrs r3, r2
|
|||
|
|
8003e36: b29a uxth r2, r3
|
|||
|
|
8003e38: 4b08 ldr r3, [pc, #32] ; (8003e5c <HAL_GPIO_EXTI_Callback+0xfc>)
|
|||
|
|
8003e3a: 801a strh r2, [r3, #0]
|
|||
|
|
else
|
|||
|
|
{
|
|||
|
|
AMP_STATUS &= ~KZ_Pin;
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
8003e3c: e007 b.n 8003e4e <HAL_GPIO_EXTI_Callback+0xee>
|
|||
|
|
AMP_STATUS &= ~KZ_Pin;
|
|||
|
|
8003e3e: 4b07 ldr r3, [pc, #28] ; (8003e5c <HAL_GPIO_EXTI_Callback+0xfc>)
|
|||
|
|
8003e40: 881b ldrh r3, [r3, #0]
|
|||
|
|
8003e42: b29b uxth r3, r3
|
|||
|
|
8003e44: 2204 movs r2, #4
|
|||
|
|
8003e46: 4393 bics r3, r2
|
|||
|
|
8003e48: b29a uxth r2, r3
|
|||
|
|
8003e4a: 4b04 ldr r3, [pc, #16] ; (8003e5c <HAL_GPIO_EXTI_Callback+0xfc>)
|
|||
|
|
8003e4c: 801a strh r2, [r3, #0]
|
|||
|
|
}
|
|||
|
|
8003e4e: 46c0 nop ; (mov r8, r8)
|
|||
|
|
8003e50: 46bd mov sp, r7
|
|||
|
|
8003e52: b002 add sp, #8
|
|||
|
|
8003e54: bd80 pop {r7, pc}
|
|||
|
|
8003e56: 46c0 nop ; (mov r8, r8)
|
|||
|
|
8003e58: 40010400 .word 0x40010400
|
|||
|
|
8003e5c: 2000002c .word 0x2000002c
|
|||
|
|
|
|||
|
|
08003e60 <HAL_Init>:
|
|||
|
|
* In the default implementation,Systick is used as source of time base.
|
|||
|
|
* the tick variable is incremented each 1ms in its ISR.
|
|||
|
|
* @retval HAL status
|
|||
|
|
*/
|
|||
|
|
HAL_StatusTypeDef HAL_Init(void)
|
|||
|
|
{
|
|||
|
|
8003e60: b580 push {r7, lr}
|
|||
|
|
8003e62: b082 sub sp, #8
|
|||
|
|
8003e64: af00 add r7, sp, #0
|
|||
|
|
HAL_StatusTypeDef status = HAL_OK;
|
|||
|
|
8003e66: 1dfb adds r3, r7, #7
|
|||
|
|
8003e68: 2200 movs r2, #0
|
|||
|
|
8003e6a: 701a strb r2, [r3, #0]
|
|||
|
|
#if (BUFFER_CACHE_DISABLE != 0)
|
|||
|
|
__HAL_FLASH_BUFFER_CACHE_DISABLE();
|
|||
|
|
#endif /* BUFFER_CACHE_DISABLE */
|
|||
|
|
|
|||
|
|
#if (PREREAD_ENABLE != 0)
|
|||
|
|
__HAL_FLASH_PREREAD_BUFFER_ENABLE();
|
|||
|
|
8003e6c: 4b0b ldr r3, [pc, #44] ; (8003e9c <HAL_Init+0x3c>)
|
|||
|
|
8003e6e: 4a0b ldr r2, [pc, #44] ; (8003e9c <HAL_Init+0x3c>)
|
|||
|
|
8003e70: 6812 ldr r2, [r2, #0]
|
|||
|
|
8003e72: 2140 movs r1, #64 ; 0x40
|
|||
|
|
8003e74: 430a orrs r2, r1
|
|||
|
|
8003e76: 601a str r2, [r3, #0]
|
|||
|
|
#if (PREFETCH_ENABLE != 0)
|
|||
|
|
__HAL_FLASH_PREFETCH_BUFFER_ENABLE();
|
|||
|
|
#endif /* PREFETCH_ENABLE */
|
|||
|
|
|
|||
|
|
/* Use SysTick as time base source and configure 1ms tick (default clock after Reset is MSI) */
|
|||
|
|
if (HAL_InitTick(TICK_INT_PRIORITY) != HAL_OK)
|
|||
|
|
8003e78: 2000 movs r0, #0
|
|||
|
|
8003e7a: f000 f811 bl 8003ea0 <HAL_InitTick>
|
|||
|
|
8003e7e: 1e03 subs r3, r0, #0
|
|||
|
|
8003e80: d003 beq.n 8003e8a <HAL_Init+0x2a>
|
|||
|
|
{
|
|||
|
|
status = HAL_ERROR;
|
|||
|
|
8003e82: 1dfb adds r3, r7, #7
|
|||
|
|
8003e84: 2201 movs r2, #1
|
|||
|
|
8003e86: 701a strb r2, [r3, #0]
|
|||
|
|
8003e88: e001 b.n 8003e8e <HAL_Init+0x2e>
|
|||
|
|
}
|
|||
|
|
else
|
|||
|
|
{
|
|||
|
|
/* Init the low level hardware */
|
|||
|
|
HAL_MspInit();
|
|||
|
|
8003e8a: f7fe f9b3 bl 80021f4 <HAL_MspInit>
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
/* Return function status */
|
|||
|
|
return status;
|
|||
|
|
8003e8e: 1dfb adds r3, r7, #7
|
|||
|
|
8003e90: 781b ldrb r3, [r3, #0]
|
|||
|
|
}
|
|||
|
|
8003e92: 0018 movs r0, r3
|
|||
|
|
8003e94: 46bd mov sp, r7
|
|||
|
|
8003e96: b002 add sp, #8
|
|||
|
|
8003e98: bd80 pop {r7, pc}
|
|||
|
|
8003e9a: 46c0 nop ; (mov r8, r8)
|
|||
|
|
8003e9c: 40022000 .word 0x40022000
|
|||
|
|
|
|||
|
|
08003ea0 <HAL_InitTick>:
|
|||
|
|
* implementation in user file.
|
|||
|
|
* @param TickPriority Tick interrupt priority.
|
|||
|
|
* @retval HAL status
|
|||
|
|
*/
|
|||
|
|
__weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
|
|||
|
|
{
|
|||
|
|
8003ea0: b590 push {r4, r7, lr}
|
|||
|
|
8003ea2: b083 sub sp, #12
|
|||
|
|
8003ea4: af00 add r7, sp, #0
|
|||
|
|
8003ea6: 6078 str r0, [r7, #4]
|
|||
|
|
/* Configure the SysTick to have interrupt in 1ms time basis*/
|
|||
|
|
if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / uwTickFreq)) > 0U)
|
|||
|
|
8003ea8: 4b14 ldr r3, [pc, #80] ; (8003efc <HAL_InitTick+0x5c>)
|
|||
|
|
8003eaa: 681c ldr r4, [r3, #0]
|
|||
|
|
8003eac: 4b14 ldr r3, [pc, #80] ; (8003f00 <HAL_InitTick+0x60>)
|
|||
|
|
8003eae: 781b ldrb r3, [r3, #0]
|
|||
|
|
8003eb0: 0019 movs r1, r3
|
|||
|
|
8003eb2: 23fa movs r3, #250 ; 0xfa
|
|||
|
|
8003eb4: 0098 lsls r0, r3, #2
|
|||
|
|
8003eb6: f7fc f927 bl 8000108 <__udivsi3>
|
|||
|
|
8003eba: 0003 movs r3, r0
|
|||
|
|
8003ebc: 0019 movs r1, r3
|
|||
|
|
8003ebe: 0020 movs r0, r4
|
|||
|
|
8003ec0: f7fc f922 bl 8000108 <__udivsi3>
|
|||
|
|
8003ec4: 0003 movs r3, r0
|
|||
|
|
8003ec6: 0018 movs r0, r3
|
|||
|
|
8003ec8: f000 f93c bl 8004144 <HAL_SYSTICK_Config>
|
|||
|
|
8003ecc: 1e03 subs r3, r0, #0
|
|||
|
|
8003ece: d001 beq.n 8003ed4 <HAL_InitTick+0x34>
|
|||
|
|
{
|
|||
|
|
return HAL_ERROR;
|
|||
|
|
8003ed0: 2301 movs r3, #1
|
|||
|
|
8003ed2: e00f b.n 8003ef4 <HAL_InitTick+0x54>
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
/* Configure the SysTick IRQ priority */
|
|||
|
|
if (TickPriority < (1UL << __NVIC_PRIO_BITS))
|
|||
|
|
8003ed4: 687b ldr r3, [r7, #4]
|
|||
|
|
8003ed6: 2b03 cmp r3, #3
|
|||
|
|
8003ed8: d80b bhi.n 8003ef2 <HAL_InitTick+0x52>
|
|||
|
|
{
|
|||
|
|
HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U);
|
|||
|
|
8003eda: 6879 ldr r1, [r7, #4]
|
|||
|
|
8003edc: 2301 movs r3, #1
|
|||
|
|
8003ede: 425b negs r3, r3
|
|||
|
|
8003ee0: 2200 movs r2, #0
|
|||
|
|
8003ee2: 0018 movs r0, r3
|
|||
|
|
8003ee4: f000 f8f8 bl 80040d8 <HAL_NVIC_SetPriority>
|
|||
|
|
uwTickPrio = TickPriority;
|
|||
|
|
8003ee8: 4b06 ldr r3, [pc, #24] ; (8003f04 <HAL_InitTick+0x64>)
|
|||
|
|
8003eea: 687a ldr r2, [r7, #4]
|
|||
|
|
8003eec: 601a str r2, [r3, #0]
|
|||
|
|
{
|
|||
|
|
return HAL_ERROR;
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
/* Return function status */
|
|||
|
|
return HAL_OK;
|
|||
|
|
8003eee: 2300 movs r3, #0
|
|||
|
|
8003ef0: e000 b.n 8003ef4 <HAL_InitTick+0x54>
|
|||
|
|
return HAL_ERROR;
|
|||
|
|
8003ef2: 2301 movs r3, #1
|
|||
|
|
}
|
|||
|
|
8003ef4: 0018 movs r0, r3
|
|||
|
|
8003ef6: 46bd mov sp, r7
|
|||
|
|
8003ef8: b003 add sp, #12
|
|||
|
|
8003efa: bd90 pop {r4, r7, pc}
|
|||
|
|
8003efc: 20000000 .word 0x20000000
|
|||
|
|
8003f00: 2000000c .word 0x2000000c
|
|||
|
|
8003f04: 20000008 .word 0x20000008
|
|||
|
|
|
|||
|
|
08003f08 <HAL_IncTick>:
|
|||
|
|
* @note This function is declared as __weak to be overwritten in case of other
|
|||
|
|
* implementations in user file.
|
|||
|
|
* @retval None
|
|||
|
|
*/
|
|||
|
|
__weak void HAL_IncTick(void)
|
|||
|
|
{
|
|||
|
|
8003f08: b580 push {r7, lr}
|
|||
|
|
8003f0a: af00 add r7, sp, #0
|
|||
|
|
uwTick += uwTickFreq;
|
|||
|
|
8003f0c: 4b05 ldr r3, [pc, #20] ; (8003f24 <HAL_IncTick+0x1c>)
|
|||
|
|
8003f0e: 781b ldrb r3, [r3, #0]
|
|||
|
|
8003f10: 001a movs r2, r3
|
|||
|
|
8003f12: 4b05 ldr r3, [pc, #20] ; (8003f28 <HAL_IncTick+0x20>)
|
|||
|
|
8003f14: 681b ldr r3, [r3, #0]
|
|||
|
|
8003f16: 18d2 adds r2, r2, r3
|
|||
|
|
8003f18: 4b03 ldr r3, [pc, #12] ; (8003f28 <HAL_IncTick+0x20>)
|
|||
|
|
8003f1a: 601a str r2, [r3, #0]
|
|||
|
|
}
|
|||
|
|
8003f1c: 46c0 nop ; (mov r8, r8)
|
|||
|
|
8003f1e: 46bd mov sp, r7
|
|||
|
|
8003f20: bd80 pop {r7, pc}
|
|||
|
|
8003f22: 46c0 nop ; (mov r8, r8)
|
|||
|
|
8003f24: 2000000c .word 0x2000000c
|
|||
|
|
8003f28: 2000038c .word 0x2000038c
|
|||
|
|
|
|||
|
|
08003f2c <HAL_GetTick>:
|
|||
|
|
* @note This function is declared as __weak to be overwritten in case of other
|
|||
|
|
* implementations in user file.
|
|||
|
|
* @retval tick value
|
|||
|
|
*/
|
|||
|
|
__weak uint32_t HAL_GetTick(void)
|
|||
|
|
{
|
|||
|
|
8003f2c: b580 push {r7, lr}
|
|||
|
|
8003f2e: af00 add r7, sp, #0
|
|||
|
|
return uwTick;
|
|||
|
|
8003f30: 4b02 ldr r3, [pc, #8] ; (8003f3c <HAL_GetTick+0x10>)
|
|||
|
|
8003f32: 681b ldr r3, [r3, #0]
|
|||
|
|
}
|
|||
|
|
8003f34: 0018 movs r0, r3
|
|||
|
|
8003f36: 46bd mov sp, r7
|
|||
|
|
8003f38: bd80 pop {r7, pc}
|
|||
|
|
8003f3a: 46c0 nop ; (mov r8, r8)
|
|||
|
|
8003f3c: 2000038c .word 0x2000038c
|
|||
|
|
|
|||
|
|
08003f40 <__NVIC_EnableIRQ>:
|
|||
|
|
\details Enables a device specific interrupt in the NVIC interrupt controller.
|
|||
|
|
\param [in] IRQn Device specific interrupt number.
|
|||
|
|
\note IRQn must not be negative.
|
|||
|
|
*/
|
|||
|
|
__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
|
|||
|
|
{
|
|||
|
|
8003f40: b580 push {r7, lr}
|
|||
|
|
8003f42: b082 sub sp, #8
|
|||
|
|
8003f44: af00 add r7, sp, #0
|
|||
|
|
8003f46: 0002 movs r2, r0
|
|||
|
|
8003f48: 1dfb adds r3, r7, #7
|
|||
|
|
8003f4a: 701a strb r2, [r3, #0]
|
|||
|
|
if ((int32_t)(IRQn) >= 0)
|
|||
|
|
8003f4c: 1dfb adds r3, r7, #7
|
|||
|
|
8003f4e: 781b ldrb r3, [r3, #0]
|
|||
|
|
8003f50: 2b7f cmp r3, #127 ; 0x7f
|
|||
|
|
8003f52: d809 bhi.n 8003f68 <__NVIC_EnableIRQ+0x28>
|
|||
|
|
{
|
|||
|
|
NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
|
|||
|
|
8003f54: 4b06 ldr r3, [pc, #24] ; (8003f70 <__NVIC_EnableIRQ+0x30>)
|
|||
|
|
8003f56: 1dfa adds r2, r7, #7
|
|||
|
|
8003f58: 7812 ldrb r2, [r2, #0]
|
|||
|
|
8003f5a: 0011 movs r1, r2
|
|||
|
|
8003f5c: 221f movs r2, #31
|
|||
|
|
8003f5e: 400a ands r2, r1
|
|||
|
|
8003f60: 2101 movs r1, #1
|
|||
|
|
8003f62: 4091 lsls r1, r2
|
|||
|
|
8003f64: 000a movs r2, r1
|
|||
|
|
8003f66: 601a str r2, [r3, #0]
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
8003f68: 46c0 nop ; (mov r8, r8)
|
|||
|
|
8003f6a: 46bd mov sp, r7
|
|||
|
|
8003f6c: b002 add sp, #8
|
|||
|
|
8003f6e: bd80 pop {r7, pc}
|
|||
|
|
8003f70: e000e100 .word 0xe000e100
|
|||
|
|
|
|||
|
|
08003f74 <__NVIC_DisableIRQ>:
|
|||
|
|
\details Disables a device specific interrupt in the NVIC interrupt controller.
|
|||
|
|
\param [in] IRQn Device specific interrupt number.
|
|||
|
|
\note IRQn must not be negative.
|
|||
|
|
*/
|
|||
|
|
__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
|
|||
|
|
{
|
|||
|
|
8003f74: b580 push {r7, lr}
|
|||
|
|
8003f76: b082 sub sp, #8
|
|||
|
|
8003f78: af00 add r7, sp, #0
|
|||
|
|
8003f7a: 0002 movs r2, r0
|
|||
|
|
8003f7c: 1dfb adds r3, r7, #7
|
|||
|
|
8003f7e: 701a strb r2, [r3, #0]
|
|||
|
|
if ((int32_t)(IRQn) >= 0)
|
|||
|
|
8003f80: 1dfb adds r3, r7, #7
|
|||
|
|
8003f82: 781b ldrb r3, [r3, #0]
|
|||
|
|
8003f84: 2b7f cmp r3, #127 ; 0x7f
|
|||
|
|
8003f86: d80e bhi.n 8003fa6 <__NVIC_DisableIRQ+0x32>
|
|||
|
|
{
|
|||
|
|
NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
|
|||
|
|
8003f88: 4909 ldr r1, [pc, #36] ; (8003fb0 <__NVIC_DisableIRQ+0x3c>)
|
|||
|
|
8003f8a: 1dfb adds r3, r7, #7
|
|||
|
|
8003f8c: 781b ldrb r3, [r3, #0]
|
|||
|
|
8003f8e: 001a movs r2, r3
|
|||
|
|
8003f90: 231f movs r3, #31
|
|||
|
|
8003f92: 4013 ands r3, r2
|
|||
|
|
8003f94: 2201 movs r2, #1
|
|||
|
|
8003f96: 409a lsls r2, r3
|
|||
|
|
8003f98: 0013 movs r3, r2
|
|||
|
|
8003f9a: 2280 movs r2, #128 ; 0x80
|
|||
|
|
8003f9c: 508b str r3, [r1, r2]
|
|||
|
|
\details Acts as a special kind of Data Memory Barrier.
|
|||
|
|
It completes when all explicit memory accesses before this instruction complete.
|
|||
|
|
*/
|
|||
|
|
__STATIC_FORCEINLINE void __DSB(void)
|
|||
|
|
{
|
|||
|
|
__ASM volatile ("dsb 0xF":::"memory");
|
|||
|
|
8003f9e: f3bf 8f4f dsb sy
|
|||
|
|
__ASM volatile ("isb 0xF":::"memory");
|
|||
|
|
8003fa2: f3bf 8f6f isb sy
|
|||
|
|
__DSB();
|
|||
|
|
__ISB();
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
8003fa6: 46c0 nop ; (mov r8, r8)
|
|||
|
|
8003fa8: 46bd mov sp, r7
|
|||
|
|
8003faa: b002 add sp, #8
|
|||
|
|
8003fac: bd80 pop {r7, pc}
|
|||
|
|
8003fae: 46c0 nop ; (mov r8, r8)
|
|||
|
|
8003fb0: e000e100 .word 0xe000e100
|
|||
|
|
|
|||
|
|
08003fb4 <__NVIC_SetPriority>:
|
|||
|
|
\param [in] IRQn Interrupt number.
|
|||
|
|
\param [in] priority Priority to set.
|
|||
|
|
\note The priority cannot be set for every processor exception.
|
|||
|
|
*/
|
|||
|
|
__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
|
|||
|
|
{
|
|||
|
|
8003fb4: b5b0 push {r4, r5, r7, lr}
|
|||
|
|
8003fb6: b082 sub sp, #8
|
|||
|
|
8003fb8: af00 add r7, sp, #0
|
|||
|
|
8003fba: 0002 movs r2, r0
|
|||
|
|
8003fbc: 6039 str r1, [r7, #0]
|
|||
|
|
8003fbe: 1dfb adds r3, r7, #7
|
|||
|
|
8003fc0: 701a strb r2, [r3, #0]
|
|||
|
|
if ((int32_t)(IRQn) >= 0)
|
|||
|
|
8003fc2: 1dfb adds r3, r7, #7
|
|||
|
|
8003fc4: 781b ldrb r3, [r3, #0]
|
|||
|
|
8003fc6: 2b7f cmp r3, #127 ; 0x7f
|
|||
|
|
8003fc8: d828 bhi.n 800401c <__NVIC_SetPriority+0x68>
|
|||
|
|
{
|
|||
|
|
NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
|
|||
|
|
8003fca: 4c2f ldr r4, [pc, #188] ; (8004088 <__NVIC_SetPriority+0xd4>)
|
|||
|
|
8003fcc: 1dfb adds r3, r7, #7
|
|||
|
|
8003fce: 781b ldrb r3, [r3, #0]
|
|||
|
|
8003fd0: b25b sxtb r3, r3
|
|||
|
|
8003fd2: 089b lsrs r3, r3, #2
|
|||
|
|
8003fd4: 492c ldr r1, [pc, #176] ; (8004088 <__NVIC_SetPriority+0xd4>)
|
|||
|
|
8003fd6: 1dfa adds r2, r7, #7
|
|||
|
|
8003fd8: 7812 ldrb r2, [r2, #0]
|
|||
|
|
8003fda: b252 sxtb r2, r2
|
|||
|
|
8003fdc: 0892 lsrs r2, r2, #2
|
|||
|
|
8003fde: 32c0 adds r2, #192 ; 0xc0
|
|||
|
|
8003fe0: 0092 lsls r2, r2, #2
|
|||
|
|
8003fe2: 5852 ldr r2, [r2, r1]
|
|||
|
|
8003fe4: 1df9 adds r1, r7, #7
|
|||
|
|
8003fe6: 7809 ldrb r1, [r1, #0]
|
|||
|
|
8003fe8: 0008 movs r0, r1
|
|||
|
|
8003fea: 2103 movs r1, #3
|
|||
|
|
8003fec: 4001 ands r1, r0
|
|||
|
|
8003fee: 00c9 lsls r1, r1, #3
|
|||
|
|
8003ff0: 20ff movs r0, #255 ; 0xff
|
|||
|
|
8003ff2: 4088 lsls r0, r1
|
|||
|
|
8003ff4: 0001 movs r1, r0
|
|||
|
|
8003ff6: 43c9 mvns r1, r1
|
|||
|
|
8003ff8: 4011 ands r1, r2
|
|||
|
|
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
|
|||
|
|
8003ffa: 683a ldr r2, [r7, #0]
|
|||
|
|
8003ffc: 0192 lsls r2, r2, #6
|
|||
|
|
8003ffe: 20ff movs r0, #255 ; 0xff
|
|||
|
|
8004000: 4010 ands r0, r2
|
|||
|
|
8004002: 1dfa adds r2, r7, #7
|
|||
|
|
8004004: 7812 ldrb r2, [r2, #0]
|
|||
|
|
8004006: 0015 movs r5, r2
|
|||
|
|
8004008: 2203 movs r2, #3
|
|||
|
|
800400a: 402a ands r2, r5
|
|||
|
|
800400c: 00d2 lsls r2, r2, #3
|
|||
|
|
800400e: 4090 lsls r0, r2
|
|||
|
|
8004010: 0002 movs r2, r0
|
|||
|
|
NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
|
|||
|
|
8004012: 430a orrs r2, r1
|
|||
|
|
8004014: 33c0 adds r3, #192 ; 0xc0
|
|||
|
|
8004016: 009b lsls r3, r3, #2
|
|||
|
|
8004018: 511a str r2, [r3, r4]
|
|||
|
|
else
|
|||
|
|
{
|
|||
|
|
SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
|
|||
|
|
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
800401a: e031 b.n 8004080 <__NVIC_SetPriority+0xcc>
|
|||
|
|
SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
|
|||
|
|
800401c: 4c1b ldr r4, [pc, #108] ; (800408c <__NVIC_SetPriority+0xd8>)
|
|||
|
|
800401e: 1dfb adds r3, r7, #7
|
|||
|
|
8004020: 781b ldrb r3, [r3, #0]
|
|||
|
|
8004022: 001a movs r2, r3
|
|||
|
|
8004024: 230f movs r3, #15
|
|||
|
|
8004026: 4013 ands r3, r2
|
|||
|
|
8004028: 3b08 subs r3, #8
|
|||
|
|
800402a: 0899 lsrs r1, r3, #2
|
|||
|
|
800402c: 4a17 ldr r2, [pc, #92] ; (800408c <__NVIC_SetPriority+0xd8>)
|
|||
|
|
800402e: 1dfb adds r3, r7, #7
|
|||
|
|
8004030: 781b ldrb r3, [r3, #0]
|
|||
|
|
8004032: 0018 movs r0, r3
|
|||
|
|
8004034: 230f movs r3, #15
|
|||
|
|
8004036: 4003 ands r3, r0
|
|||
|
|
8004038: 3b08 subs r3, #8
|
|||
|
|
800403a: 089b lsrs r3, r3, #2
|
|||
|
|
800403c: 3306 adds r3, #6
|
|||
|
|
800403e: 009b lsls r3, r3, #2
|
|||
|
|
8004040: 18d3 adds r3, r2, r3
|
|||
|
|
8004042: 3304 adds r3, #4
|
|||
|
|
8004044: 681b ldr r3, [r3, #0]
|
|||
|
|
8004046: 1dfa adds r2, r7, #7
|
|||
|
|
8004048: 7812 ldrb r2, [r2, #0]
|
|||
|
|
800404a: 0010 movs r0, r2
|
|||
|
|
800404c: 2203 movs r2, #3
|
|||
|
|
800404e: 4002 ands r2, r0
|
|||
|
|
8004050: 00d2 lsls r2, r2, #3
|
|||
|
|
8004052: 20ff movs r0, #255 ; 0xff
|
|||
|
|
8004054: 4090 lsls r0, r2
|
|||
|
|
8004056: 0002 movs r2, r0
|
|||
|
|
8004058: 43d2 mvns r2, r2
|
|||
|
|
800405a: 401a ands r2, r3
|
|||
|
|
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
|
|||
|
|
800405c: 683b ldr r3, [r7, #0]
|
|||
|
|
800405e: 019b lsls r3, r3, #6
|
|||
|
|
8004060: 20ff movs r0, #255 ; 0xff
|
|||
|
|
8004062: 4018 ands r0, r3
|
|||
|
|
8004064: 1dfb adds r3, r7, #7
|
|||
|
|
8004066: 781b ldrb r3, [r3, #0]
|
|||
|
|
8004068: 001d movs r5, r3
|
|||
|
|
800406a: 2303 movs r3, #3
|
|||
|
|
800406c: 402b ands r3, r5
|
|||
|
|
800406e: 00db lsls r3, r3, #3
|
|||
|
|
8004070: 4098 lsls r0, r3
|
|||
|
|
8004072: 0003 movs r3, r0
|
|||
|
|
SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
|
|||
|
|
8004074: 431a orrs r2, r3
|
|||
|
|
8004076: 1d8b adds r3, r1, #6
|
|||
|
|
8004078: 009b lsls r3, r3, #2
|
|||
|
|
800407a: 18e3 adds r3, r4, r3
|
|||
|
|
800407c: 3304 adds r3, #4
|
|||
|
|
800407e: 601a str r2, [r3, #0]
|
|||
|
|
}
|
|||
|
|
8004080: 46c0 nop ; (mov r8, r8)
|
|||
|
|
8004082: 46bd mov sp, r7
|
|||
|
|
8004084: b002 add sp, #8
|
|||
|
|
8004086: bdb0 pop {r4, r5, r7, pc}
|
|||
|
|
8004088: e000e100 .word 0xe000e100
|
|||
|
|
800408c: e000ed00 .word 0xe000ed00
|
|||
|
|
|
|||
|
|
08004090 <SysTick_Config>:
|
|||
|
|
\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
|
|||
|
|
function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
|
|||
|
|
must contain a vendor-specific implementation of this function.
|
|||
|
|
*/
|
|||
|
|
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
|
|||
|
|
{
|
|||
|
|
8004090: b580 push {r7, lr}
|
|||
|
|
8004092: b082 sub sp, #8
|
|||
|
|
8004094: af00 add r7, sp, #0
|
|||
|
|
8004096: 6078 str r0, [r7, #4]
|
|||
|
|
if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
|
|||
|
|
8004098: 687b ldr r3, [r7, #4]
|
|||
|
|
800409a: 3b01 subs r3, #1
|
|||
|
|
800409c: 4a0c ldr r2, [pc, #48] ; (80040d0 <SysTick_Config+0x40>)
|
|||
|
|
800409e: 4293 cmp r3, r2
|
|||
|
|
80040a0: d901 bls.n 80040a6 <SysTick_Config+0x16>
|
|||
|
|
{
|
|||
|
|
return (1UL); /* Reload value impossible */
|
|||
|
|
80040a2: 2301 movs r3, #1
|
|||
|
|
80040a4: e010 b.n 80040c8 <SysTick_Config+0x38>
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
|
|||
|
|
80040a6: 4b0b ldr r3, [pc, #44] ; (80040d4 <SysTick_Config+0x44>)
|
|||
|
|
80040a8: 687a ldr r2, [r7, #4]
|
|||
|
|
80040aa: 3a01 subs r2, #1
|
|||
|
|
80040ac: 605a str r2, [r3, #4]
|
|||
|
|
NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
|
|||
|
|
80040ae: 2301 movs r3, #1
|
|||
|
|
80040b0: 425b negs r3, r3
|
|||
|
|
80040b2: 2103 movs r1, #3
|
|||
|
|
80040b4: 0018 movs r0, r3
|
|||
|
|
80040b6: f7ff ff7d bl 8003fb4 <__NVIC_SetPriority>
|
|||
|
|
SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
|
|||
|
|
80040ba: 4b06 ldr r3, [pc, #24] ; (80040d4 <SysTick_Config+0x44>)
|
|||
|
|
80040bc: 2200 movs r2, #0
|
|||
|
|
80040be: 609a str r2, [r3, #8]
|
|||
|
|
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
|
|||
|
|
80040c0: 4b04 ldr r3, [pc, #16] ; (80040d4 <SysTick_Config+0x44>)
|
|||
|
|
80040c2: 2207 movs r2, #7
|
|||
|
|
80040c4: 601a str r2, [r3, #0]
|
|||
|
|
SysTick_CTRL_TICKINT_Msk |
|
|||
|
|
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
|
|||
|
|
return (0UL); /* Function successful */
|
|||
|
|
80040c6: 2300 movs r3, #0
|
|||
|
|
}
|
|||
|
|
80040c8: 0018 movs r0, r3
|
|||
|
|
80040ca: 46bd mov sp, r7
|
|||
|
|
80040cc: b002 add sp, #8
|
|||
|
|
80040ce: bd80 pop {r7, pc}
|
|||
|
|
80040d0: 00ffffff .word 0x00ffffff
|
|||
|
|
80040d4: e000e010 .word 0xe000e010
|
|||
|
|
|
|||
|
|
080040d8 <HAL_NVIC_SetPriority>:
|
|||
|
|
* with stm32l0xx devices, this parameter is a dummy value and it is ignored, because
|
|||
|
|
* no subpriority supported in Cortex M0+ based products.
|
|||
|
|
* @retval None
|
|||
|
|
*/
|
|||
|
|
void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
|
|||
|
|
{
|
|||
|
|
80040d8: b580 push {r7, lr}
|
|||
|
|
80040da: b084 sub sp, #16
|
|||
|
|
80040dc: af00 add r7, sp, #0
|
|||
|
|
80040de: 60b9 str r1, [r7, #8]
|
|||
|
|
80040e0: 607a str r2, [r7, #4]
|
|||
|
|
80040e2: 230f movs r3, #15
|
|||
|
|
80040e4: 18fb adds r3, r7, r3
|
|||
|
|
80040e6: 1c02 adds r2, r0, #0
|
|||
|
|
80040e8: 701a strb r2, [r3, #0]
|
|||
|
|
/* Check the parameters */
|
|||
|
|
assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority));
|
|||
|
|
NVIC_SetPriority(IRQn,PreemptPriority);
|
|||
|
|
80040ea: 68ba ldr r2, [r7, #8]
|
|||
|
|
80040ec: 230f movs r3, #15
|
|||
|
|
80040ee: 18fb adds r3, r7, r3
|
|||
|
|
80040f0: 781b ldrb r3, [r3, #0]
|
|||
|
|
80040f2: b25b sxtb r3, r3
|
|||
|
|
80040f4: 0011 movs r1, r2
|
|||
|
|
80040f6: 0018 movs r0, r3
|
|||
|
|
80040f8: f7ff ff5c bl 8003fb4 <__NVIC_SetPriority>
|
|||
|
|
}
|
|||
|
|
80040fc: 46c0 nop ; (mov r8, r8)
|
|||
|
|
80040fe: 46bd mov sp, r7
|
|||
|
|
8004100: b004 add sp, #16
|
|||
|
|
8004102: bd80 pop {r7, pc}
|
|||
|
|
|
|||
|
|
08004104 <HAL_NVIC_EnableIRQ>:
|
|||
|
|
* This parameter can be an enumerator of IRQn_Type enumeration
|
|||
|
|
* (For the complete STM32 Devices IRQ Channels list, please refer to stm32l0xx.h file)
|
|||
|
|
* @retval None
|
|||
|
|
*/
|
|||
|
|
void HAL_NVIC_EnableIRQ(IRQn_Type IRQn)
|
|||
|
|
{
|
|||
|
|
8004104: b580 push {r7, lr}
|
|||
|
|
8004106: b082 sub sp, #8
|
|||
|
|
8004108: af00 add r7, sp, #0
|
|||
|
|
800410a: 0002 movs r2, r0
|
|||
|
|
800410c: 1dfb adds r3, r7, #7
|
|||
|
|
800410e: 701a strb r2, [r3, #0]
|
|||
|
|
/* Check the parameters */
|
|||
|
|
assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
|
|||
|
|
|
|||
|
|
/* Enable interrupt */
|
|||
|
|
NVIC_EnableIRQ(IRQn);
|
|||
|
|
8004110: 1dfb adds r3, r7, #7
|
|||
|
|
8004112: 781b ldrb r3, [r3, #0]
|
|||
|
|
8004114: b25b sxtb r3, r3
|
|||
|
|
8004116: 0018 movs r0, r3
|
|||
|
|
8004118: f7ff ff12 bl 8003f40 <__NVIC_EnableIRQ>
|
|||
|
|
}
|
|||
|
|
800411c: 46c0 nop ; (mov r8, r8)
|
|||
|
|
800411e: 46bd mov sp, r7
|
|||
|
|
8004120: b002 add sp, #8
|
|||
|
|
8004122: bd80 pop {r7, pc}
|
|||
|
|
|
|||
|
|
08004124 <HAL_NVIC_DisableIRQ>:
|
|||
|
|
* This parameter can be an enumerator of IRQn_Type enumeration
|
|||
|
|
* (For the complete STM32 Devices IRQ Channels list, please refer to stm32l0xx.h file)
|
|||
|
|
* @retval None
|
|||
|
|
*/
|
|||
|
|
void HAL_NVIC_DisableIRQ(IRQn_Type IRQn)
|
|||
|
|
{
|
|||
|
|
8004124: b580 push {r7, lr}
|
|||
|
|
8004126: b082 sub sp, #8
|
|||
|
|
8004128: af00 add r7, sp, #0
|
|||
|
|
800412a: 0002 movs r2, r0
|
|||
|
|
800412c: 1dfb adds r3, r7, #7
|
|||
|
|
800412e: 701a strb r2, [r3, #0]
|
|||
|
|
/* Check the parameters */
|
|||
|
|
assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
|
|||
|
|
|
|||
|
|
/* Disable interrupt */
|
|||
|
|
NVIC_DisableIRQ(IRQn);
|
|||
|
|
8004130: 1dfb adds r3, r7, #7
|
|||
|
|
8004132: 781b ldrb r3, [r3, #0]
|
|||
|
|
8004134: b25b sxtb r3, r3
|
|||
|
|
8004136: 0018 movs r0, r3
|
|||
|
|
8004138: f7ff ff1c bl 8003f74 <__NVIC_DisableIRQ>
|
|||
|
|
}
|
|||
|
|
800413c: 46c0 nop ; (mov r8, r8)
|
|||
|
|
800413e: 46bd mov sp, r7
|
|||
|
|
8004140: b002 add sp, #8
|
|||
|
|
8004142: bd80 pop {r7, pc}
|
|||
|
|
|
|||
|
|
08004144 <HAL_SYSTICK_Config>:
|
|||
|
|
* @param TicksNumb Specifies the ticks Number of ticks between two interrupts.
|
|||
|
|
* @retval status: - 0 Function succeeded.
|
|||
|
|
* - 1 Function failed.
|
|||
|
|
*/
|
|||
|
|
uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb)
|
|||
|
|
{
|
|||
|
|
8004144: b580 push {r7, lr}
|
|||
|
|
8004146: b082 sub sp, #8
|
|||
|
|
8004148: af00 add r7, sp, #0
|
|||
|
|
800414a: 6078 str r0, [r7, #4]
|
|||
|
|
return SysTick_Config(TicksNumb);
|
|||
|
|
800414c: 687b ldr r3, [r7, #4]
|
|||
|
|
800414e: 0018 movs r0, r3
|
|||
|
|
8004150: f7ff ff9e bl 8004090 <SysTick_Config>
|
|||
|
|
8004154: 0003 movs r3, r0
|
|||
|
|
}
|
|||
|
|
8004156: 0018 movs r0, r3
|
|||
|
|
8004158: 46bd mov sp, r7
|
|||
|
|
800415a: b002 add sp, #8
|
|||
|
|
800415c: bd80 pop {r7, pc}
|
|||
|
|
|
|||
|
|
0800415e <HAL_DMA_Abort>:
|
|||
|
|
* @param hdma pointer to a DMA_HandleTypeDef structure that contains
|
|||
|
|
* the configuration information for the specified DMA Channel.
|
|||
|
|
* @retval HAL status
|
|||
|
|
*/
|
|||
|
|
HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma)
|
|||
|
|
{
|
|||
|
|
800415e: b580 push {r7, lr}
|
|||
|
|
8004160: b084 sub sp, #16
|
|||
|
|
8004162: af00 add r7, sp, #0
|
|||
|
|
8004164: 6078 str r0, [r7, #4]
|
|||
|
|
HAL_StatusTypeDef status = HAL_OK;
|
|||
|
|
8004166: 230f movs r3, #15
|
|||
|
|
8004168: 18fb adds r3, r7, r3
|
|||
|
|
800416a: 2200 movs r2, #0
|
|||
|
|
800416c: 701a strb r2, [r3, #0]
|
|||
|
|
|
|||
|
|
/* Check the DMA peripheral state */
|
|||
|
|
if(hdma->State != HAL_DMA_STATE_BUSY)
|
|||
|
|
800416e: 687b ldr r3, [r7, #4]
|
|||
|
|
8004170: 2225 movs r2, #37 ; 0x25
|
|||
|
|
8004172: 5c9b ldrb r3, [r3, r2]
|
|||
|
|
8004174: b2db uxtb r3, r3
|
|||
|
|
8004176: 2b02 cmp r3, #2
|
|||
|
|
8004178: d008 beq.n 800418c <HAL_DMA_Abort+0x2e>
|
|||
|
|
{
|
|||
|
|
hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
|
|||
|
|
800417a: 687b ldr r3, [r7, #4]
|
|||
|
|
800417c: 2204 movs r2, #4
|
|||
|
|
800417e: 63da str r2, [r3, #60] ; 0x3c
|
|||
|
|
|
|||
|
|
/* Process Unlocked */
|
|||
|
|
__HAL_UNLOCK(hdma);
|
|||
|
|
8004180: 687b ldr r3, [r7, #4]
|
|||
|
|
8004182: 2224 movs r2, #36 ; 0x24
|
|||
|
|
8004184: 2100 movs r1, #0
|
|||
|
|
8004186: 5499 strb r1, [r3, r2]
|
|||
|
|
|
|||
|
|
return HAL_ERROR;
|
|||
|
|
8004188: 2301 movs r3, #1
|
|||
|
|
800418a: e024 b.n 80041d6 <HAL_DMA_Abort+0x78>
|
|||
|
|
}
|
|||
|
|
else
|
|||
|
|
{
|
|||
|
|
/* Disable DMA IT */
|
|||
|
|
__HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));
|
|||
|
|
800418c: 687b ldr r3, [r7, #4]
|
|||
|
|
800418e: 681b ldr r3, [r3, #0]
|
|||
|
|
8004190: 687a ldr r2, [r7, #4]
|
|||
|
|
8004192: 6812 ldr r2, [r2, #0]
|
|||
|
|
8004194: 6812 ldr r2, [r2, #0]
|
|||
|
|
8004196: 210e movs r1, #14
|
|||
|
|
8004198: 438a bics r2, r1
|
|||
|
|
800419a: 601a str r2, [r3, #0]
|
|||
|
|
|
|||
|
|
/* Disable the channel */
|
|||
|
|
__HAL_DMA_DISABLE(hdma);
|
|||
|
|
800419c: 687b ldr r3, [r7, #4]
|
|||
|
|
800419e: 681b ldr r3, [r3, #0]
|
|||
|
|
80041a0: 687a ldr r2, [r7, #4]
|
|||
|
|
80041a2: 6812 ldr r2, [r2, #0]
|
|||
|
|
80041a4: 6812 ldr r2, [r2, #0]
|
|||
|
|
80041a6: 2101 movs r1, #1
|
|||
|
|
80041a8: 438a bics r2, r1
|
|||
|
|
80041aa: 601a str r2, [r3, #0]
|
|||
|
|
|
|||
|
|
/* Clear all flags */
|
|||
|
|
hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1cU));
|
|||
|
|
80041ac: 687b ldr r3, [r7, #4]
|
|||
|
|
80041ae: 6c1b ldr r3, [r3, #64] ; 0x40
|
|||
|
|
80041b0: 687a ldr r2, [r7, #4]
|
|||
|
|
80041b2: 6c52 ldr r2, [r2, #68] ; 0x44
|
|||
|
|
80041b4: 211c movs r1, #28
|
|||
|
|
80041b6: 400a ands r2, r1
|
|||
|
|
80041b8: 2101 movs r1, #1
|
|||
|
|
80041ba: 4091 lsls r1, r2
|
|||
|
|
80041bc: 000a movs r2, r1
|
|||
|
|
80041be: 605a str r2, [r3, #4]
|
|||
|
|
|
|||
|
|
/* Change the DMA state */
|
|||
|
|
hdma->State = HAL_DMA_STATE_READY;
|
|||
|
|
80041c0: 687b ldr r3, [r7, #4]
|
|||
|
|
80041c2: 2225 movs r2, #37 ; 0x25
|
|||
|
|
80041c4: 2101 movs r1, #1
|
|||
|
|
80041c6: 5499 strb r1, [r3, r2]
|
|||
|
|
|
|||
|
|
/* Process Unlocked */
|
|||
|
|
__HAL_UNLOCK(hdma);
|
|||
|
|
80041c8: 687b ldr r3, [r7, #4]
|
|||
|
|
80041ca: 2224 movs r2, #36 ; 0x24
|
|||
|
|
80041cc: 2100 movs r1, #0
|
|||
|
|
80041ce: 5499 strb r1, [r3, r2]
|
|||
|
|
|
|||
|
|
return status;
|
|||
|
|
80041d0: 230f movs r3, #15
|
|||
|
|
80041d2: 18fb adds r3, r7, r3
|
|||
|
|
80041d4: 781b ldrb r3, [r3, #0]
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
80041d6: 0018 movs r0, r3
|
|||
|
|
80041d8: 46bd mov sp, r7
|
|||
|
|
80041da: b004 add sp, #16
|
|||
|
|
80041dc: bd80 pop {r7, pc}
|
|||
|
|
|
|||
|
|
080041de <HAL_DMA_Abort_IT>:
|
|||
|
|
* @param hdma pointer to a DMA_HandleTypeDef structure that contains
|
|||
|
|
* the configuration information for the specified DMA Channel.
|
|||
|
|
* @retval HAL status
|
|||
|
|
*/
|
|||
|
|
HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma)
|
|||
|
|
{
|
|||
|
|
80041de: b580 push {r7, lr}
|
|||
|
|
80041e0: b084 sub sp, #16
|
|||
|
|
80041e2: af00 add r7, sp, #0
|
|||
|
|
80041e4: 6078 str r0, [r7, #4]
|
|||
|
|
HAL_StatusTypeDef status = HAL_OK;
|
|||
|
|
80041e6: 230f movs r3, #15
|
|||
|
|
80041e8: 18fb adds r3, r7, r3
|
|||
|
|
80041ea: 2200 movs r2, #0
|
|||
|
|
80041ec: 701a strb r2, [r3, #0]
|
|||
|
|
|
|||
|
|
if(HAL_DMA_STATE_BUSY != hdma->State)
|
|||
|
|
80041ee: 687b ldr r3, [r7, #4]
|
|||
|
|
80041f0: 2225 movs r2, #37 ; 0x25
|
|||
|
|
80041f2: 5c9b ldrb r3, [r3, r2]
|
|||
|
|
80041f4: b2db uxtb r3, r3
|
|||
|
|
80041f6: 2b02 cmp r3, #2
|
|||
|
|
80041f8: d007 beq.n 800420a <HAL_DMA_Abort_IT+0x2c>
|
|||
|
|
{
|
|||
|
|
/* no transfer ongoing */
|
|||
|
|
hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
|
|||
|
|
80041fa: 687b ldr r3, [r7, #4]
|
|||
|
|
80041fc: 2204 movs r2, #4
|
|||
|
|
80041fe: 63da str r2, [r3, #60] ; 0x3c
|
|||
|
|
|
|||
|
|
status = HAL_ERROR;
|
|||
|
|
8004200: 230f movs r3, #15
|
|||
|
|
8004202: 18fb adds r3, r7, r3
|
|||
|
|
8004204: 2201 movs r2, #1
|
|||
|
|
8004206: 701a strb r2, [r3, #0]
|
|||
|
|
8004208: e02a b.n 8004260 <HAL_DMA_Abort_IT+0x82>
|
|||
|
|
}
|
|||
|
|
else
|
|||
|
|
{
|
|||
|
|
/* Disable DMA IT */
|
|||
|
|
__HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));
|
|||
|
|
800420a: 687b ldr r3, [r7, #4]
|
|||
|
|
800420c: 681b ldr r3, [r3, #0]
|
|||
|
|
800420e: 687a ldr r2, [r7, #4]
|
|||
|
|
8004210: 6812 ldr r2, [r2, #0]
|
|||
|
|
8004212: 6812 ldr r2, [r2, #0]
|
|||
|
|
8004214: 210e movs r1, #14
|
|||
|
|
8004216: 438a bics r2, r1
|
|||
|
|
8004218: 601a str r2, [r3, #0]
|
|||
|
|
|
|||
|
|
/* Disable the channel */
|
|||
|
|
__HAL_DMA_DISABLE(hdma);
|
|||
|
|
800421a: 687b ldr r3, [r7, #4]
|
|||
|
|
800421c: 681b ldr r3, [r3, #0]
|
|||
|
|
800421e: 687a ldr r2, [r7, #4]
|
|||
|
|
8004220: 6812 ldr r2, [r2, #0]
|
|||
|
|
8004222: 6812 ldr r2, [r2, #0]
|
|||
|
|
8004224: 2101 movs r1, #1
|
|||
|
|
8004226: 438a bics r2, r1
|
|||
|
|
8004228: 601a str r2, [r3, #0]
|
|||
|
|
|
|||
|
|
/* Clear all flags */
|
|||
|
|
hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1cU));
|
|||
|
|
800422a: 687b ldr r3, [r7, #4]
|
|||
|
|
800422c: 6c1b ldr r3, [r3, #64] ; 0x40
|
|||
|
|
800422e: 687a ldr r2, [r7, #4]
|
|||
|
|
8004230: 6c52 ldr r2, [r2, #68] ; 0x44
|
|||
|
|
8004232: 211c movs r1, #28
|
|||
|
|
8004234: 400a ands r2, r1
|
|||
|
|
8004236: 2101 movs r1, #1
|
|||
|
|
8004238: 4091 lsls r1, r2
|
|||
|
|
800423a: 000a movs r2, r1
|
|||
|
|
800423c: 605a str r2, [r3, #4]
|
|||
|
|
|
|||
|
|
/* Change the DMA state */
|
|||
|
|
hdma->State = HAL_DMA_STATE_READY;
|
|||
|
|
800423e: 687b ldr r3, [r7, #4]
|
|||
|
|
8004240: 2225 movs r2, #37 ; 0x25
|
|||
|
|
8004242: 2101 movs r1, #1
|
|||
|
|
8004244: 5499 strb r1, [r3, r2]
|
|||
|
|
|
|||
|
|
/* Process Unlocked */
|
|||
|
|
__HAL_UNLOCK(hdma);
|
|||
|
|
8004246: 687b ldr r3, [r7, #4]
|
|||
|
|
8004248: 2224 movs r2, #36 ; 0x24
|
|||
|
|
800424a: 2100 movs r1, #0
|
|||
|
|
800424c: 5499 strb r1, [r3, r2]
|
|||
|
|
|
|||
|
|
/* Call User Abort callback */
|
|||
|
|
if(hdma->XferAbortCallback != NULL)
|
|||
|
|
800424e: 687b ldr r3, [r7, #4]
|
|||
|
|
8004250: 6b9b ldr r3, [r3, #56] ; 0x38
|
|||
|
|
8004252: 2b00 cmp r3, #0
|
|||
|
|
8004254: d004 beq.n 8004260 <HAL_DMA_Abort_IT+0x82>
|
|||
|
|
{
|
|||
|
|
hdma->XferAbortCallback(hdma);
|
|||
|
|
8004256: 687b ldr r3, [r7, #4]
|
|||
|
|
8004258: 6b9b ldr r3, [r3, #56] ; 0x38
|
|||
|
|
800425a: 687a ldr r2, [r7, #4]
|
|||
|
|
800425c: 0010 movs r0, r2
|
|||
|
|
800425e: 4798 blx r3
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
return status;
|
|||
|
|
8004260: 230f movs r3, #15
|
|||
|
|
8004262: 18fb adds r3, r7, r3
|
|||
|
|
8004264: 781b ldrb r3, [r3, #0]
|
|||
|
|
}
|
|||
|
|
8004266: 0018 movs r0, r3
|
|||
|
|
8004268: 46bd mov sp, r7
|
|||
|
|
800426a: b004 add sp, #16
|
|||
|
|
800426c: bd80 pop {r7, pc}
|
|||
|
|
...
|
|||
|
|
|
|||
|
|
08004270 <HAL_FLASH_Program>:
|
|||
|
|
* @param Data Specifie the data to be programmed
|
|||
|
|
*
|
|||
|
|
* @retval HAL_StatusTypeDef HAL Status
|
|||
|
|
*/
|
|||
|
|
HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint32_t Data)
|
|||
|
|
{
|
|||
|
|
8004270: b590 push {r4, r7, lr}
|
|||
|
|
8004272: b087 sub sp, #28
|
|||
|
|
8004274: af00 add r7, sp, #0
|
|||
|
|
8004276: 60f8 str r0, [r7, #12]
|
|||
|
|
8004278: 60b9 str r1, [r7, #8]
|
|||
|
|
800427a: 607a str r2, [r7, #4]
|
|||
|
|
HAL_StatusTypeDef status = HAL_ERROR;
|
|||
|
|
800427c: 2317 movs r3, #23
|
|||
|
|
800427e: 18fb adds r3, r7, r3
|
|||
|
|
8004280: 2201 movs r2, #1
|
|||
|
|
8004282: 701a strb r2, [r3, #0]
|
|||
|
|
|
|||
|
|
/* Process Locked */
|
|||
|
|
__HAL_LOCK(&pFlash);
|
|||
|
|
8004284: 4b16 ldr r3, [pc, #88] ; (80042e0 <HAL_FLASH_Program+0x70>)
|
|||
|
|
8004286: 7c1b ldrb r3, [r3, #16]
|
|||
|
|
8004288: 2b01 cmp r3, #1
|
|||
|
|
800428a: d101 bne.n 8004290 <HAL_FLASH_Program+0x20>
|
|||
|
|
800428c: 2302 movs r3, #2
|
|||
|
|
800428e: e023 b.n 80042d8 <HAL_FLASH_Program+0x68>
|
|||
|
|
8004290: 4b13 ldr r3, [pc, #76] ; (80042e0 <HAL_FLASH_Program+0x70>)
|
|||
|
|
8004292: 2201 movs r2, #1
|
|||
|
|
8004294: 741a strb r2, [r3, #16]
|
|||
|
|
/* Check the parameters */
|
|||
|
|
assert_param(IS_FLASH_TYPEPROGRAM(TypeProgram));
|
|||
|
|
assert_param(IS_FLASH_PROGRAM_ADDRESS(Address));
|
|||
|
|
|
|||
|
|
/* Wait for last operation to be completed */
|
|||
|
|
status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
|
|||
|
|
8004296: 2317 movs r3, #23
|
|||
|
|
8004298: 18fc adds r4, r7, r3
|
|||
|
|
800429a: 4b12 ldr r3, [pc, #72] ; (80042e4 <HAL_FLASH_Program+0x74>)
|
|||
|
|
800429c: 0018 movs r0, r3
|
|||
|
|
800429e: f000 f887 bl 80043b0 <FLASH_WaitForLastOperation>
|
|||
|
|
80042a2: 0003 movs r3, r0
|
|||
|
|
80042a4: 7023 strb r3, [r4, #0]
|
|||
|
|
|
|||
|
|
if(status == HAL_OK)
|
|||
|
|
80042a6: 2317 movs r3, #23
|
|||
|
|
80042a8: 18fb adds r3, r7, r3
|
|||
|
|
80042aa: 781b ldrb r3, [r3, #0]
|
|||
|
|
80042ac: 2b00 cmp r3, #0
|
|||
|
|
80042ae: d10d bne.n 80042cc <HAL_FLASH_Program+0x5c>
|
|||
|
|
{
|
|||
|
|
/* Clean the error context */
|
|||
|
|
pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
|
|||
|
|
80042b0: 4b0b ldr r3, [pc, #44] ; (80042e0 <HAL_FLASH_Program+0x70>)
|
|||
|
|
80042b2: 2200 movs r2, #0
|
|||
|
|
80042b4: 615a str r2, [r3, #20]
|
|||
|
|
|
|||
|
|
/*Program word (32-bit) at a specified address.*/
|
|||
|
|
*(__IO uint32_t *)Address = Data;
|
|||
|
|
80042b6: 68bb ldr r3, [r7, #8]
|
|||
|
|
80042b8: 687a ldr r2, [r7, #4]
|
|||
|
|
80042ba: 601a str r2, [r3, #0]
|
|||
|
|
|
|||
|
|
/* Wait for last operation to be completed */
|
|||
|
|
status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
|
|||
|
|
80042bc: 2317 movs r3, #23
|
|||
|
|
80042be: 18fc adds r4, r7, r3
|
|||
|
|
80042c0: 4b08 ldr r3, [pc, #32] ; (80042e4 <HAL_FLASH_Program+0x74>)
|
|||
|
|
80042c2: 0018 movs r0, r3
|
|||
|
|
80042c4: f000 f874 bl 80043b0 <FLASH_WaitForLastOperation>
|
|||
|
|
80042c8: 0003 movs r3, r0
|
|||
|
|
80042ca: 7023 strb r3, [r4, #0]
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
/* Process Unlocked */
|
|||
|
|
__HAL_UNLOCK(&pFlash);
|
|||
|
|
80042cc: 4b04 ldr r3, [pc, #16] ; (80042e0 <HAL_FLASH_Program+0x70>)
|
|||
|
|
80042ce: 2200 movs r2, #0
|
|||
|
|
80042d0: 741a strb r2, [r3, #16]
|
|||
|
|
|
|||
|
|
return status;
|
|||
|
|
80042d2: 2317 movs r3, #23
|
|||
|
|
80042d4: 18fb adds r3, r7, r3
|
|||
|
|
80042d6: 781b ldrb r3, [r3, #0]
|
|||
|
|
}
|
|||
|
|
80042d8: 0018 movs r0, r3
|
|||
|
|
80042da: 46bd mov sp, r7
|
|||
|
|
80042dc: b007 add sp, #28
|
|||
|
|
80042de: bd90 pop {r4, r7, pc}
|
|||
|
|
80042e0: 20000390 .word 0x20000390
|
|||
|
|
80042e4: 0000c350 .word 0x0000c350
|
|||
|
|
|
|||
|
|
080042e8 <HAL_FLASH_Unlock>:
|
|||
|
|
/**
|
|||
|
|
* @brief Unlock the FLASH control register access
|
|||
|
|
* @retval HAL Status
|
|||
|
|
*/
|
|||
|
|
HAL_StatusTypeDef HAL_FLASH_Unlock(void)
|
|||
|
|
{
|
|||
|
|
80042e8: b580 push {r7, lr}
|
|||
|
|
80042ea: b086 sub sp, #24
|
|||
|
|
80042ec: af00 add r7, sp, #0
|
|||
|
|
uint32_t primask_bit;
|
|||
|
|
|
|||
|
|
/* Unlocking FLASH_PECR register access*/
|
|||
|
|
if(HAL_IS_BIT_SET(FLASH->PECR, FLASH_PECR_PELOCK))
|
|||
|
|
80042ee: 4b21 ldr r3, [pc, #132] ; (8004374 <HAL_FLASH_Unlock+0x8c>)
|
|||
|
|
80042f0: 685b ldr r3, [r3, #4]
|
|||
|
|
80042f2: 2201 movs r2, #1
|
|||
|
|
80042f4: 4013 ands r3, r2
|
|||
|
|
80042f6: 2b01 cmp r3, #1
|
|||
|
|
80042f8: d118 bne.n 800432c <HAL_FLASH_Unlock+0x44>
|
|||
|
|
__ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory");
|
|||
|
|
80042fa: f3ef 8310 mrs r3, PRIMASK
|
|||
|
|
80042fe: 60fb str r3, [r7, #12]
|
|||
|
|
return(result);
|
|||
|
|
8004300: 68fb ldr r3, [r7, #12]
|
|||
|
|
{
|
|||
|
|
/* Disable interrupts to avoid any interruption during unlock sequence */
|
|||
|
|
primask_bit = __get_PRIMASK();
|
|||
|
|
8004302: 617b str r3, [r7, #20]
|
|||
|
|
__ASM volatile ("cpsid i" : : : "memory");
|
|||
|
|
8004304: b672 cpsid i
|
|||
|
|
__disable_irq();
|
|||
|
|
|
|||
|
|
WRITE_REG(FLASH->PEKEYR, FLASH_PEKEY1);
|
|||
|
|
8004306: 4b1b ldr r3, [pc, #108] ; (8004374 <HAL_FLASH_Unlock+0x8c>)
|
|||
|
|
8004308: 4a1b ldr r2, [pc, #108] ; (8004378 <HAL_FLASH_Unlock+0x90>)
|
|||
|
|
800430a: 60da str r2, [r3, #12]
|
|||
|
|
WRITE_REG(FLASH->PEKEYR, FLASH_PEKEY2);
|
|||
|
|
800430c: 4b19 ldr r3, [pc, #100] ; (8004374 <HAL_FLASH_Unlock+0x8c>)
|
|||
|
|
800430e: 4a1b ldr r2, [pc, #108] ; (800437c <HAL_FLASH_Unlock+0x94>)
|
|||
|
|
8004310: 60da str r2, [r3, #12]
|
|||
|
|
8004312: 697b ldr r3, [r7, #20]
|
|||
|
|
8004314: 613b str r3, [r7, #16]
|
|||
|
|
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
|
|||
|
|
8004316: 693b ldr r3, [r7, #16]
|
|||
|
|
8004318: f383 8810 msr PRIMASK, r3
|
|||
|
|
|
|||
|
|
/* Re-enable the interrupts: restore previous priority mask */
|
|||
|
|
__set_PRIMASK(primask_bit);
|
|||
|
|
|
|||
|
|
if(HAL_IS_BIT_SET(FLASH->PECR, FLASH_PECR_PELOCK))
|
|||
|
|
800431c: 4b15 ldr r3, [pc, #84] ; (8004374 <HAL_FLASH_Unlock+0x8c>)
|
|||
|
|
800431e: 685b ldr r3, [r3, #4]
|
|||
|
|
8004320: 2201 movs r2, #1
|
|||
|
|
8004322: 4013 ands r3, r2
|
|||
|
|
8004324: 2b01 cmp r3, #1
|
|||
|
|
8004326: d101 bne.n 800432c <HAL_FLASH_Unlock+0x44>
|
|||
|
|
{
|
|||
|
|
return HAL_ERROR;
|
|||
|
|
8004328: 2301 movs r3, #1
|
|||
|
|
800432a: e01f b.n 800436c <HAL_FLASH_Unlock+0x84>
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
if (HAL_IS_BIT_SET(FLASH->PECR, FLASH_PECR_PRGLOCK))
|
|||
|
|
800432c: 4b11 ldr r3, [pc, #68] ; (8004374 <HAL_FLASH_Unlock+0x8c>)
|
|||
|
|
800432e: 685b ldr r3, [r3, #4]
|
|||
|
|
8004330: 2202 movs r2, #2
|
|||
|
|
8004332: 4013 ands r3, r2
|
|||
|
|
8004334: 2b02 cmp r3, #2
|
|||
|
|
8004336: d118 bne.n 800436a <HAL_FLASH_Unlock+0x82>
|
|||
|
|
__ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory");
|
|||
|
|
8004338: f3ef 8310 mrs r3, PRIMASK
|
|||
|
|
800433c: 607b str r3, [r7, #4]
|
|||
|
|
return(result);
|
|||
|
|
800433e: 687b ldr r3, [r7, #4]
|
|||
|
|
{
|
|||
|
|
/* Disable interrupts to avoid any interruption during unlock sequence */
|
|||
|
|
primask_bit = __get_PRIMASK();
|
|||
|
|
8004340: 617b str r3, [r7, #20]
|
|||
|
|
__ASM volatile ("cpsid i" : : : "memory");
|
|||
|
|
8004342: b672 cpsid i
|
|||
|
|
__disable_irq();
|
|||
|
|
|
|||
|
|
/* Unlocking the program memory access */
|
|||
|
|
WRITE_REG(FLASH->PRGKEYR, FLASH_PRGKEY1);
|
|||
|
|
8004344: 4b0b ldr r3, [pc, #44] ; (8004374 <HAL_FLASH_Unlock+0x8c>)
|
|||
|
|
8004346: 4a0e ldr r2, [pc, #56] ; (8004380 <HAL_FLASH_Unlock+0x98>)
|
|||
|
|
8004348: 611a str r2, [r3, #16]
|
|||
|
|
WRITE_REG(FLASH->PRGKEYR, FLASH_PRGKEY2);
|
|||
|
|
800434a: 4b0a ldr r3, [pc, #40] ; (8004374 <HAL_FLASH_Unlock+0x8c>)
|
|||
|
|
800434c: 4a0d ldr r2, [pc, #52] ; (8004384 <HAL_FLASH_Unlock+0x9c>)
|
|||
|
|
800434e: 611a str r2, [r3, #16]
|
|||
|
|
8004350: 697b ldr r3, [r7, #20]
|
|||
|
|
8004352: 60bb str r3, [r7, #8]
|
|||
|
|
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
|
|||
|
|
8004354: 68bb ldr r3, [r7, #8]
|
|||
|
|
8004356: f383 8810 msr PRIMASK, r3
|
|||
|
|
|
|||
|
|
/* Re-enable the interrupts: restore previous priority mask */
|
|||
|
|
__set_PRIMASK(primask_bit);
|
|||
|
|
|
|||
|
|
if (HAL_IS_BIT_SET(FLASH->PECR, FLASH_PECR_PRGLOCK))
|
|||
|
|
800435a: 4b06 ldr r3, [pc, #24] ; (8004374 <HAL_FLASH_Unlock+0x8c>)
|
|||
|
|
800435c: 685b ldr r3, [r3, #4]
|
|||
|
|
800435e: 2202 movs r2, #2
|
|||
|
|
8004360: 4013 ands r3, r2
|
|||
|
|
8004362: 2b02 cmp r3, #2
|
|||
|
|
8004364: d101 bne.n 800436a <HAL_FLASH_Unlock+0x82>
|
|||
|
|
{
|
|||
|
|
return HAL_ERROR;
|
|||
|
|
8004366: 2301 movs r3, #1
|
|||
|
|
8004368: e000 b.n 800436c <HAL_FLASH_Unlock+0x84>
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
return HAL_OK;
|
|||
|
|
800436a: 2300 movs r3, #0
|
|||
|
|
}
|
|||
|
|
800436c: 0018 movs r0, r3
|
|||
|
|
800436e: 46bd mov sp, r7
|
|||
|
|
8004370: b006 add sp, #24
|
|||
|
|
8004372: bd80 pop {r7, pc}
|
|||
|
|
8004374: 40022000 .word 0x40022000
|
|||
|
|
8004378: 89abcdef .word 0x89abcdef
|
|||
|
|
800437c: 02030405 .word 0x02030405
|
|||
|
|
8004380: 8c9daebf .word 0x8c9daebf
|
|||
|
|
8004384: 13141516 .word 0x13141516
|
|||
|
|
|
|||
|
|
08004388 <HAL_FLASH_Lock>:
|
|||
|
|
/**
|
|||
|
|
* @brief Locks the FLASH control register access
|
|||
|
|
* @retval HAL Status
|
|||
|
|
*/
|
|||
|
|
HAL_StatusTypeDef HAL_FLASH_Lock(void)
|
|||
|
|
{
|
|||
|
|
8004388: b580 push {r7, lr}
|
|||
|
|
800438a: af00 add r7, sp, #0
|
|||
|
|
/* Set the PRGLOCK Bit to lock the FLASH Registers access */
|
|||
|
|
SET_BIT(FLASH->PECR, FLASH_PECR_PRGLOCK);
|
|||
|
|
800438c: 4b07 ldr r3, [pc, #28] ; (80043ac <HAL_FLASH_Lock+0x24>)
|
|||
|
|
800438e: 4a07 ldr r2, [pc, #28] ; (80043ac <HAL_FLASH_Lock+0x24>)
|
|||
|
|
8004390: 6852 ldr r2, [r2, #4]
|
|||
|
|
8004392: 2102 movs r1, #2
|
|||
|
|
8004394: 430a orrs r2, r1
|
|||
|
|
8004396: 605a str r2, [r3, #4]
|
|||
|
|
|
|||
|
|
/* Set the PELOCK Bit to lock the PECR Register access */
|
|||
|
|
SET_BIT(FLASH->PECR, FLASH_PECR_PELOCK);
|
|||
|
|
8004398: 4b04 ldr r3, [pc, #16] ; (80043ac <HAL_FLASH_Lock+0x24>)
|
|||
|
|
800439a: 4a04 ldr r2, [pc, #16] ; (80043ac <HAL_FLASH_Lock+0x24>)
|
|||
|
|
800439c: 6852 ldr r2, [r2, #4]
|
|||
|
|
800439e: 2101 movs r1, #1
|
|||
|
|
80043a0: 430a orrs r2, r1
|
|||
|
|
80043a2: 605a str r2, [r3, #4]
|
|||
|
|
|
|||
|
|
return HAL_OK;
|
|||
|
|
80043a4: 2300 movs r3, #0
|
|||
|
|
}
|
|||
|
|
80043a6: 0018 movs r0, r3
|
|||
|
|
80043a8: 46bd mov sp, r7
|
|||
|
|
80043aa: bd80 pop {r7, pc}
|
|||
|
|
80043ac: 40022000 .word 0x40022000
|
|||
|
|
|
|||
|
|
080043b0 <FLASH_WaitForLastOperation>:
|
|||
|
|
* @brief Wait for a FLASH operation to complete.
|
|||
|
|
* @param Timeout maximum flash operation timeout
|
|||
|
|
* @retval HAL Status
|
|||
|
|
*/
|
|||
|
|
HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout)
|
|||
|
|
{
|
|||
|
|
80043b0: b580 push {r7, lr}
|
|||
|
|
80043b2: b084 sub sp, #16
|
|||
|
|
80043b4: af00 add r7, sp, #0
|
|||
|
|
80043b6: 6078 str r0, [r7, #4]
|
|||
|
|
/* Wait for the FLASH operation to complete by polling on BUSY flag to be reset.
|
|||
|
|
Even if the FLASH operation fails, the BUSY flag will be reset and an error
|
|||
|
|
flag will be set */
|
|||
|
|
|
|||
|
|
uint32_t tickstart = HAL_GetTick();
|
|||
|
|
80043b8: f7ff fdb8 bl 8003f2c <HAL_GetTick>
|
|||
|
|
80043bc: 0003 movs r3, r0
|
|||
|
|
80043be: 60fb str r3, [r7, #12]
|
|||
|
|
|
|||
|
|
while(__HAL_FLASH_GET_FLAG(FLASH_FLAG_BSY))
|
|||
|
|
80043c0: e00f b.n 80043e2 <FLASH_WaitForLastOperation+0x32>
|
|||
|
|
{
|
|||
|
|
if (Timeout != HAL_MAX_DELAY)
|
|||
|
|
80043c2: 687b ldr r3, [r7, #4]
|
|||
|
|
80043c4: 3301 adds r3, #1
|
|||
|
|
80043c6: d00c beq.n 80043e2 <FLASH_WaitForLastOperation+0x32>
|
|||
|
|
{
|
|||
|
|
if((Timeout == 0U) || ((HAL_GetTick()-tickstart) > Timeout))
|
|||
|
|
80043c8: 687b ldr r3, [r7, #4]
|
|||
|
|
80043ca: 2b00 cmp r3, #0
|
|||
|
|
80043cc: d007 beq.n 80043de <FLASH_WaitForLastOperation+0x2e>
|
|||
|
|
80043ce: f7ff fdad bl 8003f2c <HAL_GetTick>
|
|||
|
|
80043d2: 0002 movs r2, r0
|
|||
|
|
80043d4: 68fb ldr r3, [r7, #12]
|
|||
|
|
80043d6: 1ad2 subs r2, r2, r3
|
|||
|
|
80043d8: 687b ldr r3, [r7, #4]
|
|||
|
|
80043da: 429a cmp r2, r3
|
|||
|
|
80043dc: d901 bls.n 80043e2 <FLASH_WaitForLastOperation+0x32>
|
|||
|
|
{
|
|||
|
|
return HAL_TIMEOUT;
|
|||
|
|
80043de: 2303 movs r3, #3
|
|||
|
|
80043e0: e052 b.n 8004488 <FLASH_WaitForLastOperation+0xd8>
|
|||
|
|
while(__HAL_FLASH_GET_FLAG(FLASH_FLAG_BSY))
|
|||
|
|
80043e2: 4b2b ldr r3, [pc, #172] ; (8004490 <FLASH_WaitForLastOperation+0xe0>)
|
|||
|
|
80043e4: 699b ldr r3, [r3, #24]
|
|||
|
|
80043e6: 2201 movs r2, #1
|
|||
|
|
80043e8: 4013 ands r3, r2
|
|||
|
|
80043ea: 2b01 cmp r3, #1
|
|||
|
|
80043ec: d0e9 beq.n 80043c2 <FLASH_WaitForLastOperation+0x12>
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
/* Check FLASH End of Operation flag */
|
|||
|
|
if (__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP))
|
|||
|
|
80043ee: 4b28 ldr r3, [pc, #160] ; (8004490 <FLASH_WaitForLastOperation+0xe0>)
|
|||
|
|
80043f0: 699b ldr r3, [r3, #24]
|
|||
|
|
80043f2: 2202 movs r2, #2
|
|||
|
|
80043f4: 4013 ands r3, r2
|
|||
|
|
80043f6: 2b02 cmp r3, #2
|
|||
|
|
80043f8: d102 bne.n 8004400 <FLASH_WaitForLastOperation+0x50>
|
|||
|
|
{
|
|||
|
|
/* Clear FLASH End of Operation pending bit */
|
|||
|
|
__HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP);
|
|||
|
|
80043fa: 4b25 ldr r3, [pc, #148] ; (8004490 <FLASH_WaitForLastOperation+0xe0>)
|
|||
|
|
80043fc: 2202 movs r2, #2
|
|||
|
|
80043fe: 619a str r2, [r3, #24]
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
if( __HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR) ||
|
|||
|
|
8004400: 4b23 ldr r3, [pc, #140] ; (8004490 <FLASH_WaitForLastOperation+0xe0>)
|
|||
|
|
8004402: 699a ldr r2, [r3, #24]
|
|||
|
|
8004404: 2380 movs r3, #128 ; 0x80
|
|||
|
|
8004406: 005b lsls r3, r3, #1
|
|||
|
|
8004408: 401a ands r2, r3
|
|||
|
|
800440a: 2380 movs r3, #128 ; 0x80
|
|||
|
|
800440c: 005b lsls r3, r3, #1
|
|||
|
|
800440e: 429a cmp r2, r3
|
|||
|
|
8004410: d035 beq.n 800447e <FLASH_WaitForLastOperation+0xce>
|
|||
|
|
__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGAERR) ||
|
|||
|
|
8004412: 4b1f ldr r3, [pc, #124] ; (8004490 <FLASH_WaitForLastOperation+0xe0>)
|
|||
|
|
8004414: 699a ldr r2, [r3, #24]
|
|||
|
|
8004416: 2380 movs r3, #128 ; 0x80
|
|||
|
|
8004418: 009b lsls r3, r3, #2
|
|||
|
|
800441a: 401a ands r2, r3
|
|||
|
|
if( __HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR) ||
|
|||
|
|
800441c: 2380 movs r3, #128 ; 0x80
|
|||
|
|
800441e: 009b lsls r3, r3, #2
|
|||
|
|
8004420: 429a cmp r2, r3
|
|||
|
|
8004422: d02c beq.n 800447e <FLASH_WaitForLastOperation+0xce>
|
|||
|
|
__HAL_FLASH_GET_FLAG(FLASH_FLAG_SIZERR) ||
|
|||
|
|
8004424: 4b1a ldr r3, [pc, #104] ; (8004490 <FLASH_WaitForLastOperation+0xe0>)
|
|||
|
|
8004426: 699a ldr r2, [r3, #24]
|
|||
|
|
8004428: 2380 movs r3, #128 ; 0x80
|
|||
|
|
800442a: 00db lsls r3, r3, #3
|
|||
|
|
800442c: 401a ands r2, r3
|
|||
|
|
__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGAERR) ||
|
|||
|
|
800442e: 2380 movs r3, #128 ; 0x80
|
|||
|
|
8004430: 00db lsls r3, r3, #3
|
|||
|
|
8004432: 429a cmp r2, r3
|
|||
|
|
8004434: d023 beq.n 800447e <FLASH_WaitForLastOperation+0xce>
|
|||
|
|
__HAL_FLASH_GET_FLAG(FLASH_FLAG_OPTVERR) ||
|
|||
|
|
8004436: 4b16 ldr r3, [pc, #88] ; (8004490 <FLASH_WaitForLastOperation+0xe0>)
|
|||
|
|
8004438: 699a ldr r2, [r3, #24]
|
|||
|
|
800443a: 2380 movs r3, #128 ; 0x80
|
|||
|
|
800443c: 011b lsls r3, r3, #4
|
|||
|
|
800443e: 401a ands r2, r3
|
|||
|
|
__HAL_FLASH_GET_FLAG(FLASH_FLAG_SIZERR) ||
|
|||
|
|
8004440: 2380 movs r3, #128 ; 0x80
|
|||
|
|
8004442: 011b lsls r3, r3, #4
|
|||
|
|
8004444: 429a cmp r2, r3
|
|||
|
|
8004446: d01a beq.n 800447e <FLASH_WaitForLastOperation+0xce>
|
|||
|
|
__HAL_FLASH_GET_FLAG(FLASH_FLAG_RDERR) ||
|
|||
|
|
8004448: 4b11 ldr r3, [pc, #68] ; (8004490 <FLASH_WaitForLastOperation+0xe0>)
|
|||
|
|
800444a: 699a ldr r2, [r3, #24]
|
|||
|
|
800444c: 2380 movs r3, #128 ; 0x80
|
|||
|
|
800444e: 019b lsls r3, r3, #6
|
|||
|
|
8004450: 401a ands r2, r3
|
|||
|
|
__HAL_FLASH_GET_FLAG(FLASH_FLAG_OPTVERR) ||
|
|||
|
|
8004452: 2380 movs r3, #128 ; 0x80
|
|||
|
|
8004454: 019b lsls r3, r3, #6
|
|||
|
|
8004456: 429a cmp r2, r3
|
|||
|
|
8004458: d011 beq.n 800447e <FLASH_WaitForLastOperation+0xce>
|
|||
|
|
__HAL_FLASH_GET_FLAG(FLASH_FLAG_FWWERR) ||
|
|||
|
|
800445a: 4b0d ldr r3, [pc, #52] ; (8004490 <FLASH_WaitForLastOperation+0xe0>)
|
|||
|
|
800445c: 699a ldr r2, [r3, #24]
|
|||
|
|
800445e: 2380 movs r3, #128 ; 0x80
|
|||
|
|
8004460: 029b lsls r3, r3, #10
|
|||
|
|
8004462: 401a ands r2, r3
|
|||
|
|
__HAL_FLASH_GET_FLAG(FLASH_FLAG_RDERR) ||
|
|||
|
|
8004464: 2380 movs r3, #128 ; 0x80
|
|||
|
|
8004466: 029b lsls r3, r3, #10
|
|||
|
|
8004468: 429a cmp r2, r3
|
|||
|
|
800446a: d008 beq.n 800447e <FLASH_WaitForLastOperation+0xce>
|
|||
|
|
__HAL_FLASH_GET_FLAG(FLASH_FLAG_NOTZEROERR) )
|
|||
|
|
800446c: 4b08 ldr r3, [pc, #32] ; (8004490 <FLASH_WaitForLastOperation+0xe0>)
|
|||
|
|
800446e: 699a ldr r2, [r3, #24]
|
|||
|
|
8004470: 2380 movs r3, #128 ; 0x80
|
|||
|
|
8004472: 025b lsls r3, r3, #9
|
|||
|
|
8004474: 401a ands r2, r3
|
|||
|
|
__HAL_FLASH_GET_FLAG(FLASH_FLAG_FWWERR) ||
|
|||
|
|
8004476: 2380 movs r3, #128 ; 0x80
|
|||
|
|
8004478: 025b lsls r3, r3, #9
|
|||
|
|
800447a: 429a cmp r2, r3
|
|||
|
|
800447c: d103 bne.n 8004486 <FLASH_WaitForLastOperation+0xd6>
|
|||
|
|
* cut of the STM32L031xx device or the first cut of the STM32L041xx
|
|||
|
|
* device, this error should be ignored. The revId of the device
|
|||
|
|
* can be retrieved via the HAL_GetREVID() function.
|
|||
|
|
*
|
|||
|
|
*/
|
|||
|
|
FLASH_SetErrorCode();
|
|||
|
|
800447e: f000 f809 bl 8004494 <FLASH_SetErrorCode>
|
|||
|
|
return HAL_ERROR;
|
|||
|
|
8004482: 2301 movs r3, #1
|
|||
|
|
8004484: e000 b.n 8004488 <FLASH_WaitForLastOperation+0xd8>
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
/* There is no error flag set */
|
|||
|
|
return HAL_OK;
|
|||
|
|
8004486: 2300 movs r3, #0
|
|||
|
|
}
|
|||
|
|
8004488: 0018 movs r0, r3
|
|||
|
|
800448a: 46bd mov sp, r7
|
|||
|
|
800448c: b004 add sp, #16
|
|||
|
|
800448e: bd80 pop {r7, pc}
|
|||
|
|
8004490: 40022000 .word 0x40022000
|
|||
|
|
|
|||
|
|
08004494 <FLASH_SetErrorCode>:
|
|||
|
|
/**
|
|||
|
|
* @brief Set the specific FLASH error flag.
|
|||
|
|
* @retval None
|
|||
|
|
*/
|
|||
|
|
static void FLASH_SetErrorCode(void)
|
|||
|
|
{
|
|||
|
|
8004494: b580 push {r7, lr}
|
|||
|
|
8004496: b082 sub sp, #8
|
|||
|
|
8004498: af00 add r7, sp, #0
|
|||
|
|
uint32_t flags = 0;
|
|||
|
|
800449a: 2300 movs r3, #0
|
|||
|
|
800449c: 607b str r3, [r7, #4]
|
|||
|
|
|
|||
|
|
if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR))
|
|||
|
|
800449e: 4b49 ldr r3, [pc, #292] ; (80045c4 <FLASH_SetErrorCode+0x130>)
|
|||
|
|
80044a0: 699a ldr r2, [r3, #24]
|
|||
|
|
80044a2: 2380 movs r3, #128 ; 0x80
|
|||
|
|
80044a4: 005b lsls r3, r3, #1
|
|||
|
|
80044a6: 401a ands r2, r3
|
|||
|
|
80044a8: 2380 movs r3, #128 ; 0x80
|
|||
|
|
80044aa: 005b lsls r3, r3, #1
|
|||
|
|
80044ac: 429a cmp r2, r3
|
|||
|
|
80044ae: d10a bne.n 80044c6 <FLASH_SetErrorCode+0x32>
|
|||
|
|
{
|
|||
|
|
pFlash.ErrorCode |= HAL_FLASH_ERROR_WRP;
|
|||
|
|
80044b0: 4b45 ldr r3, [pc, #276] ; (80045c8 <FLASH_SetErrorCode+0x134>)
|
|||
|
|
80044b2: 695b ldr r3, [r3, #20]
|
|||
|
|
80044b4: 2202 movs r2, #2
|
|||
|
|
80044b6: 431a orrs r2, r3
|
|||
|
|
80044b8: 4b43 ldr r3, [pc, #268] ; (80045c8 <FLASH_SetErrorCode+0x134>)
|
|||
|
|
80044ba: 615a str r2, [r3, #20]
|
|||
|
|
flags |= FLASH_FLAG_WRPERR;
|
|||
|
|
80044bc: 687b ldr r3, [r7, #4]
|
|||
|
|
80044be: 2280 movs r2, #128 ; 0x80
|
|||
|
|
80044c0: 0052 lsls r2, r2, #1
|
|||
|
|
80044c2: 4313 orrs r3, r2
|
|||
|
|
80044c4: 607b str r3, [r7, #4]
|
|||
|
|
}
|
|||
|
|
if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGAERR))
|
|||
|
|
80044c6: 4b3f ldr r3, [pc, #252] ; (80045c4 <FLASH_SetErrorCode+0x130>)
|
|||
|
|
80044c8: 699a ldr r2, [r3, #24]
|
|||
|
|
80044ca: 2380 movs r3, #128 ; 0x80
|
|||
|
|
80044cc: 009b lsls r3, r3, #2
|
|||
|
|
80044ce: 401a ands r2, r3
|
|||
|
|
80044d0: 2380 movs r3, #128 ; 0x80
|
|||
|
|
80044d2: 009b lsls r3, r3, #2
|
|||
|
|
80044d4: 429a cmp r2, r3
|
|||
|
|
80044d6: d10a bne.n 80044ee <FLASH_SetErrorCode+0x5a>
|
|||
|
|
{
|
|||
|
|
pFlash.ErrorCode |= HAL_FLASH_ERROR_PGA;
|
|||
|
|
80044d8: 4b3b ldr r3, [pc, #236] ; (80045c8 <FLASH_SetErrorCode+0x134>)
|
|||
|
|
80044da: 695b ldr r3, [r3, #20]
|
|||
|
|
80044dc: 2201 movs r2, #1
|
|||
|
|
80044de: 431a orrs r2, r3
|
|||
|
|
80044e0: 4b39 ldr r3, [pc, #228] ; (80045c8 <FLASH_SetErrorCode+0x134>)
|
|||
|
|
80044e2: 615a str r2, [r3, #20]
|
|||
|
|
flags |= FLASH_FLAG_PGAERR;
|
|||
|
|
80044e4: 687b ldr r3, [r7, #4]
|
|||
|
|
80044e6: 2280 movs r2, #128 ; 0x80
|
|||
|
|
80044e8: 0092 lsls r2, r2, #2
|
|||
|
|
80044ea: 4313 orrs r3, r2
|
|||
|
|
80044ec: 607b str r3, [r7, #4]
|
|||
|
|
}
|
|||
|
|
if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_SIZERR))
|
|||
|
|
80044ee: 4b35 ldr r3, [pc, #212] ; (80045c4 <FLASH_SetErrorCode+0x130>)
|
|||
|
|
80044f0: 699a ldr r2, [r3, #24]
|
|||
|
|
80044f2: 2380 movs r3, #128 ; 0x80
|
|||
|
|
80044f4: 00db lsls r3, r3, #3
|
|||
|
|
80044f6: 401a ands r2, r3
|
|||
|
|
80044f8: 2380 movs r3, #128 ; 0x80
|
|||
|
|
80044fa: 00db lsls r3, r3, #3
|
|||
|
|
80044fc: 429a cmp r2, r3
|
|||
|
|
80044fe: d10a bne.n 8004516 <FLASH_SetErrorCode+0x82>
|
|||
|
|
{
|
|||
|
|
pFlash.ErrorCode |= HAL_FLASH_ERROR_SIZE;
|
|||
|
|
8004500: 4b31 ldr r3, [pc, #196] ; (80045c8 <FLASH_SetErrorCode+0x134>)
|
|||
|
|
8004502: 695b ldr r3, [r3, #20]
|
|||
|
|
8004504: 2208 movs r2, #8
|
|||
|
|
8004506: 431a orrs r2, r3
|
|||
|
|
8004508: 4b2f ldr r3, [pc, #188] ; (80045c8 <FLASH_SetErrorCode+0x134>)
|
|||
|
|
800450a: 615a str r2, [r3, #20]
|
|||
|
|
flags |= FLASH_FLAG_SIZERR;
|
|||
|
|
800450c: 687b ldr r3, [r7, #4]
|
|||
|
|
800450e: 2280 movs r2, #128 ; 0x80
|
|||
|
|
8004510: 00d2 lsls r2, r2, #3
|
|||
|
|
8004512: 4313 orrs r3, r2
|
|||
|
|
8004514: 607b str r3, [r7, #4]
|
|||
|
|
}
|
|||
|
|
if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_OPTVERR))
|
|||
|
|
8004516: 4b2b ldr r3, [pc, #172] ; (80045c4 <FLASH_SetErrorCode+0x130>)
|
|||
|
|
8004518: 699a ldr r2, [r3, #24]
|
|||
|
|
800451a: 2380 movs r3, #128 ; 0x80
|
|||
|
|
800451c: 011b lsls r3, r3, #4
|
|||
|
|
800451e: 401a ands r2, r3
|
|||
|
|
8004520: 2380 movs r3, #128 ; 0x80
|
|||
|
|
8004522: 011b lsls r3, r3, #4
|
|||
|
|
8004524: 429a cmp r2, r3
|
|||
|
|
8004526: d10a bne.n 800453e <FLASH_SetErrorCode+0xaa>
|
|||
|
|
* cut of the STM32L031xx device or the first cut of the STM32L041xx
|
|||
|
|
* device, this error should be ignored. The revId of the device
|
|||
|
|
* can be retrieved via the HAL_GetREVID() function.
|
|||
|
|
*
|
|||
|
|
*/
|
|||
|
|
pFlash.ErrorCode |= HAL_FLASH_ERROR_OPTV;
|
|||
|
|
8004528: 4b27 ldr r3, [pc, #156] ; (80045c8 <FLASH_SetErrorCode+0x134>)
|
|||
|
|
800452a: 695b ldr r3, [r3, #20]
|
|||
|
|
800452c: 2204 movs r2, #4
|
|||
|
|
800452e: 431a orrs r2, r3
|
|||
|
|
8004530: 4b25 ldr r3, [pc, #148] ; (80045c8 <FLASH_SetErrorCode+0x134>)
|
|||
|
|
8004532: 615a str r2, [r3, #20]
|
|||
|
|
flags |= FLASH_FLAG_OPTVERR;
|
|||
|
|
8004534: 687b ldr r3, [r7, #4]
|
|||
|
|
8004536: 2280 movs r2, #128 ; 0x80
|
|||
|
|
8004538: 0112 lsls r2, r2, #4
|
|||
|
|
800453a: 4313 orrs r3, r2
|
|||
|
|
800453c: 607b str r3, [r7, #4]
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_RDERR))
|
|||
|
|
800453e: 4b21 ldr r3, [pc, #132] ; (80045c4 <FLASH_SetErrorCode+0x130>)
|
|||
|
|
8004540: 699a ldr r2, [r3, #24]
|
|||
|
|
8004542: 2380 movs r3, #128 ; 0x80
|
|||
|
|
8004544: 019b lsls r3, r3, #6
|
|||
|
|
8004546: 401a ands r2, r3
|
|||
|
|
8004548: 2380 movs r3, #128 ; 0x80
|
|||
|
|
800454a: 019b lsls r3, r3, #6
|
|||
|
|
800454c: 429a cmp r2, r3
|
|||
|
|
800454e: d10a bne.n 8004566 <FLASH_SetErrorCode+0xd2>
|
|||
|
|
{
|
|||
|
|
pFlash.ErrorCode |= HAL_FLASH_ERROR_RD;
|
|||
|
|
8004550: 4b1d ldr r3, [pc, #116] ; (80045c8 <FLASH_SetErrorCode+0x134>)
|
|||
|
|
8004552: 695b ldr r3, [r3, #20]
|
|||
|
|
8004554: 2210 movs r2, #16
|
|||
|
|
8004556: 431a orrs r2, r3
|
|||
|
|
8004558: 4b1b ldr r3, [pc, #108] ; (80045c8 <FLASH_SetErrorCode+0x134>)
|
|||
|
|
800455a: 615a str r2, [r3, #20]
|
|||
|
|
flags |= FLASH_FLAG_RDERR;
|
|||
|
|
800455c: 687b ldr r3, [r7, #4]
|
|||
|
|
800455e: 2280 movs r2, #128 ; 0x80
|
|||
|
|
8004560: 0192 lsls r2, r2, #6
|
|||
|
|
8004562: 4313 orrs r3, r2
|
|||
|
|
8004564: 607b str r3, [r7, #4]
|
|||
|
|
}
|
|||
|
|
if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_FWWERR))
|
|||
|
|
8004566: 4b17 ldr r3, [pc, #92] ; (80045c4 <FLASH_SetErrorCode+0x130>)
|
|||
|
|
8004568: 699a ldr r2, [r3, #24]
|
|||
|
|
800456a: 2380 movs r3, #128 ; 0x80
|
|||
|
|
800456c: 029b lsls r3, r3, #10
|
|||
|
|
800456e: 401a ands r2, r3
|
|||
|
|
8004570: 2380 movs r3, #128 ; 0x80
|
|||
|
|
8004572: 029b lsls r3, r3, #10
|
|||
|
|
8004574: 429a cmp r2, r3
|
|||
|
|
8004576: d109 bne.n 800458c <FLASH_SetErrorCode+0xf8>
|
|||
|
|
{
|
|||
|
|
pFlash.ErrorCode |= HAL_FLASH_ERROR_FWWERR;
|
|||
|
|
8004578: 4b13 ldr r3, [pc, #76] ; (80045c8 <FLASH_SetErrorCode+0x134>)
|
|||
|
|
800457a: 695b ldr r3, [r3, #20]
|
|||
|
|
800457c: 2220 movs r2, #32
|
|||
|
|
800457e: 431a orrs r2, r3
|
|||
|
|
8004580: 4b11 ldr r3, [pc, #68] ; (80045c8 <FLASH_SetErrorCode+0x134>)
|
|||
|
|
8004582: 615a str r2, [r3, #20]
|
|||
|
|
flags |= HAL_FLASH_ERROR_FWWERR;
|
|||
|
|
8004584: 687b ldr r3, [r7, #4]
|
|||
|
|
8004586: 2220 movs r2, #32
|
|||
|
|
8004588: 4313 orrs r3, r2
|
|||
|
|
800458a: 607b str r3, [r7, #4]
|
|||
|
|
}
|
|||
|
|
if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_NOTZEROERR))
|
|||
|
|
800458c: 4b0d ldr r3, [pc, #52] ; (80045c4 <FLASH_SetErrorCode+0x130>)
|
|||
|
|
800458e: 699a ldr r2, [r3, #24]
|
|||
|
|
8004590: 2380 movs r3, #128 ; 0x80
|
|||
|
|
8004592: 025b lsls r3, r3, #9
|
|||
|
|
8004594: 401a ands r2, r3
|
|||
|
|
8004596: 2380 movs r3, #128 ; 0x80
|
|||
|
|
8004598: 025b lsls r3, r3, #9
|
|||
|
|
800459a: 429a cmp r2, r3
|
|||
|
|
800459c: d10a bne.n 80045b4 <FLASH_SetErrorCode+0x120>
|
|||
|
|
{
|
|||
|
|
pFlash.ErrorCode |= HAL_FLASH_ERROR_NOTZERO;
|
|||
|
|
800459e: 4b0a ldr r3, [pc, #40] ; (80045c8 <FLASH_SetErrorCode+0x134>)
|
|||
|
|
80045a0: 695b ldr r3, [r3, #20]
|
|||
|
|
80045a2: 2240 movs r2, #64 ; 0x40
|
|||
|
|
80045a4: 431a orrs r2, r3
|
|||
|
|
80045a6: 4b08 ldr r3, [pc, #32] ; (80045c8 <FLASH_SetErrorCode+0x134>)
|
|||
|
|
80045a8: 615a str r2, [r3, #20]
|
|||
|
|
flags |= FLASH_FLAG_NOTZEROERR;
|
|||
|
|
80045aa: 687b ldr r3, [r7, #4]
|
|||
|
|
80045ac: 2280 movs r2, #128 ; 0x80
|
|||
|
|
80045ae: 0252 lsls r2, r2, #9
|
|||
|
|
80045b0: 4313 orrs r3, r2
|
|||
|
|
80045b2: 607b str r3, [r7, #4]
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
/* Clear FLASH error pending bits */
|
|||
|
|
__HAL_FLASH_CLEAR_FLAG(flags);
|
|||
|
|
80045b4: 4b03 ldr r3, [pc, #12] ; (80045c4 <FLASH_SetErrorCode+0x130>)
|
|||
|
|
80045b6: 687a ldr r2, [r7, #4]
|
|||
|
|
80045b8: 619a str r2, [r3, #24]
|
|||
|
|
}
|
|||
|
|
80045ba: 46c0 nop ; (mov r8, r8)
|
|||
|
|
80045bc: 46bd mov sp, r7
|
|||
|
|
80045be: b002 add sp, #8
|
|||
|
|
80045c0: bd80 pop {r7, pc}
|
|||
|
|
80045c2: 46c0 nop ; (mov r8, r8)
|
|||
|
|
80045c4: 40022000 .word 0x40022000
|
|||
|
|
80045c8: 20000390 .word 0x20000390
|
|||
|
|
|
|||
|
|
080045cc <FLASH_PageErase>:
|
|||
|
|
* @note A Page is erased in the Program memory only if the address to load
|
|||
|
|
* is the start address of a page (multiple of @ref FLASH_PAGE_SIZE bytes).
|
|||
|
|
* @retval None
|
|||
|
|
*/
|
|||
|
|
void FLASH_PageErase(uint32_t PageAddress)
|
|||
|
|
{
|
|||
|
|
80045cc: b580 push {r7, lr}
|
|||
|
|
80045ce: b082 sub sp, #8
|
|||
|
|
80045d0: af00 add r7, sp, #0
|
|||
|
|
80045d2: 6078 str r0, [r7, #4]
|
|||
|
|
/* Clean the error context */
|
|||
|
|
pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
|
|||
|
|
80045d4: 4b0c ldr r3, [pc, #48] ; (8004608 <FLASH_PageErase+0x3c>)
|
|||
|
|
80045d6: 2200 movs r2, #0
|
|||
|
|
80045d8: 615a str r2, [r3, #20]
|
|||
|
|
|
|||
|
|
/* Set the ERASE bit */
|
|||
|
|
SET_BIT(FLASH->PECR, FLASH_PECR_ERASE);
|
|||
|
|
80045da: 4b0c ldr r3, [pc, #48] ; (800460c <FLASH_PageErase+0x40>)
|
|||
|
|
80045dc: 4a0b ldr r2, [pc, #44] ; (800460c <FLASH_PageErase+0x40>)
|
|||
|
|
80045de: 6852 ldr r2, [r2, #4]
|
|||
|
|
80045e0: 2180 movs r1, #128 ; 0x80
|
|||
|
|
80045e2: 0089 lsls r1, r1, #2
|
|||
|
|
80045e4: 430a orrs r2, r1
|
|||
|
|
80045e6: 605a str r2, [r3, #4]
|
|||
|
|
|
|||
|
|
/* Set PROG bit */
|
|||
|
|
SET_BIT(FLASH->PECR, FLASH_PECR_PROG);
|
|||
|
|
80045e8: 4b08 ldr r3, [pc, #32] ; (800460c <FLASH_PageErase+0x40>)
|
|||
|
|
80045ea: 4a08 ldr r2, [pc, #32] ; (800460c <FLASH_PageErase+0x40>)
|
|||
|
|
80045ec: 6852 ldr r2, [r2, #4]
|
|||
|
|
80045ee: 2108 movs r1, #8
|
|||
|
|
80045f0: 430a orrs r2, r1
|
|||
|
|
80045f2: 605a str r2, [r3, #4]
|
|||
|
|
|
|||
|
|
/* Write 00000000h to the first word of the program page to erase */
|
|||
|
|
*(__IO uint32_t *)(uint32_t)(PageAddress & ~(FLASH_PAGE_SIZE - 1)) = 0x00000000;
|
|||
|
|
80045f4: 687b ldr r3, [r7, #4]
|
|||
|
|
80045f6: 227f movs r2, #127 ; 0x7f
|
|||
|
|
80045f8: 4393 bics r3, r2
|
|||
|
|
80045fa: 2200 movs r2, #0
|
|||
|
|
80045fc: 601a str r2, [r3, #0]
|
|||
|
|
}
|
|||
|
|
80045fe: 46c0 nop ; (mov r8, r8)
|
|||
|
|
8004600: 46bd mov sp, r7
|
|||
|
|
8004602: b002 add sp, #8
|
|||
|
|
8004604: bd80 pop {r7, pc}
|
|||
|
|
8004606: 46c0 nop ; (mov r8, r8)
|
|||
|
|
8004608: 20000390 .word 0x20000390
|
|||
|
|
800460c: 40022000 .word 0x40022000
|
|||
|
|
|
|||
|
|
08004610 <HAL_GPIO_Init>:
|
|||
|
|
* @param GPIO_Init pointer to a GPIO_InitTypeDef structure that contains
|
|||
|
|
* the configuration information for the specified GPIO peripheral.
|
|||
|
|
* @retval None
|
|||
|
|
*/
|
|||
|
|
void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init)
|
|||
|
|
{
|
|||
|
|
8004610: b580 push {r7, lr}
|
|||
|
|
8004612: b086 sub sp, #24
|
|||
|
|
8004614: af00 add r7, sp, #0
|
|||
|
|
8004616: 6078 str r0, [r7, #4]
|
|||
|
|
8004618: 6039 str r1, [r7, #0]
|
|||
|
|
uint32_t position = 0x00U;
|
|||
|
|
800461a: 2300 movs r3, #0
|
|||
|
|
800461c: 617b str r3, [r7, #20]
|
|||
|
|
uint32_t iocurrent = 0x00U;
|
|||
|
|
800461e: 2300 movs r3, #0
|
|||
|
|
8004620: 60fb str r3, [r7, #12]
|
|||
|
|
uint32_t temp = 0x00U;
|
|||
|
|
8004622: 2300 movs r3, #0
|
|||
|
|
8004624: 613b str r3, [r7, #16]
|
|||
|
|
assert_param(IS_GPIO_MODE(GPIO_Init->Mode));
|
|||
|
|
assert_param(IS_GPIO_PULL(GPIO_Init->Pull));
|
|||
|
|
assert_param(IS_GPIO_PIN_AVAILABLE(GPIOx, (GPIO_Init->Pin)));
|
|||
|
|
|
|||
|
|
/* Configure the port pins */
|
|||
|
|
while (((GPIO_Init->Pin) >> position) != 0)
|
|||
|
|
8004626: e155 b.n 80048d4 <HAL_GPIO_Init+0x2c4>
|
|||
|
|
{
|
|||
|
|
/* Get the IO position */
|
|||
|
|
iocurrent = (GPIO_Init->Pin) & (1U << position);
|
|||
|
|
8004628: 683b ldr r3, [r7, #0]
|
|||
|
|
800462a: 681b ldr r3, [r3, #0]
|
|||
|
|
800462c: 2101 movs r1, #1
|
|||
|
|
800462e: 697a ldr r2, [r7, #20]
|
|||
|
|
8004630: 4091 lsls r1, r2
|
|||
|
|
8004632: 000a movs r2, r1
|
|||
|
|
8004634: 4013 ands r3, r2
|
|||
|
|
8004636: 60fb str r3, [r7, #12]
|
|||
|
|
|
|||
|
|
if (iocurrent)
|
|||
|
|
8004638: 68fb ldr r3, [r7, #12]
|
|||
|
|
800463a: 2b00 cmp r3, #0
|
|||
|
|
800463c: d100 bne.n 8004640 <HAL_GPIO_Init+0x30>
|
|||
|
|
800463e: e146 b.n 80048ce <HAL_GPIO_Init+0x2be>
|
|||
|
|
{
|
|||
|
|
/*--------------------- GPIO Mode Configuration ------------------------*/
|
|||
|
|
/* In case of Output or Alternate function mode selection */
|
|||
|
|
if ((GPIO_Init->Mode == GPIO_MODE_OUTPUT_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_PP) ||
|
|||
|
|
8004640: 683b ldr r3, [r7, #0]
|
|||
|
|
8004642: 685b ldr r3, [r3, #4]
|
|||
|
|
8004644: 2b01 cmp r3, #1
|
|||
|
|
8004646: d00b beq.n 8004660 <HAL_GPIO_Init+0x50>
|
|||
|
|
8004648: 683b ldr r3, [r7, #0]
|
|||
|
|
800464a: 685b ldr r3, [r3, #4]
|
|||
|
|
800464c: 2b02 cmp r3, #2
|
|||
|
|
800464e: d007 beq.n 8004660 <HAL_GPIO_Init+0x50>
|
|||
|
|
(GPIO_Init->Mode == GPIO_MODE_OUTPUT_OD) || (GPIO_Init->Mode == GPIO_MODE_AF_OD))
|
|||
|
|
8004650: 683b ldr r3, [r7, #0]
|
|||
|
|
8004652: 685b ldr r3, [r3, #4]
|
|||
|
|
if ((GPIO_Init->Mode == GPIO_MODE_OUTPUT_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_PP) ||
|
|||
|
|
8004654: 2b11 cmp r3, #17
|
|||
|
|
8004656: d003 beq.n 8004660 <HAL_GPIO_Init+0x50>
|
|||
|
|
(GPIO_Init->Mode == GPIO_MODE_OUTPUT_OD) || (GPIO_Init->Mode == GPIO_MODE_AF_OD))
|
|||
|
|
8004658: 683b ldr r3, [r7, #0]
|
|||
|
|
800465a: 685b ldr r3, [r3, #4]
|
|||
|
|
800465c: 2b12 cmp r3, #18
|
|||
|
|
800465e: d130 bne.n 80046c2 <HAL_GPIO_Init+0xb2>
|
|||
|
|
{
|
|||
|
|
/* Check the Speed parameter */
|
|||
|
|
assert_param(IS_GPIO_SPEED(GPIO_Init->Speed));
|
|||
|
|
/* Configure the IO Speed */
|
|||
|
|
temp = GPIOx->OSPEEDR;
|
|||
|
|
8004660: 687b ldr r3, [r7, #4]
|
|||
|
|
8004662: 689b ldr r3, [r3, #8]
|
|||
|
|
8004664: 613b str r3, [r7, #16]
|
|||
|
|
temp &= ~(GPIO_OSPEEDER_OSPEED0 << (position * 2U));
|
|||
|
|
8004666: 697b ldr r3, [r7, #20]
|
|||
|
|
8004668: 005b lsls r3, r3, #1
|
|||
|
|
800466a: 2203 movs r2, #3
|
|||
|
|
800466c: 409a lsls r2, r3
|
|||
|
|
800466e: 0013 movs r3, r2
|
|||
|
|
8004670: 43da mvns r2, r3
|
|||
|
|
8004672: 693b ldr r3, [r7, #16]
|
|||
|
|
8004674: 4013 ands r3, r2
|
|||
|
|
8004676: 613b str r3, [r7, #16]
|
|||
|
|
temp |= (GPIO_Init->Speed << (position * 2U));
|
|||
|
|
8004678: 683b ldr r3, [r7, #0]
|
|||
|
|
800467a: 68da ldr r2, [r3, #12]
|
|||
|
|
800467c: 697b ldr r3, [r7, #20]
|
|||
|
|
800467e: 005b lsls r3, r3, #1
|
|||
|
|
8004680: 409a lsls r2, r3
|
|||
|
|
8004682: 0013 movs r3, r2
|
|||
|
|
8004684: 693a ldr r2, [r7, #16]
|
|||
|
|
8004686: 4313 orrs r3, r2
|
|||
|
|
8004688: 613b str r3, [r7, #16]
|
|||
|
|
GPIOx->OSPEEDR = temp;
|
|||
|
|
800468a: 687b ldr r3, [r7, #4]
|
|||
|
|
800468c: 693a ldr r2, [r7, #16]
|
|||
|
|
800468e: 609a str r2, [r3, #8]
|
|||
|
|
|
|||
|
|
/* Configure the IO Output Type */
|
|||
|
|
temp = GPIOx->OTYPER;
|
|||
|
|
8004690: 687b ldr r3, [r7, #4]
|
|||
|
|
8004692: 685b ldr r3, [r3, #4]
|
|||
|
|
8004694: 613b str r3, [r7, #16]
|
|||
|
|
temp &= ~(GPIO_OTYPER_OT_0 << position) ;
|
|||
|
|
8004696: 2201 movs r2, #1
|
|||
|
|
8004698: 697b ldr r3, [r7, #20]
|
|||
|
|
800469a: 409a lsls r2, r3
|
|||
|
|
800469c: 0013 movs r3, r2
|
|||
|
|
800469e: 43da mvns r2, r3
|
|||
|
|
80046a0: 693b ldr r3, [r7, #16]
|
|||
|
|
80046a2: 4013 ands r3, r2
|
|||
|
|
80046a4: 613b str r3, [r7, #16]
|
|||
|
|
temp |= (((GPIO_Init->Mode & GPIO_OUTPUT_TYPE) >> 4U) << position);
|
|||
|
|
80046a6: 683b ldr r3, [r7, #0]
|
|||
|
|
80046a8: 685b ldr r3, [r3, #4]
|
|||
|
|
80046aa: 091b lsrs r3, r3, #4
|
|||
|
|
80046ac: 2201 movs r2, #1
|
|||
|
|
80046ae: 401a ands r2, r3
|
|||
|
|
80046b0: 697b ldr r3, [r7, #20]
|
|||
|
|
80046b2: 409a lsls r2, r3
|
|||
|
|
80046b4: 0013 movs r3, r2
|
|||
|
|
80046b6: 693a ldr r2, [r7, #16]
|
|||
|
|
80046b8: 4313 orrs r3, r2
|
|||
|
|
80046ba: 613b str r3, [r7, #16]
|
|||
|
|
GPIOx->OTYPER = temp;
|
|||
|
|
80046bc: 687b ldr r3, [r7, #4]
|
|||
|
|
80046be: 693a ldr r2, [r7, #16]
|
|||
|
|
80046c0: 605a str r2, [r3, #4]
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
/* Activate the Pull-up or Pull down resistor for the current IO */
|
|||
|
|
temp = GPIOx->PUPDR;
|
|||
|
|
80046c2: 687b ldr r3, [r7, #4]
|
|||
|
|
80046c4: 68db ldr r3, [r3, #12]
|
|||
|
|
80046c6: 613b str r3, [r7, #16]
|
|||
|
|
temp &= ~(GPIO_PUPDR_PUPD0 << (position * 2U));
|
|||
|
|
80046c8: 697b ldr r3, [r7, #20]
|
|||
|
|
80046ca: 005b lsls r3, r3, #1
|
|||
|
|
80046cc: 2203 movs r2, #3
|
|||
|
|
80046ce: 409a lsls r2, r3
|
|||
|
|
80046d0: 0013 movs r3, r2
|
|||
|
|
80046d2: 43da mvns r2, r3
|
|||
|
|
80046d4: 693b ldr r3, [r7, #16]
|
|||
|
|
80046d6: 4013 ands r3, r2
|
|||
|
|
80046d8: 613b str r3, [r7, #16]
|
|||
|
|
temp |= ((GPIO_Init->Pull) << (position * 2U));
|
|||
|
|
80046da: 683b ldr r3, [r7, #0]
|
|||
|
|
80046dc: 689a ldr r2, [r3, #8]
|
|||
|
|
80046de: 697b ldr r3, [r7, #20]
|
|||
|
|
80046e0: 005b lsls r3, r3, #1
|
|||
|
|
80046e2: 409a lsls r2, r3
|
|||
|
|
80046e4: 0013 movs r3, r2
|
|||
|
|
80046e6: 693a ldr r2, [r7, #16]
|
|||
|
|
80046e8: 4313 orrs r3, r2
|
|||
|
|
80046ea: 613b str r3, [r7, #16]
|
|||
|
|
GPIOx->PUPDR = temp;
|
|||
|
|
80046ec: 687b ldr r3, [r7, #4]
|
|||
|
|
80046ee: 693a ldr r2, [r7, #16]
|
|||
|
|
80046f0: 60da str r2, [r3, #12]
|
|||
|
|
|
|||
|
|
/* In case of Alternate function mode selection */
|
|||
|
|
if ((GPIO_Init->Mode == GPIO_MODE_AF_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_OD))
|
|||
|
|
80046f2: 683b ldr r3, [r7, #0]
|
|||
|
|
80046f4: 685b ldr r3, [r3, #4]
|
|||
|
|
80046f6: 2b02 cmp r3, #2
|
|||
|
|
80046f8: d003 beq.n 8004702 <HAL_GPIO_Init+0xf2>
|
|||
|
|
80046fa: 683b ldr r3, [r7, #0]
|
|||
|
|
80046fc: 685b ldr r3, [r3, #4]
|
|||
|
|
80046fe: 2b12 cmp r3, #18
|
|||
|
|
8004700: d123 bne.n 800474a <HAL_GPIO_Init+0x13a>
|
|||
|
|
/* Check the Alternate function parameters */
|
|||
|
|
assert_param(IS_GPIO_AF_INSTANCE(GPIOx));
|
|||
|
|
assert_param(IS_GPIO_AF(GPIO_Init->Alternate));
|
|||
|
|
|
|||
|
|
/* Configure Alternate function mapped with the current IO */
|
|||
|
|
temp = GPIOx->AFR[position >> 3U];
|
|||
|
|
8004702: 697b ldr r3, [r7, #20]
|
|||
|
|
8004704: 08da lsrs r2, r3, #3
|
|||
|
|
8004706: 687b ldr r3, [r7, #4]
|
|||
|
|
8004708: 3208 adds r2, #8
|
|||
|
|
800470a: 0092 lsls r2, r2, #2
|
|||
|
|
800470c: 58d3 ldr r3, [r2, r3]
|
|||
|
|
800470e: 613b str r3, [r7, #16]
|
|||
|
|
temp &= ~(0xFUL << ((uint32_t)(position & 0x07UL) * 4U));
|
|||
|
|
8004710: 697b ldr r3, [r7, #20]
|
|||
|
|
8004712: 2207 movs r2, #7
|
|||
|
|
8004714: 4013 ands r3, r2
|
|||
|
|
8004716: 009b lsls r3, r3, #2
|
|||
|
|
8004718: 220f movs r2, #15
|
|||
|
|
800471a: 409a lsls r2, r3
|
|||
|
|
800471c: 0013 movs r3, r2
|
|||
|
|
800471e: 43da mvns r2, r3
|
|||
|
|
8004720: 693b ldr r3, [r7, #16]
|
|||
|
|
8004722: 4013 ands r3, r2
|
|||
|
|
8004724: 613b str r3, [r7, #16]
|
|||
|
|
temp |= ((uint32_t)(GPIO_Init->Alternate) << (((uint32_t)position & (uint32_t)0x07U) * 4U));
|
|||
|
|
8004726: 683b ldr r3, [r7, #0]
|
|||
|
|
8004728: 691a ldr r2, [r3, #16]
|
|||
|
|
800472a: 697b ldr r3, [r7, #20]
|
|||
|
|
800472c: 2107 movs r1, #7
|
|||
|
|
800472e: 400b ands r3, r1
|
|||
|
|
8004730: 009b lsls r3, r3, #2
|
|||
|
|
8004732: 409a lsls r2, r3
|
|||
|
|
8004734: 0013 movs r3, r2
|
|||
|
|
8004736: 693a ldr r2, [r7, #16]
|
|||
|
|
8004738: 4313 orrs r3, r2
|
|||
|
|
800473a: 613b str r3, [r7, #16]
|
|||
|
|
GPIOx->AFR[position >> 3U] = temp;
|
|||
|
|
800473c: 697b ldr r3, [r7, #20]
|
|||
|
|
800473e: 08da lsrs r2, r3, #3
|
|||
|
|
8004740: 687b ldr r3, [r7, #4]
|
|||
|
|
8004742: 3208 adds r2, #8
|
|||
|
|
8004744: 0092 lsls r2, r2, #2
|
|||
|
|
8004746: 6939 ldr r1, [r7, #16]
|
|||
|
|
8004748: 50d1 str r1, [r2, r3]
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
/* Configure IO Direction mode (Input, Output, Alternate or Analog) */
|
|||
|
|
temp = GPIOx->MODER;
|
|||
|
|
800474a: 687b ldr r3, [r7, #4]
|
|||
|
|
800474c: 681b ldr r3, [r3, #0]
|
|||
|
|
800474e: 613b str r3, [r7, #16]
|
|||
|
|
temp &= ~(GPIO_MODER_MODE0 << (position * 2U));
|
|||
|
|
8004750: 697b ldr r3, [r7, #20]
|
|||
|
|
8004752: 005b lsls r3, r3, #1
|
|||
|
|
8004754: 2203 movs r2, #3
|
|||
|
|
8004756: 409a lsls r2, r3
|
|||
|
|
8004758: 0013 movs r3, r2
|
|||
|
|
800475a: 43da mvns r2, r3
|
|||
|
|
800475c: 693b ldr r3, [r7, #16]
|
|||
|
|
800475e: 4013 ands r3, r2
|
|||
|
|
8004760: 613b str r3, [r7, #16]
|
|||
|
|
temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2U));
|
|||
|
|
8004762: 683b ldr r3, [r7, #0]
|
|||
|
|
8004764: 685b ldr r3, [r3, #4]
|
|||
|
|
8004766: 2203 movs r2, #3
|
|||
|
|
8004768: 401a ands r2, r3
|
|||
|
|
800476a: 697b ldr r3, [r7, #20]
|
|||
|
|
800476c: 005b lsls r3, r3, #1
|
|||
|
|
800476e: 409a lsls r2, r3
|
|||
|
|
8004770: 0013 movs r3, r2
|
|||
|
|
8004772: 693a ldr r2, [r7, #16]
|
|||
|
|
8004774: 4313 orrs r3, r2
|
|||
|
|
8004776: 613b str r3, [r7, #16]
|
|||
|
|
GPIOx->MODER = temp;
|
|||
|
|
8004778: 687b ldr r3, [r7, #4]
|
|||
|
|
800477a: 693a ldr r2, [r7, #16]
|
|||
|
|
800477c: 601a str r2, [r3, #0]
|
|||
|
|
|
|||
|
|
/*--------------------- EXTI Mode Configuration ------------------------*/
|
|||
|
|
/* Configure the External Interrupt or event for the current IO */
|
|||
|
|
if ((GPIO_Init->Mode & EXTI_MODE) == EXTI_MODE)
|
|||
|
|
800477e: 683b ldr r3, [r7, #0]
|
|||
|
|
8004780: 685a ldr r2, [r3, #4]
|
|||
|
|
8004782: 2380 movs r3, #128 ; 0x80
|
|||
|
|
8004784: 055b lsls r3, r3, #21
|
|||
|
|
8004786: 4013 ands r3, r2
|
|||
|
|
8004788: d100 bne.n 800478c <HAL_GPIO_Init+0x17c>
|
|||
|
|
800478a: e0a0 b.n 80048ce <HAL_GPIO_Init+0x2be>
|
|||
|
|
{
|
|||
|
|
/* Enable SYSCFG Clock */
|
|||
|
|
__HAL_RCC_SYSCFG_CLK_ENABLE();
|
|||
|
|
800478c: 4b57 ldr r3, [pc, #348] ; (80048ec <HAL_GPIO_Init+0x2dc>)
|
|||
|
|
800478e: 4a57 ldr r2, [pc, #348] ; (80048ec <HAL_GPIO_Init+0x2dc>)
|
|||
|
|
8004790: 6b52 ldr r2, [r2, #52] ; 0x34
|
|||
|
|
8004792: 2101 movs r1, #1
|
|||
|
|
8004794: 430a orrs r2, r1
|
|||
|
|
8004796: 635a str r2, [r3, #52] ; 0x34
|
|||
|
|
|
|||
|
|
temp = SYSCFG->EXTICR[position >> 2U];
|
|||
|
|
8004798: 4a55 ldr r2, [pc, #340] ; (80048f0 <HAL_GPIO_Init+0x2e0>)
|
|||
|
|
800479a: 697b ldr r3, [r7, #20]
|
|||
|
|
800479c: 089b lsrs r3, r3, #2
|
|||
|
|
800479e: 3302 adds r3, #2
|
|||
|
|
80047a0: 009b lsls r3, r3, #2
|
|||
|
|
80047a2: 589b ldr r3, [r3, r2]
|
|||
|
|
80047a4: 613b str r3, [r7, #16]
|
|||
|
|
CLEAR_BIT(temp, (0x0FUL) << (4U * (position & 0x03U)));
|
|||
|
|
80047a6: 697b ldr r3, [r7, #20]
|
|||
|
|
80047a8: 2203 movs r2, #3
|
|||
|
|
80047aa: 4013 ands r3, r2
|
|||
|
|
80047ac: 009b lsls r3, r3, #2
|
|||
|
|
80047ae: 220f movs r2, #15
|
|||
|
|
80047b0: 409a lsls r2, r3
|
|||
|
|
80047b2: 0013 movs r3, r2
|
|||
|
|
80047b4: 43da mvns r2, r3
|
|||
|
|
80047b6: 693b ldr r3, [r7, #16]
|
|||
|
|
80047b8: 4013 ands r3, r2
|
|||
|
|
80047ba: 613b str r3, [r7, #16]
|
|||
|
|
SET_BIT(temp, (GPIO_GET_INDEX(GPIOx)) << (4 * (position & 0x03U)));
|
|||
|
|
80047bc: 687a ldr r2, [r7, #4]
|
|||
|
|
80047be: 23a0 movs r3, #160 ; 0xa0
|
|||
|
|
80047c0: 05db lsls r3, r3, #23
|
|||
|
|
80047c2: 429a cmp r2, r3
|
|||
|
|
80047c4: d01f beq.n 8004806 <HAL_GPIO_Init+0x1f6>
|
|||
|
|
80047c6: 687b ldr r3, [r7, #4]
|
|||
|
|
80047c8: 4a4a ldr r2, [pc, #296] ; (80048f4 <HAL_GPIO_Init+0x2e4>)
|
|||
|
|
80047ca: 4293 cmp r3, r2
|
|||
|
|
80047cc: d019 beq.n 8004802 <HAL_GPIO_Init+0x1f2>
|
|||
|
|
80047ce: 687b ldr r3, [r7, #4]
|
|||
|
|
80047d0: 4a49 ldr r2, [pc, #292] ; (80048f8 <HAL_GPIO_Init+0x2e8>)
|
|||
|
|
80047d2: 4293 cmp r3, r2
|
|||
|
|
80047d4: d013 beq.n 80047fe <HAL_GPIO_Init+0x1ee>
|
|||
|
|
80047d6: 687b ldr r3, [r7, #4]
|
|||
|
|
80047d8: 4a48 ldr r2, [pc, #288] ; (80048fc <HAL_GPIO_Init+0x2ec>)
|
|||
|
|
80047da: 4293 cmp r3, r2
|
|||
|
|
80047dc: d00d beq.n 80047fa <HAL_GPIO_Init+0x1ea>
|
|||
|
|
80047de: 687b ldr r3, [r7, #4]
|
|||
|
|
80047e0: 4a47 ldr r2, [pc, #284] ; (8004900 <HAL_GPIO_Init+0x2f0>)
|
|||
|
|
80047e2: 4293 cmp r3, r2
|
|||
|
|
80047e4: d007 beq.n 80047f6 <HAL_GPIO_Init+0x1e6>
|
|||
|
|
80047e6: 687b ldr r3, [r7, #4]
|
|||
|
|
80047e8: 4a46 ldr r2, [pc, #280] ; (8004904 <HAL_GPIO_Init+0x2f4>)
|
|||
|
|
80047ea: 4293 cmp r3, r2
|
|||
|
|
80047ec: d101 bne.n 80047f2 <HAL_GPIO_Init+0x1e2>
|
|||
|
|
80047ee: 2305 movs r3, #5
|
|||
|
|
80047f0: e00a b.n 8004808 <HAL_GPIO_Init+0x1f8>
|
|||
|
|
80047f2: 2306 movs r3, #6
|
|||
|
|
80047f4: e008 b.n 8004808 <HAL_GPIO_Init+0x1f8>
|
|||
|
|
80047f6: 2304 movs r3, #4
|
|||
|
|
80047f8: e006 b.n 8004808 <HAL_GPIO_Init+0x1f8>
|
|||
|
|
80047fa: 2303 movs r3, #3
|
|||
|
|
80047fc: e004 b.n 8004808 <HAL_GPIO_Init+0x1f8>
|
|||
|
|
80047fe: 2302 movs r3, #2
|
|||
|
|
8004800: e002 b.n 8004808 <HAL_GPIO_Init+0x1f8>
|
|||
|
|
8004802: 2301 movs r3, #1
|
|||
|
|
8004804: e000 b.n 8004808 <HAL_GPIO_Init+0x1f8>
|
|||
|
|
8004806: 2300 movs r3, #0
|
|||
|
|
8004808: 697a ldr r2, [r7, #20]
|
|||
|
|
800480a: 2103 movs r1, #3
|
|||
|
|
800480c: 400a ands r2, r1
|
|||
|
|
800480e: 0092 lsls r2, r2, #2
|
|||
|
|
8004810: 4093 lsls r3, r2
|
|||
|
|
8004812: 693a ldr r2, [r7, #16]
|
|||
|
|
8004814: 4313 orrs r3, r2
|
|||
|
|
8004816: 613b str r3, [r7, #16]
|
|||
|
|
SYSCFG->EXTICR[position >> 2U] = temp;
|
|||
|
|
8004818: 4935 ldr r1, [pc, #212] ; (80048f0 <HAL_GPIO_Init+0x2e0>)
|
|||
|
|
800481a: 697b ldr r3, [r7, #20]
|
|||
|
|
800481c: 089b lsrs r3, r3, #2
|
|||
|
|
800481e: 3302 adds r3, #2
|
|||
|
|
8004820: 009b lsls r3, r3, #2
|
|||
|
|
8004822: 693a ldr r2, [r7, #16]
|
|||
|
|
8004824: 505a str r2, [r3, r1]
|
|||
|
|
|
|||
|
|
/* Clear EXTI line configuration */
|
|||
|
|
temp = EXTI->IMR;
|
|||
|
|
8004826: 4b38 ldr r3, [pc, #224] ; (8004908 <HAL_GPIO_Init+0x2f8>)
|
|||
|
|
8004828: 681b ldr r3, [r3, #0]
|
|||
|
|
800482a: 613b str r3, [r7, #16]
|
|||
|
|
temp &= ~((uint32_t)iocurrent);
|
|||
|
|
800482c: 68fb ldr r3, [r7, #12]
|
|||
|
|
800482e: 43da mvns r2, r3
|
|||
|
|
8004830: 693b ldr r3, [r7, #16]
|
|||
|
|
8004832: 4013 ands r3, r2
|
|||
|
|
8004834: 613b str r3, [r7, #16]
|
|||
|
|
if ((GPIO_Init->Mode & GPIO_MODE_IT) == GPIO_MODE_IT)
|
|||
|
|
8004836: 683b ldr r3, [r7, #0]
|
|||
|
|
8004838: 685a ldr r2, [r3, #4]
|
|||
|
|
800483a: 2380 movs r3, #128 ; 0x80
|
|||
|
|
800483c: 025b lsls r3, r3, #9
|
|||
|
|
800483e: 4013 ands r3, r2
|
|||
|
|
8004840: d003 beq.n 800484a <HAL_GPIO_Init+0x23a>
|
|||
|
|
{
|
|||
|
|
temp |= iocurrent;
|
|||
|
|
8004842: 693a ldr r2, [r7, #16]
|
|||
|
|
8004844: 68fb ldr r3, [r7, #12]
|
|||
|
|
8004846: 4313 orrs r3, r2
|
|||
|
|
8004848: 613b str r3, [r7, #16]
|
|||
|
|
}
|
|||
|
|
EXTI->IMR = temp;
|
|||
|
|
800484a: 4b2f ldr r3, [pc, #188] ; (8004908 <HAL_GPIO_Init+0x2f8>)
|
|||
|
|
800484c: 693a ldr r2, [r7, #16]
|
|||
|
|
800484e: 601a str r2, [r3, #0]
|
|||
|
|
|
|||
|
|
temp = EXTI->EMR;
|
|||
|
|
8004850: 4b2d ldr r3, [pc, #180] ; (8004908 <HAL_GPIO_Init+0x2f8>)
|
|||
|
|
8004852: 685b ldr r3, [r3, #4]
|
|||
|
|
8004854: 613b str r3, [r7, #16]
|
|||
|
|
temp &= ~((uint32_t)iocurrent);
|
|||
|
|
8004856: 68fb ldr r3, [r7, #12]
|
|||
|
|
8004858: 43da mvns r2, r3
|
|||
|
|
800485a: 693b ldr r3, [r7, #16]
|
|||
|
|
800485c: 4013 ands r3, r2
|
|||
|
|
800485e: 613b str r3, [r7, #16]
|
|||
|
|
if ((GPIO_Init->Mode & GPIO_MODE_EVT) == GPIO_MODE_EVT)
|
|||
|
|
8004860: 683b ldr r3, [r7, #0]
|
|||
|
|
8004862: 685a ldr r2, [r3, #4]
|
|||
|
|
8004864: 2380 movs r3, #128 ; 0x80
|
|||
|
|
8004866: 029b lsls r3, r3, #10
|
|||
|
|
8004868: 4013 ands r3, r2
|
|||
|
|
800486a: d003 beq.n 8004874 <HAL_GPIO_Init+0x264>
|
|||
|
|
{
|
|||
|
|
temp |= iocurrent;
|
|||
|
|
800486c: 693a ldr r2, [r7, #16]
|
|||
|
|
800486e: 68fb ldr r3, [r7, #12]
|
|||
|
|
8004870: 4313 orrs r3, r2
|
|||
|
|
8004872: 613b str r3, [r7, #16]
|
|||
|
|
}
|
|||
|
|
EXTI->EMR = temp;
|
|||
|
|
8004874: 4b24 ldr r3, [pc, #144] ; (8004908 <HAL_GPIO_Init+0x2f8>)
|
|||
|
|
8004876: 693a ldr r2, [r7, #16]
|
|||
|
|
8004878: 605a str r2, [r3, #4]
|
|||
|
|
|
|||
|
|
/* Clear Rising Falling edge configuration */
|
|||
|
|
temp = EXTI->RTSR;
|
|||
|
|
800487a: 4b23 ldr r3, [pc, #140] ; (8004908 <HAL_GPIO_Init+0x2f8>)
|
|||
|
|
800487c: 689b ldr r3, [r3, #8]
|
|||
|
|
800487e: 613b str r3, [r7, #16]
|
|||
|
|
temp &= ~((uint32_t)iocurrent);
|
|||
|
|
8004880: 68fb ldr r3, [r7, #12]
|
|||
|
|
8004882: 43da mvns r2, r3
|
|||
|
|
8004884: 693b ldr r3, [r7, #16]
|
|||
|
|
8004886: 4013 ands r3, r2
|
|||
|
|
8004888: 613b str r3, [r7, #16]
|
|||
|
|
if ((GPIO_Init->Mode & RISING_EDGE) == RISING_EDGE)
|
|||
|
|
800488a: 683b ldr r3, [r7, #0]
|
|||
|
|
800488c: 685a ldr r2, [r3, #4]
|
|||
|
|
800488e: 2380 movs r3, #128 ; 0x80
|
|||
|
|
8004890: 035b lsls r3, r3, #13
|
|||
|
|
8004892: 4013 ands r3, r2
|
|||
|
|
8004894: d003 beq.n 800489e <HAL_GPIO_Init+0x28e>
|
|||
|
|
{
|
|||
|
|
temp |= iocurrent;
|
|||
|
|
8004896: 693a ldr r2, [r7, #16]
|
|||
|
|
8004898: 68fb ldr r3, [r7, #12]
|
|||
|
|
800489a: 4313 orrs r3, r2
|
|||
|
|
800489c: 613b str r3, [r7, #16]
|
|||
|
|
}
|
|||
|
|
EXTI->RTSR = temp;
|
|||
|
|
800489e: 4b1a ldr r3, [pc, #104] ; (8004908 <HAL_GPIO_Init+0x2f8>)
|
|||
|
|
80048a0: 693a ldr r2, [r7, #16]
|
|||
|
|
80048a2: 609a str r2, [r3, #8]
|
|||
|
|
|
|||
|
|
temp = EXTI->FTSR;
|
|||
|
|
80048a4: 4b18 ldr r3, [pc, #96] ; (8004908 <HAL_GPIO_Init+0x2f8>)
|
|||
|
|
80048a6: 68db ldr r3, [r3, #12]
|
|||
|
|
80048a8: 613b str r3, [r7, #16]
|
|||
|
|
temp &= ~((uint32_t)iocurrent);
|
|||
|
|
80048aa: 68fb ldr r3, [r7, #12]
|
|||
|
|
80048ac: 43da mvns r2, r3
|
|||
|
|
80048ae: 693b ldr r3, [r7, #16]
|
|||
|
|
80048b0: 4013 ands r3, r2
|
|||
|
|
80048b2: 613b str r3, [r7, #16]
|
|||
|
|
if ((GPIO_Init->Mode & FALLING_EDGE) == FALLING_EDGE)
|
|||
|
|
80048b4: 683b ldr r3, [r7, #0]
|
|||
|
|
80048b6: 685a ldr r2, [r3, #4]
|
|||
|
|
80048b8: 2380 movs r3, #128 ; 0x80
|
|||
|
|
80048ba: 039b lsls r3, r3, #14
|
|||
|
|
80048bc: 4013 ands r3, r2
|
|||
|
|
80048be: d003 beq.n 80048c8 <HAL_GPIO_Init+0x2b8>
|
|||
|
|
{
|
|||
|
|
temp |= iocurrent;
|
|||
|
|
80048c0: 693a ldr r2, [r7, #16]
|
|||
|
|
80048c2: 68fb ldr r3, [r7, #12]
|
|||
|
|
80048c4: 4313 orrs r3, r2
|
|||
|
|
80048c6: 613b str r3, [r7, #16]
|
|||
|
|
}
|
|||
|
|
EXTI->FTSR = temp;
|
|||
|
|
80048c8: 4b0f ldr r3, [pc, #60] ; (8004908 <HAL_GPIO_Init+0x2f8>)
|
|||
|
|
80048ca: 693a ldr r2, [r7, #16]
|
|||
|
|
80048cc: 60da str r2, [r3, #12]
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
position++;
|
|||
|
|
80048ce: 697b ldr r3, [r7, #20]
|
|||
|
|
80048d0: 3301 adds r3, #1
|
|||
|
|
80048d2: 617b str r3, [r7, #20]
|
|||
|
|
while (((GPIO_Init->Pin) >> position) != 0)
|
|||
|
|
80048d4: 683b ldr r3, [r7, #0]
|
|||
|
|
80048d6: 681a ldr r2, [r3, #0]
|
|||
|
|
80048d8: 697b ldr r3, [r7, #20]
|
|||
|
|
80048da: 40da lsrs r2, r3
|
|||
|
|
80048dc: 1e13 subs r3, r2, #0
|
|||
|
|
80048de: d000 beq.n 80048e2 <HAL_GPIO_Init+0x2d2>
|
|||
|
|
80048e0: e6a2 b.n 8004628 <HAL_GPIO_Init+0x18>
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
80048e2: 46c0 nop ; (mov r8, r8)
|
|||
|
|
80048e4: 46bd mov sp, r7
|
|||
|
|
80048e6: b006 add sp, #24
|
|||
|
|
80048e8: bd80 pop {r7, pc}
|
|||
|
|
80048ea: 46c0 nop ; (mov r8, r8)
|
|||
|
|
80048ec: 40021000 .word 0x40021000
|
|||
|
|
80048f0: 40010000 .word 0x40010000
|
|||
|
|
80048f4: 50000400 .word 0x50000400
|
|||
|
|
80048f8: 50000800 .word 0x50000800
|
|||
|
|
80048fc: 50000c00 .word 0x50000c00
|
|||
|
|
8004900: 50001000 .word 0x50001000
|
|||
|
|
8004904: 50001c00 .word 0x50001c00
|
|||
|
|
8004908: 40010400 .word 0x40010400
|
|||
|
|
|
|||
|
|
0800490c <HAL_GPIO_DeInit>:
|
|||
|
|
* This parameter can be one of GPIO_PIN_x where x can be (0..15).
|
|||
|
|
* All port bits are not necessarily available on all GPIOs.
|
|||
|
|
* @retval None
|
|||
|
|
*/
|
|||
|
|
void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin)
|
|||
|
|
{
|
|||
|
|
800490c: b580 push {r7, lr}
|
|||
|
|
800490e: b086 sub sp, #24
|
|||
|
|
8004910: af00 add r7, sp, #0
|
|||
|
|
8004912: 6078 str r0, [r7, #4]
|
|||
|
|
8004914: 6039 str r1, [r7, #0]
|
|||
|
|
uint32_t position = 0x00U;
|
|||
|
|
8004916: 2300 movs r3, #0
|
|||
|
|
8004918: 617b str r3, [r7, #20]
|
|||
|
|
uint32_t iocurrent = 0x00U;
|
|||
|
|
800491a: 2300 movs r3, #0
|
|||
|
|
800491c: 613b str r3, [r7, #16]
|
|||
|
|
uint32_t tmp = 0x00U;
|
|||
|
|
800491e: 2300 movs r3, #0
|
|||
|
|
8004920: 60fb str r3, [r7, #12]
|
|||
|
|
|
|||
|
|
/* Check the parameters */
|
|||
|
|
assert_param(IS_GPIO_PIN_AVAILABLE(GPIOx, GPIO_Pin));
|
|||
|
|
|
|||
|
|
/* Configure the port pins */
|
|||
|
|
while ((GPIO_Pin >> position) != 0)
|
|||
|
|
8004922: e0be b.n 8004aa2 <HAL_GPIO_DeInit+0x196>
|
|||
|
|
{
|
|||
|
|
/* Get the IO position */
|
|||
|
|
iocurrent = (GPIO_Pin) & (1U << position);
|
|||
|
|
8004924: 2201 movs r2, #1
|
|||
|
|
8004926: 697b ldr r3, [r7, #20]
|
|||
|
|
8004928: 409a lsls r2, r3
|
|||
|
|
800492a: 0013 movs r3, r2
|
|||
|
|
800492c: 683a ldr r2, [r7, #0]
|
|||
|
|
800492e: 4013 ands r3, r2
|
|||
|
|
8004930: 613b str r3, [r7, #16]
|
|||
|
|
|
|||
|
|
if (iocurrent)
|
|||
|
|
8004932: 693b ldr r3, [r7, #16]
|
|||
|
|
8004934: 2b00 cmp r3, #0
|
|||
|
|
8004936: d100 bne.n 800493a <HAL_GPIO_DeInit+0x2e>
|
|||
|
|
8004938: e0b0 b.n 8004a9c <HAL_GPIO_DeInit+0x190>
|
|||
|
|
{
|
|||
|
|
/*------------------------- EXTI Mode Configuration --------------------*/
|
|||
|
|
/* Clear the External Interrupt or Event for the current IO */
|
|||
|
|
|
|||
|
|
tmp = SYSCFG->EXTICR[position >> 2U];
|
|||
|
|
800493a: 4a5f ldr r2, [pc, #380] ; (8004ab8 <HAL_GPIO_DeInit+0x1ac>)
|
|||
|
|
800493c: 697b ldr r3, [r7, #20]
|
|||
|
|
800493e: 089b lsrs r3, r3, #2
|
|||
|
|
8004940: 3302 adds r3, #2
|
|||
|
|
8004942: 009b lsls r3, r3, #2
|
|||
|
|
8004944: 589b ldr r3, [r3, r2]
|
|||
|
|
8004946: 60fb str r3, [r7, #12]
|
|||
|
|
tmp &= ((0x0FUL) << (4U * (position & 0x03U)));
|
|||
|
|
8004948: 697b ldr r3, [r7, #20]
|
|||
|
|
800494a: 2203 movs r2, #3
|
|||
|
|
800494c: 4013 ands r3, r2
|
|||
|
|
800494e: 009b lsls r3, r3, #2
|
|||
|
|
8004950: 220f movs r2, #15
|
|||
|
|
8004952: 409a lsls r2, r3
|
|||
|
|
8004954: 68fb ldr r3, [r7, #12]
|
|||
|
|
8004956: 4013 ands r3, r2
|
|||
|
|
8004958: 60fb str r3, [r7, #12]
|
|||
|
|
if (tmp == (GPIO_GET_INDEX(GPIOx) << (4U * (position & 0x03U))))
|
|||
|
|
800495a: 687a ldr r2, [r7, #4]
|
|||
|
|
800495c: 23a0 movs r3, #160 ; 0xa0
|
|||
|
|
800495e: 05db lsls r3, r3, #23
|
|||
|
|
8004960: 429a cmp r2, r3
|
|||
|
|
8004962: d01f beq.n 80049a4 <HAL_GPIO_DeInit+0x98>
|
|||
|
|
8004964: 687b ldr r3, [r7, #4]
|
|||
|
|
8004966: 4a55 ldr r2, [pc, #340] ; (8004abc <HAL_GPIO_DeInit+0x1b0>)
|
|||
|
|
8004968: 4293 cmp r3, r2
|
|||
|
|
800496a: d019 beq.n 80049a0 <HAL_GPIO_DeInit+0x94>
|
|||
|
|
800496c: 687b ldr r3, [r7, #4]
|
|||
|
|
800496e: 4a54 ldr r2, [pc, #336] ; (8004ac0 <HAL_GPIO_DeInit+0x1b4>)
|
|||
|
|
8004970: 4293 cmp r3, r2
|
|||
|
|
8004972: d013 beq.n 800499c <HAL_GPIO_DeInit+0x90>
|
|||
|
|
8004974: 687b ldr r3, [r7, #4]
|
|||
|
|
8004976: 4a53 ldr r2, [pc, #332] ; (8004ac4 <HAL_GPIO_DeInit+0x1b8>)
|
|||
|
|
8004978: 4293 cmp r3, r2
|
|||
|
|
800497a: d00d beq.n 8004998 <HAL_GPIO_DeInit+0x8c>
|
|||
|
|
800497c: 687b ldr r3, [r7, #4]
|
|||
|
|
800497e: 4a52 ldr r2, [pc, #328] ; (8004ac8 <HAL_GPIO_DeInit+0x1bc>)
|
|||
|
|
8004980: 4293 cmp r3, r2
|
|||
|
|
8004982: d007 beq.n 8004994 <HAL_GPIO_DeInit+0x88>
|
|||
|
|
8004984: 687b ldr r3, [r7, #4]
|
|||
|
|
8004986: 4a51 ldr r2, [pc, #324] ; (8004acc <HAL_GPIO_DeInit+0x1c0>)
|
|||
|
|
8004988: 4293 cmp r3, r2
|
|||
|
|
800498a: d101 bne.n 8004990 <HAL_GPIO_DeInit+0x84>
|
|||
|
|
800498c: 2305 movs r3, #5
|
|||
|
|
800498e: e00a b.n 80049a6 <HAL_GPIO_DeInit+0x9a>
|
|||
|
|
8004990: 2306 movs r3, #6
|
|||
|
|
8004992: e008 b.n 80049a6 <HAL_GPIO_DeInit+0x9a>
|
|||
|
|
8004994: 2304 movs r3, #4
|
|||
|
|
8004996: e006 b.n 80049a6 <HAL_GPIO_DeInit+0x9a>
|
|||
|
|
8004998: 2303 movs r3, #3
|
|||
|
|
800499a: e004 b.n 80049a6 <HAL_GPIO_DeInit+0x9a>
|
|||
|
|
800499c: 2302 movs r3, #2
|
|||
|
|
800499e: e002 b.n 80049a6 <HAL_GPIO_DeInit+0x9a>
|
|||
|
|
80049a0: 2301 movs r3, #1
|
|||
|
|
80049a2: e000 b.n 80049a6 <HAL_GPIO_DeInit+0x9a>
|
|||
|
|
80049a4: 2300 movs r3, #0
|
|||
|
|
80049a6: 697a ldr r2, [r7, #20]
|
|||
|
|
80049a8: 2103 movs r1, #3
|
|||
|
|
80049aa: 400a ands r2, r1
|
|||
|
|
80049ac: 0092 lsls r2, r2, #2
|
|||
|
|
80049ae: 4093 lsls r3, r2
|
|||
|
|
80049b0: 001a movs r2, r3
|
|||
|
|
80049b2: 68fb ldr r3, [r7, #12]
|
|||
|
|
80049b4: 429a cmp r2, r3
|
|||
|
|
80049b6: d132 bne.n 8004a1e <HAL_GPIO_DeInit+0x112>
|
|||
|
|
{
|
|||
|
|
/* Clear EXTI line configuration */
|
|||
|
|
EXTI->IMR &= ~((uint32_t)iocurrent);
|
|||
|
|
80049b8: 4b45 ldr r3, [pc, #276] ; (8004ad0 <HAL_GPIO_DeInit+0x1c4>)
|
|||
|
|
80049ba: 4a45 ldr r2, [pc, #276] ; (8004ad0 <HAL_GPIO_DeInit+0x1c4>)
|
|||
|
|
80049bc: 6812 ldr r2, [r2, #0]
|
|||
|
|
80049be: 6939 ldr r1, [r7, #16]
|
|||
|
|
80049c0: 43c9 mvns r1, r1
|
|||
|
|
80049c2: 400a ands r2, r1
|
|||
|
|
80049c4: 601a str r2, [r3, #0]
|
|||
|
|
EXTI->EMR &= ~((uint32_t)iocurrent);
|
|||
|
|
80049c6: 4b42 ldr r3, [pc, #264] ; (8004ad0 <HAL_GPIO_DeInit+0x1c4>)
|
|||
|
|
80049c8: 4a41 ldr r2, [pc, #260] ; (8004ad0 <HAL_GPIO_DeInit+0x1c4>)
|
|||
|
|
80049ca: 6852 ldr r2, [r2, #4]
|
|||
|
|
80049cc: 6939 ldr r1, [r7, #16]
|
|||
|
|
80049ce: 43c9 mvns r1, r1
|
|||
|
|
80049d0: 400a ands r2, r1
|
|||
|
|
80049d2: 605a str r2, [r3, #4]
|
|||
|
|
|
|||
|
|
/* Clear Rising Falling edge configuration */
|
|||
|
|
EXTI->RTSR &= ~((uint32_t)iocurrent);
|
|||
|
|
80049d4: 4b3e ldr r3, [pc, #248] ; (8004ad0 <HAL_GPIO_DeInit+0x1c4>)
|
|||
|
|
80049d6: 4a3e ldr r2, [pc, #248] ; (8004ad0 <HAL_GPIO_DeInit+0x1c4>)
|
|||
|
|
80049d8: 6892 ldr r2, [r2, #8]
|
|||
|
|
80049da: 6939 ldr r1, [r7, #16]
|
|||
|
|
80049dc: 43c9 mvns r1, r1
|
|||
|
|
80049de: 400a ands r2, r1
|
|||
|
|
80049e0: 609a str r2, [r3, #8]
|
|||
|
|
EXTI->FTSR &= ~((uint32_t)iocurrent);
|
|||
|
|
80049e2: 4b3b ldr r3, [pc, #236] ; (8004ad0 <HAL_GPIO_DeInit+0x1c4>)
|
|||
|
|
80049e4: 4a3a ldr r2, [pc, #232] ; (8004ad0 <HAL_GPIO_DeInit+0x1c4>)
|
|||
|
|
80049e6: 68d2 ldr r2, [r2, #12]
|
|||
|
|
80049e8: 6939 ldr r1, [r7, #16]
|
|||
|
|
80049ea: 43c9 mvns r1, r1
|
|||
|
|
80049ec: 400a ands r2, r1
|
|||
|
|
80049ee: 60da str r2, [r3, #12]
|
|||
|
|
|
|||
|
|
tmp = (0x0FUL) << (4U * (position & 0x03U));
|
|||
|
|
80049f0: 697b ldr r3, [r7, #20]
|
|||
|
|
80049f2: 2203 movs r2, #3
|
|||
|
|
80049f4: 4013 ands r3, r2
|
|||
|
|
80049f6: 009b lsls r3, r3, #2
|
|||
|
|
80049f8: 220f movs r2, #15
|
|||
|
|
80049fa: 409a lsls r2, r3
|
|||
|
|
80049fc: 0013 movs r3, r2
|
|||
|
|
80049fe: 60fb str r3, [r7, #12]
|
|||
|
|
SYSCFG->EXTICR[position >> 2U] &= ~tmp;
|
|||
|
|
8004a00: 482d ldr r0, [pc, #180] ; (8004ab8 <HAL_GPIO_DeInit+0x1ac>)
|
|||
|
|
8004a02: 697b ldr r3, [r7, #20]
|
|||
|
|
8004a04: 089b lsrs r3, r3, #2
|
|||
|
|
8004a06: 492c ldr r1, [pc, #176] ; (8004ab8 <HAL_GPIO_DeInit+0x1ac>)
|
|||
|
|
8004a08: 697a ldr r2, [r7, #20]
|
|||
|
|
8004a0a: 0892 lsrs r2, r2, #2
|
|||
|
|
8004a0c: 3202 adds r2, #2
|
|||
|
|
8004a0e: 0092 lsls r2, r2, #2
|
|||
|
|
8004a10: 5852 ldr r2, [r2, r1]
|
|||
|
|
8004a12: 68f9 ldr r1, [r7, #12]
|
|||
|
|
8004a14: 43c9 mvns r1, r1
|
|||
|
|
8004a16: 400a ands r2, r1
|
|||
|
|
8004a18: 3302 adds r3, #2
|
|||
|
|
8004a1a: 009b lsls r3, r3, #2
|
|||
|
|
8004a1c: 501a str r2, [r3, r0]
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
/*------------------------- GPIO Mode Configuration --------------------*/
|
|||
|
|
/* Configure IO Direction in Input Floting Mode */
|
|||
|
|
GPIOx->MODER |= (GPIO_MODER_MODE0 << (position * 2U));
|
|||
|
|
8004a1e: 687b ldr r3, [r7, #4]
|
|||
|
|
8004a20: 681a ldr r2, [r3, #0]
|
|||
|
|
8004a22: 697b ldr r3, [r7, #20]
|
|||
|
|
8004a24: 005b lsls r3, r3, #1
|
|||
|
|
8004a26: 2103 movs r1, #3
|
|||
|
|
8004a28: 4099 lsls r1, r3
|
|||
|
|
8004a2a: 000b movs r3, r1
|
|||
|
|
8004a2c: 431a orrs r2, r3
|
|||
|
|
8004a2e: 687b ldr r3, [r7, #4]
|
|||
|
|
8004a30: 601a str r2, [r3, #0]
|
|||
|
|
|
|||
|
|
/* Configure the default Alternate Function in current IO */
|
|||
|
|
GPIOx->AFR[position >> 3U] &= ~(0xFUL << ((uint32_t)(position & 0x07UL) * 4U));
|
|||
|
|
8004a32: 697b ldr r3, [r7, #20]
|
|||
|
|
8004a34: 08da lsrs r2, r3, #3
|
|||
|
|
8004a36: 697b ldr r3, [r7, #20]
|
|||
|
|
8004a38: 08d9 lsrs r1, r3, #3
|
|||
|
|
8004a3a: 687b ldr r3, [r7, #4]
|
|||
|
|
8004a3c: 3108 adds r1, #8
|
|||
|
|
8004a3e: 0089 lsls r1, r1, #2
|
|||
|
|
8004a40: 58cb ldr r3, [r1, r3]
|
|||
|
|
8004a42: 6979 ldr r1, [r7, #20]
|
|||
|
|
8004a44: 2007 movs r0, #7
|
|||
|
|
8004a46: 4001 ands r1, r0
|
|||
|
|
8004a48: 0089 lsls r1, r1, #2
|
|||
|
|
8004a4a: 200f movs r0, #15
|
|||
|
|
8004a4c: 4088 lsls r0, r1
|
|||
|
|
8004a4e: 0001 movs r1, r0
|
|||
|
|
8004a50: 43c9 mvns r1, r1
|
|||
|
|
8004a52: 4019 ands r1, r3
|
|||
|
|
8004a54: 687b ldr r3, [r7, #4]
|
|||
|
|
8004a56: 3208 adds r2, #8
|
|||
|
|
8004a58: 0092 lsls r2, r2, #2
|
|||
|
|
8004a5a: 50d1 str r1, [r2, r3]
|
|||
|
|
|
|||
|
|
/* Deactivate the Pull-up oand Pull-down resistor for the current IO */
|
|||
|
|
GPIOx->PUPDR &= ~(GPIO_PUPDR_PUPD0 << (position * 2U));
|
|||
|
|
8004a5c: 687b ldr r3, [r7, #4]
|
|||
|
|
8004a5e: 68db ldr r3, [r3, #12]
|
|||
|
|
8004a60: 697a ldr r2, [r7, #20]
|
|||
|
|
8004a62: 0052 lsls r2, r2, #1
|
|||
|
|
8004a64: 2103 movs r1, #3
|
|||
|
|
8004a66: 4091 lsls r1, r2
|
|||
|
|
8004a68: 000a movs r2, r1
|
|||
|
|
8004a6a: 43d2 mvns r2, r2
|
|||
|
|
8004a6c: 401a ands r2, r3
|
|||
|
|
8004a6e: 687b ldr r3, [r7, #4]
|
|||
|
|
8004a70: 60da str r2, [r3, #12]
|
|||
|
|
|
|||
|
|
/* Configure the default value IO Output Type */
|
|||
|
|
GPIOx->OTYPER &= ~(GPIO_OTYPER_OT_0 << position);
|
|||
|
|
8004a72: 687b ldr r3, [r7, #4]
|
|||
|
|
8004a74: 685b ldr r3, [r3, #4]
|
|||
|
|
8004a76: 2101 movs r1, #1
|
|||
|
|
8004a78: 697a ldr r2, [r7, #20]
|
|||
|
|
8004a7a: 4091 lsls r1, r2
|
|||
|
|
8004a7c: 000a movs r2, r1
|
|||
|
|
8004a7e: 43d2 mvns r2, r2
|
|||
|
|
8004a80: 401a ands r2, r3
|
|||
|
|
8004a82: 687b ldr r3, [r7, #4]
|
|||
|
|
8004a84: 605a str r2, [r3, #4]
|
|||
|
|
|
|||
|
|
/* Configure the default value for IO Speed */
|
|||
|
|
GPIOx->OSPEEDR &= ~(GPIO_OSPEEDER_OSPEED0 << (position * 2U));
|
|||
|
|
8004a86: 687b ldr r3, [r7, #4]
|
|||
|
|
8004a88: 689b ldr r3, [r3, #8]
|
|||
|
|
8004a8a: 697a ldr r2, [r7, #20]
|
|||
|
|
8004a8c: 0052 lsls r2, r2, #1
|
|||
|
|
8004a8e: 2103 movs r1, #3
|
|||
|
|
8004a90: 4091 lsls r1, r2
|
|||
|
|
8004a92: 000a movs r2, r1
|
|||
|
|
8004a94: 43d2 mvns r2, r2
|
|||
|
|
8004a96: 401a ands r2, r3
|
|||
|
|
8004a98: 687b ldr r3, [r7, #4]
|
|||
|
|
8004a9a: 609a str r2, [r3, #8]
|
|||
|
|
}
|
|||
|
|
position++;
|
|||
|
|
8004a9c: 697b ldr r3, [r7, #20]
|
|||
|
|
8004a9e: 3301 adds r3, #1
|
|||
|
|
8004aa0: 617b str r3, [r7, #20]
|
|||
|
|
while ((GPIO_Pin >> position) != 0)
|
|||
|
|
8004aa2: 683a ldr r2, [r7, #0]
|
|||
|
|
8004aa4: 697b ldr r3, [r7, #20]
|
|||
|
|
8004aa6: 40da lsrs r2, r3
|
|||
|
|
8004aa8: 1e13 subs r3, r2, #0
|
|||
|
|
8004aaa: d000 beq.n 8004aae <HAL_GPIO_DeInit+0x1a2>
|
|||
|
|
8004aac: e73a b.n 8004924 <HAL_GPIO_DeInit+0x18>
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
8004aae: 46c0 nop ; (mov r8, r8)
|
|||
|
|
8004ab0: 46bd mov sp, r7
|
|||
|
|
8004ab2: b006 add sp, #24
|
|||
|
|
8004ab4: bd80 pop {r7, pc}
|
|||
|
|
8004ab6: 46c0 nop ; (mov r8, r8)
|
|||
|
|
8004ab8: 40010000 .word 0x40010000
|
|||
|
|
8004abc: 50000400 .word 0x50000400
|
|||
|
|
8004ac0: 50000800 .word 0x50000800
|
|||
|
|
8004ac4: 50000c00 .word 0x50000c00
|
|||
|
|
8004ac8: 50001000 .word 0x50001000
|
|||
|
|
8004acc: 50001c00 .word 0x50001c00
|
|||
|
|
8004ad0: 40010400 .word 0x40010400
|
|||
|
|
|
|||
|
|
08004ad4 <HAL_GPIO_ReadPin>:
|
|||
|
|
* This parameter can be GPIO_PIN_x where x can be (0..15).
|
|||
|
|
* All port bits are not necessarily available on all GPIOs.
|
|||
|
|
* @retval The input port pin value.
|
|||
|
|
*/
|
|||
|
|
GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
|
|||
|
|
{
|
|||
|
|
8004ad4: b580 push {r7, lr}
|
|||
|
|
8004ad6: b084 sub sp, #16
|
|||
|
|
8004ad8: af00 add r7, sp, #0
|
|||
|
|
8004ada: 6078 str r0, [r7, #4]
|
|||
|
|
8004adc: 000a movs r2, r1
|
|||
|
|
8004ade: 1cbb adds r3, r7, #2
|
|||
|
|
8004ae0: 801a strh r2, [r3, #0]
|
|||
|
|
GPIO_PinState bitstatus;
|
|||
|
|
|
|||
|
|
/* Check the parameters */
|
|||
|
|
assert_param(IS_GPIO_PIN_AVAILABLE(GPIOx, GPIO_Pin));
|
|||
|
|
|
|||
|
|
if ((GPIOx->IDR & GPIO_Pin) != (uint32_t)GPIO_PIN_RESET)
|
|||
|
|
8004ae2: 687b ldr r3, [r7, #4]
|
|||
|
|
8004ae4: 691b ldr r3, [r3, #16]
|
|||
|
|
8004ae6: 1cba adds r2, r7, #2
|
|||
|
|
8004ae8: 8812 ldrh r2, [r2, #0]
|
|||
|
|
8004aea: 4013 ands r3, r2
|
|||
|
|
8004aec: d004 beq.n 8004af8 <HAL_GPIO_ReadPin+0x24>
|
|||
|
|
{
|
|||
|
|
bitstatus = GPIO_PIN_SET;
|
|||
|
|
8004aee: 230f movs r3, #15
|
|||
|
|
8004af0: 18fb adds r3, r7, r3
|
|||
|
|
8004af2: 2201 movs r2, #1
|
|||
|
|
8004af4: 701a strb r2, [r3, #0]
|
|||
|
|
8004af6: e003 b.n 8004b00 <HAL_GPIO_ReadPin+0x2c>
|
|||
|
|
}
|
|||
|
|
else
|
|||
|
|
{
|
|||
|
|
bitstatus = GPIO_PIN_RESET;
|
|||
|
|
8004af8: 230f movs r3, #15
|
|||
|
|
8004afa: 18fb adds r3, r7, r3
|
|||
|
|
8004afc: 2200 movs r2, #0
|
|||
|
|
8004afe: 701a strb r2, [r3, #0]
|
|||
|
|
}
|
|||
|
|
return bitstatus;
|
|||
|
|
8004b00: 230f movs r3, #15
|
|||
|
|
8004b02: 18fb adds r3, r7, r3
|
|||
|
|
8004b04: 781b ldrb r3, [r3, #0]
|
|||
|
|
}
|
|||
|
|
8004b06: 0018 movs r0, r3
|
|||
|
|
8004b08: 46bd mov sp, r7
|
|||
|
|
8004b0a: b004 add sp, #16
|
|||
|
|
8004b0c: bd80 pop {r7, pc}
|
|||
|
|
|
|||
|
|
08004b0e <HAL_GPIO_WritePin>:
|
|||
|
|
* GPIO_PIN_RESET: to clear the port pin
|
|||
|
|
* GPIO_PIN_SET: to set the port pin
|
|||
|
|
* @retval None
|
|||
|
|
*/
|
|||
|
|
void HAL_GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState)
|
|||
|
|
{
|
|||
|
|
8004b0e: b580 push {r7, lr}
|
|||
|
|
8004b10: b082 sub sp, #8
|
|||
|
|
8004b12: af00 add r7, sp, #0
|
|||
|
|
8004b14: 6078 str r0, [r7, #4]
|
|||
|
|
8004b16: 0008 movs r0, r1
|
|||
|
|
8004b18: 0011 movs r1, r2
|
|||
|
|
8004b1a: 1cbb adds r3, r7, #2
|
|||
|
|
8004b1c: 1c02 adds r2, r0, #0
|
|||
|
|
8004b1e: 801a strh r2, [r3, #0]
|
|||
|
|
8004b20: 1c7b adds r3, r7, #1
|
|||
|
|
8004b22: 1c0a adds r2, r1, #0
|
|||
|
|
8004b24: 701a strb r2, [r3, #0]
|
|||
|
|
/* Check the parameters */
|
|||
|
|
assert_param(IS_GPIO_PIN_AVAILABLE(GPIOx, GPIO_Pin));
|
|||
|
|
assert_param(IS_GPIO_PIN_ACTION(PinState));
|
|||
|
|
|
|||
|
|
if (PinState != GPIO_PIN_RESET)
|
|||
|
|
8004b26: 1c7b adds r3, r7, #1
|
|||
|
|
8004b28: 781b ldrb r3, [r3, #0]
|
|||
|
|
8004b2a: 2b00 cmp r3, #0
|
|||
|
|
8004b2c: d004 beq.n 8004b38 <HAL_GPIO_WritePin+0x2a>
|
|||
|
|
{
|
|||
|
|
GPIOx->BSRR = GPIO_Pin;
|
|||
|
|
8004b2e: 1cbb adds r3, r7, #2
|
|||
|
|
8004b30: 881a ldrh r2, [r3, #0]
|
|||
|
|
8004b32: 687b ldr r3, [r7, #4]
|
|||
|
|
8004b34: 619a str r2, [r3, #24]
|
|||
|
|
}
|
|||
|
|
else
|
|||
|
|
{
|
|||
|
|
GPIOx->BRR = GPIO_Pin ;
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
8004b36: e003 b.n 8004b40 <HAL_GPIO_WritePin+0x32>
|
|||
|
|
GPIOx->BRR = GPIO_Pin ;
|
|||
|
|
8004b38: 1cbb adds r3, r7, #2
|
|||
|
|
8004b3a: 881a ldrh r2, [r3, #0]
|
|||
|
|
8004b3c: 687b ldr r3, [r7, #4]
|
|||
|
|
8004b3e: 629a str r2, [r3, #40] ; 0x28
|
|||
|
|
}
|
|||
|
|
8004b40: 46c0 nop ; (mov r8, r8)
|
|||
|
|
8004b42: 46bd mov sp, r7
|
|||
|
|
8004b44: b002 add sp, #8
|
|||
|
|
8004b46: bd80 pop {r7, pc}
|
|||
|
|
|
|||
|
|
08004b48 <HAL_GPIO_EXTI_IRQHandler>:
|
|||
|
|
* @brief This function handles EXTI interrupt request.
|
|||
|
|
* @param GPIO_Pin Specifies the pins connected to the EXTI line.
|
|||
|
|
* @retval None
|
|||
|
|
*/
|
|||
|
|
void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin)
|
|||
|
|
{
|
|||
|
|
8004b48: b580 push {r7, lr}
|
|||
|
|
8004b4a: b082 sub sp, #8
|
|||
|
|
8004b4c: af00 add r7, sp, #0
|
|||
|
|
8004b4e: 0002 movs r2, r0
|
|||
|
|
8004b50: 1dbb adds r3, r7, #6
|
|||
|
|
8004b52: 801a strh r2, [r3, #0]
|
|||
|
|
/* EXTI line interrupt detected */
|
|||
|
|
if (__HAL_GPIO_EXTI_GET_IT(GPIO_Pin) != RESET)
|
|||
|
|
8004b54: 4b09 ldr r3, [pc, #36] ; (8004b7c <HAL_GPIO_EXTI_IRQHandler+0x34>)
|
|||
|
|
8004b56: 695b ldr r3, [r3, #20]
|
|||
|
|
8004b58: 1dba adds r2, r7, #6
|
|||
|
|
8004b5a: 8812 ldrh r2, [r2, #0]
|
|||
|
|
8004b5c: 4013 ands r3, r2
|
|||
|
|
8004b5e: d008 beq.n 8004b72 <HAL_GPIO_EXTI_IRQHandler+0x2a>
|
|||
|
|
{
|
|||
|
|
__HAL_GPIO_EXTI_CLEAR_IT(GPIO_Pin);
|
|||
|
|
8004b60: 4b06 ldr r3, [pc, #24] ; (8004b7c <HAL_GPIO_EXTI_IRQHandler+0x34>)
|
|||
|
|
8004b62: 1dba adds r2, r7, #6
|
|||
|
|
8004b64: 8812 ldrh r2, [r2, #0]
|
|||
|
|
8004b66: 615a str r2, [r3, #20]
|
|||
|
|
HAL_GPIO_EXTI_Callback(GPIO_Pin);
|
|||
|
|
8004b68: 1dbb adds r3, r7, #6
|
|||
|
|
8004b6a: 881b ldrh r3, [r3, #0]
|
|||
|
|
8004b6c: 0018 movs r0, r3
|
|||
|
|
8004b6e: f7ff f8f7 bl 8003d60 <HAL_GPIO_EXTI_Callback>
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
8004b72: 46c0 nop ; (mov r8, r8)
|
|||
|
|
8004b74: 46bd mov sp, r7
|
|||
|
|
8004b76: b002 add sp, #8
|
|||
|
|
8004b78: bd80 pop {r7, pc}
|
|||
|
|
8004b7a: 46c0 nop ; (mov r8, r8)
|
|||
|
|
8004b7c: 40010400 .word 0x40010400
|
|||
|
|
|
|||
|
|
08004b80 <HAL_RCC_OscConfig>:
|
|||
|
|
* supported by this macro. User should request a transition to HSE Off
|
|||
|
|
* first and then HSE On or HSE Bypass.
|
|||
|
|
* @retval HAL status
|
|||
|
|
*/
|
|||
|
|
HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
|
|||
|
|
{
|
|||
|
|
8004b80: b590 push {r4, r7, lr}
|
|||
|
|
8004b82: b08b sub sp, #44 ; 0x2c
|
|||
|
|
8004b84: af00 add r7, sp, #0
|
|||
|
|
8004b86: 6078 str r0, [r7, #4]
|
|||
|
|
uint32_t hsi_state;
|
|||
|
|
HAL_StatusTypeDef status;
|
|||
|
|
uint32_t sysclk_source, pll_config;
|
|||
|
|
|
|||
|
|
/* Check Null pointer */
|
|||
|
|
if(RCC_OscInitStruct == NULL)
|
|||
|
|
8004b88: 687b ldr r3, [r7, #4]
|
|||
|
|
8004b8a: 2b00 cmp r3, #0
|
|||
|
|
8004b8c: d102 bne.n 8004b94 <HAL_RCC_OscConfig+0x14>
|
|||
|
|
{
|
|||
|
|
return HAL_ERROR;
|
|||
|
|
8004b8e: 2301 movs r3, #1
|
|||
|
|
8004b90: f000 fbbe bl 8005310 <HAL_RCC_OscConfig+0x790>
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
/* Check the parameters */
|
|||
|
|
assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType));
|
|||
|
|
|
|||
|
|
sysclk_source = __HAL_RCC_GET_SYSCLK_SOURCE();
|
|||
|
|
8004b94: 4bc9 ldr r3, [pc, #804] ; (8004ebc <HAL_RCC_OscConfig+0x33c>)
|
|||
|
|
8004b96: 68db ldr r3, [r3, #12]
|
|||
|
|
8004b98: 220c movs r2, #12
|
|||
|
|
8004b9a: 4013 ands r3, r2
|
|||
|
|
8004b9c: 61fb str r3, [r7, #28]
|
|||
|
|
pll_config = __HAL_RCC_GET_PLL_OSCSOURCE();
|
|||
|
|
8004b9e: 4bc7 ldr r3, [pc, #796] ; (8004ebc <HAL_RCC_OscConfig+0x33c>)
|
|||
|
|
8004ba0: 68da ldr r2, [r3, #12]
|
|||
|
|
8004ba2: 2380 movs r3, #128 ; 0x80
|
|||
|
|
8004ba4: 025b lsls r3, r3, #9
|
|||
|
|
8004ba6: 4013 ands r3, r2
|
|||
|
|
8004ba8: 61bb str r3, [r7, #24]
|
|||
|
|
|
|||
|
|
/*------------------------------- HSE Configuration ------------------------*/
|
|||
|
|
if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)
|
|||
|
|
8004baa: 687b ldr r3, [r7, #4]
|
|||
|
|
8004bac: 681b ldr r3, [r3, #0]
|
|||
|
|
8004bae: 2201 movs r2, #1
|
|||
|
|
8004bb0: 4013 ands r3, r2
|
|||
|
|
8004bb2: d100 bne.n 8004bb6 <HAL_RCC_OscConfig+0x36>
|
|||
|
|
8004bb4: e07e b.n 8004cb4 <HAL_RCC_OscConfig+0x134>
|
|||
|
|
{
|
|||
|
|
/* Check the parameters */
|
|||
|
|
assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState));
|
|||
|
|
|
|||
|
|
/* When the HSE is used as system clock or clock source for PLL in these cases it is not allowed to be disabled */
|
|||
|
|
if((sysclk_source == RCC_SYSCLKSOURCE_STATUS_HSE)
|
|||
|
|
8004bb6: 69fb ldr r3, [r7, #28]
|
|||
|
|
8004bb8: 2b08 cmp r3, #8
|
|||
|
|
8004bba: d007 beq.n 8004bcc <HAL_RCC_OscConfig+0x4c>
|
|||
|
|
|| ((sysclk_source == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (pll_config == RCC_PLLSOURCE_HSE)))
|
|||
|
|
8004bbc: 69fb ldr r3, [r7, #28]
|
|||
|
|
8004bbe: 2b0c cmp r3, #12
|
|||
|
|
8004bc0: d112 bne.n 8004be8 <HAL_RCC_OscConfig+0x68>
|
|||
|
|
8004bc2: 69ba ldr r2, [r7, #24]
|
|||
|
|
8004bc4: 2380 movs r3, #128 ; 0x80
|
|||
|
|
8004bc6: 025b lsls r3, r3, #9
|
|||
|
|
8004bc8: 429a cmp r2, r3
|
|||
|
|
8004bca: d10d bne.n 8004be8 <HAL_RCC_OscConfig+0x68>
|
|||
|
|
{
|
|||
|
|
if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != 0U) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
|
|||
|
|
8004bcc: 4bbb ldr r3, [pc, #748] ; (8004ebc <HAL_RCC_OscConfig+0x33c>)
|
|||
|
|
8004bce: 681a ldr r2, [r3, #0]
|
|||
|
|
8004bd0: 2380 movs r3, #128 ; 0x80
|
|||
|
|
8004bd2: 029b lsls r3, r3, #10
|
|||
|
|
8004bd4: 4013 ands r3, r2
|
|||
|
|
8004bd6: d100 bne.n 8004bda <HAL_RCC_OscConfig+0x5a>
|
|||
|
|
8004bd8: e06b b.n 8004cb2 <HAL_RCC_OscConfig+0x132>
|
|||
|
|
8004bda: 687b ldr r3, [r7, #4]
|
|||
|
|
8004bdc: 685b ldr r3, [r3, #4]
|
|||
|
|
8004bde: 2b00 cmp r3, #0
|
|||
|
|
8004be0: d167 bne.n 8004cb2 <HAL_RCC_OscConfig+0x132>
|
|||
|
|
{
|
|||
|
|
return HAL_ERROR;
|
|||
|
|
8004be2: 2301 movs r3, #1
|
|||
|
|
8004be4: f000 fb94 bl 8005310 <HAL_RCC_OscConfig+0x790>
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
else
|
|||
|
|
{
|
|||
|
|
/* Set the new HSE configuration ---------------------------------------*/
|
|||
|
|
__HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
|
|||
|
|
8004be8: 687b ldr r3, [r7, #4]
|
|||
|
|
8004bea: 685a ldr r2, [r3, #4]
|
|||
|
|
8004bec: 2380 movs r3, #128 ; 0x80
|
|||
|
|
8004bee: 025b lsls r3, r3, #9
|
|||
|
|
8004bf0: 429a cmp r2, r3
|
|||
|
|
8004bf2: d107 bne.n 8004c04 <HAL_RCC_OscConfig+0x84>
|
|||
|
|
8004bf4: 4bb1 ldr r3, [pc, #708] ; (8004ebc <HAL_RCC_OscConfig+0x33c>)
|
|||
|
|
8004bf6: 4ab1 ldr r2, [pc, #708] ; (8004ebc <HAL_RCC_OscConfig+0x33c>)
|
|||
|
|
8004bf8: 6812 ldr r2, [r2, #0]
|
|||
|
|
8004bfa: 2180 movs r1, #128 ; 0x80
|
|||
|
|
8004bfc: 0249 lsls r1, r1, #9
|
|||
|
|
8004bfe: 430a orrs r2, r1
|
|||
|
|
8004c00: 601a str r2, [r3, #0]
|
|||
|
|
8004c02: e027 b.n 8004c54 <HAL_RCC_OscConfig+0xd4>
|
|||
|
|
8004c04: 687b ldr r3, [r7, #4]
|
|||
|
|
8004c06: 685a ldr r2, [r3, #4]
|
|||
|
|
8004c08: 23a0 movs r3, #160 ; 0xa0
|
|||
|
|
8004c0a: 02db lsls r3, r3, #11
|
|||
|
|
8004c0c: 429a cmp r2, r3
|
|||
|
|
8004c0e: d10e bne.n 8004c2e <HAL_RCC_OscConfig+0xae>
|
|||
|
|
8004c10: 4baa ldr r3, [pc, #680] ; (8004ebc <HAL_RCC_OscConfig+0x33c>)
|
|||
|
|
8004c12: 4aaa ldr r2, [pc, #680] ; (8004ebc <HAL_RCC_OscConfig+0x33c>)
|
|||
|
|
8004c14: 6812 ldr r2, [r2, #0]
|
|||
|
|
8004c16: 2180 movs r1, #128 ; 0x80
|
|||
|
|
8004c18: 02c9 lsls r1, r1, #11
|
|||
|
|
8004c1a: 430a orrs r2, r1
|
|||
|
|
8004c1c: 601a str r2, [r3, #0]
|
|||
|
|
8004c1e: 4ba7 ldr r3, [pc, #668] ; (8004ebc <HAL_RCC_OscConfig+0x33c>)
|
|||
|
|
8004c20: 4aa6 ldr r2, [pc, #664] ; (8004ebc <HAL_RCC_OscConfig+0x33c>)
|
|||
|
|
8004c22: 6812 ldr r2, [r2, #0]
|
|||
|
|
8004c24: 2180 movs r1, #128 ; 0x80
|
|||
|
|
8004c26: 0249 lsls r1, r1, #9
|
|||
|
|
8004c28: 430a orrs r2, r1
|
|||
|
|
8004c2a: 601a str r2, [r3, #0]
|
|||
|
|
8004c2c: e012 b.n 8004c54 <HAL_RCC_OscConfig+0xd4>
|
|||
|
|
8004c2e: 4ba3 ldr r3, [pc, #652] ; (8004ebc <HAL_RCC_OscConfig+0x33c>)
|
|||
|
|
8004c30: 4aa2 ldr r2, [pc, #648] ; (8004ebc <HAL_RCC_OscConfig+0x33c>)
|
|||
|
|
8004c32: 6812 ldr r2, [r2, #0]
|
|||
|
|
8004c34: 49a2 ldr r1, [pc, #648] ; (8004ec0 <HAL_RCC_OscConfig+0x340>)
|
|||
|
|
8004c36: 400a ands r2, r1
|
|||
|
|
8004c38: 601a str r2, [r3, #0]
|
|||
|
|
8004c3a: 4ba0 ldr r3, [pc, #640] ; (8004ebc <HAL_RCC_OscConfig+0x33c>)
|
|||
|
|
8004c3c: 681a ldr r2, [r3, #0]
|
|||
|
|
8004c3e: 2380 movs r3, #128 ; 0x80
|
|||
|
|
8004c40: 025b lsls r3, r3, #9
|
|||
|
|
8004c42: 4013 ands r3, r2
|
|||
|
|
8004c44: 60fb str r3, [r7, #12]
|
|||
|
|
8004c46: 68fb ldr r3, [r7, #12]
|
|||
|
|
8004c48: 4b9c ldr r3, [pc, #624] ; (8004ebc <HAL_RCC_OscConfig+0x33c>)
|
|||
|
|
8004c4a: 4a9c ldr r2, [pc, #624] ; (8004ebc <HAL_RCC_OscConfig+0x33c>)
|
|||
|
|
8004c4c: 6812 ldr r2, [r2, #0]
|
|||
|
|
8004c4e: 499d ldr r1, [pc, #628] ; (8004ec4 <HAL_RCC_OscConfig+0x344>)
|
|||
|
|
8004c50: 400a ands r2, r1
|
|||
|
|
8004c52: 601a str r2, [r3, #0]
|
|||
|
|
|
|||
|
|
/* Check the HSE State */
|
|||
|
|
if(RCC_OscInitStruct->HSEState != RCC_HSE_OFF)
|
|||
|
|
8004c54: 687b ldr r3, [r7, #4]
|
|||
|
|
8004c56: 685b ldr r3, [r3, #4]
|
|||
|
|
8004c58: 2b00 cmp r3, #0
|
|||
|
|
8004c5a: d015 beq.n 8004c88 <HAL_RCC_OscConfig+0x108>
|
|||
|
|
{
|
|||
|
|
/* Get Start Tick */
|
|||
|
|
tickstart = HAL_GetTick();
|
|||
|
|
8004c5c: f7ff f966 bl 8003f2c <HAL_GetTick>
|
|||
|
|
8004c60: 0003 movs r3, r0
|
|||
|
|
8004c62: 617b str r3, [r7, #20]
|
|||
|
|
|
|||
|
|
/* Wait till HSE is ready */
|
|||
|
|
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == 0U)
|
|||
|
|
8004c64: e009 b.n 8004c7a <HAL_RCC_OscConfig+0xfa>
|
|||
|
|
{
|
|||
|
|
if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
|
|||
|
|
8004c66: f7ff f961 bl 8003f2c <HAL_GetTick>
|
|||
|
|
8004c6a: 0002 movs r2, r0
|
|||
|
|
8004c6c: 697b ldr r3, [r7, #20]
|
|||
|
|
8004c6e: 1ad3 subs r3, r2, r3
|
|||
|
|
8004c70: 2b64 cmp r3, #100 ; 0x64
|
|||
|
|
8004c72: d902 bls.n 8004c7a <HAL_RCC_OscConfig+0xfa>
|
|||
|
|
{
|
|||
|
|
return HAL_TIMEOUT;
|
|||
|
|
8004c74: 2303 movs r3, #3
|
|||
|
|
8004c76: f000 fb4b bl 8005310 <HAL_RCC_OscConfig+0x790>
|
|||
|
|
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == 0U)
|
|||
|
|
8004c7a: 4b90 ldr r3, [pc, #576] ; (8004ebc <HAL_RCC_OscConfig+0x33c>)
|
|||
|
|
8004c7c: 681a ldr r2, [r3, #0]
|
|||
|
|
8004c7e: 2380 movs r3, #128 ; 0x80
|
|||
|
|
8004c80: 029b lsls r3, r3, #10
|
|||
|
|
8004c82: 4013 ands r3, r2
|
|||
|
|
8004c84: d0ef beq.n 8004c66 <HAL_RCC_OscConfig+0xe6>
|
|||
|
|
8004c86: e015 b.n 8004cb4 <HAL_RCC_OscConfig+0x134>
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
else
|
|||
|
|
{
|
|||
|
|
/* Get Start Tick */
|
|||
|
|
tickstart = HAL_GetTick();
|
|||
|
|
8004c88: f7ff f950 bl 8003f2c <HAL_GetTick>
|
|||
|
|
8004c8c: 0003 movs r3, r0
|
|||
|
|
8004c8e: 617b str r3, [r7, #20]
|
|||
|
|
|
|||
|
|
/* Wait till HSE is disabled */
|
|||
|
|
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != 0U)
|
|||
|
|
8004c90: e008 b.n 8004ca4 <HAL_RCC_OscConfig+0x124>
|
|||
|
|
{
|
|||
|
|
if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
|
|||
|
|
8004c92: f7ff f94b bl 8003f2c <HAL_GetTick>
|
|||
|
|
8004c96: 0002 movs r2, r0
|
|||
|
|
8004c98: 697b ldr r3, [r7, #20]
|
|||
|
|
8004c9a: 1ad3 subs r3, r2, r3
|
|||
|
|
8004c9c: 2b64 cmp r3, #100 ; 0x64
|
|||
|
|
8004c9e: d901 bls.n 8004ca4 <HAL_RCC_OscConfig+0x124>
|
|||
|
|
{
|
|||
|
|
return HAL_TIMEOUT;
|
|||
|
|
8004ca0: 2303 movs r3, #3
|
|||
|
|
8004ca2: e335 b.n 8005310 <HAL_RCC_OscConfig+0x790>
|
|||
|
|
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != 0U)
|
|||
|
|
8004ca4: 4b85 ldr r3, [pc, #532] ; (8004ebc <HAL_RCC_OscConfig+0x33c>)
|
|||
|
|
8004ca6: 681a ldr r2, [r3, #0]
|
|||
|
|
8004ca8: 2380 movs r3, #128 ; 0x80
|
|||
|
|
8004caa: 029b lsls r3, r3, #10
|
|||
|
|
8004cac: 4013 ands r3, r2
|
|||
|
|
8004cae: d1f0 bne.n 8004c92 <HAL_RCC_OscConfig+0x112>
|
|||
|
|
8004cb0: e000 b.n 8004cb4 <HAL_RCC_OscConfig+0x134>
|
|||
|
|
if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != 0U) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
|
|||
|
|
8004cb2: 46c0 nop ; (mov r8, r8)
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
/*----------------------------- HSI Configuration --------------------------*/
|
|||
|
|
if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI)
|
|||
|
|
8004cb4: 687b ldr r3, [r7, #4]
|
|||
|
|
8004cb6: 681b ldr r3, [r3, #0]
|
|||
|
|
8004cb8: 2202 movs r2, #2
|
|||
|
|
8004cba: 4013 ands r3, r2
|
|||
|
|
8004cbc: d100 bne.n 8004cc0 <HAL_RCC_OscConfig+0x140>
|
|||
|
|
8004cbe: e099 b.n 8004df4 <HAL_RCC_OscConfig+0x274>
|
|||
|
|
{
|
|||
|
|
/* Check the parameters */
|
|||
|
|
assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState));
|
|||
|
|
assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue));
|
|||
|
|
|
|||
|
|
hsi_state = RCC_OscInitStruct->HSIState;
|
|||
|
|
8004cc0: 687b ldr r3, [r7, #4]
|
|||
|
|
8004cc2: 68db ldr r3, [r3, #12]
|
|||
|
|
8004cc4: 627b str r3, [r7, #36] ; 0x24
|
|||
|
|
|
|||
|
|
#if defined(RCC_CR_HSIOUTEN)
|
|||
|
|
if((hsi_state & RCC_HSI_OUTEN) != 0U)
|
|||
|
|
8004cc6: 6a7b ldr r3, [r7, #36] ; 0x24
|
|||
|
|
8004cc8: 2220 movs r2, #32
|
|||
|
|
8004cca: 4013 ands r3, r2
|
|||
|
|
8004ccc: d009 beq.n 8004ce2 <HAL_RCC_OscConfig+0x162>
|
|||
|
|
{
|
|||
|
|
/* HSI Output enable for timer requested */
|
|||
|
|
SET_BIT(RCC->CR, RCC_CR_HSIOUTEN);
|
|||
|
|
8004cce: 4b7b ldr r3, [pc, #492] ; (8004ebc <HAL_RCC_OscConfig+0x33c>)
|
|||
|
|
8004cd0: 4a7a ldr r2, [pc, #488] ; (8004ebc <HAL_RCC_OscConfig+0x33c>)
|
|||
|
|
8004cd2: 6812 ldr r2, [r2, #0]
|
|||
|
|
8004cd4: 2120 movs r1, #32
|
|||
|
|
8004cd6: 430a orrs r2, r1
|
|||
|
|
8004cd8: 601a str r2, [r3, #0]
|
|||
|
|
|
|||
|
|
hsi_state &= ~RCC_CR_HSIOUTEN;
|
|||
|
|
8004cda: 6a7b ldr r3, [r7, #36] ; 0x24
|
|||
|
|
8004cdc: 2220 movs r2, #32
|
|||
|
|
8004cde: 4393 bics r3, r2
|
|||
|
|
8004ce0: 627b str r3, [r7, #36] ; 0x24
|
|||
|
|
}
|
|||
|
|
#endif
|
|||
|
|
|
|||
|
|
/* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */
|
|||
|
|
if((sysclk_source == RCC_SYSCLKSOURCE_STATUS_HSI)
|
|||
|
|
8004ce2: 69fb ldr r3, [r7, #28]
|
|||
|
|
8004ce4: 2b04 cmp r3, #4
|
|||
|
|
8004ce6: d005 beq.n 8004cf4 <HAL_RCC_OscConfig+0x174>
|
|||
|
|
|| ((sysclk_source == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (pll_config == RCC_PLLSOURCE_HSI)))
|
|||
|
|
8004ce8: 69fb ldr r3, [r7, #28]
|
|||
|
|
8004cea: 2b0c cmp r3, #12
|
|||
|
|
8004cec: d13f bne.n 8004d6e <HAL_RCC_OscConfig+0x1ee>
|
|||
|
|
8004cee: 69bb ldr r3, [r7, #24]
|
|||
|
|
8004cf0: 2b00 cmp r3, #0
|
|||
|
|
8004cf2: d13c bne.n 8004d6e <HAL_RCC_OscConfig+0x1ee>
|
|||
|
|
{
|
|||
|
|
/* When HSI is used as system clock it will not disabled */
|
|||
|
|
if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != 0U) && (hsi_state == RCC_HSI_OFF))
|
|||
|
|
8004cf4: 4b71 ldr r3, [pc, #452] ; (8004ebc <HAL_RCC_OscConfig+0x33c>)
|
|||
|
|
8004cf6: 681b ldr r3, [r3, #0]
|
|||
|
|
8004cf8: 2204 movs r2, #4
|
|||
|
|
8004cfa: 4013 ands r3, r2
|
|||
|
|
8004cfc: d004 beq.n 8004d08 <HAL_RCC_OscConfig+0x188>
|
|||
|
|
8004cfe: 6a7b ldr r3, [r7, #36] ; 0x24
|
|||
|
|
8004d00: 2b00 cmp r3, #0
|
|||
|
|
8004d02: d101 bne.n 8004d08 <HAL_RCC_OscConfig+0x188>
|
|||
|
|
{
|
|||
|
|
return HAL_ERROR;
|
|||
|
|
8004d04: 2301 movs r3, #1
|
|||
|
|
8004d06: e303 b.n 8005310 <HAL_RCC_OscConfig+0x790>
|
|||
|
|
}
|
|||
|
|
/* Otherwise, just the calibration and HSI or HSIdiv4 are allowed */
|
|||
|
|
else
|
|||
|
|
{
|
|||
|
|
/* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
|
|||
|
|
__HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
|
|||
|
|
8004d08: 4a6c ldr r2, [pc, #432] ; (8004ebc <HAL_RCC_OscConfig+0x33c>)
|
|||
|
|
8004d0a: 4b6c ldr r3, [pc, #432] ; (8004ebc <HAL_RCC_OscConfig+0x33c>)
|
|||
|
|
8004d0c: 685b ldr r3, [r3, #4]
|
|||
|
|
8004d0e: 496e ldr r1, [pc, #440] ; (8004ec8 <HAL_RCC_OscConfig+0x348>)
|
|||
|
|
8004d10: 4019 ands r1, r3
|
|||
|
|
8004d12: 687b ldr r3, [r7, #4]
|
|||
|
|
8004d14: 691b ldr r3, [r3, #16]
|
|||
|
|
8004d16: 021b lsls r3, r3, #8
|
|||
|
|
8004d18: 430b orrs r3, r1
|
|||
|
|
8004d1a: 6053 str r3, [r2, #4]
|
|||
|
|
|
|||
|
|
/* Enable the Internal High Speed oscillator (HSI or HSIdiv4) */
|
|||
|
|
__HAL_RCC_HSI_CONFIG(hsi_state);
|
|||
|
|
8004d1c: 4b67 ldr r3, [pc, #412] ; (8004ebc <HAL_RCC_OscConfig+0x33c>)
|
|||
|
|
8004d1e: 4a67 ldr r2, [pc, #412] ; (8004ebc <HAL_RCC_OscConfig+0x33c>)
|
|||
|
|
8004d20: 6812 ldr r2, [r2, #0]
|
|||
|
|
8004d22: 2109 movs r1, #9
|
|||
|
|
8004d24: 438a bics r2, r1
|
|||
|
|
8004d26: 0011 movs r1, r2
|
|||
|
|
8004d28: 6a7a ldr r2, [r7, #36] ; 0x24
|
|||
|
|
8004d2a: 430a orrs r2, r1
|
|||
|
|
8004d2c: 601a str r2, [r3, #0]
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
/* Update the SystemCoreClock global variable */
|
|||
|
|
SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE)>> RCC_CFGR_HPRE_Pos];
|
|||
|
|
8004d2e: f000 fc41 bl 80055b4 <HAL_RCC_GetSysClockFreq>
|
|||
|
|
8004d32: 0001 movs r1, r0
|
|||
|
|
8004d34: 4b61 ldr r3, [pc, #388] ; (8004ebc <HAL_RCC_OscConfig+0x33c>)
|
|||
|
|
8004d36: 68db ldr r3, [r3, #12]
|
|||
|
|
8004d38: 091b lsrs r3, r3, #4
|
|||
|
|
8004d3a: 220f movs r2, #15
|
|||
|
|
8004d3c: 4013 ands r3, r2
|
|||
|
|
8004d3e: 4a63 ldr r2, [pc, #396] ; (8004ecc <HAL_RCC_OscConfig+0x34c>)
|
|||
|
|
8004d40: 5cd3 ldrb r3, [r2, r3]
|
|||
|
|
8004d42: 000a movs r2, r1
|
|||
|
|
8004d44: 40da lsrs r2, r3
|
|||
|
|
8004d46: 4b62 ldr r3, [pc, #392] ; (8004ed0 <HAL_RCC_OscConfig+0x350>)
|
|||
|
|
8004d48: 601a str r2, [r3, #0]
|
|||
|
|
|
|||
|
|
/* Configure the source of time base considering new system clocks settings*/
|
|||
|
|
status = HAL_InitTick (uwTickPrio);
|
|||
|
|
8004d4a: 4b62 ldr r3, [pc, #392] ; (8004ed4 <HAL_RCC_OscConfig+0x354>)
|
|||
|
|
8004d4c: 681b ldr r3, [r3, #0]
|
|||
|
|
8004d4e: 2213 movs r2, #19
|
|||
|
|
8004d50: 18bc adds r4, r7, r2
|
|||
|
|
8004d52: 0018 movs r0, r3
|
|||
|
|
8004d54: f7ff f8a4 bl 8003ea0 <HAL_InitTick>
|
|||
|
|
8004d58: 0003 movs r3, r0
|
|||
|
|
8004d5a: 7023 strb r3, [r4, #0]
|
|||
|
|
if(status != HAL_OK)
|
|||
|
|
8004d5c: 2313 movs r3, #19
|
|||
|
|
8004d5e: 18fb adds r3, r7, r3
|
|||
|
|
8004d60: 781b ldrb r3, [r3, #0]
|
|||
|
|
8004d62: 2b00 cmp r3, #0
|
|||
|
|
8004d64: d046 beq.n 8004df4 <HAL_RCC_OscConfig+0x274>
|
|||
|
|
{
|
|||
|
|
return status;
|
|||
|
|
8004d66: 2313 movs r3, #19
|
|||
|
|
8004d68: 18fb adds r3, r7, r3
|
|||
|
|
8004d6a: 781b ldrb r3, [r3, #0]
|
|||
|
|
8004d6c: e2d0 b.n 8005310 <HAL_RCC_OscConfig+0x790>
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
else
|
|||
|
|
{
|
|||
|
|
/* Check the HSI State */
|
|||
|
|
if(hsi_state != RCC_HSI_OFF)
|
|||
|
|
8004d6e: 6a7b ldr r3, [r7, #36] ; 0x24
|
|||
|
|
8004d70: 2b00 cmp r3, #0
|
|||
|
|
8004d72: d026 beq.n 8004dc2 <HAL_RCC_OscConfig+0x242>
|
|||
|
|
{
|
|||
|
|
/* Enable the Internal High Speed oscillator (HSI or HSIdiv4) */
|
|||
|
|
__HAL_RCC_HSI_CONFIG(hsi_state);
|
|||
|
|
8004d74: 4b51 ldr r3, [pc, #324] ; (8004ebc <HAL_RCC_OscConfig+0x33c>)
|
|||
|
|
8004d76: 4a51 ldr r2, [pc, #324] ; (8004ebc <HAL_RCC_OscConfig+0x33c>)
|
|||
|
|
8004d78: 6812 ldr r2, [r2, #0]
|
|||
|
|
8004d7a: 2109 movs r1, #9
|
|||
|
|
8004d7c: 438a bics r2, r1
|
|||
|
|
8004d7e: 0011 movs r1, r2
|
|||
|
|
8004d80: 6a7a ldr r2, [r7, #36] ; 0x24
|
|||
|
|
8004d82: 430a orrs r2, r1
|
|||
|
|
8004d84: 601a str r2, [r3, #0]
|
|||
|
|
|
|||
|
|
/* Get Start Tick */
|
|||
|
|
tickstart = HAL_GetTick();
|
|||
|
|
8004d86: f7ff f8d1 bl 8003f2c <HAL_GetTick>
|
|||
|
|
8004d8a: 0003 movs r3, r0
|
|||
|
|
8004d8c: 617b str r3, [r7, #20]
|
|||
|
|
|
|||
|
|
/* Wait till HSI is ready */
|
|||
|
|
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == 0U)
|
|||
|
|
8004d8e: e008 b.n 8004da2 <HAL_RCC_OscConfig+0x222>
|
|||
|
|
{
|
|||
|
|
if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
|
|||
|
|
8004d90: f7ff f8cc bl 8003f2c <HAL_GetTick>
|
|||
|
|
8004d94: 0002 movs r2, r0
|
|||
|
|
8004d96: 697b ldr r3, [r7, #20]
|
|||
|
|
8004d98: 1ad3 subs r3, r2, r3
|
|||
|
|
8004d9a: 2b02 cmp r3, #2
|
|||
|
|
8004d9c: d901 bls.n 8004da2 <HAL_RCC_OscConfig+0x222>
|
|||
|
|
{
|
|||
|
|
return HAL_TIMEOUT;
|
|||
|
|
8004d9e: 2303 movs r3, #3
|
|||
|
|
8004da0: e2b6 b.n 8005310 <HAL_RCC_OscConfig+0x790>
|
|||
|
|
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == 0U)
|
|||
|
|
8004da2: 4b46 ldr r3, [pc, #280] ; (8004ebc <HAL_RCC_OscConfig+0x33c>)
|
|||
|
|
8004da4: 681b ldr r3, [r3, #0]
|
|||
|
|
8004da6: 2204 movs r2, #4
|
|||
|
|
8004da8: 4013 ands r3, r2
|
|||
|
|
8004daa: d0f1 beq.n 8004d90 <HAL_RCC_OscConfig+0x210>
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
/* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
|
|||
|
|
__HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
|
|||
|
|
8004dac: 4a43 ldr r2, [pc, #268] ; (8004ebc <HAL_RCC_OscConfig+0x33c>)
|
|||
|
|
8004dae: 4b43 ldr r3, [pc, #268] ; (8004ebc <HAL_RCC_OscConfig+0x33c>)
|
|||
|
|
8004db0: 685b ldr r3, [r3, #4]
|
|||
|
|
8004db2: 4945 ldr r1, [pc, #276] ; (8004ec8 <HAL_RCC_OscConfig+0x348>)
|
|||
|
|
8004db4: 4019 ands r1, r3
|
|||
|
|
8004db6: 687b ldr r3, [r7, #4]
|
|||
|
|
8004db8: 691b ldr r3, [r3, #16]
|
|||
|
|
8004dba: 021b lsls r3, r3, #8
|
|||
|
|
8004dbc: 430b orrs r3, r1
|
|||
|
|
8004dbe: 6053 str r3, [r2, #4]
|
|||
|
|
8004dc0: e018 b.n 8004df4 <HAL_RCC_OscConfig+0x274>
|
|||
|
|
}
|
|||
|
|
else
|
|||
|
|
{
|
|||
|
|
/* Disable the Internal High Speed oscillator (HSI). */
|
|||
|
|
__HAL_RCC_HSI_DISABLE();
|
|||
|
|
8004dc2: 4b3e ldr r3, [pc, #248] ; (8004ebc <HAL_RCC_OscConfig+0x33c>)
|
|||
|
|
8004dc4: 4a3d ldr r2, [pc, #244] ; (8004ebc <HAL_RCC_OscConfig+0x33c>)
|
|||
|
|
8004dc6: 6812 ldr r2, [r2, #0]
|
|||
|
|
8004dc8: 2101 movs r1, #1
|
|||
|
|
8004dca: 438a bics r2, r1
|
|||
|
|
8004dcc: 601a str r2, [r3, #0]
|
|||
|
|
|
|||
|
|
/* Get Start Tick */
|
|||
|
|
tickstart = HAL_GetTick();
|
|||
|
|
8004dce: f7ff f8ad bl 8003f2c <HAL_GetTick>
|
|||
|
|
8004dd2: 0003 movs r3, r0
|
|||
|
|
8004dd4: 617b str r3, [r7, #20]
|
|||
|
|
|
|||
|
|
/* Wait till HSI is disabled */
|
|||
|
|
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != 0U)
|
|||
|
|
8004dd6: e008 b.n 8004dea <HAL_RCC_OscConfig+0x26a>
|
|||
|
|
{
|
|||
|
|
if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
|
|||
|
|
8004dd8: f7ff f8a8 bl 8003f2c <HAL_GetTick>
|
|||
|
|
8004ddc: 0002 movs r2, r0
|
|||
|
|
8004dde: 697b ldr r3, [r7, #20]
|
|||
|
|
8004de0: 1ad3 subs r3, r2, r3
|
|||
|
|
8004de2: 2b02 cmp r3, #2
|
|||
|
|
8004de4: d901 bls.n 8004dea <HAL_RCC_OscConfig+0x26a>
|
|||
|
|
{
|
|||
|
|
return HAL_TIMEOUT;
|
|||
|
|
8004de6: 2303 movs r3, #3
|
|||
|
|
8004de8: e292 b.n 8005310 <HAL_RCC_OscConfig+0x790>
|
|||
|
|
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != 0U)
|
|||
|
|
8004dea: 4b34 ldr r3, [pc, #208] ; (8004ebc <HAL_RCC_OscConfig+0x33c>)
|
|||
|
|
8004dec: 681b ldr r3, [r3, #0]
|
|||
|
|
8004dee: 2204 movs r2, #4
|
|||
|
|
8004df0: 4013 ands r3, r2
|
|||
|
|
8004df2: d1f1 bne.n 8004dd8 <HAL_RCC_OscConfig+0x258>
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
/*----------------------------- MSI Configuration --------------------------*/
|
|||
|
|
if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_MSI) == RCC_OSCILLATORTYPE_MSI)
|
|||
|
|
8004df4: 687b ldr r3, [r7, #4]
|
|||
|
|
8004df6: 681b ldr r3, [r3, #0]
|
|||
|
|
8004df8: 2210 movs r2, #16
|
|||
|
|
8004dfa: 4013 ands r3, r2
|
|||
|
|
8004dfc: d100 bne.n 8004e00 <HAL_RCC_OscConfig+0x280>
|
|||
|
|
8004dfe: e0a1 b.n 8004f44 <HAL_RCC_OscConfig+0x3c4>
|
|||
|
|
{
|
|||
|
|
/* When the MSI is used as system clock it will not be disabled */
|
|||
|
|
if(sysclk_source == RCC_CFGR_SWS_MSI)
|
|||
|
|
8004e00: 69fb ldr r3, [r7, #28]
|
|||
|
|
8004e02: 2b00 cmp r3, #0
|
|||
|
|
8004e04: d141 bne.n 8004e8a <HAL_RCC_OscConfig+0x30a>
|
|||
|
|
{
|
|||
|
|
if((__HAL_RCC_GET_FLAG(RCC_FLAG_MSIRDY) != 0U) && (RCC_OscInitStruct->MSIState == RCC_MSI_OFF))
|
|||
|
|
8004e06: 4b2d ldr r3, [pc, #180] ; (8004ebc <HAL_RCC_OscConfig+0x33c>)
|
|||
|
|
8004e08: 681a ldr r2, [r3, #0]
|
|||
|
|
8004e0a: 2380 movs r3, #128 ; 0x80
|
|||
|
|
8004e0c: 009b lsls r3, r3, #2
|
|||
|
|
8004e0e: 4013 ands r3, r2
|
|||
|
|
8004e10: d005 beq.n 8004e1e <HAL_RCC_OscConfig+0x29e>
|
|||
|
|
8004e12: 687b ldr r3, [r7, #4]
|
|||
|
|
8004e14: 69db ldr r3, [r3, #28]
|
|||
|
|
8004e16: 2b00 cmp r3, #0
|
|||
|
|
8004e18: d101 bne.n 8004e1e <HAL_RCC_OscConfig+0x29e>
|
|||
|
|
{
|
|||
|
|
return HAL_ERROR;
|
|||
|
|
8004e1a: 2301 movs r3, #1
|
|||
|
|
8004e1c: e278 b.n 8005310 <HAL_RCC_OscConfig+0x790>
|
|||
|
|
/* Check MSICalibrationValue and MSIClockRange input parameters */
|
|||
|
|
assert_param(IS_RCC_MSICALIBRATION_VALUE(RCC_OscInitStruct->MSICalibrationValue));
|
|||
|
|
assert_param(IS_RCC_MSI_CLOCK_RANGE(RCC_OscInitStruct->MSIClockRange));
|
|||
|
|
|
|||
|
|
/* Selects the Multiple Speed oscillator (MSI) clock range .*/
|
|||
|
|
__HAL_RCC_MSI_RANGE_CONFIG(RCC_OscInitStruct->MSIClockRange);
|
|||
|
|
8004e1e: 4a27 ldr r2, [pc, #156] ; (8004ebc <HAL_RCC_OscConfig+0x33c>)
|
|||
|
|
8004e20: 4b26 ldr r3, [pc, #152] ; (8004ebc <HAL_RCC_OscConfig+0x33c>)
|
|||
|
|
8004e22: 685b ldr r3, [r3, #4]
|
|||
|
|
8004e24: 492c ldr r1, [pc, #176] ; (8004ed8 <HAL_RCC_OscConfig+0x358>)
|
|||
|
|
8004e26: 4019 ands r1, r3
|
|||
|
|
8004e28: 687b ldr r3, [r7, #4]
|
|||
|
|
8004e2a: 6a5b ldr r3, [r3, #36] ; 0x24
|
|||
|
|
8004e2c: 430b orrs r3, r1
|
|||
|
|
8004e2e: 6053 str r3, [r2, #4]
|
|||
|
|
/* Adjusts the Multiple Speed oscillator (MSI) calibration value.*/
|
|||
|
|
__HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->MSICalibrationValue);
|
|||
|
|
8004e30: 4a22 ldr r2, [pc, #136] ; (8004ebc <HAL_RCC_OscConfig+0x33c>)
|
|||
|
|
8004e32: 4b22 ldr r3, [pc, #136] ; (8004ebc <HAL_RCC_OscConfig+0x33c>)
|
|||
|
|
8004e34: 685b ldr r3, [r3, #4]
|
|||
|
|
8004e36: 021b lsls r3, r3, #8
|
|||
|
|
8004e38: 0a19 lsrs r1, r3, #8
|
|||
|
|
8004e3a: 687b ldr r3, [r7, #4]
|
|||
|
|
8004e3c: 6a1b ldr r3, [r3, #32]
|
|||
|
|
8004e3e: 061b lsls r3, r3, #24
|
|||
|
|
8004e40: 430b orrs r3, r1
|
|||
|
|
8004e42: 6053 str r3, [r2, #4]
|
|||
|
|
|
|||
|
|
|
|||
|
|
/* Update the SystemCoreClock global variable */
|
|||
|
|
SystemCoreClock = (32768U * (1UL << ((RCC_OscInitStruct->MSIClockRange >> RCC_ICSCR_MSIRANGE_Pos) + 1U)))
|
|||
|
|
8004e44: 687b ldr r3, [r7, #4]
|
|||
|
|
8004e46: 6a5b ldr r3, [r3, #36] ; 0x24
|
|||
|
|
8004e48: 0b5b lsrs r3, r3, #13
|
|||
|
|
8004e4a: 3301 adds r3, #1
|
|||
|
|
8004e4c: 2280 movs r2, #128 ; 0x80
|
|||
|
|
8004e4e: 0212 lsls r2, r2, #8
|
|||
|
|
8004e50: 409a lsls r2, r3
|
|||
|
|
>> AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos)];
|
|||
|
|
8004e52: 4b1a ldr r3, [pc, #104] ; (8004ebc <HAL_RCC_OscConfig+0x33c>)
|
|||
|
|
8004e54: 68db ldr r3, [r3, #12]
|
|||
|
|
8004e56: 091b lsrs r3, r3, #4
|
|||
|
|
8004e58: 210f movs r1, #15
|
|||
|
|
8004e5a: 400b ands r3, r1
|
|||
|
|
8004e5c: 491b ldr r1, [pc, #108] ; (8004ecc <HAL_RCC_OscConfig+0x34c>)
|
|||
|
|
8004e5e: 5ccb ldrb r3, [r1, r3]
|
|||
|
|
8004e60: 40da lsrs r2, r3
|
|||
|
|
SystemCoreClock = (32768U * (1UL << ((RCC_OscInitStruct->MSIClockRange >> RCC_ICSCR_MSIRANGE_Pos) + 1U)))
|
|||
|
|
8004e62: 4b1b ldr r3, [pc, #108] ; (8004ed0 <HAL_RCC_OscConfig+0x350>)
|
|||
|
|
8004e64: 601a str r2, [r3, #0]
|
|||
|
|
|
|||
|
|
/* Configure the source of time base considering new system clocks settings*/
|
|||
|
|
status = HAL_InitTick (uwTickPrio);
|
|||
|
|
8004e66: 4b1b ldr r3, [pc, #108] ; (8004ed4 <HAL_RCC_OscConfig+0x354>)
|
|||
|
|
8004e68: 681b ldr r3, [r3, #0]
|
|||
|
|
8004e6a: 2213 movs r2, #19
|
|||
|
|
8004e6c: 18bc adds r4, r7, r2
|
|||
|
|
8004e6e: 0018 movs r0, r3
|
|||
|
|
8004e70: f7ff f816 bl 8003ea0 <HAL_InitTick>
|
|||
|
|
8004e74: 0003 movs r3, r0
|
|||
|
|
8004e76: 7023 strb r3, [r4, #0]
|
|||
|
|
if(status != HAL_OK)
|
|||
|
|
8004e78: 2313 movs r3, #19
|
|||
|
|
8004e7a: 18fb adds r3, r7, r3
|
|||
|
|
8004e7c: 781b ldrb r3, [r3, #0]
|
|||
|
|
8004e7e: 2b00 cmp r3, #0
|
|||
|
|
8004e80: d060 beq.n 8004f44 <HAL_RCC_OscConfig+0x3c4>
|
|||
|
|
{
|
|||
|
|
return status;
|
|||
|
|
8004e82: 2313 movs r3, #19
|
|||
|
|
8004e84: 18fb adds r3, r7, r3
|
|||
|
|
8004e86: 781b ldrb r3, [r3, #0]
|
|||
|
|
8004e88: e242 b.n 8005310 <HAL_RCC_OscConfig+0x790>
|
|||
|
|
{
|
|||
|
|
/* Check MSI State */
|
|||
|
|
assert_param(IS_RCC_MSI(RCC_OscInitStruct->MSIState));
|
|||
|
|
|
|||
|
|
/* Check the MSI State */
|
|||
|
|
if(RCC_OscInitStruct->MSIState != RCC_MSI_OFF)
|
|||
|
|
8004e8a: 687b ldr r3, [r7, #4]
|
|||
|
|
8004e8c: 69db ldr r3, [r3, #28]
|
|||
|
|
8004e8e: 2b00 cmp r3, #0
|
|||
|
|
8004e90: d03e beq.n 8004f10 <HAL_RCC_OscConfig+0x390>
|
|||
|
|
{
|
|||
|
|
/* Enable the Multi Speed oscillator (MSI). */
|
|||
|
|
__HAL_RCC_MSI_ENABLE();
|
|||
|
|
8004e92: 4b0a ldr r3, [pc, #40] ; (8004ebc <HAL_RCC_OscConfig+0x33c>)
|
|||
|
|
8004e94: 4a09 ldr r2, [pc, #36] ; (8004ebc <HAL_RCC_OscConfig+0x33c>)
|
|||
|
|
8004e96: 6812 ldr r2, [r2, #0]
|
|||
|
|
8004e98: 2180 movs r1, #128 ; 0x80
|
|||
|
|
8004e9a: 0049 lsls r1, r1, #1
|
|||
|
|
8004e9c: 430a orrs r2, r1
|
|||
|
|
8004e9e: 601a str r2, [r3, #0]
|
|||
|
|
|
|||
|
|
/* Get Start Tick */
|
|||
|
|
tickstart = HAL_GetTick();
|
|||
|
|
8004ea0: f7ff f844 bl 8003f2c <HAL_GetTick>
|
|||
|
|
8004ea4: 0003 movs r3, r0
|
|||
|
|
8004ea6: 617b str r3, [r7, #20]
|
|||
|
|
|
|||
|
|
/* Wait till MSI is ready */
|
|||
|
|
while(__HAL_RCC_GET_FLAG(RCC_FLAG_MSIRDY) == 0U)
|
|||
|
|
8004ea8: e018 b.n 8004edc <HAL_RCC_OscConfig+0x35c>
|
|||
|
|
{
|
|||
|
|
if((HAL_GetTick() - tickstart) > MSI_TIMEOUT_VALUE)
|
|||
|
|
8004eaa: f7ff f83f bl 8003f2c <HAL_GetTick>
|
|||
|
|
8004eae: 0002 movs r2, r0
|
|||
|
|
8004eb0: 697b ldr r3, [r7, #20]
|
|||
|
|
8004eb2: 1ad3 subs r3, r2, r3
|
|||
|
|
8004eb4: 2b02 cmp r3, #2
|
|||
|
|
8004eb6: d911 bls.n 8004edc <HAL_RCC_OscConfig+0x35c>
|
|||
|
|
{
|
|||
|
|
return HAL_TIMEOUT;
|
|||
|
|
8004eb8: 2303 movs r3, #3
|
|||
|
|
8004eba: e229 b.n 8005310 <HAL_RCC_OscConfig+0x790>
|
|||
|
|
8004ebc: 40021000 .word 0x40021000
|
|||
|
|
8004ec0: fffeffff .word 0xfffeffff
|
|||
|
|
8004ec4: fffbffff .word 0xfffbffff
|
|||
|
|
8004ec8: ffffe0ff .word 0xffffe0ff
|
|||
|
|
8004ecc: 080071d0 .word 0x080071d0
|
|||
|
|
8004ed0: 20000000 .word 0x20000000
|
|||
|
|
8004ed4: 20000008 .word 0x20000008
|
|||
|
|
8004ed8: ffff1fff .word 0xffff1fff
|
|||
|
|
while(__HAL_RCC_GET_FLAG(RCC_FLAG_MSIRDY) == 0U)
|
|||
|
|
8004edc: 4bca ldr r3, [pc, #808] ; (8005208 <HAL_RCC_OscConfig+0x688>)
|
|||
|
|
8004ede: 681a ldr r2, [r3, #0]
|
|||
|
|
8004ee0: 2380 movs r3, #128 ; 0x80
|
|||
|
|
8004ee2: 009b lsls r3, r3, #2
|
|||
|
|
8004ee4: 4013 ands r3, r2
|
|||
|
|
8004ee6: d0e0 beq.n 8004eaa <HAL_RCC_OscConfig+0x32a>
|
|||
|
|
/* Check MSICalibrationValue and MSIClockRange input parameters */
|
|||
|
|
assert_param(IS_RCC_MSICALIBRATION_VALUE(RCC_OscInitStruct->MSICalibrationValue));
|
|||
|
|
assert_param(IS_RCC_MSI_CLOCK_RANGE(RCC_OscInitStruct->MSIClockRange));
|
|||
|
|
|
|||
|
|
/* Selects the Multiple Speed oscillator (MSI) clock range .*/
|
|||
|
|
__HAL_RCC_MSI_RANGE_CONFIG(RCC_OscInitStruct->MSIClockRange);
|
|||
|
|
8004ee8: 4ac7 ldr r2, [pc, #796] ; (8005208 <HAL_RCC_OscConfig+0x688>)
|
|||
|
|
8004eea: 4bc7 ldr r3, [pc, #796] ; (8005208 <HAL_RCC_OscConfig+0x688>)
|
|||
|
|
8004eec: 685b ldr r3, [r3, #4]
|
|||
|
|
8004eee: 49c7 ldr r1, [pc, #796] ; (800520c <HAL_RCC_OscConfig+0x68c>)
|
|||
|
|
8004ef0: 4019 ands r1, r3
|
|||
|
|
8004ef2: 687b ldr r3, [r7, #4]
|
|||
|
|
8004ef4: 6a5b ldr r3, [r3, #36] ; 0x24
|
|||
|
|
8004ef6: 430b orrs r3, r1
|
|||
|
|
8004ef8: 6053 str r3, [r2, #4]
|
|||
|
|
/* Adjusts the Multiple Speed oscillator (MSI) calibration value.*/
|
|||
|
|
__HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->MSICalibrationValue);
|
|||
|
|
8004efa: 4ac3 ldr r2, [pc, #780] ; (8005208 <HAL_RCC_OscConfig+0x688>)
|
|||
|
|
8004efc: 4bc2 ldr r3, [pc, #776] ; (8005208 <HAL_RCC_OscConfig+0x688>)
|
|||
|
|
8004efe: 685b ldr r3, [r3, #4]
|
|||
|
|
8004f00: 021b lsls r3, r3, #8
|
|||
|
|
8004f02: 0a19 lsrs r1, r3, #8
|
|||
|
|
8004f04: 687b ldr r3, [r7, #4]
|
|||
|
|
8004f06: 6a1b ldr r3, [r3, #32]
|
|||
|
|
8004f08: 061b lsls r3, r3, #24
|
|||
|
|
8004f0a: 430b orrs r3, r1
|
|||
|
|
8004f0c: 6053 str r3, [r2, #4]
|
|||
|
|
8004f0e: e019 b.n 8004f44 <HAL_RCC_OscConfig+0x3c4>
|
|||
|
|
}
|
|||
|
|
else
|
|||
|
|
{
|
|||
|
|
/* Disable the Multi Speed oscillator (MSI). */
|
|||
|
|
__HAL_RCC_MSI_DISABLE();
|
|||
|
|
8004f10: 4bbd ldr r3, [pc, #756] ; (8005208 <HAL_RCC_OscConfig+0x688>)
|
|||
|
|
8004f12: 4abd ldr r2, [pc, #756] ; (8005208 <HAL_RCC_OscConfig+0x688>)
|
|||
|
|
8004f14: 6812 ldr r2, [r2, #0]
|
|||
|
|
8004f16: 49be ldr r1, [pc, #760] ; (8005210 <HAL_RCC_OscConfig+0x690>)
|
|||
|
|
8004f18: 400a ands r2, r1
|
|||
|
|
8004f1a: 601a str r2, [r3, #0]
|
|||
|
|
|
|||
|
|
/* Get Start Tick */
|
|||
|
|
tickstart = HAL_GetTick();
|
|||
|
|
8004f1c: f7ff f806 bl 8003f2c <HAL_GetTick>
|
|||
|
|
8004f20: 0003 movs r3, r0
|
|||
|
|
8004f22: 617b str r3, [r7, #20]
|
|||
|
|
|
|||
|
|
/* Wait till MSI is ready */
|
|||
|
|
while(__HAL_RCC_GET_FLAG(RCC_FLAG_MSIRDY) != 0U)
|
|||
|
|
8004f24: e008 b.n 8004f38 <HAL_RCC_OscConfig+0x3b8>
|
|||
|
|
{
|
|||
|
|
if((HAL_GetTick() - tickstart) > MSI_TIMEOUT_VALUE)
|
|||
|
|
8004f26: f7ff f801 bl 8003f2c <HAL_GetTick>
|
|||
|
|
8004f2a: 0002 movs r2, r0
|
|||
|
|
8004f2c: 697b ldr r3, [r7, #20]
|
|||
|
|
8004f2e: 1ad3 subs r3, r2, r3
|
|||
|
|
8004f30: 2b02 cmp r3, #2
|
|||
|
|
8004f32: d901 bls.n 8004f38 <HAL_RCC_OscConfig+0x3b8>
|
|||
|
|
{
|
|||
|
|
return HAL_TIMEOUT;
|
|||
|
|
8004f34: 2303 movs r3, #3
|
|||
|
|
8004f36: e1eb b.n 8005310 <HAL_RCC_OscConfig+0x790>
|
|||
|
|
while(__HAL_RCC_GET_FLAG(RCC_FLAG_MSIRDY) != 0U)
|
|||
|
|
8004f38: 4bb3 ldr r3, [pc, #716] ; (8005208 <HAL_RCC_OscConfig+0x688>)
|
|||
|
|
8004f3a: 681a ldr r2, [r3, #0]
|
|||
|
|
8004f3c: 2380 movs r3, #128 ; 0x80
|
|||
|
|
8004f3e: 009b lsls r3, r3, #2
|
|||
|
|
8004f40: 4013 ands r3, r2
|
|||
|
|
8004f42: d1f0 bne.n 8004f26 <HAL_RCC_OscConfig+0x3a6>
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
/*------------------------------ LSI Configuration -------------------------*/
|
|||
|
|
if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)
|
|||
|
|
8004f44: 687b ldr r3, [r7, #4]
|
|||
|
|
8004f46: 681b ldr r3, [r3, #0]
|
|||
|
|
8004f48: 2208 movs r2, #8
|
|||
|
|
8004f4a: 4013 ands r3, r2
|
|||
|
|
8004f4c: d036 beq.n 8004fbc <HAL_RCC_OscConfig+0x43c>
|
|||
|
|
{
|
|||
|
|
/* Check the parameters */
|
|||
|
|
assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState));
|
|||
|
|
|
|||
|
|
/* Check the LSI State */
|
|||
|
|
if(RCC_OscInitStruct->LSIState != RCC_LSI_OFF)
|
|||
|
|
8004f4e: 687b ldr r3, [r7, #4]
|
|||
|
|
8004f50: 695b ldr r3, [r3, #20]
|
|||
|
|
8004f52: 2b00 cmp r3, #0
|
|||
|
|
8004f54: d019 beq.n 8004f8a <HAL_RCC_OscConfig+0x40a>
|
|||
|
|
{
|
|||
|
|
/* Enable the Internal Low Speed oscillator (LSI). */
|
|||
|
|
__HAL_RCC_LSI_ENABLE();
|
|||
|
|
8004f56: 4bac ldr r3, [pc, #688] ; (8005208 <HAL_RCC_OscConfig+0x688>)
|
|||
|
|
8004f58: 4aab ldr r2, [pc, #684] ; (8005208 <HAL_RCC_OscConfig+0x688>)
|
|||
|
|
8004f5a: 6d12 ldr r2, [r2, #80] ; 0x50
|
|||
|
|
8004f5c: 2101 movs r1, #1
|
|||
|
|
8004f5e: 430a orrs r2, r1
|
|||
|
|
8004f60: 651a str r2, [r3, #80] ; 0x50
|
|||
|
|
|
|||
|
|
/* Get Start Tick */
|
|||
|
|
tickstart = HAL_GetTick();
|
|||
|
|
8004f62: f7fe ffe3 bl 8003f2c <HAL_GetTick>
|
|||
|
|
8004f66: 0003 movs r3, r0
|
|||
|
|
8004f68: 617b str r3, [r7, #20]
|
|||
|
|
|
|||
|
|
/* Wait till LSI is ready */
|
|||
|
|
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == 0U)
|
|||
|
|
8004f6a: e008 b.n 8004f7e <HAL_RCC_OscConfig+0x3fe>
|
|||
|
|
{
|
|||
|
|
if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
|
|||
|
|
8004f6c: f7fe ffde bl 8003f2c <HAL_GetTick>
|
|||
|
|
8004f70: 0002 movs r2, r0
|
|||
|
|
8004f72: 697b ldr r3, [r7, #20]
|
|||
|
|
8004f74: 1ad3 subs r3, r2, r3
|
|||
|
|
8004f76: 2b02 cmp r3, #2
|
|||
|
|
8004f78: d901 bls.n 8004f7e <HAL_RCC_OscConfig+0x3fe>
|
|||
|
|
{
|
|||
|
|
return HAL_TIMEOUT;
|
|||
|
|
8004f7a: 2303 movs r3, #3
|
|||
|
|
8004f7c: e1c8 b.n 8005310 <HAL_RCC_OscConfig+0x790>
|
|||
|
|
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == 0U)
|
|||
|
|
8004f7e: 4ba2 ldr r3, [pc, #648] ; (8005208 <HAL_RCC_OscConfig+0x688>)
|
|||
|
|
8004f80: 6d1b ldr r3, [r3, #80] ; 0x50
|
|||
|
|
8004f82: 2202 movs r2, #2
|
|||
|
|
8004f84: 4013 ands r3, r2
|
|||
|
|
8004f86: d0f1 beq.n 8004f6c <HAL_RCC_OscConfig+0x3ec>
|
|||
|
|
8004f88: e018 b.n 8004fbc <HAL_RCC_OscConfig+0x43c>
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
else
|
|||
|
|
{
|
|||
|
|
/* Disable the Internal Low Speed oscillator (LSI). */
|
|||
|
|
__HAL_RCC_LSI_DISABLE();
|
|||
|
|
8004f8a: 4b9f ldr r3, [pc, #636] ; (8005208 <HAL_RCC_OscConfig+0x688>)
|
|||
|
|
8004f8c: 4a9e ldr r2, [pc, #632] ; (8005208 <HAL_RCC_OscConfig+0x688>)
|
|||
|
|
8004f8e: 6d12 ldr r2, [r2, #80] ; 0x50
|
|||
|
|
8004f90: 2101 movs r1, #1
|
|||
|
|
8004f92: 438a bics r2, r1
|
|||
|
|
8004f94: 651a str r2, [r3, #80] ; 0x50
|
|||
|
|
|
|||
|
|
/* Get Start Tick */
|
|||
|
|
tickstart = HAL_GetTick();
|
|||
|
|
8004f96: f7fe ffc9 bl 8003f2c <HAL_GetTick>
|
|||
|
|
8004f9a: 0003 movs r3, r0
|
|||
|
|
8004f9c: 617b str r3, [r7, #20]
|
|||
|
|
|
|||
|
|
/* Wait till LSI is disabled */
|
|||
|
|
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != 0U)
|
|||
|
|
8004f9e: e008 b.n 8004fb2 <HAL_RCC_OscConfig+0x432>
|
|||
|
|
{
|
|||
|
|
if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
|
|||
|
|
8004fa0: f7fe ffc4 bl 8003f2c <HAL_GetTick>
|
|||
|
|
8004fa4: 0002 movs r2, r0
|
|||
|
|
8004fa6: 697b ldr r3, [r7, #20]
|
|||
|
|
8004fa8: 1ad3 subs r3, r2, r3
|
|||
|
|
8004faa: 2b02 cmp r3, #2
|
|||
|
|
8004fac: d901 bls.n 8004fb2 <HAL_RCC_OscConfig+0x432>
|
|||
|
|
{
|
|||
|
|
return HAL_TIMEOUT;
|
|||
|
|
8004fae: 2303 movs r3, #3
|
|||
|
|
8004fb0: e1ae b.n 8005310 <HAL_RCC_OscConfig+0x790>
|
|||
|
|
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != 0U)
|
|||
|
|
8004fb2: 4b95 ldr r3, [pc, #596] ; (8005208 <HAL_RCC_OscConfig+0x688>)
|
|||
|
|
8004fb4: 6d1b ldr r3, [r3, #80] ; 0x50
|
|||
|
|
8004fb6: 2202 movs r2, #2
|
|||
|
|
8004fb8: 4013 ands r3, r2
|
|||
|
|
8004fba: d1f1 bne.n 8004fa0 <HAL_RCC_OscConfig+0x420>
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
/*------------------------------ LSE Configuration -------------------------*/
|
|||
|
|
if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)
|
|||
|
|
8004fbc: 687b ldr r3, [r7, #4]
|
|||
|
|
8004fbe: 681b ldr r3, [r3, #0]
|
|||
|
|
8004fc0: 2204 movs r2, #4
|
|||
|
|
8004fc2: 4013 ands r3, r2
|
|||
|
|
8004fc4: d100 bne.n 8004fc8 <HAL_RCC_OscConfig+0x448>
|
|||
|
|
8004fc6: e0af b.n 8005128 <HAL_RCC_OscConfig+0x5a8>
|
|||
|
|
{
|
|||
|
|
FlagStatus pwrclkchanged = RESET;
|
|||
|
|
8004fc8: 2323 movs r3, #35 ; 0x23
|
|||
|
|
8004fca: 18fb adds r3, r7, r3
|
|||
|
|
8004fcc: 2200 movs r2, #0
|
|||
|
|
8004fce: 701a strb r2, [r3, #0]
|
|||
|
|
/* Check the parameters */
|
|||
|
|
assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState));
|
|||
|
|
|
|||
|
|
/* Update LSE configuration in Backup Domain control register */
|
|||
|
|
/* Requires to enable write access to Backup Domain of necessary */
|
|||
|
|
if(__HAL_RCC_PWR_IS_CLK_DISABLED())
|
|||
|
|
8004fd0: 4b8d ldr r3, [pc, #564] ; (8005208 <HAL_RCC_OscConfig+0x688>)
|
|||
|
|
8004fd2: 6b9a ldr r2, [r3, #56] ; 0x38
|
|||
|
|
8004fd4: 2380 movs r3, #128 ; 0x80
|
|||
|
|
8004fd6: 055b lsls r3, r3, #21
|
|||
|
|
8004fd8: 4013 ands r3, r2
|
|||
|
|
8004fda: d10a bne.n 8004ff2 <HAL_RCC_OscConfig+0x472>
|
|||
|
|
{
|
|||
|
|
__HAL_RCC_PWR_CLK_ENABLE();
|
|||
|
|
8004fdc: 4b8a ldr r3, [pc, #552] ; (8005208 <HAL_RCC_OscConfig+0x688>)
|
|||
|
|
8004fde: 4a8a ldr r2, [pc, #552] ; (8005208 <HAL_RCC_OscConfig+0x688>)
|
|||
|
|
8004fe0: 6b92 ldr r2, [r2, #56] ; 0x38
|
|||
|
|
8004fe2: 2180 movs r1, #128 ; 0x80
|
|||
|
|
8004fe4: 0549 lsls r1, r1, #21
|
|||
|
|
8004fe6: 430a orrs r2, r1
|
|||
|
|
8004fe8: 639a str r2, [r3, #56] ; 0x38
|
|||
|
|
pwrclkchanged = SET;
|
|||
|
|
8004fea: 2323 movs r3, #35 ; 0x23
|
|||
|
|
8004fec: 18fb adds r3, r7, r3
|
|||
|
|
8004fee: 2201 movs r2, #1
|
|||
|
|
8004ff0: 701a strb r2, [r3, #0]
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
if(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
|
|||
|
|
8004ff2: 4b88 ldr r3, [pc, #544] ; (8005214 <HAL_RCC_OscConfig+0x694>)
|
|||
|
|
8004ff4: 681a ldr r2, [r3, #0]
|
|||
|
|
8004ff6: 2380 movs r3, #128 ; 0x80
|
|||
|
|
8004ff8: 005b lsls r3, r3, #1
|
|||
|
|
8004ffa: 4013 ands r3, r2
|
|||
|
|
8004ffc: d11a bne.n 8005034 <HAL_RCC_OscConfig+0x4b4>
|
|||
|
|
{
|
|||
|
|
/* Enable write access to Backup domain */
|
|||
|
|
SET_BIT(PWR->CR, PWR_CR_DBP);
|
|||
|
|
8004ffe: 4b85 ldr r3, [pc, #532] ; (8005214 <HAL_RCC_OscConfig+0x694>)
|
|||
|
|
8005000: 4a84 ldr r2, [pc, #528] ; (8005214 <HAL_RCC_OscConfig+0x694>)
|
|||
|
|
8005002: 6812 ldr r2, [r2, #0]
|
|||
|
|
8005004: 2180 movs r1, #128 ; 0x80
|
|||
|
|
8005006: 0049 lsls r1, r1, #1
|
|||
|
|
8005008: 430a orrs r2, r1
|
|||
|
|
800500a: 601a str r2, [r3, #0]
|
|||
|
|
|
|||
|
|
/* Wait for Backup domain Write protection disable */
|
|||
|
|
tickstart = HAL_GetTick();
|
|||
|
|
800500c: f7fe ff8e bl 8003f2c <HAL_GetTick>
|
|||
|
|
8005010: 0003 movs r3, r0
|
|||
|
|
8005012: 617b str r3, [r7, #20]
|
|||
|
|
|
|||
|
|
while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
|
|||
|
|
8005014: e008 b.n 8005028 <HAL_RCC_OscConfig+0x4a8>
|
|||
|
|
{
|
|||
|
|
if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
|
|||
|
|
8005016: f7fe ff89 bl 8003f2c <HAL_GetTick>
|
|||
|
|
800501a: 0002 movs r2, r0
|
|||
|
|
800501c: 697b ldr r3, [r7, #20]
|
|||
|
|
800501e: 1ad3 subs r3, r2, r3
|
|||
|
|
8005020: 2b64 cmp r3, #100 ; 0x64
|
|||
|
|
8005022: d901 bls.n 8005028 <HAL_RCC_OscConfig+0x4a8>
|
|||
|
|
{
|
|||
|
|
return HAL_TIMEOUT;
|
|||
|
|
8005024: 2303 movs r3, #3
|
|||
|
|
8005026: e173 b.n 8005310 <HAL_RCC_OscConfig+0x790>
|
|||
|
|
while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
|
|||
|
|
8005028: 4b7a ldr r3, [pc, #488] ; (8005214 <HAL_RCC_OscConfig+0x694>)
|
|||
|
|
800502a: 681a ldr r2, [r3, #0]
|
|||
|
|
800502c: 2380 movs r3, #128 ; 0x80
|
|||
|
|
800502e: 005b lsls r3, r3, #1
|
|||
|
|
8005030: 4013 ands r3, r2
|
|||
|
|
8005032: d0f0 beq.n 8005016 <HAL_RCC_OscConfig+0x496>
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
/* Set the new LSE configuration -----------------------------------------*/
|
|||
|
|
__HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
|
|||
|
|
8005034: 687b ldr r3, [r7, #4]
|
|||
|
|
8005036: 689a ldr r2, [r3, #8]
|
|||
|
|
8005038: 2380 movs r3, #128 ; 0x80
|
|||
|
|
800503a: 005b lsls r3, r3, #1
|
|||
|
|
800503c: 429a cmp r2, r3
|
|||
|
|
800503e: d107 bne.n 8005050 <HAL_RCC_OscConfig+0x4d0>
|
|||
|
|
8005040: 4b71 ldr r3, [pc, #452] ; (8005208 <HAL_RCC_OscConfig+0x688>)
|
|||
|
|
8005042: 4a71 ldr r2, [pc, #452] ; (8005208 <HAL_RCC_OscConfig+0x688>)
|
|||
|
|
8005044: 6d12 ldr r2, [r2, #80] ; 0x50
|
|||
|
|
8005046: 2180 movs r1, #128 ; 0x80
|
|||
|
|
8005048: 0049 lsls r1, r1, #1
|
|||
|
|
800504a: 430a orrs r2, r1
|
|||
|
|
800504c: 651a str r2, [r3, #80] ; 0x50
|
|||
|
|
800504e: e031 b.n 80050b4 <HAL_RCC_OscConfig+0x534>
|
|||
|
|
8005050: 687b ldr r3, [r7, #4]
|
|||
|
|
8005052: 689b ldr r3, [r3, #8]
|
|||
|
|
8005054: 2b00 cmp r3, #0
|
|||
|
|
8005056: d10c bne.n 8005072 <HAL_RCC_OscConfig+0x4f2>
|
|||
|
|
8005058: 4b6b ldr r3, [pc, #428] ; (8005208 <HAL_RCC_OscConfig+0x688>)
|
|||
|
|
800505a: 4a6b ldr r2, [pc, #428] ; (8005208 <HAL_RCC_OscConfig+0x688>)
|
|||
|
|
800505c: 6d12 ldr r2, [r2, #80] ; 0x50
|
|||
|
|
800505e: 496c ldr r1, [pc, #432] ; (8005210 <HAL_RCC_OscConfig+0x690>)
|
|||
|
|
8005060: 400a ands r2, r1
|
|||
|
|
8005062: 651a str r2, [r3, #80] ; 0x50
|
|||
|
|
8005064: 4b68 ldr r3, [pc, #416] ; (8005208 <HAL_RCC_OscConfig+0x688>)
|
|||
|
|
8005066: 4a68 ldr r2, [pc, #416] ; (8005208 <HAL_RCC_OscConfig+0x688>)
|
|||
|
|
8005068: 6d12 ldr r2, [r2, #80] ; 0x50
|
|||
|
|
800506a: 496b ldr r1, [pc, #428] ; (8005218 <HAL_RCC_OscConfig+0x698>)
|
|||
|
|
800506c: 400a ands r2, r1
|
|||
|
|
800506e: 651a str r2, [r3, #80] ; 0x50
|
|||
|
|
8005070: e020 b.n 80050b4 <HAL_RCC_OscConfig+0x534>
|
|||
|
|
8005072: 687b ldr r3, [r7, #4]
|
|||
|
|
8005074: 689a ldr r2, [r3, #8]
|
|||
|
|
8005076: 23a0 movs r3, #160 ; 0xa0
|
|||
|
|
8005078: 00db lsls r3, r3, #3
|
|||
|
|
800507a: 429a cmp r2, r3
|
|||
|
|
800507c: d10e bne.n 800509c <HAL_RCC_OscConfig+0x51c>
|
|||
|
|
800507e: 4b62 ldr r3, [pc, #392] ; (8005208 <HAL_RCC_OscConfig+0x688>)
|
|||
|
|
8005080: 4a61 ldr r2, [pc, #388] ; (8005208 <HAL_RCC_OscConfig+0x688>)
|
|||
|
|
8005082: 6d12 ldr r2, [r2, #80] ; 0x50
|
|||
|
|
8005084: 2180 movs r1, #128 ; 0x80
|
|||
|
|
8005086: 00c9 lsls r1, r1, #3
|
|||
|
|
8005088: 430a orrs r2, r1
|
|||
|
|
800508a: 651a str r2, [r3, #80] ; 0x50
|
|||
|
|
800508c: 4b5e ldr r3, [pc, #376] ; (8005208 <HAL_RCC_OscConfig+0x688>)
|
|||
|
|
800508e: 4a5e ldr r2, [pc, #376] ; (8005208 <HAL_RCC_OscConfig+0x688>)
|
|||
|
|
8005090: 6d12 ldr r2, [r2, #80] ; 0x50
|
|||
|
|
8005092: 2180 movs r1, #128 ; 0x80
|
|||
|
|
8005094: 0049 lsls r1, r1, #1
|
|||
|
|
8005096: 430a orrs r2, r1
|
|||
|
|
8005098: 651a str r2, [r3, #80] ; 0x50
|
|||
|
|
800509a: e00b b.n 80050b4 <HAL_RCC_OscConfig+0x534>
|
|||
|
|
800509c: 4b5a ldr r3, [pc, #360] ; (8005208 <HAL_RCC_OscConfig+0x688>)
|
|||
|
|
800509e: 4a5a ldr r2, [pc, #360] ; (8005208 <HAL_RCC_OscConfig+0x688>)
|
|||
|
|
80050a0: 6d12 ldr r2, [r2, #80] ; 0x50
|
|||
|
|
80050a2: 495b ldr r1, [pc, #364] ; (8005210 <HAL_RCC_OscConfig+0x690>)
|
|||
|
|
80050a4: 400a ands r2, r1
|
|||
|
|
80050a6: 651a str r2, [r3, #80] ; 0x50
|
|||
|
|
80050a8: 4b57 ldr r3, [pc, #348] ; (8005208 <HAL_RCC_OscConfig+0x688>)
|
|||
|
|
80050aa: 4a57 ldr r2, [pc, #348] ; (8005208 <HAL_RCC_OscConfig+0x688>)
|
|||
|
|
80050ac: 6d12 ldr r2, [r2, #80] ; 0x50
|
|||
|
|
80050ae: 495a ldr r1, [pc, #360] ; (8005218 <HAL_RCC_OscConfig+0x698>)
|
|||
|
|
80050b0: 400a ands r2, r1
|
|||
|
|
80050b2: 651a str r2, [r3, #80] ; 0x50
|
|||
|
|
|
|||
|
|
/* Check the LSE State */
|
|||
|
|
if(RCC_OscInitStruct->LSEState != RCC_LSE_OFF)
|
|||
|
|
80050b4: 687b ldr r3, [r7, #4]
|
|||
|
|
80050b6: 689b ldr r3, [r3, #8]
|
|||
|
|
80050b8: 2b00 cmp r3, #0
|
|||
|
|
80050ba: d015 beq.n 80050e8 <HAL_RCC_OscConfig+0x568>
|
|||
|
|
{
|
|||
|
|
/* Get Start Tick */
|
|||
|
|
tickstart = HAL_GetTick();
|
|||
|
|
80050bc: f7fe ff36 bl 8003f2c <HAL_GetTick>
|
|||
|
|
80050c0: 0003 movs r3, r0
|
|||
|
|
80050c2: 617b str r3, [r7, #20]
|
|||
|
|
|
|||
|
|
/* Wait till LSE is ready */
|
|||
|
|
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == 0U)
|
|||
|
|
80050c4: e009 b.n 80050da <HAL_RCC_OscConfig+0x55a>
|
|||
|
|
{
|
|||
|
|
if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
|
|||
|
|
80050c6: f7fe ff31 bl 8003f2c <HAL_GetTick>
|
|||
|
|
80050ca: 0002 movs r2, r0
|
|||
|
|
80050cc: 697b ldr r3, [r7, #20]
|
|||
|
|
80050ce: 1ad3 subs r3, r2, r3
|
|||
|
|
80050d0: 4a52 ldr r2, [pc, #328] ; (800521c <HAL_RCC_OscConfig+0x69c>)
|
|||
|
|
80050d2: 4293 cmp r3, r2
|
|||
|
|
80050d4: d901 bls.n 80050da <HAL_RCC_OscConfig+0x55a>
|
|||
|
|
{
|
|||
|
|
return HAL_TIMEOUT;
|
|||
|
|
80050d6: 2303 movs r3, #3
|
|||
|
|
80050d8: e11a b.n 8005310 <HAL_RCC_OscConfig+0x790>
|
|||
|
|
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == 0U)
|
|||
|
|
80050da: 4b4b ldr r3, [pc, #300] ; (8005208 <HAL_RCC_OscConfig+0x688>)
|
|||
|
|
80050dc: 6d1a ldr r2, [r3, #80] ; 0x50
|
|||
|
|
80050de: 2380 movs r3, #128 ; 0x80
|
|||
|
|
80050e0: 009b lsls r3, r3, #2
|
|||
|
|
80050e2: 4013 ands r3, r2
|
|||
|
|
80050e4: d0ef beq.n 80050c6 <HAL_RCC_OscConfig+0x546>
|
|||
|
|
80050e6: e014 b.n 8005112 <HAL_RCC_OscConfig+0x592>
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
else
|
|||
|
|
{
|
|||
|
|
/* Get Start Tick */
|
|||
|
|
tickstart = HAL_GetTick();
|
|||
|
|
80050e8: f7fe ff20 bl 8003f2c <HAL_GetTick>
|
|||
|
|
80050ec: 0003 movs r3, r0
|
|||
|
|
80050ee: 617b str r3, [r7, #20]
|
|||
|
|
|
|||
|
|
/* Wait till LSE is disabled */
|
|||
|
|
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != 0U)
|
|||
|
|
80050f0: e009 b.n 8005106 <HAL_RCC_OscConfig+0x586>
|
|||
|
|
{
|
|||
|
|
if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
|
|||
|
|
80050f2: f7fe ff1b bl 8003f2c <HAL_GetTick>
|
|||
|
|
80050f6: 0002 movs r2, r0
|
|||
|
|
80050f8: 697b ldr r3, [r7, #20]
|
|||
|
|
80050fa: 1ad3 subs r3, r2, r3
|
|||
|
|
80050fc: 4a47 ldr r2, [pc, #284] ; (800521c <HAL_RCC_OscConfig+0x69c>)
|
|||
|
|
80050fe: 4293 cmp r3, r2
|
|||
|
|
8005100: d901 bls.n 8005106 <HAL_RCC_OscConfig+0x586>
|
|||
|
|
{
|
|||
|
|
return HAL_TIMEOUT;
|
|||
|
|
8005102: 2303 movs r3, #3
|
|||
|
|
8005104: e104 b.n 8005310 <HAL_RCC_OscConfig+0x790>
|
|||
|
|
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != 0U)
|
|||
|
|
8005106: 4b40 ldr r3, [pc, #256] ; (8005208 <HAL_RCC_OscConfig+0x688>)
|
|||
|
|
8005108: 6d1a ldr r2, [r3, #80] ; 0x50
|
|||
|
|
800510a: 2380 movs r3, #128 ; 0x80
|
|||
|
|
800510c: 009b lsls r3, r3, #2
|
|||
|
|
800510e: 4013 ands r3, r2
|
|||
|
|
8005110: d1ef bne.n 80050f2 <HAL_RCC_OscConfig+0x572>
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
/* Require to disable power clock if necessary */
|
|||
|
|
if(pwrclkchanged == SET)
|
|||
|
|
8005112: 2323 movs r3, #35 ; 0x23
|
|||
|
|
8005114: 18fb adds r3, r7, r3
|
|||
|
|
8005116: 781b ldrb r3, [r3, #0]
|
|||
|
|
8005118: 2b01 cmp r3, #1
|
|||
|
|
800511a: d105 bne.n 8005128 <HAL_RCC_OscConfig+0x5a8>
|
|||
|
|
{
|
|||
|
|
__HAL_RCC_PWR_CLK_DISABLE();
|
|||
|
|
800511c: 4b3a ldr r3, [pc, #232] ; (8005208 <HAL_RCC_OscConfig+0x688>)
|
|||
|
|
800511e: 4a3a ldr r2, [pc, #232] ; (8005208 <HAL_RCC_OscConfig+0x688>)
|
|||
|
|
8005120: 6b92 ldr r2, [r2, #56] ; 0x38
|
|||
|
|
8005122: 493f ldr r1, [pc, #252] ; (8005220 <HAL_RCC_OscConfig+0x6a0>)
|
|||
|
|
8005124: 400a ands r2, r1
|
|||
|
|
8005126: 639a str r2, [r3, #56] ; 0x38
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
#if defined(RCC_HSI48_SUPPORT)
|
|||
|
|
/*----------------------------- HSI48 Configuration --------------------------*/
|
|||
|
|
if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI48) == RCC_OSCILLATORTYPE_HSI48)
|
|||
|
|
8005128: 687b ldr r3, [r7, #4]
|
|||
|
|
800512a: 681b ldr r3, [r3, #0]
|
|||
|
|
800512c: 2220 movs r2, #32
|
|||
|
|
800512e: 4013 ands r3, r2
|
|||
|
|
8005130: d049 beq.n 80051c6 <HAL_RCC_OscConfig+0x646>
|
|||
|
|
{
|
|||
|
|
/* Check the parameters */
|
|||
|
|
assert_param(IS_RCC_HSI48(RCC_OscInitStruct->HSI48State));
|
|||
|
|
|
|||
|
|
/* Check the HSI48 State */
|
|||
|
|
if(RCC_OscInitStruct->HSI48State != RCC_HSI48_OFF)
|
|||
|
|
8005132: 687b ldr r3, [r7, #4]
|
|||
|
|
8005134: 699b ldr r3, [r3, #24]
|
|||
|
|
8005136: 2b00 cmp r3, #0
|
|||
|
|
8005138: d026 beq.n 8005188 <HAL_RCC_OscConfig+0x608>
|
|||
|
|
{
|
|||
|
|
/* Enable the Internal High Speed oscillator (HSI48). */
|
|||
|
|
__HAL_RCC_HSI48_ENABLE();
|
|||
|
|
800513a: 4b33 ldr r3, [pc, #204] ; (8005208 <HAL_RCC_OscConfig+0x688>)
|
|||
|
|
800513c: 4a32 ldr r2, [pc, #200] ; (8005208 <HAL_RCC_OscConfig+0x688>)
|
|||
|
|
800513e: 6892 ldr r2, [r2, #8]
|
|||
|
|
8005140: 2101 movs r1, #1
|
|||
|
|
8005142: 430a orrs r2, r1
|
|||
|
|
8005144: 609a str r2, [r3, #8]
|
|||
|
|
8005146: 4b30 ldr r3, [pc, #192] ; (8005208 <HAL_RCC_OscConfig+0x688>)
|
|||
|
|
8005148: 4a2f ldr r2, [pc, #188] ; (8005208 <HAL_RCC_OscConfig+0x688>)
|
|||
|
|
800514a: 6b52 ldr r2, [r2, #52] ; 0x34
|
|||
|
|
800514c: 2101 movs r1, #1
|
|||
|
|
800514e: 430a orrs r2, r1
|
|||
|
|
8005150: 635a str r2, [r3, #52] ; 0x34
|
|||
|
|
8005152: 4b34 ldr r3, [pc, #208] ; (8005224 <HAL_RCC_OscConfig+0x6a4>)
|
|||
|
|
8005154: 4a33 ldr r2, [pc, #204] ; (8005224 <HAL_RCC_OscConfig+0x6a4>)
|
|||
|
|
8005156: 6a12 ldr r2, [r2, #32]
|
|||
|
|
8005158: 2180 movs r1, #128 ; 0x80
|
|||
|
|
800515a: 0189 lsls r1, r1, #6
|
|||
|
|
800515c: 430a orrs r2, r1
|
|||
|
|
800515e: 621a str r2, [r3, #32]
|
|||
|
|
|
|||
|
|
/* Get Start Tick */
|
|||
|
|
tickstart = HAL_GetTick();
|
|||
|
|
8005160: f7fe fee4 bl 8003f2c <HAL_GetTick>
|
|||
|
|
8005164: 0003 movs r3, r0
|
|||
|
|
8005166: 617b str r3, [r7, #20]
|
|||
|
|
|
|||
|
|
/* Wait till HSI48 is ready */
|
|||
|
|
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSI48RDY) == 0U)
|
|||
|
|
8005168: e008 b.n 800517c <HAL_RCC_OscConfig+0x5fc>
|
|||
|
|
{
|
|||
|
|
if((HAL_GetTick() - tickstart) > HSI48_TIMEOUT_VALUE)
|
|||
|
|
800516a: f7fe fedf bl 8003f2c <HAL_GetTick>
|
|||
|
|
800516e: 0002 movs r2, r0
|
|||
|
|
8005170: 697b ldr r3, [r7, #20]
|
|||
|
|
8005172: 1ad3 subs r3, r2, r3
|
|||
|
|
8005174: 2b02 cmp r3, #2
|
|||
|
|
8005176: d901 bls.n 800517c <HAL_RCC_OscConfig+0x5fc>
|
|||
|
|
{
|
|||
|
|
return HAL_TIMEOUT;
|
|||
|
|
8005178: 2303 movs r3, #3
|
|||
|
|
800517a: e0c9 b.n 8005310 <HAL_RCC_OscConfig+0x790>
|
|||
|
|
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSI48RDY) == 0U)
|
|||
|
|
800517c: 4b22 ldr r3, [pc, #136] ; (8005208 <HAL_RCC_OscConfig+0x688>)
|
|||
|
|
800517e: 689b ldr r3, [r3, #8]
|
|||
|
|
8005180: 2202 movs r2, #2
|
|||
|
|
8005182: 4013 ands r3, r2
|
|||
|
|
8005184: d0f1 beq.n 800516a <HAL_RCC_OscConfig+0x5ea>
|
|||
|
|
8005186: e01e b.n 80051c6 <HAL_RCC_OscConfig+0x646>
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
else
|
|||
|
|
{
|
|||
|
|
/* Disable the Internal High Speed oscillator (HSI48). */
|
|||
|
|
__HAL_RCC_HSI48_DISABLE();
|
|||
|
|
8005188: 4b1f ldr r3, [pc, #124] ; (8005208 <HAL_RCC_OscConfig+0x688>)
|
|||
|
|
800518a: 4a1f ldr r2, [pc, #124] ; (8005208 <HAL_RCC_OscConfig+0x688>)
|
|||
|
|
800518c: 6892 ldr r2, [r2, #8]
|
|||
|
|
800518e: 2101 movs r1, #1
|
|||
|
|
8005190: 438a bics r2, r1
|
|||
|
|
8005192: 609a str r2, [r3, #8]
|
|||
|
|
8005194: 4b23 ldr r3, [pc, #140] ; (8005224 <HAL_RCC_OscConfig+0x6a4>)
|
|||
|
|
8005196: 4a23 ldr r2, [pc, #140] ; (8005224 <HAL_RCC_OscConfig+0x6a4>)
|
|||
|
|
8005198: 6a12 ldr r2, [r2, #32]
|
|||
|
|
800519a: 4923 ldr r1, [pc, #140] ; (8005228 <HAL_RCC_OscConfig+0x6a8>)
|
|||
|
|
800519c: 400a ands r2, r1
|
|||
|
|
800519e: 621a str r2, [r3, #32]
|
|||
|
|
|
|||
|
|
/* Get Start Tick */
|
|||
|
|
tickstart = HAL_GetTick();
|
|||
|
|
80051a0: f7fe fec4 bl 8003f2c <HAL_GetTick>
|
|||
|
|
80051a4: 0003 movs r3, r0
|
|||
|
|
80051a6: 617b str r3, [r7, #20]
|
|||
|
|
|
|||
|
|
/* Wait till HSI48 is ready */
|
|||
|
|
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSI48RDY) != 0U)
|
|||
|
|
80051a8: e008 b.n 80051bc <HAL_RCC_OscConfig+0x63c>
|
|||
|
|
{
|
|||
|
|
if((HAL_GetTick() - tickstart) > HSI48_TIMEOUT_VALUE)
|
|||
|
|
80051aa: f7fe febf bl 8003f2c <HAL_GetTick>
|
|||
|
|
80051ae: 0002 movs r2, r0
|
|||
|
|
80051b0: 697b ldr r3, [r7, #20]
|
|||
|
|
80051b2: 1ad3 subs r3, r2, r3
|
|||
|
|
80051b4: 2b02 cmp r3, #2
|
|||
|
|
80051b6: d901 bls.n 80051bc <HAL_RCC_OscConfig+0x63c>
|
|||
|
|
{
|
|||
|
|
return HAL_TIMEOUT;
|
|||
|
|
80051b8: 2303 movs r3, #3
|
|||
|
|
80051ba: e0a9 b.n 8005310 <HAL_RCC_OscConfig+0x790>
|
|||
|
|
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSI48RDY) != 0U)
|
|||
|
|
80051bc: 4b12 ldr r3, [pc, #72] ; (8005208 <HAL_RCC_OscConfig+0x688>)
|
|||
|
|
80051be: 689b ldr r3, [r3, #8]
|
|||
|
|
80051c0: 2202 movs r2, #2
|
|||
|
|
80051c2: 4013 ands r3, r2
|
|||
|
|
80051c4: d1f1 bne.n 80051aa <HAL_RCC_OscConfig+0x62a>
|
|||
|
|
#endif /* RCC_HSI48_SUPPORT */
|
|||
|
|
|
|||
|
|
/*-------------------------------- PLL Configuration -----------------------*/
|
|||
|
|
/* Check the parameters */
|
|||
|
|
assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState));
|
|||
|
|
if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE)
|
|||
|
|
80051c6: 687b ldr r3, [r7, #4]
|
|||
|
|
80051c8: 6a9b ldr r3, [r3, #40] ; 0x28
|
|||
|
|
80051ca: 2b00 cmp r3, #0
|
|||
|
|
80051cc: d100 bne.n 80051d0 <HAL_RCC_OscConfig+0x650>
|
|||
|
|
80051ce: e09e b.n 800530e <HAL_RCC_OscConfig+0x78e>
|
|||
|
|
{
|
|||
|
|
/* Check if the PLL is used as system clock or not */
|
|||
|
|
if(sysclk_source != RCC_SYSCLKSOURCE_STATUS_PLLCLK)
|
|||
|
|
80051d0: 69fb ldr r3, [r7, #28]
|
|||
|
|
80051d2: 2b0c cmp r3, #12
|
|||
|
|
80051d4: d100 bne.n 80051d8 <HAL_RCC_OscConfig+0x658>
|
|||
|
|
80051d6: e077 b.n 80052c8 <HAL_RCC_OscConfig+0x748>
|
|||
|
|
{
|
|||
|
|
if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON)
|
|||
|
|
80051d8: 687b ldr r3, [r7, #4]
|
|||
|
|
80051da: 6a9b ldr r3, [r3, #40] ; 0x28
|
|||
|
|
80051dc: 2b02 cmp r3, #2
|
|||
|
|
80051de: d158 bne.n 8005292 <HAL_RCC_OscConfig+0x712>
|
|||
|
|
assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct->PLL.PLLSource));
|
|||
|
|
assert_param(IS_RCC_PLL_MUL(RCC_OscInitStruct->PLL.PLLMUL));
|
|||
|
|
assert_param(IS_RCC_PLL_DIV(RCC_OscInitStruct->PLL.PLLDIV));
|
|||
|
|
|
|||
|
|
/* Disable the main PLL. */
|
|||
|
|
__HAL_RCC_PLL_DISABLE();
|
|||
|
|
80051e0: 4b09 ldr r3, [pc, #36] ; (8005208 <HAL_RCC_OscConfig+0x688>)
|
|||
|
|
80051e2: 4a09 ldr r2, [pc, #36] ; (8005208 <HAL_RCC_OscConfig+0x688>)
|
|||
|
|
80051e4: 6812 ldr r2, [r2, #0]
|
|||
|
|
80051e6: 4911 ldr r1, [pc, #68] ; (800522c <HAL_RCC_OscConfig+0x6ac>)
|
|||
|
|
80051e8: 400a ands r2, r1
|
|||
|
|
80051ea: 601a str r2, [r3, #0]
|
|||
|
|
|
|||
|
|
/* Get Start Tick */
|
|||
|
|
tickstart = HAL_GetTick();
|
|||
|
|
80051ec: f7fe fe9e bl 8003f2c <HAL_GetTick>
|
|||
|
|
80051f0: 0003 movs r3, r0
|
|||
|
|
80051f2: 617b str r3, [r7, #20]
|
|||
|
|
|
|||
|
|
/* Wait till PLL is ready */
|
|||
|
|
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != 0U)
|
|||
|
|
80051f4: e01c b.n 8005230 <HAL_RCC_OscConfig+0x6b0>
|
|||
|
|
{
|
|||
|
|
if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
|
|||
|
|
80051f6: f7fe fe99 bl 8003f2c <HAL_GetTick>
|
|||
|
|
80051fa: 0002 movs r2, r0
|
|||
|
|
80051fc: 697b ldr r3, [r7, #20]
|
|||
|
|
80051fe: 1ad3 subs r3, r2, r3
|
|||
|
|
8005200: 2b02 cmp r3, #2
|
|||
|
|
8005202: d915 bls.n 8005230 <HAL_RCC_OscConfig+0x6b0>
|
|||
|
|
{
|
|||
|
|
return HAL_TIMEOUT;
|
|||
|
|
8005204: 2303 movs r3, #3
|
|||
|
|
8005206: e083 b.n 8005310 <HAL_RCC_OscConfig+0x790>
|
|||
|
|
8005208: 40021000 .word 0x40021000
|
|||
|
|
800520c: ffff1fff .word 0xffff1fff
|
|||
|
|
8005210: fffffeff .word 0xfffffeff
|
|||
|
|
8005214: 40007000 .word 0x40007000
|
|||
|
|
8005218: fffffbff .word 0xfffffbff
|
|||
|
|
800521c: 00001388 .word 0x00001388
|
|||
|
|
8005220: efffffff .word 0xefffffff
|
|||
|
|
8005224: 40010000 .word 0x40010000
|
|||
|
|
8005228: ffffdfff .word 0xffffdfff
|
|||
|
|
800522c: feffffff .word 0xfeffffff
|
|||
|
|
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != 0U)
|
|||
|
|
8005230: 4b39 ldr r3, [pc, #228] ; (8005318 <HAL_RCC_OscConfig+0x798>)
|
|||
|
|
8005232: 681a ldr r2, [r3, #0]
|
|||
|
|
8005234: 2380 movs r3, #128 ; 0x80
|
|||
|
|
8005236: 049b lsls r3, r3, #18
|
|||
|
|
8005238: 4013 ands r3, r2
|
|||
|
|
800523a: d1dc bne.n 80051f6 <HAL_RCC_OscConfig+0x676>
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
/* Configure the main PLL clock source, multiplication and division factors. */
|
|||
|
|
__HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource,
|
|||
|
|
800523c: 4a36 ldr r2, [pc, #216] ; (8005318 <HAL_RCC_OscConfig+0x798>)
|
|||
|
|
800523e: 4b36 ldr r3, [pc, #216] ; (8005318 <HAL_RCC_OscConfig+0x798>)
|
|||
|
|
8005240: 68db ldr r3, [r3, #12]
|
|||
|
|
8005242: 4936 ldr r1, [pc, #216] ; (800531c <HAL_RCC_OscConfig+0x79c>)
|
|||
|
|
8005244: 4019 ands r1, r3
|
|||
|
|
8005246: 687b ldr r3, [r7, #4]
|
|||
|
|
8005248: 6ad8 ldr r0, [r3, #44] ; 0x2c
|
|||
|
|
800524a: 687b ldr r3, [r7, #4]
|
|||
|
|
800524c: 6b1b ldr r3, [r3, #48] ; 0x30
|
|||
|
|
800524e: 4318 orrs r0, r3
|
|||
|
|
8005250: 687b ldr r3, [r7, #4]
|
|||
|
|
8005252: 6b5b ldr r3, [r3, #52] ; 0x34
|
|||
|
|
8005254: 4303 orrs r3, r0
|
|||
|
|
8005256: 430b orrs r3, r1
|
|||
|
|
8005258: 60d3 str r3, [r2, #12]
|
|||
|
|
RCC_OscInitStruct->PLL.PLLMUL,
|
|||
|
|
RCC_OscInitStruct->PLL.PLLDIV);
|
|||
|
|
/* Enable the main PLL. */
|
|||
|
|
__HAL_RCC_PLL_ENABLE();
|
|||
|
|
800525a: 4b2f ldr r3, [pc, #188] ; (8005318 <HAL_RCC_OscConfig+0x798>)
|
|||
|
|
800525c: 4a2e ldr r2, [pc, #184] ; (8005318 <HAL_RCC_OscConfig+0x798>)
|
|||
|
|
800525e: 6812 ldr r2, [r2, #0]
|
|||
|
|
8005260: 2180 movs r1, #128 ; 0x80
|
|||
|
|
8005262: 0449 lsls r1, r1, #17
|
|||
|
|
8005264: 430a orrs r2, r1
|
|||
|
|
8005266: 601a str r2, [r3, #0]
|
|||
|
|
|
|||
|
|
/* Get Start Tick */
|
|||
|
|
tickstart = HAL_GetTick();
|
|||
|
|
8005268: f7fe fe60 bl 8003f2c <HAL_GetTick>
|
|||
|
|
800526c: 0003 movs r3, r0
|
|||
|
|
800526e: 617b str r3, [r7, #20]
|
|||
|
|
|
|||
|
|
/* Wait till PLL is ready */
|
|||
|
|
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == 0U)
|
|||
|
|
8005270: e008 b.n 8005284 <HAL_RCC_OscConfig+0x704>
|
|||
|
|
{
|
|||
|
|
if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
|
|||
|
|
8005272: f7fe fe5b bl 8003f2c <HAL_GetTick>
|
|||
|
|
8005276: 0002 movs r2, r0
|
|||
|
|
8005278: 697b ldr r3, [r7, #20]
|
|||
|
|
800527a: 1ad3 subs r3, r2, r3
|
|||
|
|
800527c: 2b02 cmp r3, #2
|
|||
|
|
800527e: d901 bls.n 8005284 <HAL_RCC_OscConfig+0x704>
|
|||
|
|
{
|
|||
|
|
return HAL_TIMEOUT;
|
|||
|
|
8005280: 2303 movs r3, #3
|
|||
|
|
8005282: e045 b.n 8005310 <HAL_RCC_OscConfig+0x790>
|
|||
|
|
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == 0U)
|
|||
|
|
8005284: 4b24 ldr r3, [pc, #144] ; (8005318 <HAL_RCC_OscConfig+0x798>)
|
|||
|
|
8005286: 681a ldr r2, [r3, #0]
|
|||
|
|
8005288: 2380 movs r3, #128 ; 0x80
|
|||
|
|
800528a: 049b lsls r3, r3, #18
|
|||
|
|
800528c: 4013 ands r3, r2
|
|||
|
|
800528e: d0f0 beq.n 8005272 <HAL_RCC_OscConfig+0x6f2>
|
|||
|
|
8005290: e03d b.n 800530e <HAL_RCC_OscConfig+0x78e>
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
else
|
|||
|
|
{
|
|||
|
|
/* Disable the main PLL. */
|
|||
|
|
__HAL_RCC_PLL_DISABLE();
|
|||
|
|
8005292: 4b21 ldr r3, [pc, #132] ; (8005318 <HAL_RCC_OscConfig+0x798>)
|
|||
|
|
8005294: 4a20 ldr r2, [pc, #128] ; (8005318 <HAL_RCC_OscConfig+0x798>)
|
|||
|
|
8005296: 6812 ldr r2, [r2, #0]
|
|||
|
|
8005298: 4921 ldr r1, [pc, #132] ; (8005320 <HAL_RCC_OscConfig+0x7a0>)
|
|||
|
|
800529a: 400a ands r2, r1
|
|||
|
|
800529c: 601a str r2, [r3, #0]
|
|||
|
|
|
|||
|
|
/* Get Start Tick */
|
|||
|
|
tickstart = HAL_GetTick();
|
|||
|
|
800529e: f7fe fe45 bl 8003f2c <HAL_GetTick>
|
|||
|
|
80052a2: 0003 movs r3, r0
|
|||
|
|
80052a4: 617b str r3, [r7, #20]
|
|||
|
|
|
|||
|
|
/* Wait till PLL is disabled */
|
|||
|
|
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != 0U)
|
|||
|
|
80052a6: e008 b.n 80052ba <HAL_RCC_OscConfig+0x73a>
|
|||
|
|
{
|
|||
|
|
if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
|
|||
|
|
80052a8: f7fe fe40 bl 8003f2c <HAL_GetTick>
|
|||
|
|
80052ac: 0002 movs r2, r0
|
|||
|
|
80052ae: 697b ldr r3, [r7, #20]
|
|||
|
|
80052b0: 1ad3 subs r3, r2, r3
|
|||
|
|
80052b2: 2b02 cmp r3, #2
|
|||
|
|
80052b4: d901 bls.n 80052ba <HAL_RCC_OscConfig+0x73a>
|
|||
|
|
{
|
|||
|
|
return HAL_TIMEOUT;
|
|||
|
|
80052b6: 2303 movs r3, #3
|
|||
|
|
80052b8: e02a b.n 8005310 <HAL_RCC_OscConfig+0x790>
|
|||
|
|
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != 0U)
|
|||
|
|
80052ba: 4b17 ldr r3, [pc, #92] ; (8005318 <HAL_RCC_OscConfig+0x798>)
|
|||
|
|
80052bc: 681a ldr r2, [r3, #0]
|
|||
|
|
80052be: 2380 movs r3, #128 ; 0x80
|
|||
|
|
80052c0: 049b lsls r3, r3, #18
|
|||
|
|
80052c2: 4013 ands r3, r2
|
|||
|
|
80052c4: d1f0 bne.n 80052a8 <HAL_RCC_OscConfig+0x728>
|
|||
|
|
80052c6: e022 b.n 800530e <HAL_RCC_OscConfig+0x78e>
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
else
|
|||
|
|
{
|
|||
|
|
/* Check if there is a request to disable the PLL used as System clock source */
|
|||
|
|
if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF)
|
|||
|
|
80052c8: 687b ldr r3, [r7, #4]
|
|||
|
|
80052ca: 6a9b ldr r3, [r3, #40] ; 0x28
|
|||
|
|
80052cc: 2b01 cmp r3, #1
|
|||
|
|
80052ce: d101 bne.n 80052d4 <HAL_RCC_OscConfig+0x754>
|
|||
|
|
{
|
|||
|
|
return HAL_ERROR;
|
|||
|
|
80052d0: 2301 movs r3, #1
|
|||
|
|
80052d2: e01d b.n 8005310 <HAL_RCC_OscConfig+0x790>
|
|||
|
|
}
|
|||
|
|
else
|
|||
|
|
{
|
|||
|
|
/* Do not return HAL_ERROR if request repeats the current configuration */
|
|||
|
|
pll_config = RCC->CFGR;
|
|||
|
|
80052d4: 4b10 ldr r3, [pc, #64] ; (8005318 <HAL_RCC_OscConfig+0x798>)
|
|||
|
|
80052d6: 68db ldr r3, [r3, #12]
|
|||
|
|
80052d8: 61bb str r3, [r7, #24]
|
|||
|
|
if((READ_BIT(pll_config, RCC_CFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
|
|||
|
|
80052da: 69ba ldr r2, [r7, #24]
|
|||
|
|
80052dc: 2380 movs r3, #128 ; 0x80
|
|||
|
|
80052de: 025b lsls r3, r3, #9
|
|||
|
|
80052e0: 401a ands r2, r3
|
|||
|
|
80052e2: 687b ldr r3, [r7, #4]
|
|||
|
|
80052e4: 6adb ldr r3, [r3, #44] ; 0x2c
|
|||
|
|
80052e6: 429a cmp r2, r3
|
|||
|
|
80052e8: d10f bne.n 800530a <HAL_RCC_OscConfig+0x78a>
|
|||
|
|
(READ_BIT(pll_config, RCC_CFGR_PLLMUL) != RCC_OscInitStruct->PLL.PLLMUL) ||
|
|||
|
|
80052ea: 69ba ldr r2, [r7, #24]
|
|||
|
|
80052ec: 23f0 movs r3, #240 ; 0xf0
|
|||
|
|
80052ee: 039b lsls r3, r3, #14
|
|||
|
|
80052f0: 401a ands r2, r3
|
|||
|
|
80052f2: 687b ldr r3, [r7, #4]
|
|||
|
|
80052f4: 6b1b ldr r3, [r3, #48] ; 0x30
|
|||
|
|
if((READ_BIT(pll_config, RCC_CFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
|
|||
|
|
80052f6: 429a cmp r2, r3
|
|||
|
|
80052f8: d107 bne.n 800530a <HAL_RCC_OscConfig+0x78a>
|
|||
|
|
(READ_BIT(pll_config, RCC_CFGR_PLLDIV) != RCC_OscInitStruct->PLL.PLLDIV))
|
|||
|
|
80052fa: 69ba ldr r2, [r7, #24]
|
|||
|
|
80052fc: 23c0 movs r3, #192 ; 0xc0
|
|||
|
|
80052fe: 041b lsls r3, r3, #16
|
|||
|
|
8005300: 401a ands r2, r3
|
|||
|
|
8005302: 687b ldr r3, [r7, #4]
|
|||
|
|
8005304: 6b5b ldr r3, [r3, #52] ; 0x34
|
|||
|
|
(READ_BIT(pll_config, RCC_CFGR_PLLMUL) != RCC_OscInitStruct->PLL.PLLMUL) ||
|
|||
|
|
8005306: 429a cmp r2, r3
|
|||
|
|
8005308: d001 beq.n 800530e <HAL_RCC_OscConfig+0x78e>
|
|||
|
|
{
|
|||
|
|
return HAL_ERROR;
|
|||
|
|
800530a: 2301 movs r3, #1
|
|||
|
|
800530c: e000 b.n 8005310 <HAL_RCC_OscConfig+0x790>
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
return HAL_OK;
|
|||
|
|
800530e: 2300 movs r3, #0
|
|||
|
|
}
|
|||
|
|
8005310: 0018 movs r0, r3
|
|||
|
|
8005312: 46bd mov sp, r7
|
|||
|
|
8005314: b00b add sp, #44 ; 0x2c
|
|||
|
|
8005316: bd90 pop {r4, r7, pc}
|
|||
|
|
8005318: 40021000 .word 0x40021000
|
|||
|
|
800531c: ff02ffff .word 0xff02ffff
|
|||
|
|
8005320: feffffff .word 0xfeffffff
|
|||
|
|
|
|||
|
|
08005324 <HAL_RCC_ClockConfig>:
|
|||
|
|
* HPRE[3:0] bits to ensure that HCLK not exceed the maximum allowed frequency
|
|||
|
|
* (for more details refer to section above "Initialization/de-initialization functions")
|
|||
|
|
* @retval HAL status
|
|||
|
|
*/
|
|||
|
|
HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency)
|
|||
|
|
{
|
|||
|
|
8005324: b590 push {r4, r7, lr}
|
|||
|
|
8005326: b085 sub sp, #20
|
|||
|
|
8005328: af00 add r7, sp, #0
|
|||
|
|
800532a: 6078 str r0, [r7, #4]
|
|||
|
|
800532c: 6039 str r1, [r7, #0]
|
|||
|
|
uint32_t tickstart;
|
|||
|
|
HAL_StatusTypeDef status;
|
|||
|
|
|
|||
|
|
/* Check Null pointer */
|
|||
|
|
if(RCC_ClkInitStruct == NULL)
|
|||
|
|
800532e: 687b ldr r3, [r7, #4]
|
|||
|
|
8005330: 2b00 cmp r3, #0
|
|||
|
|
8005332: d101 bne.n 8005338 <HAL_RCC_ClockConfig+0x14>
|
|||
|
|
{
|
|||
|
|
return HAL_ERROR;
|
|||
|
|
8005334: 2301 movs r3, #1
|
|||
|
|
8005336: e128 b.n 800558a <HAL_RCC_ClockConfig+0x266>
|
|||
|
|
/* To correctly read data from FLASH memory, the number of wait states (LATENCY)
|
|||
|
|
must be correctly programmed according to the frequency of the CPU clock
|
|||
|
|
(HCLK) and the supply voltage of the device. */
|
|||
|
|
|
|||
|
|
/* Increasing the number of wait states because of higher CPU frequency */
|
|||
|
|
if(FLatency > __HAL_FLASH_GET_LATENCY())
|
|||
|
|
8005338: 4b96 ldr r3, [pc, #600] ; (8005594 <HAL_RCC_ClockConfig+0x270>)
|
|||
|
|
800533a: 681b ldr r3, [r3, #0]
|
|||
|
|
800533c: 2201 movs r2, #1
|
|||
|
|
800533e: 401a ands r2, r3
|
|||
|
|
8005340: 683b ldr r3, [r7, #0]
|
|||
|
|
8005342: 429a cmp r2, r3
|
|||
|
|
8005344: d21e bcs.n 8005384 <HAL_RCC_ClockConfig+0x60>
|
|||
|
|
{
|
|||
|
|
/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
|
|||
|
|
__HAL_FLASH_SET_LATENCY(FLatency);
|
|||
|
|
8005346: 4b93 ldr r3, [pc, #588] ; (8005594 <HAL_RCC_ClockConfig+0x270>)
|
|||
|
|
8005348: 4a92 ldr r2, [pc, #584] ; (8005594 <HAL_RCC_ClockConfig+0x270>)
|
|||
|
|
800534a: 6812 ldr r2, [r2, #0]
|
|||
|
|
800534c: 2101 movs r1, #1
|
|||
|
|
800534e: 438a bics r2, r1
|
|||
|
|
8005350: 0011 movs r1, r2
|
|||
|
|
8005352: 683a ldr r2, [r7, #0]
|
|||
|
|
8005354: 430a orrs r2, r1
|
|||
|
|
8005356: 601a str r2, [r3, #0]
|
|||
|
|
|
|||
|
|
/* Check that the new number of wait states is taken into account to access the Flash
|
|||
|
|
memory by polling the FLASH_ACR register */
|
|||
|
|
tickstart = HAL_GetTick();
|
|||
|
|
8005358: f7fe fde8 bl 8003f2c <HAL_GetTick>
|
|||
|
|
800535c: 0003 movs r3, r0
|
|||
|
|
800535e: 60fb str r3, [r7, #12]
|
|||
|
|
|
|||
|
|
while (__HAL_FLASH_GET_LATENCY() != FLatency)
|
|||
|
|
8005360: e009 b.n 8005376 <HAL_RCC_ClockConfig+0x52>
|
|||
|
|
{
|
|||
|
|
if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
|
|||
|
|
8005362: f7fe fde3 bl 8003f2c <HAL_GetTick>
|
|||
|
|
8005366: 0002 movs r2, r0
|
|||
|
|
8005368: 68fb ldr r3, [r7, #12]
|
|||
|
|
800536a: 1ad3 subs r3, r2, r3
|
|||
|
|
800536c: 4a8a ldr r2, [pc, #552] ; (8005598 <HAL_RCC_ClockConfig+0x274>)
|
|||
|
|
800536e: 4293 cmp r3, r2
|
|||
|
|
8005370: d901 bls.n 8005376 <HAL_RCC_ClockConfig+0x52>
|
|||
|
|
{
|
|||
|
|
return HAL_TIMEOUT;
|
|||
|
|
8005372: 2303 movs r3, #3
|
|||
|
|
8005374: e109 b.n 800558a <HAL_RCC_ClockConfig+0x266>
|
|||
|
|
while (__HAL_FLASH_GET_LATENCY() != FLatency)
|
|||
|
|
8005376: 4b87 ldr r3, [pc, #540] ; (8005594 <HAL_RCC_ClockConfig+0x270>)
|
|||
|
|
8005378: 681b ldr r3, [r3, #0]
|
|||
|
|
800537a: 2201 movs r2, #1
|
|||
|
|
800537c: 401a ands r2, r3
|
|||
|
|
800537e: 683b ldr r3, [r7, #0]
|
|||
|
|
8005380: 429a cmp r2, r3
|
|||
|
|
8005382: d1ee bne.n 8005362 <HAL_RCC_ClockConfig+0x3e>
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
/*-------------------------- HCLK Configuration --------------------------*/
|
|||
|
|
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
|
|||
|
|
8005384: 687b ldr r3, [r7, #4]
|
|||
|
|
8005386: 681b ldr r3, [r3, #0]
|
|||
|
|
8005388: 2202 movs r2, #2
|
|||
|
|
800538a: 4013 ands r3, r2
|
|||
|
|
800538c: d009 beq.n 80053a2 <HAL_RCC_ClockConfig+0x7e>
|
|||
|
|
{
|
|||
|
|
assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));
|
|||
|
|
MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
|
|||
|
|
800538e: 4a83 ldr r2, [pc, #524] ; (800559c <HAL_RCC_ClockConfig+0x278>)
|
|||
|
|
8005390: 4b82 ldr r3, [pc, #520] ; (800559c <HAL_RCC_ClockConfig+0x278>)
|
|||
|
|
8005392: 68db ldr r3, [r3, #12]
|
|||
|
|
8005394: 21f0 movs r1, #240 ; 0xf0
|
|||
|
|
8005396: 438b bics r3, r1
|
|||
|
|
8005398: 0019 movs r1, r3
|
|||
|
|
800539a: 687b ldr r3, [r7, #4]
|
|||
|
|
800539c: 689b ldr r3, [r3, #8]
|
|||
|
|
800539e: 430b orrs r3, r1
|
|||
|
|
80053a0: 60d3 str r3, [r2, #12]
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
/*------------------------- SYSCLK Configuration ---------------------------*/
|
|||
|
|
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
|
|||
|
|
80053a2: 687b ldr r3, [r7, #4]
|
|||
|
|
80053a4: 681b ldr r3, [r3, #0]
|
|||
|
|
80053a6: 2201 movs r2, #1
|
|||
|
|
80053a8: 4013 ands r3, r2
|
|||
|
|
80053aa: d100 bne.n 80053ae <HAL_RCC_ClockConfig+0x8a>
|
|||
|
|
80053ac: e089 b.n 80054c2 <HAL_RCC_ClockConfig+0x19e>
|
|||
|
|
{
|
|||
|
|
assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource));
|
|||
|
|
|
|||
|
|
/* HSE is selected as System Clock Source */
|
|||
|
|
if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
|
|||
|
|
80053ae: 687b ldr r3, [r7, #4]
|
|||
|
|
80053b0: 685b ldr r3, [r3, #4]
|
|||
|
|
80053b2: 2b02 cmp r3, #2
|
|||
|
|
80053b4: d107 bne.n 80053c6 <HAL_RCC_ClockConfig+0xa2>
|
|||
|
|
{
|
|||
|
|
/* Check the HSE ready flag */
|
|||
|
|
if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == 0U)
|
|||
|
|
80053b6: 4b79 ldr r3, [pc, #484] ; (800559c <HAL_RCC_ClockConfig+0x278>)
|
|||
|
|
80053b8: 681a ldr r2, [r3, #0]
|
|||
|
|
80053ba: 2380 movs r3, #128 ; 0x80
|
|||
|
|
80053bc: 029b lsls r3, r3, #10
|
|||
|
|
80053be: 4013 ands r3, r2
|
|||
|
|
80053c0: d120 bne.n 8005404 <HAL_RCC_ClockConfig+0xe0>
|
|||
|
|
{
|
|||
|
|
return HAL_ERROR;
|
|||
|
|
80053c2: 2301 movs r3, #1
|
|||
|
|
80053c4: e0e1 b.n 800558a <HAL_RCC_ClockConfig+0x266>
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
/* PLL is selected as System Clock Source */
|
|||
|
|
else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
|
|||
|
|
80053c6: 687b ldr r3, [r7, #4]
|
|||
|
|
80053c8: 685b ldr r3, [r3, #4]
|
|||
|
|
80053ca: 2b03 cmp r3, #3
|
|||
|
|
80053cc: d107 bne.n 80053de <HAL_RCC_ClockConfig+0xba>
|
|||
|
|
{
|
|||
|
|
/* Check the PLL ready flag */
|
|||
|
|
if(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == 0U)
|
|||
|
|
80053ce: 4b73 ldr r3, [pc, #460] ; (800559c <HAL_RCC_ClockConfig+0x278>)
|
|||
|
|
80053d0: 681a ldr r2, [r3, #0]
|
|||
|
|
80053d2: 2380 movs r3, #128 ; 0x80
|
|||
|
|
80053d4: 049b lsls r3, r3, #18
|
|||
|
|
80053d6: 4013 ands r3, r2
|
|||
|
|
80053d8: d114 bne.n 8005404 <HAL_RCC_ClockConfig+0xe0>
|
|||
|
|
{
|
|||
|
|
return HAL_ERROR;
|
|||
|
|
80053da: 2301 movs r3, #1
|
|||
|
|
80053dc: e0d5 b.n 800558a <HAL_RCC_ClockConfig+0x266>
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
/* HSI is selected as System Clock Source */
|
|||
|
|
else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSI)
|
|||
|
|
80053de: 687b ldr r3, [r7, #4]
|
|||
|
|
80053e0: 685b ldr r3, [r3, #4]
|
|||
|
|
80053e2: 2b01 cmp r3, #1
|
|||
|
|
80053e4: d106 bne.n 80053f4 <HAL_RCC_ClockConfig+0xd0>
|
|||
|
|
{
|
|||
|
|
/* Check the HSI ready flag */
|
|||
|
|
if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == 0U)
|
|||
|
|
80053e6: 4b6d ldr r3, [pc, #436] ; (800559c <HAL_RCC_ClockConfig+0x278>)
|
|||
|
|
80053e8: 681b ldr r3, [r3, #0]
|
|||
|
|
80053ea: 2204 movs r2, #4
|
|||
|
|
80053ec: 4013 ands r3, r2
|
|||
|
|
80053ee: d109 bne.n 8005404 <HAL_RCC_ClockConfig+0xe0>
|
|||
|
|
{
|
|||
|
|
return HAL_ERROR;
|
|||
|
|
80053f0: 2301 movs r3, #1
|
|||
|
|
80053f2: e0ca b.n 800558a <HAL_RCC_ClockConfig+0x266>
|
|||
|
|
}
|
|||
|
|
/* MSI is selected as System Clock Source */
|
|||
|
|
else
|
|||
|
|
{
|
|||
|
|
/* Check the MSI ready flag */
|
|||
|
|
if(__HAL_RCC_GET_FLAG(RCC_FLAG_MSIRDY) == 0U)
|
|||
|
|
80053f4: 4b69 ldr r3, [pc, #420] ; (800559c <HAL_RCC_ClockConfig+0x278>)
|
|||
|
|
80053f6: 681a ldr r2, [r3, #0]
|
|||
|
|
80053f8: 2380 movs r3, #128 ; 0x80
|
|||
|
|
80053fa: 009b lsls r3, r3, #2
|
|||
|
|
80053fc: 4013 ands r3, r2
|
|||
|
|
80053fe: d101 bne.n 8005404 <HAL_RCC_ClockConfig+0xe0>
|
|||
|
|
{
|
|||
|
|
return HAL_ERROR;
|
|||
|
|
8005400: 2301 movs r3, #1
|
|||
|
|
8005402: e0c2 b.n 800558a <HAL_RCC_ClockConfig+0x266>
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
__HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource);
|
|||
|
|
8005404: 4a65 ldr r2, [pc, #404] ; (800559c <HAL_RCC_ClockConfig+0x278>)
|
|||
|
|
8005406: 4b65 ldr r3, [pc, #404] ; (800559c <HAL_RCC_ClockConfig+0x278>)
|
|||
|
|
8005408: 68db ldr r3, [r3, #12]
|
|||
|
|
800540a: 2103 movs r1, #3
|
|||
|
|
800540c: 438b bics r3, r1
|
|||
|
|
800540e: 0019 movs r1, r3
|
|||
|
|
8005410: 687b ldr r3, [r7, #4]
|
|||
|
|
8005412: 685b ldr r3, [r3, #4]
|
|||
|
|
8005414: 430b orrs r3, r1
|
|||
|
|
8005416: 60d3 str r3, [r2, #12]
|
|||
|
|
|
|||
|
|
/* Get Start Tick */
|
|||
|
|
tickstart = HAL_GetTick();
|
|||
|
|
8005418: f7fe fd88 bl 8003f2c <HAL_GetTick>
|
|||
|
|
800541c: 0003 movs r3, r0
|
|||
|
|
800541e: 60fb str r3, [r7, #12]
|
|||
|
|
|
|||
|
|
if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
|
|||
|
|
8005420: 687b ldr r3, [r7, #4]
|
|||
|
|
8005422: 685b ldr r3, [r3, #4]
|
|||
|
|
8005424: 2b02 cmp r3, #2
|
|||
|
|
8005426: d111 bne.n 800544c <HAL_RCC_ClockConfig+0x128>
|
|||
|
|
{
|
|||
|
|
while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSE)
|
|||
|
|
8005428: e009 b.n 800543e <HAL_RCC_ClockConfig+0x11a>
|
|||
|
|
{
|
|||
|
|
if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
|
|||
|
|
800542a: f7fe fd7f bl 8003f2c <HAL_GetTick>
|
|||
|
|
800542e: 0002 movs r2, r0
|
|||
|
|
8005430: 68fb ldr r3, [r7, #12]
|
|||
|
|
8005432: 1ad3 subs r3, r2, r3
|
|||
|
|
8005434: 4a58 ldr r2, [pc, #352] ; (8005598 <HAL_RCC_ClockConfig+0x274>)
|
|||
|
|
8005436: 4293 cmp r3, r2
|
|||
|
|
8005438: d901 bls.n 800543e <HAL_RCC_ClockConfig+0x11a>
|
|||
|
|
{
|
|||
|
|
return HAL_TIMEOUT;
|
|||
|
|
800543a: 2303 movs r3, #3
|
|||
|
|
800543c: e0a5 b.n 800558a <HAL_RCC_ClockConfig+0x266>
|
|||
|
|
while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSE)
|
|||
|
|
800543e: 4b57 ldr r3, [pc, #348] ; (800559c <HAL_RCC_ClockConfig+0x278>)
|
|||
|
|
8005440: 68db ldr r3, [r3, #12]
|
|||
|
|
8005442: 220c movs r2, #12
|
|||
|
|
8005444: 4013 ands r3, r2
|
|||
|
|
8005446: 2b08 cmp r3, #8
|
|||
|
|
8005448: d1ef bne.n 800542a <HAL_RCC_ClockConfig+0x106>
|
|||
|
|
800544a: e03a b.n 80054c2 <HAL_RCC_ClockConfig+0x19e>
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
|
|||
|
|
800544c: 687b ldr r3, [r7, #4]
|
|||
|
|
800544e: 685b ldr r3, [r3, #4]
|
|||
|
|
8005450: 2b03 cmp r3, #3
|
|||
|
|
8005452: d111 bne.n 8005478 <HAL_RCC_ClockConfig+0x154>
|
|||
|
|
{
|
|||
|
|
while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK)
|
|||
|
|
8005454: e009 b.n 800546a <HAL_RCC_ClockConfig+0x146>
|
|||
|
|
{
|
|||
|
|
if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
|
|||
|
|
8005456: f7fe fd69 bl 8003f2c <HAL_GetTick>
|
|||
|
|
800545a: 0002 movs r2, r0
|
|||
|
|
800545c: 68fb ldr r3, [r7, #12]
|
|||
|
|
800545e: 1ad3 subs r3, r2, r3
|
|||
|
|
8005460: 4a4d ldr r2, [pc, #308] ; (8005598 <HAL_RCC_ClockConfig+0x274>)
|
|||
|
|
8005462: 4293 cmp r3, r2
|
|||
|
|
8005464: d901 bls.n 800546a <HAL_RCC_ClockConfig+0x146>
|
|||
|
|
{
|
|||
|
|
return HAL_TIMEOUT;
|
|||
|
|
8005466: 2303 movs r3, #3
|
|||
|
|
8005468: e08f b.n 800558a <HAL_RCC_ClockConfig+0x266>
|
|||
|
|
while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK)
|
|||
|
|
800546a: 4b4c ldr r3, [pc, #304] ; (800559c <HAL_RCC_ClockConfig+0x278>)
|
|||
|
|
800546c: 68db ldr r3, [r3, #12]
|
|||
|
|
800546e: 220c movs r2, #12
|
|||
|
|
8005470: 4013 ands r3, r2
|
|||
|
|
8005472: 2b0c cmp r3, #12
|
|||
|
|
8005474: d1ef bne.n 8005456 <HAL_RCC_ClockConfig+0x132>
|
|||
|
|
8005476: e024 b.n 80054c2 <HAL_RCC_ClockConfig+0x19e>
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSI)
|
|||
|
|
8005478: 687b ldr r3, [r7, #4]
|
|||
|
|
800547a: 685b ldr r3, [r3, #4]
|
|||
|
|
800547c: 2b01 cmp r3, #1
|
|||
|
|
800547e: d11b bne.n 80054b8 <HAL_RCC_ClockConfig+0x194>
|
|||
|
|
{
|
|||
|
|
while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSI)
|
|||
|
|
8005480: e009 b.n 8005496 <HAL_RCC_ClockConfig+0x172>
|
|||
|
|
{
|
|||
|
|
if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
|
|||
|
|
8005482: f7fe fd53 bl 8003f2c <HAL_GetTick>
|
|||
|
|
8005486: 0002 movs r2, r0
|
|||
|
|
8005488: 68fb ldr r3, [r7, #12]
|
|||
|
|
800548a: 1ad3 subs r3, r2, r3
|
|||
|
|
800548c: 4a42 ldr r2, [pc, #264] ; (8005598 <HAL_RCC_ClockConfig+0x274>)
|
|||
|
|
800548e: 4293 cmp r3, r2
|
|||
|
|
8005490: d901 bls.n 8005496 <HAL_RCC_ClockConfig+0x172>
|
|||
|
|
{
|
|||
|
|
return HAL_TIMEOUT;
|
|||
|
|
8005492: 2303 movs r3, #3
|
|||
|
|
8005494: e079 b.n 800558a <HAL_RCC_ClockConfig+0x266>
|
|||
|
|
while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSI)
|
|||
|
|
8005496: 4b41 ldr r3, [pc, #260] ; (800559c <HAL_RCC_ClockConfig+0x278>)
|
|||
|
|
8005498: 68db ldr r3, [r3, #12]
|
|||
|
|
800549a: 220c movs r2, #12
|
|||
|
|
800549c: 4013 ands r3, r2
|
|||
|
|
800549e: 2b04 cmp r3, #4
|
|||
|
|
80054a0: d1ef bne.n 8005482 <HAL_RCC_ClockConfig+0x15e>
|
|||
|
|
80054a2: e00e b.n 80054c2 <HAL_RCC_ClockConfig+0x19e>
|
|||
|
|
}
|
|||
|
|
else
|
|||
|
|
{
|
|||
|
|
while(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_MSI)
|
|||
|
|
{
|
|||
|
|
if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
|
|||
|
|
80054a4: f7fe fd42 bl 8003f2c <HAL_GetTick>
|
|||
|
|
80054a8: 0002 movs r2, r0
|
|||
|
|
80054aa: 68fb ldr r3, [r7, #12]
|
|||
|
|
80054ac: 1ad3 subs r3, r2, r3
|
|||
|
|
80054ae: 4a3a ldr r2, [pc, #232] ; (8005598 <HAL_RCC_ClockConfig+0x274>)
|
|||
|
|
80054b0: 4293 cmp r3, r2
|
|||
|
|
80054b2: d901 bls.n 80054b8 <HAL_RCC_ClockConfig+0x194>
|
|||
|
|
{
|
|||
|
|
return HAL_TIMEOUT;
|
|||
|
|
80054b4: 2303 movs r3, #3
|
|||
|
|
80054b6: e068 b.n 800558a <HAL_RCC_ClockConfig+0x266>
|
|||
|
|
while(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_MSI)
|
|||
|
|
80054b8: 4b38 ldr r3, [pc, #224] ; (800559c <HAL_RCC_ClockConfig+0x278>)
|
|||
|
|
80054ba: 68db ldr r3, [r3, #12]
|
|||
|
|
80054bc: 220c movs r2, #12
|
|||
|
|
80054be: 4013 ands r3, r2
|
|||
|
|
80054c0: d1f0 bne.n 80054a4 <HAL_RCC_ClockConfig+0x180>
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
/* Decreasing the number of wait states because of lower CPU frequency */
|
|||
|
|
if(FLatency < __HAL_FLASH_GET_LATENCY())
|
|||
|
|
80054c2: 4b34 ldr r3, [pc, #208] ; (8005594 <HAL_RCC_ClockConfig+0x270>)
|
|||
|
|
80054c4: 681b ldr r3, [r3, #0]
|
|||
|
|
80054c6: 2201 movs r2, #1
|
|||
|
|
80054c8: 401a ands r2, r3
|
|||
|
|
80054ca: 683b ldr r3, [r7, #0]
|
|||
|
|
80054cc: 429a cmp r2, r3
|
|||
|
|
80054ce: d91e bls.n 800550e <HAL_RCC_ClockConfig+0x1ea>
|
|||
|
|
{
|
|||
|
|
/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
|
|||
|
|
__HAL_FLASH_SET_LATENCY(FLatency);
|
|||
|
|
80054d0: 4b30 ldr r3, [pc, #192] ; (8005594 <HAL_RCC_ClockConfig+0x270>)
|
|||
|
|
80054d2: 4a30 ldr r2, [pc, #192] ; (8005594 <HAL_RCC_ClockConfig+0x270>)
|
|||
|
|
80054d4: 6812 ldr r2, [r2, #0]
|
|||
|
|
80054d6: 2101 movs r1, #1
|
|||
|
|
80054d8: 438a bics r2, r1
|
|||
|
|
80054da: 0011 movs r1, r2
|
|||
|
|
80054dc: 683a ldr r2, [r7, #0]
|
|||
|
|
80054de: 430a orrs r2, r1
|
|||
|
|
80054e0: 601a str r2, [r3, #0]
|
|||
|
|
|
|||
|
|
/* Check that the new number of wait states is taken into account to access the Flash
|
|||
|
|
memory by polling the FLASH_ACR register */
|
|||
|
|
tickstart = HAL_GetTick();
|
|||
|
|
80054e2: f7fe fd23 bl 8003f2c <HAL_GetTick>
|
|||
|
|
80054e6: 0003 movs r3, r0
|
|||
|
|
80054e8: 60fb str r3, [r7, #12]
|
|||
|
|
|
|||
|
|
while (__HAL_FLASH_GET_LATENCY() != FLatency)
|
|||
|
|
80054ea: e009 b.n 8005500 <HAL_RCC_ClockConfig+0x1dc>
|
|||
|
|
{
|
|||
|
|
if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
|
|||
|
|
80054ec: f7fe fd1e bl 8003f2c <HAL_GetTick>
|
|||
|
|
80054f0: 0002 movs r2, r0
|
|||
|
|
80054f2: 68fb ldr r3, [r7, #12]
|
|||
|
|
80054f4: 1ad3 subs r3, r2, r3
|
|||
|
|
80054f6: 4a28 ldr r2, [pc, #160] ; (8005598 <HAL_RCC_ClockConfig+0x274>)
|
|||
|
|
80054f8: 4293 cmp r3, r2
|
|||
|
|
80054fa: d901 bls.n 8005500 <HAL_RCC_ClockConfig+0x1dc>
|
|||
|
|
{
|
|||
|
|
return HAL_TIMEOUT;
|
|||
|
|
80054fc: 2303 movs r3, #3
|
|||
|
|
80054fe: e044 b.n 800558a <HAL_RCC_ClockConfig+0x266>
|
|||
|
|
while (__HAL_FLASH_GET_LATENCY() != FLatency)
|
|||
|
|
8005500: 4b24 ldr r3, [pc, #144] ; (8005594 <HAL_RCC_ClockConfig+0x270>)
|
|||
|
|
8005502: 681b ldr r3, [r3, #0]
|
|||
|
|
8005504: 2201 movs r2, #1
|
|||
|
|
8005506: 401a ands r2, r3
|
|||
|
|
8005508: 683b ldr r3, [r7, #0]
|
|||
|
|
800550a: 429a cmp r2, r3
|
|||
|
|
800550c: d1ee bne.n 80054ec <HAL_RCC_ClockConfig+0x1c8>
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
/*-------------------------- PCLK1 Configuration ---------------------------*/
|
|||
|
|
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
|
|||
|
|
800550e: 687b ldr r3, [r7, #4]
|
|||
|
|
8005510: 681b ldr r3, [r3, #0]
|
|||
|
|
8005512: 2204 movs r2, #4
|
|||
|
|
8005514: 4013 ands r3, r2
|
|||
|
|
8005516: d008 beq.n 800552a <HAL_RCC_ClockConfig+0x206>
|
|||
|
|
{
|
|||
|
|
assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider));
|
|||
|
|
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider);
|
|||
|
|
8005518: 4a20 ldr r2, [pc, #128] ; (800559c <HAL_RCC_ClockConfig+0x278>)
|
|||
|
|
800551a: 4b20 ldr r3, [pc, #128] ; (800559c <HAL_RCC_ClockConfig+0x278>)
|
|||
|
|
800551c: 68db ldr r3, [r3, #12]
|
|||
|
|
800551e: 4920 ldr r1, [pc, #128] ; (80055a0 <HAL_RCC_ClockConfig+0x27c>)
|
|||
|
|
8005520: 4019 ands r1, r3
|
|||
|
|
8005522: 687b ldr r3, [r7, #4]
|
|||
|
|
8005524: 68db ldr r3, [r3, #12]
|
|||
|
|
8005526: 430b orrs r3, r1
|
|||
|
|
8005528: 60d3 str r3, [r2, #12]
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
/*-------------------------- PCLK2 Configuration ---------------------------*/
|
|||
|
|
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
|
|||
|
|
800552a: 687b ldr r3, [r7, #4]
|
|||
|
|
800552c: 681b ldr r3, [r3, #0]
|
|||
|
|
800552e: 2208 movs r2, #8
|
|||
|
|
8005530: 4013 ands r3, r2
|
|||
|
|
8005532: d009 beq.n 8005548 <HAL_RCC_ClockConfig+0x224>
|
|||
|
|
{
|
|||
|
|
assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider));
|
|||
|
|
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3));
|
|||
|
|
8005534: 4a19 ldr r2, [pc, #100] ; (800559c <HAL_RCC_ClockConfig+0x278>)
|
|||
|
|
8005536: 4b19 ldr r3, [pc, #100] ; (800559c <HAL_RCC_ClockConfig+0x278>)
|
|||
|
|
8005538: 68db ldr r3, [r3, #12]
|
|||
|
|
800553a: 491a ldr r1, [pc, #104] ; (80055a4 <HAL_RCC_ClockConfig+0x280>)
|
|||
|
|
800553c: 4019 ands r1, r3
|
|||
|
|
800553e: 687b ldr r3, [r7, #4]
|
|||
|
|
8005540: 691b ldr r3, [r3, #16]
|
|||
|
|
8005542: 00db lsls r3, r3, #3
|
|||
|
|
8005544: 430b orrs r3, r1
|
|||
|
|
8005546: 60d3 str r3, [r2, #12]
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
/* Update the SystemCoreClock global variable */
|
|||
|
|
SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE)>> RCC_CFGR_HPRE_Pos];
|
|||
|
|
8005548: f000 f834 bl 80055b4 <HAL_RCC_GetSysClockFreq>
|
|||
|
|
800554c: 0001 movs r1, r0
|
|||
|
|
800554e: 4b13 ldr r3, [pc, #76] ; (800559c <HAL_RCC_ClockConfig+0x278>)
|
|||
|
|
8005550: 68db ldr r3, [r3, #12]
|
|||
|
|
8005552: 091b lsrs r3, r3, #4
|
|||
|
|
8005554: 220f movs r2, #15
|
|||
|
|
8005556: 4013 ands r3, r2
|
|||
|
|
8005558: 4a13 ldr r2, [pc, #76] ; (80055a8 <HAL_RCC_ClockConfig+0x284>)
|
|||
|
|
800555a: 5cd3 ldrb r3, [r2, r3]
|
|||
|
|
800555c: 000a movs r2, r1
|
|||
|
|
800555e: 40da lsrs r2, r3
|
|||
|
|
8005560: 4b12 ldr r3, [pc, #72] ; (80055ac <HAL_RCC_ClockConfig+0x288>)
|
|||
|
|
8005562: 601a str r2, [r3, #0]
|
|||
|
|
|
|||
|
|
/* Configure the source of time base considering new system clocks settings*/
|
|||
|
|
status = HAL_InitTick(uwTickPrio);
|
|||
|
|
8005564: 4b12 ldr r3, [pc, #72] ; (80055b0 <HAL_RCC_ClockConfig+0x28c>)
|
|||
|
|
8005566: 681b ldr r3, [r3, #0]
|
|||
|
|
8005568: 220b movs r2, #11
|
|||
|
|
800556a: 18bc adds r4, r7, r2
|
|||
|
|
800556c: 0018 movs r0, r3
|
|||
|
|
800556e: f7fe fc97 bl 8003ea0 <HAL_InitTick>
|
|||
|
|
8005572: 0003 movs r3, r0
|
|||
|
|
8005574: 7023 strb r3, [r4, #0]
|
|||
|
|
if(status != HAL_OK)
|
|||
|
|
8005576: 230b movs r3, #11
|
|||
|
|
8005578: 18fb adds r3, r7, r3
|
|||
|
|
800557a: 781b ldrb r3, [r3, #0]
|
|||
|
|
800557c: 2b00 cmp r3, #0
|
|||
|
|
800557e: d003 beq.n 8005588 <HAL_RCC_ClockConfig+0x264>
|
|||
|
|
{
|
|||
|
|
return status;
|
|||
|
|
8005580: 230b movs r3, #11
|
|||
|
|
8005582: 18fb adds r3, r7, r3
|
|||
|
|
8005584: 781b ldrb r3, [r3, #0]
|
|||
|
|
8005586: e000 b.n 800558a <HAL_RCC_ClockConfig+0x266>
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
return HAL_OK;
|
|||
|
|
8005588: 2300 movs r3, #0
|
|||
|
|
}
|
|||
|
|
800558a: 0018 movs r0, r3
|
|||
|
|
800558c: 46bd mov sp, r7
|
|||
|
|
800558e: b005 add sp, #20
|
|||
|
|
8005590: bd90 pop {r4, r7, pc}
|
|||
|
|
8005592: 46c0 nop ; (mov r8, r8)
|
|||
|
|
8005594: 40022000 .word 0x40022000
|
|||
|
|
8005598: 00001388 .word 0x00001388
|
|||
|
|
800559c: 40021000 .word 0x40021000
|
|||
|
|
80055a0: fffff8ff .word 0xfffff8ff
|
|||
|
|
80055a4: ffffc7ff .word 0xffffc7ff
|
|||
|
|
80055a8: 080071d0 .word 0x080071d0
|
|||
|
|
80055ac: 20000000 .word 0x20000000
|
|||
|
|
80055b0: 20000008 .word 0x20000008
|
|||
|
|
|
|||
|
|
080055b4 <HAL_RCC_GetSysClockFreq>:
|
|||
|
|
* right SYSCLK value. Otherwise, any configuration based on this function will be incorrect.
|
|||
|
|
*
|
|||
|
|
* @retval SYSCLK frequency
|
|||
|
|
*/
|
|||
|
|
uint32_t HAL_RCC_GetSysClockFreq(void)
|
|||
|
|
{
|
|||
|
|
80055b4: b5f0 push {r4, r5, r6, r7, lr}
|
|||
|
|
80055b6: b08f sub sp, #60 ; 0x3c
|
|||
|
|
80055b8: af00 add r7, sp, #0
|
|||
|
|
uint32_t tmpreg, pllm, plld, pllvco, msiclkrange; /* no init needed */
|
|||
|
|
uint32_t sysclockfreq;
|
|||
|
|
|
|||
|
|
tmpreg = RCC->CFGR;
|
|||
|
|
80055ba: 4b4a ldr r3, [pc, #296] ; (80056e4 <HAL_RCC_GetSysClockFreq+0x130>)
|
|||
|
|
80055bc: 68db ldr r3, [r3, #12]
|
|||
|
|
80055be: 62fb str r3, [r7, #44] ; 0x2c
|
|||
|
|
|
|||
|
|
/* Get SYSCLK source -------------------------------------------------------*/
|
|||
|
|
switch (tmpreg & RCC_CFGR_SWS)
|
|||
|
|
80055c0: 6afa ldr r2, [r7, #44] ; 0x2c
|
|||
|
|
80055c2: 230c movs r3, #12
|
|||
|
|
80055c4: 4013 ands r3, r2
|
|||
|
|
80055c6: 2b08 cmp r3, #8
|
|||
|
|
80055c8: d00f beq.n 80055ea <HAL_RCC_GetSysClockFreq+0x36>
|
|||
|
|
80055ca: 2b0c cmp r3, #12
|
|||
|
|
80055cc: d010 beq.n 80055f0 <HAL_RCC_GetSysClockFreq+0x3c>
|
|||
|
|
80055ce: 2b04 cmp r3, #4
|
|||
|
|
80055d0: d000 beq.n 80055d4 <HAL_RCC_GetSysClockFreq+0x20>
|
|||
|
|
80055d2: e073 b.n 80056bc <HAL_RCC_GetSysClockFreq+0x108>
|
|||
|
|
{
|
|||
|
|
case RCC_SYSCLKSOURCE_STATUS_HSI: /* HSI used as system clock source */
|
|||
|
|
{
|
|||
|
|
if ((RCC->CR & RCC_CR_HSIDIVF) != 0U)
|
|||
|
|
80055d4: 4b43 ldr r3, [pc, #268] ; (80056e4 <HAL_RCC_GetSysClockFreq+0x130>)
|
|||
|
|
80055d6: 681b ldr r3, [r3, #0]
|
|||
|
|
80055d8: 2210 movs r2, #16
|
|||
|
|
80055da: 4013 ands r3, r2
|
|||
|
|
80055dc: d002 beq.n 80055e4 <HAL_RCC_GetSysClockFreq+0x30>
|
|||
|
|
{
|
|||
|
|
sysclockfreq = (HSI_VALUE >> 2);
|
|||
|
|
80055de: 4b42 ldr r3, [pc, #264] ; (80056e8 <HAL_RCC_GetSysClockFreq+0x134>)
|
|||
|
|
80055e0: 633b str r3, [r7, #48] ; 0x30
|
|||
|
|
}
|
|||
|
|
else
|
|||
|
|
{
|
|||
|
|
sysclockfreq = HSI_VALUE;
|
|||
|
|
}
|
|||
|
|
break;
|
|||
|
|
80055e2: e079 b.n 80056d8 <HAL_RCC_GetSysClockFreq+0x124>
|
|||
|
|
sysclockfreq = HSI_VALUE;
|
|||
|
|
80055e4: 4b41 ldr r3, [pc, #260] ; (80056ec <HAL_RCC_GetSysClockFreq+0x138>)
|
|||
|
|
80055e6: 633b str r3, [r7, #48] ; 0x30
|
|||
|
|
break;
|
|||
|
|
80055e8: e076 b.n 80056d8 <HAL_RCC_GetSysClockFreq+0x124>
|
|||
|
|
}
|
|||
|
|
case RCC_SYSCLKSOURCE_STATUS_HSE: /* HSE used as system clock */
|
|||
|
|
{
|
|||
|
|
sysclockfreq = HSE_VALUE;
|
|||
|
|
80055ea: 4b41 ldr r3, [pc, #260] ; (80056f0 <HAL_RCC_GetSysClockFreq+0x13c>)
|
|||
|
|
80055ec: 633b str r3, [r7, #48] ; 0x30
|
|||
|
|
break;
|
|||
|
|
80055ee: e073 b.n 80056d8 <HAL_RCC_GetSysClockFreq+0x124>
|
|||
|
|
}
|
|||
|
|
case RCC_SYSCLKSOURCE_STATUS_PLLCLK: /* PLL used as system clock */
|
|||
|
|
{
|
|||
|
|
pllm = PLLMulTable[(uint32_t)(tmpreg & RCC_CFGR_PLLMUL) >> RCC_CFGR_PLLMUL_Pos];
|
|||
|
|
80055f0: 6afb ldr r3, [r7, #44] ; 0x2c
|
|||
|
|
80055f2: 0c9a lsrs r2, r3, #18
|
|||
|
|
80055f4: 230f movs r3, #15
|
|||
|
|
80055f6: 401a ands r2, r3
|
|||
|
|
80055f8: 4b3e ldr r3, [pc, #248] ; (80056f4 <HAL_RCC_GetSysClockFreq+0x140>)
|
|||
|
|
80055fa: 5c9b ldrb r3, [r3, r2]
|
|||
|
|
80055fc: 62bb str r3, [r7, #40] ; 0x28
|
|||
|
|
plld = ((uint32_t)(tmpreg & RCC_CFGR_PLLDIV) >> RCC_CFGR_PLLDIV_Pos) + 1U;
|
|||
|
|
80055fe: 6afb ldr r3, [r7, #44] ; 0x2c
|
|||
|
|
8005600: 0d9a lsrs r2, r3, #22
|
|||
|
|
8005602: 2303 movs r3, #3
|
|||
|
|
8005604: 4013 ands r3, r2
|
|||
|
|
8005606: 3301 adds r3, #1
|
|||
|
|
8005608: 627b str r3, [r7, #36] ; 0x24
|
|||
|
|
if (__HAL_RCC_GET_PLL_OSCSOURCE() != RCC_PLLSOURCE_HSI)
|
|||
|
|
800560a: 4b36 ldr r3, [pc, #216] ; (80056e4 <HAL_RCC_GetSysClockFreq+0x130>)
|
|||
|
|
800560c: 68da ldr r2, [r3, #12]
|
|||
|
|
800560e: 2380 movs r3, #128 ; 0x80
|
|||
|
|
8005610: 025b lsls r3, r3, #9
|
|||
|
|
8005612: 4013 ands r3, r2
|
|||
|
|
8005614: d019 beq.n 800564a <HAL_RCC_GetSysClockFreq+0x96>
|
|||
|
|
{
|
|||
|
|
/* HSE used as PLL clock source */
|
|||
|
|
pllvco = (uint32_t)(((uint64_t)HSE_VALUE * (uint64_t)pllm) / (uint64_t)plld);
|
|||
|
|
8005616: 6abb ldr r3, [r7, #40] ; 0x28
|
|||
|
|
8005618: 61bb str r3, [r7, #24]
|
|||
|
|
800561a: 2300 movs r3, #0
|
|||
|
|
800561c: 61fb str r3, [r7, #28]
|
|||
|
|
800561e: 4a34 ldr r2, [pc, #208] ; (80056f0 <HAL_RCC_GetSysClockFreq+0x13c>)
|
|||
|
|
8005620: 2300 movs r3, #0
|
|||
|
|
8005622: 69b8 ldr r0, [r7, #24]
|
|||
|
|
8005624: 69f9 ldr r1, [r7, #28]
|
|||
|
|
8005626: f7fa fe93 bl 8000350 <__aeabi_lmul>
|
|||
|
|
800562a: 0003 movs r3, r0
|
|||
|
|
800562c: 000c movs r4, r1
|
|||
|
|
800562e: 0018 movs r0, r3
|
|||
|
|
8005630: 0021 movs r1, r4
|
|||
|
|
8005632: 6a7b ldr r3, [r7, #36] ; 0x24
|
|||
|
|
8005634: 613b str r3, [r7, #16]
|
|||
|
|
8005636: 2300 movs r3, #0
|
|||
|
|
8005638: 617b str r3, [r7, #20]
|
|||
|
|
800563a: 693a ldr r2, [r7, #16]
|
|||
|
|
800563c: 697b ldr r3, [r7, #20]
|
|||
|
|
800563e: f7fa fe67 bl 8000310 <__aeabi_uldivmod>
|
|||
|
|
8005642: 0003 movs r3, r0
|
|||
|
|
8005644: 000c movs r4, r1
|
|||
|
|
8005646: 637b str r3, [r7, #52] ; 0x34
|
|||
|
|
8005648: e035 b.n 80056b6 <HAL_RCC_GetSysClockFreq+0x102>
|
|||
|
|
}
|
|||
|
|
else
|
|||
|
|
{
|
|||
|
|
if ((RCC->CR & RCC_CR_HSIDIVF) != 0U)
|
|||
|
|
800564a: 4b26 ldr r3, [pc, #152] ; (80056e4 <HAL_RCC_GetSysClockFreq+0x130>)
|
|||
|
|
800564c: 681b ldr r3, [r3, #0]
|
|||
|
|
800564e: 2210 movs r2, #16
|
|||
|
|
8005650: 4013 ands r3, r2
|
|||
|
|
8005652: d019 beq.n 8005688 <HAL_RCC_GetSysClockFreq+0xd4>
|
|||
|
|
{
|
|||
|
|
pllvco = (uint32_t)((((uint64_t)(HSI_VALUE >> 2)) * (uint64_t)pllm) / (uint64_t)plld);
|
|||
|
|
8005654: 6abb ldr r3, [r7, #40] ; 0x28
|
|||
|
|
8005656: 60bb str r3, [r7, #8]
|
|||
|
|
8005658: 2300 movs r3, #0
|
|||
|
|
800565a: 60fb str r3, [r7, #12]
|
|||
|
|
800565c: 4a22 ldr r2, [pc, #136] ; (80056e8 <HAL_RCC_GetSysClockFreq+0x134>)
|
|||
|
|
800565e: 2300 movs r3, #0
|
|||
|
|
8005660: 68b8 ldr r0, [r7, #8]
|
|||
|
|
8005662: 68f9 ldr r1, [r7, #12]
|
|||
|
|
8005664: f7fa fe74 bl 8000350 <__aeabi_lmul>
|
|||
|
|
8005668: 0003 movs r3, r0
|
|||
|
|
800566a: 000c movs r4, r1
|
|||
|
|
800566c: 0018 movs r0, r3
|
|||
|
|
800566e: 0021 movs r1, r4
|
|||
|
|
8005670: 6a7b ldr r3, [r7, #36] ; 0x24
|
|||
|
|
8005672: 603b str r3, [r7, #0]
|
|||
|
|
8005674: 2300 movs r3, #0
|
|||
|
|
8005676: 607b str r3, [r7, #4]
|
|||
|
|
8005678: 683a ldr r2, [r7, #0]
|
|||
|
|
800567a: 687b ldr r3, [r7, #4]
|
|||
|
|
800567c: f7fa fe48 bl 8000310 <__aeabi_uldivmod>
|
|||
|
|
8005680: 0003 movs r3, r0
|
|||
|
|
8005682: 000c movs r4, r1
|
|||
|
|
8005684: 637b str r3, [r7, #52] ; 0x34
|
|||
|
|
8005686: e016 b.n 80056b6 <HAL_RCC_GetSysClockFreq+0x102>
|
|||
|
|
}
|
|||
|
|
else
|
|||
|
|
{
|
|||
|
|
pllvco = (uint32_t)(((uint64_t)HSI_VALUE * (uint64_t)pllm) / (uint64_t)plld);
|
|||
|
|
8005688: 6abb ldr r3, [r7, #40] ; 0x28
|
|||
|
|
800568a: 0018 movs r0, r3
|
|||
|
|
800568c: 2300 movs r3, #0
|
|||
|
|
800568e: 0019 movs r1, r3
|
|||
|
|
8005690: 4a16 ldr r2, [pc, #88] ; (80056ec <HAL_RCC_GetSysClockFreq+0x138>)
|
|||
|
|
8005692: 2300 movs r3, #0
|
|||
|
|
8005694: f7fa fe5c bl 8000350 <__aeabi_lmul>
|
|||
|
|
8005698: 0003 movs r3, r0
|
|||
|
|
800569a: 000c movs r4, r1
|
|||
|
|
800569c: 0018 movs r0, r3
|
|||
|
|
800569e: 0021 movs r1, r4
|
|||
|
|
80056a0: 6a7b ldr r3, [r7, #36] ; 0x24
|
|||
|
|
80056a2: 001d movs r5, r3
|
|||
|
|
80056a4: 2300 movs r3, #0
|
|||
|
|
80056a6: 001e movs r6, r3
|
|||
|
|
80056a8: 002a movs r2, r5
|
|||
|
|
80056aa: 0033 movs r3, r6
|
|||
|
|
80056ac: f7fa fe30 bl 8000310 <__aeabi_uldivmod>
|
|||
|
|
80056b0: 0003 movs r3, r0
|
|||
|
|
80056b2: 000c movs r4, r1
|
|||
|
|
80056b4: 637b str r3, [r7, #52] ; 0x34
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
sysclockfreq = pllvco;
|
|||
|
|
80056b6: 6b7b ldr r3, [r7, #52] ; 0x34
|
|||
|
|
80056b8: 633b str r3, [r7, #48] ; 0x30
|
|||
|
|
break;
|
|||
|
|
80056ba: e00d b.n 80056d8 <HAL_RCC_GetSysClockFreq+0x124>
|
|||
|
|
}
|
|||
|
|
case RCC_SYSCLKSOURCE_STATUS_MSI: /* MSI used as system clock source */
|
|||
|
|
default: /* MSI used as system clock */
|
|||
|
|
{
|
|||
|
|
msiclkrange = (RCC->ICSCR & RCC_ICSCR_MSIRANGE ) >> RCC_ICSCR_MSIRANGE_Pos;
|
|||
|
|
80056bc: 4b09 ldr r3, [pc, #36] ; (80056e4 <HAL_RCC_GetSysClockFreq+0x130>)
|
|||
|
|
80056be: 685b ldr r3, [r3, #4]
|
|||
|
|
80056c0: 0b5b lsrs r3, r3, #13
|
|||
|
|
80056c2: 2207 movs r2, #7
|
|||
|
|
80056c4: 4013 ands r3, r2
|
|||
|
|
80056c6: 623b str r3, [r7, #32]
|
|||
|
|
sysclockfreq = (32768U * (1UL << (msiclkrange + 1U)));
|
|||
|
|
80056c8: 6a3b ldr r3, [r7, #32]
|
|||
|
|
80056ca: 3301 adds r3, #1
|
|||
|
|
80056cc: 2280 movs r2, #128 ; 0x80
|
|||
|
|
80056ce: 0212 lsls r2, r2, #8
|
|||
|
|
80056d0: 409a lsls r2, r3
|
|||
|
|
80056d2: 0013 movs r3, r2
|
|||
|
|
80056d4: 633b str r3, [r7, #48] ; 0x30
|
|||
|
|
break;
|
|||
|
|
80056d6: 46c0 nop ; (mov r8, r8)
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
return sysclockfreq;
|
|||
|
|
80056d8: 6b3b ldr r3, [r7, #48] ; 0x30
|
|||
|
|
}
|
|||
|
|
80056da: 0018 movs r0, r3
|
|||
|
|
80056dc: 46bd mov sp, r7
|
|||
|
|
80056de: b00f add sp, #60 ; 0x3c
|
|||
|
|
80056e0: bdf0 pop {r4, r5, r6, r7, pc}
|
|||
|
|
80056e2: 46c0 nop ; (mov r8, r8)
|
|||
|
|
80056e4: 40021000 .word 0x40021000
|
|||
|
|
80056e8: 003d0900 .word 0x003d0900
|
|||
|
|
80056ec: 00f42400 .word 0x00f42400
|
|||
|
|
80056f0: 007a1200 .word 0x007a1200
|
|||
|
|
80056f4: 080071e8 .word 0x080071e8
|
|||
|
|
|
|||
|
|
080056f8 <HAL_RCC_GetHCLKFreq>:
|
|||
|
|
* @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency
|
|||
|
|
* and updated within this function
|
|||
|
|
* @retval HCLK frequency
|
|||
|
|
*/
|
|||
|
|
uint32_t HAL_RCC_GetHCLKFreq(void)
|
|||
|
|
{
|
|||
|
|
80056f8: b580 push {r7, lr}
|
|||
|
|
80056fa: af00 add r7, sp, #0
|
|||
|
|
return SystemCoreClock;
|
|||
|
|
80056fc: 4b02 ldr r3, [pc, #8] ; (8005708 <HAL_RCC_GetHCLKFreq+0x10>)
|
|||
|
|
80056fe: 681b ldr r3, [r3, #0]
|
|||
|
|
}
|
|||
|
|
8005700: 0018 movs r0, r3
|
|||
|
|
8005702: 46bd mov sp, r7
|
|||
|
|
8005704: bd80 pop {r7, pc}
|
|||
|
|
8005706: 46c0 nop ; (mov r8, r8)
|
|||
|
|
8005708: 20000000 .word 0x20000000
|
|||
|
|
|
|||
|
|
0800570c <HAL_RCC_GetPCLK1Freq>:
|
|||
|
|
* @note Each time PCLK1 changes, this function must be called to update the
|
|||
|
|
* right PCLK1 value. Otherwise, any configuration based on this function will be incorrect.
|
|||
|
|
* @retval PCLK1 frequency
|
|||
|
|
*/
|
|||
|
|
uint32_t HAL_RCC_GetPCLK1Freq(void)
|
|||
|
|
{
|
|||
|
|
800570c: b580 push {r7, lr}
|
|||
|
|
800570e: af00 add r7, sp, #0
|
|||
|
|
/* Get HCLK source and Compute PCLK1 frequency ---------------------------*/
|
|||
|
|
return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE1) >> RCC_CFGR_PPRE1_Pos]);
|
|||
|
|
8005710: f7ff fff2 bl 80056f8 <HAL_RCC_GetHCLKFreq>
|
|||
|
|
8005714: 0001 movs r1, r0
|
|||
|
|
8005716: 4b06 ldr r3, [pc, #24] ; (8005730 <HAL_RCC_GetPCLK1Freq+0x24>)
|
|||
|
|
8005718: 68db ldr r3, [r3, #12]
|
|||
|
|
800571a: 0a1b lsrs r3, r3, #8
|
|||
|
|
800571c: 2207 movs r2, #7
|
|||
|
|
800571e: 4013 ands r3, r2
|
|||
|
|
8005720: 4a04 ldr r2, [pc, #16] ; (8005734 <HAL_RCC_GetPCLK1Freq+0x28>)
|
|||
|
|
8005722: 5cd3 ldrb r3, [r2, r3]
|
|||
|
|
8005724: 40d9 lsrs r1, r3
|
|||
|
|
8005726: 000b movs r3, r1
|
|||
|
|
}
|
|||
|
|
8005728: 0018 movs r0, r3
|
|||
|
|
800572a: 46bd mov sp, r7
|
|||
|
|
800572c: bd80 pop {r7, pc}
|
|||
|
|
800572e: 46c0 nop ; (mov r8, r8)
|
|||
|
|
8005730: 40021000 .word 0x40021000
|
|||
|
|
8005734: 080071e0 .word 0x080071e0
|
|||
|
|
|
|||
|
|
08005738 <HAL_RCC_GetPCLK2Freq>:
|
|||
|
|
* @note Each time PCLK2 changes, this function must be called to update the
|
|||
|
|
* right PCLK2 value. Otherwise, any configuration based on this function will be incorrect.
|
|||
|
|
* @retval PCLK2 frequency
|
|||
|
|
*/
|
|||
|
|
uint32_t HAL_RCC_GetPCLK2Freq(void)
|
|||
|
|
{
|
|||
|
|
8005738: b580 push {r7, lr}
|
|||
|
|
800573a: af00 add r7, sp, #0
|
|||
|
|
/* Get HCLK source and Compute PCLK2 frequency ---------------------------*/
|
|||
|
|
return (HAL_RCC_GetHCLKFreq()>> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE2) >> RCC_CFGR_PPRE2_Pos]);
|
|||
|
|
800573c: f7ff ffdc bl 80056f8 <HAL_RCC_GetHCLKFreq>
|
|||
|
|
8005740: 0001 movs r1, r0
|
|||
|
|
8005742: 4b06 ldr r3, [pc, #24] ; (800575c <HAL_RCC_GetPCLK2Freq+0x24>)
|
|||
|
|
8005744: 68db ldr r3, [r3, #12]
|
|||
|
|
8005746: 0adb lsrs r3, r3, #11
|
|||
|
|
8005748: 2207 movs r2, #7
|
|||
|
|
800574a: 4013 ands r3, r2
|
|||
|
|
800574c: 4a04 ldr r2, [pc, #16] ; (8005760 <HAL_RCC_GetPCLK2Freq+0x28>)
|
|||
|
|
800574e: 5cd3 ldrb r3, [r2, r3]
|
|||
|
|
8005750: 40d9 lsrs r1, r3
|
|||
|
|
8005752: 000b movs r3, r1
|
|||
|
|
}
|
|||
|
|
8005754: 0018 movs r0, r3
|
|||
|
|
8005756: 46bd mov sp, r7
|
|||
|
|
8005758: bd80 pop {r7, pc}
|
|||
|
|
800575a: 46c0 nop ; (mov r8, r8)
|
|||
|
|
800575c: 40021000 .word 0x40021000
|
|||
|
|
8005760: 080071e0 .word 0x080071e0
|
|||
|
|
|
|||
|
|
08005764 <HAL_RCCEx_PeriphCLKConfig>:
|
|||
|
|
* @retval HAL status
|
|||
|
|
* @note If HAL_ERROR returned, first switch-OFF HSE clock oscillator with @ref HAL_RCC_OscConfig()
|
|||
|
|
* to possibly update HSE divider.
|
|||
|
|
*/
|
|||
|
|
HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
|
|||
|
|
{
|
|||
|
|
8005764: b580 push {r7, lr}
|
|||
|
|
8005766: b086 sub sp, #24
|
|||
|
|
8005768: af00 add r7, sp, #0
|
|||
|
|
800576a: 6078 str r0, [r7, #4]
|
|||
|
|
uint32_t tickstart;
|
|||
|
|
uint32_t temp_reg;
|
|||
|
|
FlagStatus pwrclkchanged = RESET;
|
|||
|
|
800576c: 2317 movs r3, #23
|
|||
|
|
800576e: 18fb adds r3, r7, r3
|
|||
|
|
8005770: 2200 movs r2, #0
|
|||
|
|
8005772: 701a strb r2, [r3, #0]
|
|||
|
|
|
|||
|
|
/* Check the parameters */
|
|||
|
|
assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection));
|
|||
|
|
|
|||
|
|
/*------------------------------- RTC/LCD Configuration ------------------------*/
|
|||
|
|
if ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC)
|
|||
|
|
8005774: 687b ldr r3, [r7, #4]
|
|||
|
|
8005776: 681b ldr r3, [r3, #0]
|
|||
|
|
8005778: 2220 movs r2, #32
|
|||
|
|
800577a: 4013 ands r3, r2
|
|||
|
|
800577c: d100 bne.n 8005780 <HAL_RCCEx_PeriphCLKConfig+0x1c>
|
|||
|
|
800577e: e0c2 b.n 8005906 <HAL_RCCEx_PeriphCLKConfig+0x1a2>
|
|||
|
|
#endif /* LCD */
|
|||
|
|
|
|||
|
|
/* As soon as function is called to change RTC clock source, activation of the
|
|||
|
|
power domain is done. */
|
|||
|
|
/* Requires to enable write access to Backup Domain of necessary */
|
|||
|
|
if(__HAL_RCC_PWR_IS_CLK_DISABLED())
|
|||
|
|
8005780: 4b96 ldr r3, [pc, #600] ; (80059dc <HAL_RCCEx_PeriphCLKConfig+0x278>)
|
|||
|
|
8005782: 6b9a ldr r2, [r3, #56] ; 0x38
|
|||
|
|
8005784: 2380 movs r3, #128 ; 0x80
|
|||
|
|
8005786: 055b lsls r3, r3, #21
|
|||
|
|
8005788: 4013 ands r3, r2
|
|||
|
|
800578a: d10a bne.n 80057a2 <HAL_RCCEx_PeriphCLKConfig+0x3e>
|
|||
|
|
{
|
|||
|
|
__HAL_RCC_PWR_CLK_ENABLE();
|
|||
|
|
800578c: 4b93 ldr r3, [pc, #588] ; (80059dc <HAL_RCCEx_PeriphCLKConfig+0x278>)
|
|||
|
|
800578e: 4a93 ldr r2, [pc, #588] ; (80059dc <HAL_RCCEx_PeriphCLKConfig+0x278>)
|
|||
|
|
8005790: 6b92 ldr r2, [r2, #56] ; 0x38
|
|||
|
|
8005792: 2180 movs r1, #128 ; 0x80
|
|||
|
|
8005794: 0549 lsls r1, r1, #21
|
|||
|
|
8005796: 430a orrs r2, r1
|
|||
|
|
8005798: 639a str r2, [r3, #56] ; 0x38
|
|||
|
|
pwrclkchanged = SET;
|
|||
|
|
800579a: 2317 movs r3, #23
|
|||
|
|
800579c: 18fb adds r3, r7, r3
|
|||
|
|
800579e: 2201 movs r2, #1
|
|||
|
|
80057a0: 701a strb r2, [r3, #0]
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
if(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
|
|||
|
|
80057a2: 4b8f ldr r3, [pc, #572] ; (80059e0 <HAL_RCCEx_PeriphCLKConfig+0x27c>)
|
|||
|
|
80057a4: 681a ldr r2, [r3, #0]
|
|||
|
|
80057a6: 2380 movs r3, #128 ; 0x80
|
|||
|
|
80057a8: 005b lsls r3, r3, #1
|
|||
|
|
80057aa: 4013 ands r3, r2
|
|||
|
|
80057ac: d11a bne.n 80057e4 <HAL_RCCEx_PeriphCLKConfig+0x80>
|
|||
|
|
{
|
|||
|
|
/* Enable write access to Backup domain */
|
|||
|
|
SET_BIT(PWR->CR, PWR_CR_DBP);
|
|||
|
|
80057ae: 4b8c ldr r3, [pc, #560] ; (80059e0 <HAL_RCCEx_PeriphCLKConfig+0x27c>)
|
|||
|
|
80057b0: 4a8b ldr r2, [pc, #556] ; (80059e0 <HAL_RCCEx_PeriphCLKConfig+0x27c>)
|
|||
|
|
80057b2: 6812 ldr r2, [r2, #0]
|
|||
|
|
80057b4: 2180 movs r1, #128 ; 0x80
|
|||
|
|
80057b6: 0049 lsls r1, r1, #1
|
|||
|
|
80057b8: 430a orrs r2, r1
|
|||
|
|
80057ba: 601a str r2, [r3, #0]
|
|||
|
|
|
|||
|
|
/* Wait for Backup domain Write protection disable */
|
|||
|
|
tickstart = HAL_GetTick();
|
|||
|
|
80057bc: f7fe fbb6 bl 8003f2c <HAL_GetTick>
|
|||
|
|
80057c0: 0003 movs r3, r0
|
|||
|
|
80057c2: 613b str r3, [r7, #16]
|
|||
|
|
|
|||
|
|
while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
|
|||
|
|
80057c4: e008 b.n 80057d8 <HAL_RCCEx_PeriphCLKConfig+0x74>
|
|||
|
|
{
|
|||
|
|
if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
|
|||
|
|
80057c6: f7fe fbb1 bl 8003f2c <HAL_GetTick>
|
|||
|
|
80057ca: 0002 movs r2, r0
|
|||
|
|
80057cc: 693b ldr r3, [r7, #16]
|
|||
|
|
80057ce: 1ad3 subs r3, r2, r3
|
|||
|
|
80057d0: 2b64 cmp r3, #100 ; 0x64
|
|||
|
|
80057d2: d901 bls.n 80057d8 <HAL_RCCEx_PeriphCLKConfig+0x74>
|
|||
|
|
{
|
|||
|
|
return HAL_TIMEOUT;
|
|||
|
|
80057d4: 2303 movs r3, #3
|
|||
|
|
80057d6: e0fc b.n 80059d2 <HAL_RCCEx_PeriphCLKConfig+0x26e>
|
|||
|
|
while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
|
|||
|
|
80057d8: 4b81 ldr r3, [pc, #516] ; (80059e0 <HAL_RCCEx_PeriphCLKConfig+0x27c>)
|
|||
|
|
80057da: 681a ldr r2, [r3, #0]
|
|||
|
|
80057dc: 2380 movs r3, #128 ; 0x80
|
|||
|
|
80057de: 005b lsls r3, r3, #1
|
|||
|
|
80057e0: 4013 ands r3, r2
|
|||
|
|
80057e2: d0f0 beq.n 80057c6 <HAL_RCCEx_PeriphCLKConfig+0x62>
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
/* Check if user wants to change HSE RTC prescaler whereas HSE is enabled */
|
|||
|
|
temp_reg = (RCC->CR & RCC_CR_RTCPRE);
|
|||
|
|
80057e4: 4b7d ldr r3, [pc, #500] ; (80059dc <HAL_RCCEx_PeriphCLKConfig+0x278>)
|
|||
|
|
80057e6: 681a ldr r2, [r3, #0]
|
|||
|
|
80057e8: 23c0 movs r3, #192 ; 0xc0
|
|||
|
|
80057ea: 039b lsls r3, r3, #14
|
|||
|
|
80057ec: 4013 ands r3, r2
|
|||
|
|
80057ee: 60fb str r3, [r7, #12]
|
|||
|
|
if ((temp_reg != (PeriphClkInit->RTCClockSelection & RCC_CR_RTCPRE))
|
|||
|
|
80057f0: 687b ldr r3, [r7, #4]
|
|||
|
|
80057f2: 685a ldr r2, [r3, #4]
|
|||
|
|
80057f4: 23c0 movs r3, #192 ; 0xc0
|
|||
|
|
80057f6: 039b lsls r3, r3, #14
|
|||
|
|
80057f8: 401a ands r2, r3
|
|||
|
|
80057fa: 68fb ldr r3, [r7, #12]
|
|||
|
|
80057fc: 429a cmp r2, r3
|
|||
|
|
80057fe: d013 beq.n 8005828 <HAL_RCCEx_PeriphCLKConfig+0xc4>
|
|||
|
|
#if defined (LCD)
|
|||
|
|
|| (temp_reg != (PeriphClkInit->LCDClockSelection & RCC_CR_RTCPRE))
|
|||
|
|
#endif /* LCD */
|
|||
|
|
)
|
|||
|
|
{ /* Check HSE State */
|
|||
|
|
if ((PeriphClkInit->RTCClockSelection & RCC_CSR_RTCSEL) == RCC_CSR_RTCSEL_HSE)
|
|||
|
|
8005800: 687b ldr r3, [r7, #4]
|
|||
|
|
8005802: 685a ldr r2, [r3, #4]
|
|||
|
|
8005804: 23c0 movs r3, #192 ; 0xc0
|
|||
|
|
8005806: 029b lsls r3, r3, #10
|
|||
|
|
8005808: 401a ands r2, r3
|
|||
|
|
800580a: 23c0 movs r3, #192 ; 0xc0
|
|||
|
|
800580c: 029b lsls r3, r3, #10
|
|||
|
|
800580e: 429a cmp r2, r3
|
|||
|
|
8005810: d10a bne.n 8005828 <HAL_RCCEx_PeriphCLKConfig+0xc4>
|
|||
|
|
{
|
|||
|
|
if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY))
|
|||
|
|
8005812: 4b72 ldr r3, [pc, #456] ; (80059dc <HAL_RCCEx_PeriphCLKConfig+0x278>)
|
|||
|
|
8005814: 681a ldr r2, [r3, #0]
|
|||
|
|
8005816: 2380 movs r3, #128 ; 0x80
|
|||
|
|
8005818: 029b lsls r3, r3, #10
|
|||
|
|
800581a: 401a ands r2, r3
|
|||
|
|
800581c: 2380 movs r3, #128 ; 0x80
|
|||
|
|
800581e: 029b lsls r3, r3, #10
|
|||
|
|
8005820: 429a cmp r2, r3
|
|||
|
|
8005822: d101 bne.n 8005828 <HAL_RCCEx_PeriphCLKConfig+0xc4>
|
|||
|
|
{
|
|||
|
|
/* To update HSE divider, first switch-OFF HSE clock oscillator*/
|
|||
|
|
return HAL_ERROR;
|
|||
|
|
8005824: 2301 movs r3, #1
|
|||
|
|
8005826: e0d4 b.n 80059d2 <HAL_RCCEx_PeriphCLKConfig+0x26e>
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
/* Reset the Backup domain only if the RTC Clock source selection is modified from reset value */
|
|||
|
|
temp_reg = (RCC->CSR & RCC_CSR_RTCSEL);
|
|||
|
|
8005828: 4b6c ldr r3, [pc, #432] ; (80059dc <HAL_RCCEx_PeriphCLKConfig+0x278>)
|
|||
|
|
800582a: 6d1a ldr r2, [r3, #80] ; 0x50
|
|||
|
|
800582c: 23c0 movs r3, #192 ; 0xc0
|
|||
|
|
800582e: 029b lsls r3, r3, #10
|
|||
|
|
8005830: 4013 ands r3, r2
|
|||
|
|
8005832: 60fb str r3, [r7, #12]
|
|||
|
|
|
|||
|
|
if((temp_reg != 0x00000000U) && (((temp_reg != (PeriphClkInit->RTCClockSelection & RCC_CSR_RTCSEL)) \
|
|||
|
|
8005834: 68fb ldr r3, [r7, #12]
|
|||
|
|
8005836: 2b00 cmp r3, #0
|
|||
|
|
8005838: d03b beq.n 80058b2 <HAL_RCCEx_PeriphCLKConfig+0x14e>
|
|||
|
|
800583a: 687b ldr r3, [r7, #4]
|
|||
|
|
800583c: 685a ldr r2, [r3, #4]
|
|||
|
|
800583e: 23c0 movs r3, #192 ; 0xc0
|
|||
|
|
8005840: 029b lsls r3, r3, #10
|
|||
|
|
8005842: 401a ands r2, r3
|
|||
|
|
8005844: 68fb ldr r3, [r7, #12]
|
|||
|
|
8005846: 429a cmp r2, r3
|
|||
|
|
8005848: d033 beq.n 80058b2 <HAL_RCCEx_PeriphCLKConfig+0x14e>
|
|||
|
|
&& (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC))
|
|||
|
|
800584a: 687b ldr r3, [r7, #4]
|
|||
|
|
800584c: 681b ldr r3, [r3, #0]
|
|||
|
|
800584e: 2220 movs r2, #32
|
|||
|
|
8005850: 4013 ands r3, r2
|
|||
|
|
8005852: d02e beq.n 80058b2 <HAL_RCCEx_PeriphCLKConfig+0x14e>
|
|||
|
|
&& (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LCD) == RCC_PERIPHCLK_LCD))
|
|||
|
|
#endif /* LCD */
|
|||
|
|
))
|
|||
|
|
{
|
|||
|
|
/* Store the content of CSR register before the reset of Backup Domain */
|
|||
|
|
temp_reg = (RCC->CSR & ~(RCC_CSR_RTCSEL));
|
|||
|
|
8005854: 4b61 ldr r3, [pc, #388] ; (80059dc <HAL_RCCEx_PeriphCLKConfig+0x278>)
|
|||
|
|
8005856: 6d1b ldr r3, [r3, #80] ; 0x50
|
|||
|
|
8005858: 4a62 ldr r2, [pc, #392] ; (80059e4 <HAL_RCCEx_PeriphCLKConfig+0x280>)
|
|||
|
|
800585a: 4013 ands r3, r2
|
|||
|
|
800585c: 60fb str r3, [r7, #12]
|
|||
|
|
|
|||
|
|
/* RTC Clock selection can be changed only if the Backup Domain is reset */
|
|||
|
|
__HAL_RCC_BACKUPRESET_FORCE();
|
|||
|
|
800585e: 4b5f ldr r3, [pc, #380] ; (80059dc <HAL_RCCEx_PeriphCLKConfig+0x278>)
|
|||
|
|
8005860: 4a5e ldr r2, [pc, #376] ; (80059dc <HAL_RCCEx_PeriphCLKConfig+0x278>)
|
|||
|
|
8005862: 6d12 ldr r2, [r2, #80] ; 0x50
|
|||
|
|
8005864: 2180 movs r1, #128 ; 0x80
|
|||
|
|
8005866: 0309 lsls r1, r1, #12
|
|||
|
|
8005868: 430a orrs r2, r1
|
|||
|
|
800586a: 651a str r2, [r3, #80] ; 0x50
|
|||
|
|
__HAL_RCC_BACKUPRESET_RELEASE();
|
|||
|
|
800586c: 4b5b ldr r3, [pc, #364] ; (80059dc <HAL_RCCEx_PeriphCLKConfig+0x278>)
|
|||
|
|
800586e: 4a5b ldr r2, [pc, #364] ; (80059dc <HAL_RCCEx_PeriphCLKConfig+0x278>)
|
|||
|
|
8005870: 6d12 ldr r2, [r2, #80] ; 0x50
|
|||
|
|
8005872: 495d ldr r1, [pc, #372] ; (80059e8 <HAL_RCCEx_PeriphCLKConfig+0x284>)
|
|||
|
|
8005874: 400a ands r2, r1
|
|||
|
|
8005876: 651a str r2, [r3, #80] ; 0x50
|
|||
|
|
|
|||
|
|
/* Restore the Content of CSR register */
|
|||
|
|
RCC->CSR = temp_reg;
|
|||
|
|
8005878: 4b58 ldr r3, [pc, #352] ; (80059dc <HAL_RCCEx_PeriphCLKConfig+0x278>)
|
|||
|
|
800587a: 68fa ldr r2, [r7, #12]
|
|||
|
|
800587c: 651a str r2, [r3, #80] ; 0x50
|
|||
|
|
|
|||
|
|
/* Wait for LSERDY if LSE was enabled */
|
|||
|
|
if (HAL_IS_BIT_SET(temp_reg, RCC_CSR_LSEON))
|
|||
|
|
800587e: 68fa ldr r2, [r7, #12]
|
|||
|
|
8005880: 2380 movs r3, #128 ; 0x80
|
|||
|
|
8005882: 005b lsls r3, r3, #1
|
|||
|
|
8005884: 4013 ands r3, r2
|
|||
|
|
8005886: d014 beq.n 80058b2 <HAL_RCCEx_PeriphCLKConfig+0x14e>
|
|||
|
|
{
|
|||
|
|
/* Get Start Tick */
|
|||
|
|
tickstart = HAL_GetTick();
|
|||
|
|
8005888: f7fe fb50 bl 8003f2c <HAL_GetTick>
|
|||
|
|
800588c: 0003 movs r3, r0
|
|||
|
|
800588e: 613b str r3, [r7, #16]
|
|||
|
|
|
|||
|
|
/* Wait till LSE is ready */
|
|||
|
|
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == 0U)
|
|||
|
|
8005890: e009 b.n 80058a6 <HAL_RCCEx_PeriphCLKConfig+0x142>
|
|||
|
|
{
|
|||
|
|
if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
|
|||
|
|
8005892: f7fe fb4b bl 8003f2c <HAL_GetTick>
|
|||
|
|
8005896: 0002 movs r2, r0
|
|||
|
|
8005898: 693b ldr r3, [r7, #16]
|
|||
|
|
800589a: 1ad3 subs r3, r2, r3
|
|||
|
|
800589c: 4a53 ldr r2, [pc, #332] ; (80059ec <HAL_RCCEx_PeriphCLKConfig+0x288>)
|
|||
|
|
800589e: 4293 cmp r3, r2
|
|||
|
|
80058a0: d901 bls.n 80058a6 <HAL_RCCEx_PeriphCLKConfig+0x142>
|
|||
|
|
{
|
|||
|
|
return HAL_TIMEOUT;
|
|||
|
|
80058a2: 2303 movs r3, #3
|
|||
|
|
80058a4: e095 b.n 80059d2 <HAL_RCCEx_PeriphCLKConfig+0x26e>
|
|||
|
|
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == 0U)
|
|||
|
|
80058a6: 4b4d ldr r3, [pc, #308] ; (80059dc <HAL_RCCEx_PeriphCLKConfig+0x278>)
|
|||
|
|
80058a8: 6d1a ldr r2, [r3, #80] ; 0x50
|
|||
|
|
80058aa: 2380 movs r3, #128 ; 0x80
|
|||
|
|
80058ac: 009b lsls r3, r3, #2
|
|||
|
|
80058ae: 4013 ands r3, r2
|
|||
|
|
80058b0: d0ef beq.n 8005892 <HAL_RCCEx_PeriphCLKConfig+0x12e>
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
__HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);
|
|||
|
|
80058b2: 687b ldr r3, [r7, #4]
|
|||
|
|
80058b4: 685a ldr r2, [r3, #4]
|
|||
|
|
80058b6: 23c0 movs r3, #192 ; 0xc0
|
|||
|
|
80058b8: 029b lsls r3, r3, #10
|
|||
|
|
80058ba: 401a ands r2, r3
|
|||
|
|
80058bc: 23c0 movs r3, #192 ; 0xc0
|
|||
|
|
80058be: 029b lsls r3, r3, #10
|
|||
|
|
80058c0: 429a cmp r2, r3
|
|||
|
|
80058c2: d10b bne.n 80058dc <HAL_RCCEx_PeriphCLKConfig+0x178>
|
|||
|
|
80058c4: 4a45 ldr r2, [pc, #276] ; (80059dc <HAL_RCCEx_PeriphCLKConfig+0x278>)
|
|||
|
|
80058c6: 4b45 ldr r3, [pc, #276] ; (80059dc <HAL_RCCEx_PeriphCLKConfig+0x278>)
|
|||
|
|
80058c8: 681b ldr r3, [r3, #0]
|
|||
|
|
80058ca: 4949 ldr r1, [pc, #292] ; (80059f0 <HAL_RCCEx_PeriphCLKConfig+0x28c>)
|
|||
|
|
80058cc: 4019 ands r1, r3
|
|||
|
|
80058ce: 687b ldr r3, [r7, #4]
|
|||
|
|
80058d0: 6858 ldr r0, [r3, #4]
|
|||
|
|
80058d2: 23c0 movs r3, #192 ; 0xc0
|
|||
|
|
80058d4: 039b lsls r3, r3, #14
|
|||
|
|
80058d6: 4003 ands r3, r0
|
|||
|
|
80058d8: 430b orrs r3, r1
|
|||
|
|
80058da: 6013 str r3, [r2, #0]
|
|||
|
|
80058dc: 4a3f ldr r2, [pc, #252] ; (80059dc <HAL_RCCEx_PeriphCLKConfig+0x278>)
|
|||
|
|
80058de: 4b3f ldr r3, [pc, #252] ; (80059dc <HAL_RCCEx_PeriphCLKConfig+0x278>)
|
|||
|
|
80058e0: 6d19 ldr r1, [r3, #80] ; 0x50
|
|||
|
|
80058e2: 687b ldr r3, [r7, #4]
|
|||
|
|
80058e4: 6858 ldr r0, [r3, #4]
|
|||
|
|
80058e6: 23c0 movs r3, #192 ; 0xc0
|
|||
|
|
80058e8: 029b lsls r3, r3, #10
|
|||
|
|
80058ea: 4003 ands r3, r0
|
|||
|
|
80058ec: 430b orrs r3, r1
|
|||
|
|
80058ee: 6513 str r3, [r2, #80] ; 0x50
|
|||
|
|
|
|||
|
|
/* Require to disable power clock if necessary */
|
|||
|
|
if(pwrclkchanged == SET)
|
|||
|
|
80058f0: 2317 movs r3, #23
|
|||
|
|
80058f2: 18fb adds r3, r7, r3
|
|||
|
|
80058f4: 781b ldrb r3, [r3, #0]
|
|||
|
|
80058f6: 2b01 cmp r3, #1
|
|||
|
|
80058f8: d105 bne.n 8005906 <HAL_RCCEx_PeriphCLKConfig+0x1a2>
|
|||
|
|
{
|
|||
|
|
__HAL_RCC_PWR_CLK_DISABLE();
|
|||
|
|
80058fa: 4b38 ldr r3, [pc, #224] ; (80059dc <HAL_RCCEx_PeriphCLKConfig+0x278>)
|
|||
|
|
80058fc: 4a37 ldr r2, [pc, #220] ; (80059dc <HAL_RCCEx_PeriphCLKConfig+0x278>)
|
|||
|
|
80058fe: 6b92 ldr r2, [r2, #56] ; 0x38
|
|||
|
|
8005900: 493c ldr r1, [pc, #240] ; (80059f4 <HAL_RCCEx_PeriphCLKConfig+0x290>)
|
|||
|
|
8005902: 400a ands r2, r1
|
|||
|
|
8005904: 639a str r2, [r3, #56] ; 0x38
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
#if defined (RCC_CCIPR_USART1SEL)
|
|||
|
|
/*------------------------------- USART1 Configuration ------------------------*/
|
|||
|
|
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1)
|
|||
|
|
8005906: 687b ldr r3, [r7, #4]
|
|||
|
|
8005908: 681b ldr r3, [r3, #0]
|
|||
|
|
800590a: 2201 movs r2, #1
|
|||
|
|
800590c: 4013 ands r3, r2
|
|||
|
|
800590e: d009 beq.n 8005924 <HAL_RCCEx_PeriphCLKConfig+0x1c0>
|
|||
|
|
{
|
|||
|
|
/* Check the parameters */
|
|||
|
|
assert_param(IS_RCC_USART1CLKSOURCE(PeriphClkInit->Usart1ClockSelection));
|
|||
|
|
|
|||
|
|
/* Configure the USART1 clock source */
|
|||
|
|
__HAL_RCC_USART1_CONFIG(PeriphClkInit->Usart1ClockSelection);
|
|||
|
|
8005910: 4a32 ldr r2, [pc, #200] ; (80059dc <HAL_RCCEx_PeriphCLKConfig+0x278>)
|
|||
|
|
8005912: 4b32 ldr r3, [pc, #200] ; (80059dc <HAL_RCCEx_PeriphCLKConfig+0x278>)
|
|||
|
|
8005914: 6cdb ldr r3, [r3, #76] ; 0x4c
|
|||
|
|
8005916: 2103 movs r1, #3
|
|||
|
|
8005918: 438b bics r3, r1
|
|||
|
|
800591a: 0019 movs r1, r3
|
|||
|
|
800591c: 687b ldr r3, [r7, #4]
|
|||
|
|
800591e: 689b ldr r3, [r3, #8]
|
|||
|
|
8005920: 430b orrs r3, r1
|
|||
|
|
8005922: 64d3 str r3, [r2, #76] ; 0x4c
|
|||
|
|
}
|
|||
|
|
#endif /* RCC_CCIPR_USART1SEL */
|
|||
|
|
|
|||
|
|
/*----------------------------- USART2 Configuration --------------------------*/
|
|||
|
|
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2)
|
|||
|
|
8005924: 687b ldr r3, [r7, #4]
|
|||
|
|
8005926: 681b ldr r3, [r3, #0]
|
|||
|
|
8005928: 2202 movs r2, #2
|
|||
|
|
800592a: 4013 ands r3, r2
|
|||
|
|
800592c: d009 beq.n 8005942 <HAL_RCCEx_PeriphCLKConfig+0x1de>
|
|||
|
|
{
|
|||
|
|
/* Check the parameters */
|
|||
|
|
assert_param(IS_RCC_USART2CLKSOURCE(PeriphClkInit->Usart2ClockSelection));
|
|||
|
|
|
|||
|
|
/* Configure the USART2 clock source */
|
|||
|
|
__HAL_RCC_USART2_CONFIG(PeriphClkInit->Usart2ClockSelection);
|
|||
|
|
800592e: 4a2b ldr r2, [pc, #172] ; (80059dc <HAL_RCCEx_PeriphCLKConfig+0x278>)
|
|||
|
|
8005930: 4b2a ldr r3, [pc, #168] ; (80059dc <HAL_RCCEx_PeriphCLKConfig+0x278>)
|
|||
|
|
8005932: 6cdb ldr r3, [r3, #76] ; 0x4c
|
|||
|
|
8005934: 210c movs r1, #12
|
|||
|
|
8005936: 438b bics r3, r1
|
|||
|
|
8005938: 0019 movs r1, r3
|
|||
|
|
800593a: 687b ldr r3, [r7, #4]
|
|||
|
|
800593c: 68db ldr r3, [r3, #12]
|
|||
|
|
800593e: 430b orrs r3, r1
|
|||
|
|
8005940: 64d3 str r3, [r2, #76] ; 0x4c
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
/*------------------------------ LPUART1 Configuration ------------------------*/
|
|||
|
|
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1)
|
|||
|
|
8005942: 687b ldr r3, [r7, #4]
|
|||
|
|
8005944: 681b ldr r3, [r3, #0]
|
|||
|
|
8005946: 2204 movs r2, #4
|
|||
|
|
8005948: 4013 ands r3, r2
|
|||
|
|
800594a: d008 beq.n 800595e <HAL_RCCEx_PeriphCLKConfig+0x1fa>
|
|||
|
|
{
|
|||
|
|
/* Check the parameters */
|
|||
|
|
assert_param(IS_RCC_LPUART1CLKSOURCE(PeriphClkInit->Lpuart1ClockSelection));
|
|||
|
|
|
|||
|
|
/* Configure the LPUAR1 clock source */
|
|||
|
|
__HAL_RCC_LPUART1_CONFIG(PeriphClkInit->Lpuart1ClockSelection);
|
|||
|
|
800594c: 4a23 ldr r2, [pc, #140] ; (80059dc <HAL_RCCEx_PeriphCLKConfig+0x278>)
|
|||
|
|
800594e: 4b23 ldr r3, [pc, #140] ; (80059dc <HAL_RCCEx_PeriphCLKConfig+0x278>)
|
|||
|
|
8005950: 6cdb ldr r3, [r3, #76] ; 0x4c
|
|||
|
|
8005952: 4929 ldr r1, [pc, #164] ; (80059f8 <HAL_RCCEx_PeriphCLKConfig+0x294>)
|
|||
|
|
8005954: 4019 ands r1, r3
|
|||
|
|
8005956: 687b ldr r3, [r7, #4]
|
|||
|
|
8005958: 691b ldr r3, [r3, #16]
|
|||
|
|
800595a: 430b orrs r3, r1
|
|||
|
|
800595c: 64d3 str r3, [r2, #76] ; 0x4c
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
/*------------------------------ I2C1 Configuration ------------------------*/
|
|||
|
|
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1)
|
|||
|
|
800595e: 687b ldr r3, [r7, #4]
|
|||
|
|
8005960: 681b ldr r3, [r3, #0]
|
|||
|
|
8005962: 2208 movs r2, #8
|
|||
|
|
8005964: 4013 ands r3, r2
|
|||
|
|
8005966: d008 beq.n 800597a <HAL_RCCEx_PeriphCLKConfig+0x216>
|
|||
|
|
{
|
|||
|
|
/* Check the parameters */
|
|||
|
|
assert_param(IS_RCC_I2C1CLKSOURCE(PeriphClkInit->I2c1ClockSelection));
|
|||
|
|
|
|||
|
|
/* Configure the I2C1 clock source */
|
|||
|
|
__HAL_RCC_I2C1_CONFIG(PeriphClkInit->I2c1ClockSelection);
|
|||
|
|
8005968: 4a1c ldr r2, [pc, #112] ; (80059dc <HAL_RCCEx_PeriphCLKConfig+0x278>)
|
|||
|
|
800596a: 4b1c ldr r3, [pc, #112] ; (80059dc <HAL_RCCEx_PeriphCLKConfig+0x278>)
|
|||
|
|
800596c: 6cdb ldr r3, [r3, #76] ; 0x4c
|
|||
|
|
800596e: 4923 ldr r1, [pc, #140] ; (80059fc <HAL_RCCEx_PeriphCLKConfig+0x298>)
|
|||
|
|
8005970: 4019 ands r1, r3
|
|||
|
|
8005972: 687b ldr r3, [r7, #4]
|
|||
|
|
8005974: 695b ldr r3, [r3, #20]
|
|||
|
|
8005976: 430b orrs r3, r1
|
|||
|
|
8005978: 64d3 str r3, [r2, #76] ; 0x4c
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
#if defined (RCC_CCIPR_I2C3SEL)
|
|||
|
|
/*------------------------------ I2C3 Configuration ------------------------*/
|
|||
|
|
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3)
|
|||
|
|
800597a: 687b ldr r3, [r7, #4]
|
|||
|
|
800597c: 681a ldr r2, [r3, #0]
|
|||
|
|
800597e: 2380 movs r3, #128 ; 0x80
|
|||
|
|
8005980: 005b lsls r3, r3, #1
|
|||
|
|
8005982: 4013 ands r3, r2
|
|||
|
|
8005984: d008 beq.n 8005998 <HAL_RCCEx_PeriphCLKConfig+0x234>
|
|||
|
|
{
|
|||
|
|
/* Check the parameters */
|
|||
|
|
assert_param(IS_RCC_I2C3CLKSOURCE(PeriphClkInit->I2c3ClockSelection));
|
|||
|
|
|
|||
|
|
/* Configure the I2C3 clock source */
|
|||
|
|
__HAL_RCC_I2C3_CONFIG(PeriphClkInit->I2c3ClockSelection);
|
|||
|
|
8005986: 4a15 ldr r2, [pc, #84] ; (80059dc <HAL_RCCEx_PeriphCLKConfig+0x278>)
|
|||
|
|
8005988: 4b14 ldr r3, [pc, #80] ; (80059dc <HAL_RCCEx_PeriphCLKConfig+0x278>)
|
|||
|
|
800598a: 6cdb ldr r3, [r3, #76] ; 0x4c
|
|||
|
|
800598c: 4915 ldr r1, [pc, #84] ; (80059e4 <HAL_RCCEx_PeriphCLKConfig+0x280>)
|
|||
|
|
800598e: 4019 ands r1, r3
|
|||
|
|
8005990: 687b ldr r3, [r7, #4]
|
|||
|
|
8005992: 699b ldr r3, [r3, #24]
|
|||
|
|
8005994: 430b orrs r3, r1
|
|||
|
|
8005996: 64d3 str r3, [r2, #76] ; 0x4c
|
|||
|
|
}
|
|||
|
|
#endif /* RCC_CCIPR_I2C3SEL */
|
|||
|
|
|
|||
|
|
#if defined(USB)
|
|||
|
|
/*---------------------------- USB and RNG configuration --------------------*/
|
|||
|
|
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USB) == (RCC_PERIPHCLK_USB))
|
|||
|
|
8005998: 687b ldr r3, [r7, #4]
|
|||
|
|
800599a: 681b ldr r3, [r3, #0]
|
|||
|
|
800599c: 2240 movs r2, #64 ; 0x40
|
|||
|
|
800599e: 4013 ands r3, r2
|
|||
|
|
80059a0: d008 beq.n 80059b4 <HAL_RCCEx_PeriphCLKConfig+0x250>
|
|||
|
|
{
|
|||
|
|
assert_param(IS_RCC_USBCLKSOURCE(PeriphClkInit->UsbClockSelection));
|
|||
|
|
__HAL_RCC_USB_CONFIG(PeriphClkInit->UsbClockSelection);
|
|||
|
|
80059a2: 4a0e ldr r2, [pc, #56] ; (80059dc <HAL_RCCEx_PeriphCLKConfig+0x278>)
|
|||
|
|
80059a4: 4b0d ldr r3, [pc, #52] ; (80059dc <HAL_RCCEx_PeriphCLKConfig+0x278>)
|
|||
|
|
80059a6: 6cdb ldr r3, [r3, #76] ; 0x4c
|
|||
|
|
80059a8: 4915 ldr r1, [pc, #84] ; (8005a00 <HAL_RCCEx_PeriphCLKConfig+0x29c>)
|
|||
|
|
80059aa: 4019 ands r1, r3
|
|||
|
|
80059ac: 687b ldr r3, [r7, #4]
|
|||
|
|
80059ae: 6a1b ldr r3, [r3, #32]
|
|||
|
|
80059b0: 430b orrs r3, r1
|
|||
|
|
80059b2: 64d3 str r3, [r2, #76] ; 0x4c
|
|||
|
|
}
|
|||
|
|
#endif /* USB */
|
|||
|
|
|
|||
|
|
/*---------------------------- LPTIM1 configuration ------------------------*/
|
|||
|
|
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM1) == (RCC_PERIPHCLK_LPTIM1))
|
|||
|
|
80059b4: 687b ldr r3, [r7, #4]
|
|||
|
|
80059b6: 681b ldr r3, [r3, #0]
|
|||
|
|
80059b8: 2280 movs r2, #128 ; 0x80
|
|||
|
|
80059ba: 4013 ands r3, r2
|
|||
|
|
80059bc: d008 beq.n 80059d0 <HAL_RCCEx_PeriphCLKConfig+0x26c>
|
|||
|
|
{
|
|||
|
|
assert_param(IS_RCC_LPTIMCLK(PeriphClkInit->LptimClockSelection));
|
|||
|
|
__HAL_RCC_LPTIM1_CONFIG(PeriphClkInit->LptimClockSelection);
|
|||
|
|
80059be: 4a07 ldr r2, [pc, #28] ; (80059dc <HAL_RCCEx_PeriphCLKConfig+0x278>)
|
|||
|
|
80059c0: 4b06 ldr r3, [pc, #24] ; (80059dc <HAL_RCCEx_PeriphCLKConfig+0x278>)
|
|||
|
|
80059c2: 6cdb ldr r3, [r3, #76] ; 0x4c
|
|||
|
|
80059c4: 490f ldr r1, [pc, #60] ; (8005a04 <HAL_RCCEx_PeriphCLKConfig+0x2a0>)
|
|||
|
|
80059c6: 4019 ands r1, r3
|
|||
|
|
80059c8: 687b ldr r3, [r7, #4]
|
|||
|
|
80059ca: 69db ldr r3, [r3, #28]
|
|||
|
|
80059cc: 430b orrs r3, r1
|
|||
|
|
80059ce: 64d3 str r3, [r2, #76] ; 0x4c
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
return HAL_OK;
|
|||
|
|
80059d0: 2300 movs r3, #0
|
|||
|
|
}
|
|||
|
|
80059d2: 0018 movs r0, r3
|
|||
|
|
80059d4: 46bd mov sp, r7
|
|||
|
|
80059d6: b006 add sp, #24
|
|||
|
|
80059d8: bd80 pop {r7, pc}
|
|||
|
|
80059da: 46c0 nop ; (mov r8, r8)
|
|||
|
|
80059dc: 40021000 .word 0x40021000
|
|||
|
|
80059e0: 40007000 .word 0x40007000
|
|||
|
|
80059e4: fffcffff .word 0xfffcffff
|
|||
|
|
80059e8: fff7ffff .word 0xfff7ffff
|
|||
|
|
80059ec: 00001388 .word 0x00001388
|
|||
|
|
80059f0: ffcfffff .word 0xffcfffff
|
|||
|
|
80059f4: efffffff .word 0xefffffff
|
|||
|
|
80059f8: fffff3ff .word 0xfffff3ff
|
|||
|
|
80059fc: ffffcfff .word 0xffffcfff
|
|||
|
|
8005a00: fbffffff .word 0xfbffffff
|
|||
|
|
8005a04: fff3ffff .word 0xfff3ffff
|
|||
|
|
|
|||
|
|
08005a08 <HAL_TIM_Base_Init>:
|
|||
|
|
* Ex: call @ref HAL_TIM_Base_DeInit() before HAL_TIM_Base_Init()
|
|||
|
|
* @param htim TIM Base handle
|
|||
|
|
* @retval HAL status
|
|||
|
|
*/
|
|||
|
|
HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim)
|
|||
|
|
{
|
|||
|
|
8005a08: b580 push {r7, lr}
|
|||
|
|
8005a0a: b082 sub sp, #8
|
|||
|
|
8005a0c: af00 add r7, sp, #0
|
|||
|
|
8005a0e: 6078 str r0, [r7, #4]
|
|||
|
|
/* Check the TIM handle allocation */
|
|||
|
|
if (htim == NULL)
|
|||
|
|
8005a10: 687b ldr r3, [r7, #4]
|
|||
|
|
8005a12: 2b00 cmp r3, #0
|
|||
|
|
8005a14: d101 bne.n 8005a1a <HAL_TIM_Base_Init+0x12>
|
|||
|
|
{
|
|||
|
|
return HAL_ERROR;
|
|||
|
|
8005a16: 2301 movs r3, #1
|
|||
|
|
8005a18: e032 b.n 8005a80 <HAL_TIM_Base_Init+0x78>
|
|||
|
|
assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
|
|||
|
|
assert_param(IS_TIM_PERIOD(htim->Init.Period));
|
|||
|
|
assert_param(IS_TIM_PRESCALER(htim->Init.Prescaler));
|
|||
|
|
assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
|
|||
|
|
|
|||
|
|
if (htim->State == HAL_TIM_STATE_RESET)
|
|||
|
|
8005a1a: 687b ldr r3, [r7, #4]
|
|||
|
|
8005a1c: 2239 movs r2, #57 ; 0x39
|
|||
|
|
8005a1e: 5c9b ldrb r3, [r3, r2]
|
|||
|
|
8005a20: b2db uxtb r3, r3
|
|||
|
|
8005a22: 2b00 cmp r3, #0
|
|||
|
|
8005a24: d107 bne.n 8005a36 <HAL_TIM_Base_Init+0x2e>
|
|||
|
|
{
|
|||
|
|
/* Allocate lock resource and initialize it */
|
|||
|
|
htim->Lock = HAL_UNLOCKED;
|
|||
|
|
8005a26: 687b ldr r3, [r7, #4]
|
|||
|
|
8005a28: 2238 movs r2, #56 ; 0x38
|
|||
|
|
8005a2a: 2100 movs r1, #0
|
|||
|
|
8005a2c: 5499 strb r1, [r3, r2]
|
|||
|
|
}
|
|||
|
|
/* Init the low level hardware : GPIO, CLOCK, NVIC */
|
|||
|
|
htim->Base_MspInitCallback(htim);
|
|||
|
|
#else
|
|||
|
|
/* Init the low level hardware : GPIO, CLOCK, NVIC */
|
|||
|
|
HAL_TIM_Base_MspInit(htim);
|
|||
|
|
8005a2e: 687b ldr r3, [r7, #4]
|
|||
|
|
8005a30: 0018 movs r0, r3
|
|||
|
|
8005a32: f7fc fca9 bl 8002388 <HAL_TIM_Base_MspInit>
|
|||
|
|
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
/* Set the TIM state */
|
|||
|
|
htim->State = HAL_TIM_STATE_BUSY;
|
|||
|
|
8005a36: 687b ldr r3, [r7, #4]
|
|||
|
|
8005a38: 2239 movs r2, #57 ; 0x39
|
|||
|
|
8005a3a: 2102 movs r1, #2
|
|||
|
|
8005a3c: 5499 strb r1, [r3, r2]
|
|||
|
|
|
|||
|
|
/* Set the Time Base configuration */
|
|||
|
|
TIM_Base_SetConfig(htim->Instance, &htim->Init);
|
|||
|
|
8005a3e: 687b ldr r3, [r7, #4]
|
|||
|
|
8005a40: 681a ldr r2, [r3, #0]
|
|||
|
|
8005a42: 687b ldr r3, [r7, #4]
|
|||
|
|
8005a44: 3304 adds r3, #4
|
|||
|
|
8005a46: 0019 movs r1, r3
|
|||
|
|
8005a48: 0010 movs r0, r2
|
|||
|
|
8005a4a: f000 f977 bl 8005d3c <TIM_Base_SetConfig>
|
|||
|
|
|
|||
|
|
/* Initialize the DMA burst operation state */
|
|||
|
|
htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
|
|||
|
|
8005a4e: 687b ldr r3, [r7, #4]
|
|||
|
|
8005a50: 223e movs r2, #62 ; 0x3e
|
|||
|
|
8005a52: 2101 movs r1, #1
|
|||
|
|
8005a54: 5499 strb r1, [r3, r2]
|
|||
|
|
|
|||
|
|
/* Initialize the TIM channels state */
|
|||
|
|
TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
|
|||
|
|
8005a56: 687b ldr r3, [r7, #4]
|
|||
|
|
8005a58: 223a movs r2, #58 ; 0x3a
|
|||
|
|
8005a5a: 2101 movs r1, #1
|
|||
|
|
8005a5c: 5499 strb r1, [r3, r2]
|
|||
|
|
8005a5e: 687b ldr r3, [r7, #4]
|
|||
|
|
8005a60: 223b movs r2, #59 ; 0x3b
|
|||
|
|
8005a62: 2101 movs r1, #1
|
|||
|
|
8005a64: 5499 strb r1, [r3, r2]
|
|||
|
|
8005a66: 687b ldr r3, [r7, #4]
|
|||
|
|
8005a68: 223c movs r2, #60 ; 0x3c
|
|||
|
|
8005a6a: 2101 movs r1, #1
|
|||
|
|
8005a6c: 5499 strb r1, [r3, r2]
|
|||
|
|
8005a6e: 687b ldr r3, [r7, #4]
|
|||
|
|
8005a70: 223d movs r2, #61 ; 0x3d
|
|||
|
|
8005a72: 2101 movs r1, #1
|
|||
|
|
8005a74: 5499 strb r1, [r3, r2]
|
|||
|
|
|
|||
|
|
/* Initialize the TIM state*/
|
|||
|
|
htim->State = HAL_TIM_STATE_READY;
|
|||
|
|
8005a76: 687b ldr r3, [r7, #4]
|
|||
|
|
8005a78: 2239 movs r2, #57 ; 0x39
|
|||
|
|
8005a7a: 2101 movs r1, #1
|
|||
|
|
8005a7c: 5499 strb r1, [r3, r2]
|
|||
|
|
|
|||
|
|
return HAL_OK;
|
|||
|
|
8005a7e: 2300 movs r3, #0
|
|||
|
|
}
|
|||
|
|
8005a80: 0018 movs r0, r3
|
|||
|
|
8005a82: 46bd mov sp, r7
|
|||
|
|
8005a84: b002 add sp, #8
|
|||
|
|
8005a86: bd80 pop {r7, pc}
|
|||
|
|
|
|||
|
|
08005a88 <HAL_TIM_Base_Start_IT>:
|
|||
|
|
* @brief Starts the TIM Base generation in interrupt mode.
|
|||
|
|
* @param htim TIM Base handle
|
|||
|
|
* @retval HAL status
|
|||
|
|
*/
|
|||
|
|
HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim)
|
|||
|
|
{
|
|||
|
|
8005a88: b580 push {r7, lr}
|
|||
|
|
8005a8a: b084 sub sp, #16
|
|||
|
|
8005a8c: af00 add r7, sp, #0
|
|||
|
|
8005a8e: 6078 str r0, [r7, #4]
|
|||
|
|
|
|||
|
|
/* Check the parameters */
|
|||
|
|
assert_param(IS_TIM_INSTANCE(htim->Instance));
|
|||
|
|
|
|||
|
|
/* Check the TIM state */
|
|||
|
|
if (htim->State != HAL_TIM_STATE_READY)
|
|||
|
|
8005a90: 687b ldr r3, [r7, #4]
|
|||
|
|
8005a92: 2239 movs r2, #57 ; 0x39
|
|||
|
|
8005a94: 5c9b ldrb r3, [r3, r2]
|
|||
|
|
8005a96: b2db uxtb r3, r3
|
|||
|
|
8005a98: 2b01 cmp r3, #1
|
|||
|
|
8005a9a: d001 beq.n 8005aa0 <HAL_TIM_Base_Start_IT+0x18>
|
|||
|
|
{
|
|||
|
|
return HAL_ERROR;
|
|||
|
|
8005a9c: 2301 movs r3, #1
|
|||
|
|
8005a9e: e03b b.n 8005b18 <HAL_TIM_Base_Start_IT+0x90>
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
/* Set the TIM state */
|
|||
|
|
htim->State = HAL_TIM_STATE_BUSY;
|
|||
|
|
8005aa0: 687b ldr r3, [r7, #4]
|
|||
|
|
8005aa2: 2239 movs r2, #57 ; 0x39
|
|||
|
|
8005aa4: 2102 movs r1, #2
|
|||
|
|
8005aa6: 5499 strb r1, [r3, r2]
|
|||
|
|
|
|||
|
|
/* Enable the TIM Update interrupt */
|
|||
|
|
__HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE);
|
|||
|
|
8005aa8: 687b ldr r3, [r7, #4]
|
|||
|
|
8005aaa: 681b ldr r3, [r3, #0]
|
|||
|
|
8005aac: 687a ldr r2, [r7, #4]
|
|||
|
|
8005aae: 6812 ldr r2, [r2, #0]
|
|||
|
|
8005ab0: 68d2 ldr r2, [r2, #12]
|
|||
|
|
8005ab2: 2101 movs r1, #1
|
|||
|
|
8005ab4: 430a orrs r2, r1
|
|||
|
|
8005ab6: 60da str r2, [r3, #12]
|
|||
|
|
|
|||
|
|
/* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
|
|||
|
|
if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
|
|||
|
|
8005ab8: 687b ldr r3, [r7, #4]
|
|||
|
|
8005aba: 681a ldr r2, [r3, #0]
|
|||
|
|
8005abc: 2380 movs r3, #128 ; 0x80
|
|||
|
|
8005abe: 05db lsls r3, r3, #23
|
|||
|
|
8005ac0: 429a cmp r2, r3
|
|||
|
|
8005ac2: d00e beq.n 8005ae2 <HAL_TIM_Base_Start_IT+0x5a>
|
|||
|
|
8005ac4: 687b ldr r3, [r7, #4]
|
|||
|
|
8005ac6: 681b ldr r3, [r3, #0]
|
|||
|
|
8005ac8: 4a15 ldr r2, [pc, #84] ; (8005b20 <HAL_TIM_Base_Start_IT+0x98>)
|
|||
|
|
8005aca: 4293 cmp r3, r2
|
|||
|
|
8005acc: d009 beq.n 8005ae2 <HAL_TIM_Base_Start_IT+0x5a>
|
|||
|
|
8005ace: 687b ldr r3, [r7, #4]
|
|||
|
|
8005ad0: 681b ldr r3, [r3, #0]
|
|||
|
|
8005ad2: 4a14 ldr r2, [pc, #80] ; (8005b24 <HAL_TIM_Base_Start_IT+0x9c>)
|
|||
|
|
8005ad4: 4293 cmp r3, r2
|
|||
|
|
8005ad6: d004 beq.n 8005ae2 <HAL_TIM_Base_Start_IT+0x5a>
|
|||
|
|
8005ad8: 687b ldr r3, [r7, #4]
|
|||
|
|
8005ada: 681b ldr r3, [r3, #0]
|
|||
|
|
8005adc: 4a12 ldr r2, [pc, #72] ; (8005b28 <HAL_TIM_Base_Start_IT+0xa0>)
|
|||
|
|
8005ade: 4293 cmp r3, r2
|
|||
|
|
8005ae0: d111 bne.n 8005b06 <HAL_TIM_Base_Start_IT+0x7e>
|
|||
|
|
{
|
|||
|
|
tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
|
|||
|
|
8005ae2: 687b ldr r3, [r7, #4]
|
|||
|
|
8005ae4: 681b ldr r3, [r3, #0]
|
|||
|
|
8005ae6: 689b ldr r3, [r3, #8]
|
|||
|
|
8005ae8: 2207 movs r2, #7
|
|||
|
|
8005aea: 4013 ands r3, r2
|
|||
|
|
8005aec: 60fb str r3, [r7, #12]
|
|||
|
|
if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
|
|||
|
|
8005aee: 68fb ldr r3, [r7, #12]
|
|||
|
|
8005af0: 2b06 cmp r3, #6
|
|||
|
|
8005af2: d010 beq.n 8005b16 <HAL_TIM_Base_Start_IT+0x8e>
|
|||
|
|
{
|
|||
|
|
__HAL_TIM_ENABLE(htim);
|
|||
|
|
8005af4: 687b ldr r3, [r7, #4]
|
|||
|
|
8005af6: 681b ldr r3, [r3, #0]
|
|||
|
|
8005af8: 687a ldr r2, [r7, #4]
|
|||
|
|
8005afa: 6812 ldr r2, [r2, #0]
|
|||
|
|
8005afc: 6812 ldr r2, [r2, #0]
|
|||
|
|
8005afe: 2101 movs r1, #1
|
|||
|
|
8005b00: 430a orrs r2, r1
|
|||
|
|
8005b02: 601a str r2, [r3, #0]
|
|||
|
|
if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
|
|||
|
|
8005b04: e007 b.n 8005b16 <HAL_TIM_Base_Start_IT+0x8e>
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
else
|
|||
|
|
{
|
|||
|
|
__HAL_TIM_ENABLE(htim);
|
|||
|
|
8005b06: 687b ldr r3, [r7, #4]
|
|||
|
|
8005b08: 681b ldr r3, [r3, #0]
|
|||
|
|
8005b0a: 687a ldr r2, [r7, #4]
|
|||
|
|
8005b0c: 6812 ldr r2, [r2, #0]
|
|||
|
|
8005b0e: 6812 ldr r2, [r2, #0]
|
|||
|
|
8005b10: 2101 movs r1, #1
|
|||
|
|
8005b12: 430a orrs r2, r1
|
|||
|
|
8005b14: 601a str r2, [r3, #0]
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
/* Return function status */
|
|||
|
|
return HAL_OK;
|
|||
|
|
8005b16: 2300 movs r3, #0
|
|||
|
|
}
|
|||
|
|
8005b18: 0018 movs r0, r3
|
|||
|
|
8005b1a: 46bd mov sp, r7
|
|||
|
|
8005b1c: b004 add sp, #16
|
|||
|
|
8005b1e: bd80 pop {r7, pc}
|
|||
|
|
8005b20: 40000400 .word 0x40000400
|
|||
|
|
8005b24: 40010800 .word 0x40010800
|
|||
|
|
8005b28: 40011400 .word 0x40011400
|
|||
|
|
|
|||
|
|
08005b2c <HAL_TIM_IRQHandler>:
|
|||
|
|
* @brief This function handles TIM interrupts requests.
|
|||
|
|
* @param htim TIM handle
|
|||
|
|
* @retval None
|
|||
|
|
*/
|
|||
|
|
void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
|
|||
|
|
{
|
|||
|
|
8005b2c: b580 push {r7, lr}
|
|||
|
|
8005b2e: b082 sub sp, #8
|
|||
|
|
8005b30: af00 add r7, sp, #0
|
|||
|
|
8005b32: 6078 str r0, [r7, #4]
|
|||
|
|
/* Capture compare 1 event */
|
|||
|
|
if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC1) != RESET)
|
|||
|
|
8005b34: 687b ldr r3, [r7, #4]
|
|||
|
|
8005b36: 681b ldr r3, [r3, #0]
|
|||
|
|
8005b38: 691b ldr r3, [r3, #16]
|
|||
|
|
8005b3a: 2202 movs r2, #2
|
|||
|
|
8005b3c: 4013 ands r3, r2
|
|||
|
|
8005b3e: 2b02 cmp r3, #2
|
|||
|
|
8005b40: d124 bne.n 8005b8c <HAL_TIM_IRQHandler+0x60>
|
|||
|
|
{
|
|||
|
|
if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC1) != RESET)
|
|||
|
|
8005b42: 687b ldr r3, [r7, #4]
|
|||
|
|
8005b44: 681b ldr r3, [r3, #0]
|
|||
|
|
8005b46: 68db ldr r3, [r3, #12]
|
|||
|
|
8005b48: 2202 movs r2, #2
|
|||
|
|
8005b4a: 4013 ands r3, r2
|
|||
|
|
8005b4c: 2b02 cmp r3, #2
|
|||
|
|
8005b4e: d11d bne.n 8005b8c <HAL_TIM_IRQHandler+0x60>
|
|||
|
|
{
|
|||
|
|
{
|
|||
|
|
__HAL_TIM_CLEAR_IT(htim, TIM_IT_CC1);
|
|||
|
|
8005b50: 687b ldr r3, [r7, #4]
|
|||
|
|
8005b52: 681b ldr r3, [r3, #0]
|
|||
|
|
8005b54: 2203 movs r2, #3
|
|||
|
|
8005b56: 4252 negs r2, r2
|
|||
|
|
8005b58: 611a str r2, [r3, #16]
|
|||
|
|
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
|
|||
|
|
8005b5a: 687b ldr r3, [r7, #4]
|
|||
|
|
8005b5c: 2201 movs r2, #1
|
|||
|
|
8005b5e: 761a strb r2, [r3, #24]
|
|||
|
|
|
|||
|
|
/* Input capture event */
|
|||
|
|
if ((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00U)
|
|||
|
|
8005b60: 687b ldr r3, [r7, #4]
|
|||
|
|
8005b62: 681b ldr r3, [r3, #0]
|
|||
|
|
8005b64: 699b ldr r3, [r3, #24]
|
|||
|
|
8005b66: 2203 movs r2, #3
|
|||
|
|
8005b68: 4013 ands r3, r2
|
|||
|
|
8005b6a: d004 beq.n 8005b76 <HAL_TIM_IRQHandler+0x4a>
|
|||
|
|
{
|
|||
|
|
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
|
|||
|
|
htim->IC_CaptureCallback(htim);
|
|||
|
|
#else
|
|||
|
|
HAL_TIM_IC_CaptureCallback(htim);
|
|||
|
|
8005b6c: 687b ldr r3, [r7, #4]
|
|||
|
|
8005b6e: 0018 movs r0, r3
|
|||
|
|
8005b70: f000 f8cc bl 8005d0c <HAL_TIM_IC_CaptureCallback>
|
|||
|
|
8005b74: e007 b.n 8005b86 <HAL_TIM_IRQHandler+0x5a>
|
|||
|
|
{
|
|||
|
|
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
|
|||
|
|
htim->OC_DelayElapsedCallback(htim);
|
|||
|
|
htim->PWM_PulseFinishedCallback(htim);
|
|||
|
|
#else
|
|||
|
|
HAL_TIM_OC_DelayElapsedCallback(htim);
|
|||
|
|
8005b76: 687b ldr r3, [r7, #4]
|
|||
|
|
8005b78: 0018 movs r0, r3
|
|||
|
|
8005b7a: f000 f8bf bl 8005cfc <HAL_TIM_OC_DelayElapsedCallback>
|
|||
|
|
HAL_TIM_PWM_PulseFinishedCallback(htim);
|
|||
|
|
8005b7e: 687b ldr r3, [r7, #4]
|
|||
|
|
8005b80: 0018 movs r0, r3
|
|||
|
|
8005b82: f000 f8cb bl 8005d1c <HAL_TIM_PWM_PulseFinishedCallback>
|
|||
|
|
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
|
|||
|
|
}
|
|||
|
|
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
|
|||
|
|
8005b86: 687b ldr r3, [r7, #4]
|
|||
|
|
8005b88: 2200 movs r2, #0
|
|||
|
|
8005b8a: 761a strb r2, [r3, #24]
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
/* Capture compare 2 event */
|
|||
|
|
if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC2) != RESET)
|
|||
|
|
8005b8c: 687b ldr r3, [r7, #4]
|
|||
|
|
8005b8e: 681b ldr r3, [r3, #0]
|
|||
|
|
8005b90: 691b ldr r3, [r3, #16]
|
|||
|
|
8005b92: 2204 movs r2, #4
|
|||
|
|
8005b94: 4013 ands r3, r2
|
|||
|
|
8005b96: 2b04 cmp r3, #4
|
|||
|
|
8005b98: d125 bne.n 8005be6 <HAL_TIM_IRQHandler+0xba>
|
|||
|
|
{
|
|||
|
|
if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC2) != RESET)
|
|||
|
|
8005b9a: 687b ldr r3, [r7, #4]
|
|||
|
|
8005b9c: 681b ldr r3, [r3, #0]
|
|||
|
|
8005b9e: 68db ldr r3, [r3, #12]
|
|||
|
|
8005ba0: 2204 movs r2, #4
|
|||
|
|
8005ba2: 4013 ands r3, r2
|
|||
|
|
8005ba4: 2b04 cmp r3, #4
|
|||
|
|
8005ba6: d11e bne.n 8005be6 <HAL_TIM_IRQHandler+0xba>
|
|||
|
|
{
|
|||
|
|
__HAL_TIM_CLEAR_IT(htim, TIM_IT_CC2);
|
|||
|
|
8005ba8: 687b ldr r3, [r7, #4]
|
|||
|
|
8005baa: 681b ldr r3, [r3, #0]
|
|||
|
|
8005bac: 2205 movs r2, #5
|
|||
|
|
8005bae: 4252 negs r2, r2
|
|||
|
|
8005bb0: 611a str r2, [r3, #16]
|
|||
|
|
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
|
|||
|
|
8005bb2: 687b ldr r3, [r7, #4]
|
|||
|
|
8005bb4: 2202 movs r2, #2
|
|||
|
|
8005bb6: 761a strb r2, [r3, #24]
|
|||
|
|
/* Input capture event */
|
|||
|
|
if ((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00U)
|
|||
|
|
8005bb8: 687b ldr r3, [r7, #4]
|
|||
|
|
8005bba: 681b ldr r3, [r3, #0]
|
|||
|
|
8005bbc: 699a ldr r2, [r3, #24]
|
|||
|
|
8005bbe: 23c0 movs r3, #192 ; 0xc0
|
|||
|
|
8005bc0: 009b lsls r3, r3, #2
|
|||
|
|
8005bc2: 4013 ands r3, r2
|
|||
|
|
8005bc4: d004 beq.n 8005bd0 <HAL_TIM_IRQHandler+0xa4>
|
|||
|
|
{
|
|||
|
|
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
|
|||
|
|
htim->IC_CaptureCallback(htim);
|
|||
|
|
#else
|
|||
|
|
HAL_TIM_IC_CaptureCallback(htim);
|
|||
|
|
8005bc6: 687b ldr r3, [r7, #4]
|
|||
|
|
8005bc8: 0018 movs r0, r3
|
|||
|
|
8005bca: f000 f89f bl 8005d0c <HAL_TIM_IC_CaptureCallback>
|
|||
|
|
8005bce: e007 b.n 8005be0 <HAL_TIM_IRQHandler+0xb4>
|
|||
|
|
{
|
|||
|
|
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
|
|||
|
|
htim->OC_DelayElapsedCallback(htim);
|
|||
|
|
htim->PWM_PulseFinishedCallback(htim);
|
|||
|
|
#else
|
|||
|
|
HAL_TIM_OC_DelayElapsedCallback(htim);
|
|||
|
|
8005bd0: 687b ldr r3, [r7, #4]
|
|||
|
|
8005bd2: 0018 movs r0, r3
|
|||
|
|
8005bd4: f000 f892 bl 8005cfc <HAL_TIM_OC_DelayElapsedCallback>
|
|||
|
|
HAL_TIM_PWM_PulseFinishedCallback(htim);
|
|||
|
|
8005bd8: 687b ldr r3, [r7, #4]
|
|||
|
|
8005bda: 0018 movs r0, r3
|
|||
|
|
8005bdc: f000 f89e bl 8005d1c <HAL_TIM_PWM_PulseFinishedCallback>
|
|||
|
|
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
|
|||
|
|
}
|
|||
|
|
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
|
|||
|
|
8005be0: 687b ldr r3, [r7, #4]
|
|||
|
|
8005be2: 2200 movs r2, #0
|
|||
|
|
8005be4: 761a strb r2, [r3, #24]
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
/* Capture compare 3 event */
|
|||
|
|
if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC3) != RESET)
|
|||
|
|
8005be6: 687b ldr r3, [r7, #4]
|
|||
|
|
8005be8: 681b ldr r3, [r3, #0]
|
|||
|
|
8005bea: 691b ldr r3, [r3, #16]
|
|||
|
|
8005bec: 2208 movs r2, #8
|
|||
|
|
8005bee: 4013 ands r3, r2
|
|||
|
|
8005bf0: 2b08 cmp r3, #8
|
|||
|
|
8005bf2: d124 bne.n 8005c3e <HAL_TIM_IRQHandler+0x112>
|
|||
|
|
{
|
|||
|
|
if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC3) != RESET)
|
|||
|
|
8005bf4: 687b ldr r3, [r7, #4]
|
|||
|
|
8005bf6: 681b ldr r3, [r3, #0]
|
|||
|
|
8005bf8: 68db ldr r3, [r3, #12]
|
|||
|
|
8005bfa: 2208 movs r2, #8
|
|||
|
|
8005bfc: 4013 ands r3, r2
|
|||
|
|
8005bfe: 2b08 cmp r3, #8
|
|||
|
|
8005c00: d11d bne.n 8005c3e <HAL_TIM_IRQHandler+0x112>
|
|||
|
|
{
|
|||
|
|
__HAL_TIM_CLEAR_IT(htim, TIM_IT_CC3);
|
|||
|
|
8005c02: 687b ldr r3, [r7, #4]
|
|||
|
|
8005c04: 681b ldr r3, [r3, #0]
|
|||
|
|
8005c06: 2209 movs r2, #9
|
|||
|
|
8005c08: 4252 negs r2, r2
|
|||
|
|
8005c0a: 611a str r2, [r3, #16]
|
|||
|
|
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
|
|||
|
|
8005c0c: 687b ldr r3, [r7, #4]
|
|||
|
|
8005c0e: 2204 movs r2, #4
|
|||
|
|
8005c10: 761a strb r2, [r3, #24]
|
|||
|
|
/* Input capture event */
|
|||
|
|
if ((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00U)
|
|||
|
|
8005c12: 687b ldr r3, [r7, #4]
|
|||
|
|
8005c14: 681b ldr r3, [r3, #0]
|
|||
|
|
8005c16: 69db ldr r3, [r3, #28]
|
|||
|
|
8005c18: 2203 movs r2, #3
|
|||
|
|
8005c1a: 4013 ands r3, r2
|
|||
|
|
8005c1c: d004 beq.n 8005c28 <HAL_TIM_IRQHandler+0xfc>
|
|||
|
|
{
|
|||
|
|
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
|
|||
|
|
htim->IC_CaptureCallback(htim);
|
|||
|
|
#else
|
|||
|
|
HAL_TIM_IC_CaptureCallback(htim);
|
|||
|
|
8005c1e: 687b ldr r3, [r7, #4]
|
|||
|
|
8005c20: 0018 movs r0, r3
|
|||
|
|
8005c22: f000 f873 bl 8005d0c <HAL_TIM_IC_CaptureCallback>
|
|||
|
|
8005c26: e007 b.n 8005c38 <HAL_TIM_IRQHandler+0x10c>
|
|||
|
|
{
|
|||
|
|
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
|
|||
|
|
htim->OC_DelayElapsedCallback(htim);
|
|||
|
|
htim->PWM_PulseFinishedCallback(htim);
|
|||
|
|
#else
|
|||
|
|
HAL_TIM_OC_DelayElapsedCallback(htim);
|
|||
|
|
8005c28: 687b ldr r3, [r7, #4]
|
|||
|
|
8005c2a: 0018 movs r0, r3
|
|||
|
|
8005c2c: f000 f866 bl 8005cfc <HAL_TIM_OC_DelayElapsedCallback>
|
|||
|
|
HAL_TIM_PWM_PulseFinishedCallback(htim);
|
|||
|
|
8005c30: 687b ldr r3, [r7, #4]
|
|||
|
|
8005c32: 0018 movs r0, r3
|
|||
|
|
8005c34: f000 f872 bl 8005d1c <HAL_TIM_PWM_PulseFinishedCallback>
|
|||
|
|
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
|
|||
|
|
}
|
|||
|
|
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
|
|||
|
|
8005c38: 687b ldr r3, [r7, #4]
|
|||
|
|
8005c3a: 2200 movs r2, #0
|
|||
|
|
8005c3c: 761a strb r2, [r3, #24]
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
/* Capture compare 4 event */
|
|||
|
|
if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC4) != RESET)
|
|||
|
|
8005c3e: 687b ldr r3, [r7, #4]
|
|||
|
|
8005c40: 681b ldr r3, [r3, #0]
|
|||
|
|
8005c42: 691b ldr r3, [r3, #16]
|
|||
|
|
8005c44: 2210 movs r2, #16
|
|||
|
|
8005c46: 4013 ands r3, r2
|
|||
|
|
8005c48: 2b10 cmp r3, #16
|
|||
|
|
8005c4a: d125 bne.n 8005c98 <HAL_TIM_IRQHandler+0x16c>
|
|||
|
|
{
|
|||
|
|
if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC4) != RESET)
|
|||
|
|
8005c4c: 687b ldr r3, [r7, #4]
|
|||
|
|
8005c4e: 681b ldr r3, [r3, #0]
|
|||
|
|
8005c50: 68db ldr r3, [r3, #12]
|
|||
|
|
8005c52: 2210 movs r2, #16
|
|||
|
|
8005c54: 4013 ands r3, r2
|
|||
|
|
8005c56: 2b10 cmp r3, #16
|
|||
|
|
8005c58: d11e bne.n 8005c98 <HAL_TIM_IRQHandler+0x16c>
|
|||
|
|
{
|
|||
|
|
__HAL_TIM_CLEAR_IT(htim, TIM_IT_CC4);
|
|||
|
|
8005c5a: 687b ldr r3, [r7, #4]
|
|||
|
|
8005c5c: 681b ldr r3, [r3, #0]
|
|||
|
|
8005c5e: 2211 movs r2, #17
|
|||
|
|
8005c60: 4252 negs r2, r2
|
|||
|
|
8005c62: 611a str r2, [r3, #16]
|
|||
|
|
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
|
|||
|
|
8005c64: 687b ldr r3, [r7, #4]
|
|||
|
|
8005c66: 2208 movs r2, #8
|
|||
|
|
8005c68: 761a strb r2, [r3, #24]
|
|||
|
|
/* Input capture event */
|
|||
|
|
if ((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00U)
|
|||
|
|
8005c6a: 687b ldr r3, [r7, #4]
|
|||
|
|
8005c6c: 681b ldr r3, [r3, #0]
|
|||
|
|
8005c6e: 69da ldr r2, [r3, #28]
|
|||
|
|
8005c70: 23c0 movs r3, #192 ; 0xc0
|
|||
|
|
8005c72: 009b lsls r3, r3, #2
|
|||
|
|
8005c74: 4013 ands r3, r2
|
|||
|
|
8005c76: d004 beq.n 8005c82 <HAL_TIM_IRQHandler+0x156>
|
|||
|
|
{
|
|||
|
|
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
|
|||
|
|
htim->IC_CaptureCallback(htim);
|
|||
|
|
#else
|
|||
|
|
HAL_TIM_IC_CaptureCallback(htim);
|
|||
|
|
8005c78: 687b ldr r3, [r7, #4]
|
|||
|
|
8005c7a: 0018 movs r0, r3
|
|||
|
|
8005c7c: f000 f846 bl 8005d0c <HAL_TIM_IC_CaptureCallback>
|
|||
|
|
8005c80: e007 b.n 8005c92 <HAL_TIM_IRQHandler+0x166>
|
|||
|
|
{
|
|||
|
|
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
|
|||
|
|
htim->OC_DelayElapsedCallback(htim);
|
|||
|
|
htim->PWM_PulseFinishedCallback(htim);
|
|||
|
|
#else
|
|||
|
|
HAL_TIM_OC_DelayElapsedCallback(htim);
|
|||
|
|
8005c82: 687b ldr r3, [r7, #4]
|
|||
|
|
8005c84: 0018 movs r0, r3
|
|||
|
|
8005c86: f000 f839 bl 8005cfc <HAL_TIM_OC_DelayElapsedCallback>
|
|||
|
|
HAL_TIM_PWM_PulseFinishedCallback(htim);
|
|||
|
|
8005c8a: 687b ldr r3, [r7, #4]
|
|||
|
|
8005c8c: 0018 movs r0, r3
|
|||
|
|
8005c8e: f000 f845 bl 8005d1c <HAL_TIM_PWM_PulseFinishedCallback>
|
|||
|
|
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
|
|||
|
|
}
|
|||
|
|
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
|
|||
|
|
8005c92: 687b ldr r3, [r7, #4]
|
|||
|
|
8005c94: 2200 movs r2, #0
|
|||
|
|
8005c96: 761a strb r2, [r3, #24]
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
/* TIM Update event */
|
|||
|
|
if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_UPDATE) != RESET)
|
|||
|
|
8005c98: 687b ldr r3, [r7, #4]
|
|||
|
|
8005c9a: 681b ldr r3, [r3, #0]
|
|||
|
|
8005c9c: 691b ldr r3, [r3, #16]
|
|||
|
|
8005c9e: 2201 movs r2, #1
|
|||
|
|
8005ca0: 4013 ands r3, r2
|
|||
|
|
8005ca2: 2b01 cmp r3, #1
|
|||
|
|
8005ca4: d10f bne.n 8005cc6 <HAL_TIM_IRQHandler+0x19a>
|
|||
|
|
{
|
|||
|
|
if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_UPDATE) != RESET)
|
|||
|
|
8005ca6: 687b ldr r3, [r7, #4]
|
|||
|
|
8005ca8: 681b ldr r3, [r3, #0]
|
|||
|
|
8005caa: 68db ldr r3, [r3, #12]
|
|||
|
|
8005cac: 2201 movs r2, #1
|
|||
|
|
8005cae: 4013 ands r3, r2
|
|||
|
|
8005cb0: 2b01 cmp r3, #1
|
|||
|
|
8005cb2: d108 bne.n 8005cc6 <HAL_TIM_IRQHandler+0x19a>
|
|||
|
|
{
|
|||
|
|
__HAL_TIM_CLEAR_IT(htim, TIM_IT_UPDATE);
|
|||
|
|
8005cb4: 687b ldr r3, [r7, #4]
|
|||
|
|
8005cb6: 681b ldr r3, [r3, #0]
|
|||
|
|
8005cb8: 2202 movs r2, #2
|
|||
|
|
8005cba: 4252 negs r2, r2
|
|||
|
|
8005cbc: 611a str r2, [r3, #16]
|
|||
|
|
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
|
|||
|
|
htim->PeriodElapsedCallback(htim);
|
|||
|
|
#else
|
|||
|
|
HAL_TIM_PeriodElapsedCallback(htim);
|
|||
|
|
8005cbe: 687b ldr r3, [r7, #4]
|
|||
|
|
8005cc0: 0018 movs r0, r3
|
|||
|
|
8005cc2: f7fc fb81 bl 80023c8 <HAL_TIM_PeriodElapsedCallback>
|
|||
|
|
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
/* TIM Trigger detection event */
|
|||
|
|
if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_TRIGGER) != RESET)
|
|||
|
|
8005cc6: 687b ldr r3, [r7, #4]
|
|||
|
|
8005cc8: 681b ldr r3, [r3, #0]
|
|||
|
|
8005cca: 691b ldr r3, [r3, #16]
|
|||
|
|
8005ccc: 2240 movs r2, #64 ; 0x40
|
|||
|
|
8005cce: 4013 ands r3, r2
|
|||
|
|
8005cd0: 2b40 cmp r3, #64 ; 0x40
|
|||
|
|
8005cd2: d10f bne.n 8005cf4 <HAL_TIM_IRQHandler+0x1c8>
|
|||
|
|
{
|
|||
|
|
if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_TRIGGER) != RESET)
|
|||
|
|
8005cd4: 687b ldr r3, [r7, #4]
|
|||
|
|
8005cd6: 681b ldr r3, [r3, #0]
|
|||
|
|
8005cd8: 68db ldr r3, [r3, #12]
|
|||
|
|
8005cda: 2240 movs r2, #64 ; 0x40
|
|||
|
|
8005cdc: 4013 ands r3, r2
|
|||
|
|
8005cde: 2b40 cmp r3, #64 ; 0x40
|
|||
|
|
8005ce0: d108 bne.n 8005cf4 <HAL_TIM_IRQHandler+0x1c8>
|
|||
|
|
{
|
|||
|
|
__HAL_TIM_CLEAR_IT(htim, TIM_IT_TRIGGER);
|
|||
|
|
8005ce2: 687b ldr r3, [r7, #4]
|
|||
|
|
8005ce4: 681b ldr r3, [r3, #0]
|
|||
|
|
8005ce6: 2241 movs r2, #65 ; 0x41
|
|||
|
|
8005ce8: 4252 negs r2, r2
|
|||
|
|
8005cea: 611a str r2, [r3, #16]
|
|||
|
|
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
|
|||
|
|
htim->TriggerCallback(htim);
|
|||
|
|
#else
|
|||
|
|
HAL_TIM_TriggerCallback(htim);
|
|||
|
|
8005cec: 687b ldr r3, [r7, #4]
|
|||
|
|
8005cee: 0018 movs r0, r3
|
|||
|
|
8005cf0: f000 f81c bl 8005d2c <HAL_TIM_TriggerCallback>
|
|||
|
|
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
8005cf4: 46c0 nop ; (mov r8, r8)
|
|||
|
|
8005cf6: 46bd mov sp, r7
|
|||
|
|
8005cf8: b002 add sp, #8
|
|||
|
|
8005cfa: bd80 pop {r7, pc}
|
|||
|
|
|
|||
|
|
08005cfc <HAL_TIM_OC_DelayElapsedCallback>:
|
|||
|
|
* @brief Output Compare callback in non-blocking mode
|
|||
|
|
* @param htim TIM OC handle
|
|||
|
|
* @retval None
|
|||
|
|
*/
|
|||
|
|
__weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim)
|
|||
|
|
{
|
|||
|
|
8005cfc: b580 push {r7, lr}
|
|||
|
|
8005cfe: b082 sub sp, #8
|
|||
|
|
8005d00: af00 add r7, sp, #0
|
|||
|
|
8005d02: 6078 str r0, [r7, #4]
|
|||
|
|
UNUSED(htim);
|
|||
|
|
|
|||
|
|
/* NOTE : This function should not be modified, when the callback is needed,
|
|||
|
|
the HAL_TIM_OC_DelayElapsedCallback could be implemented in the user file
|
|||
|
|
*/
|
|||
|
|
}
|
|||
|
|
8005d04: 46c0 nop ; (mov r8, r8)
|
|||
|
|
8005d06: 46bd mov sp, r7
|
|||
|
|
8005d08: b002 add sp, #8
|
|||
|
|
8005d0a: bd80 pop {r7, pc}
|
|||
|
|
|
|||
|
|
08005d0c <HAL_TIM_IC_CaptureCallback>:
|
|||
|
|
* @brief Input Capture callback in non-blocking mode
|
|||
|
|
* @param htim TIM IC handle
|
|||
|
|
* @retval None
|
|||
|
|
*/
|
|||
|
|
__weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim)
|
|||
|
|
{
|
|||
|
|
8005d0c: b580 push {r7, lr}
|
|||
|
|
8005d0e: b082 sub sp, #8
|
|||
|
|
8005d10: af00 add r7, sp, #0
|
|||
|
|
8005d12: 6078 str r0, [r7, #4]
|
|||
|
|
UNUSED(htim);
|
|||
|
|
|
|||
|
|
/* NOTE : This function should not be modified, when the callback is needed,
|
|||
|
|
the HAL_TIM_IC_CaptureCallback could be implemented in the user file
|
|||
|
|
*/
|
|||
|
|
}
|
|||
|
|
8005d14: 46c0 nop ; (mov r8, r8)
|
|||
|
|
8005d16: 46bd mov sp, r7
|
|||
|
|
8005d18: b002 add sp, #8
|
|||
|
|
8005d1a: bd80 pop {r7, pc}
|
|||
|
|
|
|||
|
|
08005d1c <HAL_TIM_PWM_PulseFinishedCallback>:
|
|||
|
|
* @brief PWM Pulse finished callback in non-blocking mode
|
|||
|
|
* @param htim TIM handle
|
|||
|
|
* @retval None
|
|||
|
|
*/
|
|||
|
|
__weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim)
|
|||
|
|
{
|
|||
|
|
8005d1c: b580 push {r7, lr}
|
|||
|
|
8005d1e: b082 sub sp, #8
|
|||
|
|
8005d20: af00 add r7, sp, #0
|
|||
|
|
8005d22: 6078 str r0, [r7, #4]
|
|||
|
|
UNUSED(htim);
|
|||
|
|
|
|||
|
|
/* NOTE : This function should not be modified, when the callback is needed,
|
|||
|
|
the HAL_TIM_PWM_PulseFinishedCallback could be implemented in the user file
|
|||
|
|
*/
|
|||
|
|
}
|
|||
|
|
8005d24: 46c0 nop ; (mov r8, r8)
|
|||
|
|
8005d26: 46bd mov sp, r7
|
|||
|
|
8005d28: b002 add sp, #8
|
|||
|
|
8005d2a: bd80 pop {r7, pc}
|
|||
|
|
|
|||
|
|
08005d2c <HAL_TIM_TriggerCallback>:
|
|||
|
|
* @brief Hall Trigger detection callback in non-blocking mode
|
|||
|
|
* @param htim TIM handle
|
|||
|
|
* @retval None
|
|||
|
|
*/
|
|||
|
|
__weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim)
|
|||
|
|
{
|
|||
|
|
8005d2c: b580 push {r7, lr}
|
|||
|
|
8005d2e: b082 sub sp, #8
|
|||
|
|
8005d30: af00 add r7, sp, #0
|
|||
|
|
8005d32: 6078 str r0, [r7, #4]
|
|||
|
|
UNUSED(htim);
|
|||
|
|
|
|||
|
|
/* NOTE : This function should not be modified, when the callback is needed,
|
|||
|
|
the HAL_TIM_TriggerCallback could be implemented in the user file
|
|||
|
|
*/
|
|||
|
|
}
|
|||
|
|
8005d34: 46c0 nop ; (mov r8, r8)
|
|||
|
|
8005d36: 46bd mov sp, r7
|
|||
|
|
8005d38: b002 add sp, #8
|
|||
|
|
8005d3a: bd80 pop {r7, pc}
|
|||
|
|
|
|||
|
|
08005d3c <TIM_Base_SetConfig>:
|
|||
|
|
* @param TIMx TIM peripheral
|
|||
|
|
* @param Structure TIM Base configuration structure
|
|||
|
|
* @retval None
|
|||
|
|
*/
|
|||
|
|
static void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure)
|
|||
|
|
{
|
|||
|
|
8005d3c: b580 push {r7, lr}
|
|||
|
|
8005d3e: b084 sub sp, #16
|
|||
|
|
8005d40: af00 add r7, sp, #0
|
|||
|
|
8005d42: 6078 str r0, [r7, #4]
|
|||
|
|
8005d44: 6039 str r1, [r7, #0]
|
|||
|
|
uint32_t tmpcr1;
|
|||
|
|
tmpcr1 = TIMx->CR1;
|
|||
|
|
8005d46: 687b ldr r3, [r7, #4]
|
|||
|
|
8005d48: 681b ldr r3, [r3, #0]
|
|||
|
|
8005d4a: 60fb str r3, [r7, #12]
|
|||
|
|
|
|||
|
|
/* Set TIM Time Base Unit parameters ---------------------------------------*/
|
|||
|
|
if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx))
|
|||
|
|
8005d4c: 687a ldr r2, [r7, #4]
|
|||
|
|
8005d4e: 2380 movs r3, #128 ; 0x80
|
|||
|
|
8005d50: 05db lsls r3, r3, #23
|
|||
|
|
8005d52: 429a cmp r2, r3
|
|||
|
|
8005d54: d00b beq.n 8005d6e <TIM_Base_SetConfig+0x32>
|
|||
|
|
8005d56: 687b ldr r3, [r7, #4]
|
|||
|
|
8005d58: 4a23 ldr r2, [pc, #140] ; (8005de8 <TIM_Base_SetConfig+0xac>)
|
|||
|
|
8005d5a: 4293 cmp r3, r2
|
|||
|
|
8005d5c: d007 beq.n 8005d6e <TIM_Base_SetConfig+0x32>
|
|||
|
|
8005d5e: 687b ldr r3, [r7, #4]
|
|||
|
|
8005d60: 4a22 ldr r2, [pc, #136] ; (8005dec <TIM_Base_SetConfig+0xb0>)
|
|||
|
|
8005d62: 4293 cmp r3, r2
|
|||
|
|
8005d64: d003 beq.n 8005d6e <TIM_Base_SetConfig+0x32>
|
|||
|
|
8005d66: 687b ldr r3, [r7, #4]
|
|||
|
|
8005d68: 4a21 ldr r2, [pc, #132] ; (8005df0 <TIM_Base_SetConfig+0xb4>)
|
|||
|
|
8005d6a: 4293 cmp r3, r2
|
|||
|
|
8005d6c: d108 bne.n 8005d80 <TIM_Base_SetConfig+0x44>
|
|||
|
|
{
|
|||
|
|
/* Select the Counter Mode */
|
|||
|
|
tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS);
|
|||
|
|
8005d6e: 68fb ldr r3, [r7, #12]
|
|||
|
|
8005d70: 2270 movs r2, #112 ; 0x70
|
|||
|
|
8005d72: 4393 bics r3, r2
|
|||
|
|
8005d74: 60fb str r3, [r7, #12]
|
|||
|
|
tmpcr1 |= Structure->CounterMode;
|
|||
|
|
8005d76: 683b ldr r3, [r7, #0]
|
|||
|
|
8005d78: 685b ldr r3, [r3, #4]
|
|||
|
|
8005d7a: 68fa ldr r2, [r7, #12]
|
|||
|
|
8005d7c: 4313 orrs r3, r2
|
|||
|
|
8005d7e: 60fb str r3, [r7, #12]
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx))
|
|||
|
|
8005d80: 687a ldr r2, [r7, #4]
|
|||
|
|
8005d82: 2380 movs r3, #128 ; 0x80
|
|||
|
|
8005d84: 05db lsls r3, r3, #23
|
|||
|
|
8005d86: 429a cmp r2, r3
|
|||
|
|
8005d88: d00b beq.n 8005da2 <TIM_Base_SetConfig+0x66>
|
|||
|
|
8005d8a: 687b ldr r3, [r7, #4]
|
|||
|
|
8005d8c: 4a16 ldr r2, [pc, #88] ; (8005de8 <TIM_Base_SetConfig+0xac>)
|
|||
|
|
8005d8e: 4293 cmp r3, r2
|
|||
|
|
8005d90: d007 beq.n 8005da2 <TIM_Base_SetConfig+0x66>
|
|||
|
|
8005d92: 687b ldr r3, [r7, #4]
|
|||
|
|
8005d94: 4a15 ldr r2, [pc, #84] ; (8005dec <TIM_Base_SetConfig+0xb0>)
|
|||
|
|
8005d96: 4293 cmp r3, r2
|
|||
|
|
8005d98: d003 beq.n 8005da2 <TIM_Base_SetConfig+0x66>
|
|||
|
|
8005d9a: 687b ldr r3, [r7, #4]
|
|||
|
|
8005d9c: 4a14 ldr r2, [pc, #80] ; (8005df0 <TIM_Base_SetConfig+0xb4>)
|
|||
|
|
8005d9e: 4293 cmp r3, r2
|
|||
|
|
8005da0: d108 bne.n 8005db4 <TIM_Base_SetConfig+0x78>
|
|||
|
|
{
|
|||
|
|
/* Set the clock division */
|
|||
|
|
tmpcr1 &= ~TIM_CR1_CKD;
|
|||
|
|
8005da2: 68fb ldr r3, [r7, #12]
|
|||
|
|
8005da4: 4a13 ldr r2, [pc, #76] ; (8005df4 <TIM_Base_SetConfig+0xb8>)
|
|||
|
|
8005da6: 4013 ands r3, r2
|
|||
|
|
8005da8: 60fb str r3, [r7, #12]
|
|||
|
|
tmpcr1 |= (uint32_t)Structure->ClockDivision;
|
|||
|
|
8005daa: 683b ldr r3, [r7, #0]
|
|||
|
|
8005dac: 68db ldr r3, [r3, #12]
|
|||
|
|
8005dae: 68fa ldr r2, [r7, #12]
|
|||
|
|
8005db0: 4313 orrs r3, r2
|
|||
|
|
8005db2: 60fb str r3, [r7, #12]
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
/* Set the auto-reload preload */
|
|||
|
|
MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload);
|
|||
|
|
8005db4: 68fb ldr r3, [r7, #12]
|
|||
|
|
8005db6: 2280 movs r2, #128 ; 0x80
|
|||
|
|
8005db8: 4393 bics r3, r2
|
|||
|
|
8005dba: 001a movs r2, r3
|
|||
|
|
8005dbc: 683b ldr r3, [r7, #0]
|
|||
|
|
8005dbe: 691b ldr r3, [r3, #16]
|
|||
|
|
8005dc0: 4313 orrs r3, r2
|
|||
|
|
8005dc2: 60fb str r3, [r7, #12]
|
|||
|
|
|
|||
|
|
TIMx->CR1 = tmpcr1;
|
|||
|
|
8005dc4: 687b ldr r3, [r7, #4]
|
|||
|
|
8005dc6: 68fa ldr r2, [r7, #12]
|
|||
|
|
8005dc8: 601a str r2, [r3, #0]
|
|||
|
|
|
|||
|
|
/* Set the Autoreload value */
|
|||
|
|
TIMx->ARR = (uint32_t)Structure->Period ;
|
|||
|
|
8005dca: 683b ldr r3, [r7, #0]
|
|||
|
|
8005dcc: 689a ldr r2, [r3, #8]
|
|||
|
|
8005dce: 687b ldr r3, [r7, #4]
|
|||
|
|
8005dd0: 62da str r2, [r3, #44] ; 0x2c
|
|||
|
|
|
|||
|
|
/* Set the Prescaler value */
|
|||
|
|
TIMx->PSC = Structure->Prescaler;
|
|||
|
|
8005dd2: 683b ldr r3, [r7, #0]
|
|||
|
|
8005dd4: 681a ldr r2, [r3, #0]
|
|||
|
|
8005dd6: 687b ldr r3, [r7, #4]
|
|||
|
|
8005dd8: 629a str r2, [r3, #40] ; 0x28
|
|||
|
|
|
|||
|
|
/* Generate an update event to reload the Prescaler
|
|||
|
|
and the repetition counter (only for advanced timer) value immediately */
|
|||
|
|
TIMx->EGR = TIM_EGR_UG;
|
|||
|
|
8005dda: 687b ldr r3, [r7, #4]
|
|||
|
|
8005ddc: 2201 movs r2, #1
|
|||
|
|
8005dde: 615a str r2, [r3, #20]
|
|||
|
|
}
|
|||
|
|
8005de0: 46c0 nop ; (mov r8, r8)
|
|||
|
|
8005de2: 46bd mov sp, r7
|
|||
|
|
8005de4: b004 add sp, #16
|
|||
|
|
8005de6: bd80 pop {r7, pc}
|
|||
|
|
8005de8: 40000400 .word 0x40000400
|
|||
|
|
8005dec: 40010800 .word 0x40010800
|
|||
|
|
8005df0: 40011400 .word 0x40011400
|
|||
|
|
8005df4: fffffcff .word 0xfffffcff
|
|||
|
|
|
|||
|
|
08005df8 <HAL_TIMEx_MasterConfigSynchronization>:
|
|||
|
|
* mode.
|
|||
|
|
* @retval HAL status
|
|||
|
|
*/
|
|||
|
|
HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim,
|
|||
|
|
TIM_MasterConfigTypeDef *sMasterConfig)
|
|||
|
|
{
|
|||
|
|
8005df8: b580 push {r7, lr}
|
|||
|
|
8005dfa: b084 sub sp, #16
|
|||
|
|
8005dfc: af00 add r7, sp, #0
|
|||
|
|
8005dfe: 6078 str r0, [r7, #4]
|
|||
|
|
8005e00: 6039 str r1, [r7, #0]
|
|||
|
|
assert_param(IS_TIM_MASTER_INSTANCE(htim->Instance));
|
|||
|
|
assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger));
|
|||
|
|
assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode));
|
|||
|
|
|
|||
|
|
/* Check input state */
|
|||
|
|
__HAL_LOCK(htim);
|
|||
|
|
8005e02: 687b ldr r3, [r7, #4]
|
|||
|
|
8005e04: 2238 movs r2, #56 ; 0x38
|
|||
|
|
8005e06: 5c9b ldrb r3, [r3, r2]
|
|||
|
|
8005e08: 2b01 cmp r3, #1
|
|||
|
|
8005e0a: d101 bne.n 8005e10 <HAL_TIMEx_MasterConfigSynchronization+0x18>
|
|||
|
|
8005e0c: 2302 movs r3, #2
|
|||
|
|
8005e0e: e047 b.n 8005ea0 <HAL_TIMEx_MasterConfigSynchronization+0xa8>
|
|||
|
|
8005e10: 687b ldr r3, [r7, #4]
|
|||
|
|
8005e12: 2238 movs r2, #56 ; 0x38
|
|||
|
|
8005e14: 2101 movs r1, #1
|
|||
|
|
8005e16: 5499 strb r1, [r3, r2]
|
|||
|
|
|
|||
|
|
/* Change the handler state */
|
|||
|
|
htim->State = HAL_TIM_STATE_BUSY;
|
|||
|
|
8005e18: 687b ldr r3, [r7, #4]
|
|||
|
|
8005e1a: 2239 movs r2, #57 ; 0x39
|
|||
|
|
8005e1c: 2102 movs r1, #2
|
|||
|
|
8005e1e: 5499 strb r1, [r3, r2]
|
|||
|
|
|
|||
|
|
/* Get the TIMx CR2 register value */
|
|||
|
|
tmpcr2 = htim->Instance->CR2;
|
|||
|
|
8005e20: 687b ldr r3, [r7, #4]
|
|||
|
|
8005e22: 681b ldr r3, [r3, #0]
|
|||
|
|
8005e24: 685b ldr r3, [r3, #4]
|
|||
|
|
8005e26: 60fb str r3, [r7, #12]
|
|||
|
|
|
|||
|
|
/* Get the TIMx SMCR register value */
|
|||
|
|
tmpsmcr = htim->Instance->SMCR;
|
|||
|
|
8005e28: 687b ldr r3, [r7, #4]
|
|||
|
|
8005e2a: 681b ldr r3, [r3, #0]
|
|||
|
|
8005e2c: 689b ldr r3, [r3, #8]
|
|||
|
|
8005e2e: 60bb str r3, [r7, #8]
|
|||
|
|
|
|||
|
|
/* Reset the MMS Bits */
|
|||
|
|
tmpcr2 &= ~TIM_CR2_MMS;
|
|||
|
|
8005e30: 68fb ldr r3, [r7, #12]
|
|||
|
|
8005e32: 2270 movs r2, #112 ; 0x70
|
|||
|
|
8005e34: 4393 bics r3, r2
|
|||
|
|
8005e36: 60fb str r3, [r7, #12]
|
|||
|
|
/* Select the TRGO source */
|
|||
|
|
tmpcr2 |= sMasterConfig->MasterOutputTrigger;
|
|||
|
|
8005e38: 683b ldr r3, [r7, #0]
|
|||
|
|
8005e3a: 681b ldr r3, [r3, #0]
|
|||
|
|
8005e3c: 68fa ldr r2, [r7, #12]
|
|||
|
|
8005e3e: 4313 orrs r3, r2
|
|||
|
|
8005e40: 60fb str r3, [r7, #12]
|
|||
|
|
|
|||
|
|
/* Update TIMx CR2 */
|
|||
|
|
htim->Instance->CR2 = tmpcr2;
|
|||
|
|
8005e42: 687b ldr r3, [r7, #4]
|
|||
|
|
8005e44: 681b ldr r3, [r3, #0]
|
|||
|
|
8005e46: 68fa ldr r2, [r7, #12]
|
|||
|
|
8005e48: 605a str r2, [r3, #4]
|
|||
|
|
|
|||
|
|
if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
|
|||
|
|
8005e4a: 687b ldr r3, [r7, #4]
|
|||
|
|
8005e4c: 681a ldr r2, [r3, #0]
|
|||
|
|
8005e4e: 2380 movs r3, #128 ; 0x80
|
|||
|
|
8005e50: 05db lsls r3, r3, #23
|
|||
|
|
8005e52: 429a cmp r2, r3
|
|||
|
|
8005e54: d00e beq.n 8005e74 <HAL_TIMEx_MasterConfigSynchronization+0x7c>
|
|||
|
|
8005e56: 687b ldr r3, [r7, #4]
|
|||
|
|
8005e58: 681b ldr r3, [r3, #0]
|
|||
|
|
8005e5a: 4a13 ldr r2, [pc, #76] ; (8005ea8 <HAL_TIMEx_MasterConfigSynchronization+0xb0>)
|
|||
|
|
8005e5c: 4293 cmp r3, r2
|
|||
|
|
8005e5e: d009 beq.n 8005e74 <HAL_TIMEx_MasterConfigSynchronization+0x7c>
|
|||
|
|
8005e60: 687b ldr r3, [r7, #4]
|
|||
|
|
8005e62: 681b ldr r3, [r3, #0]
|
|||
|
|
8005e64: 4a11 ldr r2, [pc, #68] ; (8005eac <HAL_TIMEx_MasterConfigSynchronization+0xb4>)
|
|||
|
|
8005e66: 4293 cmp r3, r2
|
|||
|
|
8005e68: d004 beq.n 8005e74 <HAL_TIMEx_MasterConfigSynchronization+0x7c>
|
|||
|
|
8005e6a: 687b ldr r3, [r7, #4]
|
|||
|
|
8005e6c: 681b ldr r3, [r3, #0]
|
|||
|
|
8005e6e: 4a10 ldr r2, [pc, #64] ; (8005eb0 <HAL_TIMEx_MasterConfigSynchronization+0xb8>)
|
|||
|
|
8005e70: 4293 cmp r3, r2
|
|||
|
|
8005e72: d10c bne.n 8005e8e <HAL_TIMEx_MasterConfigSynchronization+0x96>
|
|||
|
|
{
|
|||
|
|
/* Reset the MSM Bit */
|
|||
|
|
tmpsmcr &= ~TIM_SMCR_MSM;
|
|||
|
|
8005e74: 68bb ldr r3, [r7, #8]
|
|||
|
|
8005e76: 2280 movs r2, #128 ; 0x80
|
|||
|
|
8005e78: 4393 bics r3, r2
|
|||
|
|
8005e7a: 60bb str r3, [r7, #8]
|
|||
|
|
/* Set master mode */
|
|||
|
|
tmpsmcr |= sMasterConfig->MasterSlaveMode;
|
|||
|
|
8005e7c: 683b ldr r3, [r7, #0]
|
|||
|
|
8005e7e: 685b ldr r3, [r3, #4]
|
|||
|
|
8005e80: 68ba ldr r2, [r7, #8]
|
|||
|
|
8005e82: 4313 orrs r3, r2
|
|||
|
|
8005e84: 60bb str r3, [r7, #8]
|
|||
|
|
|
|||
|
|
/* Update TIMx SMCR */
|
|||
|
|
htim->Instance->SMCR = tmpsmcr;
|
|||
|
|
8005e86: 687b ldr r3, [r7, #4]
|
|||
|
|
8005e88: 681b ldr r3, [r3, #0]
|
|||
|
|
8005e8a: 68ba ldr r2, [r7, #8]
|
|||
|
|
8005e8c: 609a str r2, [r3, #8]
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
/* Change the htim state */
|
|||
|
|
htim->State = HAL_TIM_STATE_READY;
|
|||
|
|
8005e8e: 687b ldr r3, [r7, #4]
|
|||
|
|
8005e90: 2239 movs r2, #57 ; 0x39
|
|||
|
|
8005e92: 2101 movs r1, #1
|
|||
|
|
8005e94: 5499 strb r1, [r3, r2]
|
|||
|
|
|
|||
|
|
__HAL_UNLOCK(htim);
|
|||
|
|
8005e96: 687b ldr r3, [r7, #4]
|
|||
|
|
8005e98: 2238 movs r2, #56 ; 0x38
|
|||
|
|
8005e9a: 2100 movs r1, #0
|
|||
|
|
8005e9c: 5499 strb r1, [r3, r2]
|
|||
|
|
|
|||
|
|
return HAL_OK;
|
|||
|
|
8005e9e: 2300 movs r3, #0
|
|||
|
|
}
|
|||
|
|
8005ea0: 0018 movs r0, r3
|
|||
|
|
8005ea2: 46bd mov sp, r7
|
|||
|
|
8005ea4: b004 add sp, #16
|
|||
|
|
8005ea6: bd80 pop {r7, pc}
|
|||
|
|
8005ea8: 40000400 .word 0x40000400
|
|||
|
|
8005eac: 40010800 .word 0x40010800
|
|||
|
|
8005eb0: 40011400 .word 0x40011400
|
|||
|
|
|
|||
|
|
08005eb4 <HAL_UART_Init>:
|
|||
|
|
* parameters in the UART_InitTypeDef and initialize the associated handle.
|
|||
|
|
* @param huart UART handle.
|
|||
|
|
* @retval HAL status
|
|||
|
|
*/
|
|||
|
|
HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart)
|
|||
|
|
{
|
|||
|
|
8005eb4: b580 push {r7, lr}
|
|||
|
|
8005eb6: b082 sub sp, #8
|
|||
|
|
8005eb8: af00 add r7, sp, #0
|
|||
|
|
8005eba: 6078 str r0, [r7, #4]
|
|||
|
|
/* Check the UART handle allocation */
|
|||
|
|
if (huart == NULL)
|
|||
|
|
8005ebc: 687b ldr r3, [r7, #4]
|
|||
|
|
8005ebe: 2b00 cmp r3, #0
|
|||
|
|
8005ec0: d101 bne.n 8005ec6 <HAL_UART_Init+0x12>
|
|||
|
|
{
|
|||
|
|
return HAL_ERROR;
|
|||
|
|
8005ec2: 2301 movs r3, #1
|
|||
|
|
8005ec4: e044 b.n 8005f50 <HAL_UART_Init+0x9c>
|
|||
|
|
{
|
|||
|
|
/* Check the parameters */
|
|||
|
|
assert_param((IS_UART_INSTANCE(huart->Instance)) || (IS_LPUART_INSTANCE(huart->Instance)));
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
if (huart->gState == HAL_UART_STATE_RESET)
|
|||
|
|
8005ec6: 687b ldr r3, [r7, #4]
|
|||
|
|
8005ec8: 6f9b ldr r3, [r3, #120] ; 0x78
|
|||
|
|
8005eca: 2b00 cmp r3, #0
|
|||
|
|
8005ecc: d107 bne.n 8005ede <HAL_UART_Init+0x2a>
|
|||
|
|
{
|
|||
|
|
/* Allocate lock resource and initialize it */
|
|||
|
|
huart->Lock = HAL_UNLOCKED;
|
|||
|
|
8005ece: 687b ldr r3, [r7, #4]
|
|||
|
|
8005ed0: 2274 movs r2, #116 ; 0x74
|
|||
|
|
8005ed2: 2100 movs r1, #0
|
|||
|
|
8005ed4: 5499 strb r1, [r3, r2]
|
|||
|
|
|
|||
|
|
/* Init the low level hardware */
|
|||
|
|
huart->MspInitCallback(huart);
|
|||
|
|
#else
|
|||
|
|
/* Init the low level hardware : GPIO, CLOCK */
|
|||
|
|
HAL_UART_MspInit(huart);
|
|||
|
|
8005ed6: 687b ldr r3, [r7, #4]
|
|||
|
|
8005ed8: 0018 movs r0, r3
|
|||
|
|
8005eda: f7fc fb3d bl 8002558 <HAL_UART_MspInit>
|
|||
|
|
#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
huart->gState = HAL_UART_STATE_BUSY;
|
|||
|
|
8005ede: 687b ldr r3, [r7, #4]
|
|||
|
|
8005ee0: 2224 movs r2, #36 ; 0x24
|
|||
|
|
8005ee2: 679a str r2, [r3, #120] ; 0x78
|
|||
|
|
|
|||
|
|
__HAL_UART_DISABLE(huart);
|
|||
|
|
8005ee4: 687b ldr r3, [r7, #4]
|
|||
|
|
8005ee6: 681b ldr r3, [r3, #0]
|
|||
|
|
8005ee8: 687a ldr r2, [r7, #4]
|
|||
|
|
8005eea: 6812 ldr r2, [r2, #0]
|
|||
|
|
8005eec: 6812 ldr r2, [r2, #0]
|
|||
|
|
8005eee: 2101 movs r1, #1
|
|||
|
|
8005ef0: 438a bics r2, r1
|
|||
|
|
8005ef2: 601a str r2, [r3, #0]
|
|||
|
|
|
|||
|
|
/* Set the UART Communication parameters */
|
|||
|
|
if (UART_SetConfig(huart) == HAL_ERROR)
|
|||
|
|
8005ef4: 687b ldr r3, [r7, #4]
|
|||
|
|
8005ef6: 0018 movs r0, r3
|
|||
|
|
8005ef8: f000 faf8 bl 80064ec <UART_SetConfig>
|
|||
|
|
8005efc: 0003 movs r3, r0
|
|||
|
|
8005efe: 2b01 cmp r3, #1
|
|||
|
|
8005f00: d101 bne.n 8005f06 <HAL_UART_Init+0x52>
|
|||
|
|
{
|
|||
|
|
return HAL_ERROR;
|
|||
|
|
8005f02: 2301 movs r3, #1
|
|||
|
|
8005f04: e024 b.n 8005f50 <HAL_UART_Init+0x9c>
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)
|
|||
|
|
8005f06: 687b ldr r3, [r7, #4]
|
|||
|
|
8005f08: 6a5b ldr r3, [r3, #36] ; 0x24
|
|||
|
|
8005f0a: 2b00 cmp r3, #0
|
|||
|
|
8005f0c: d003 beq.n 8005f16 <HAL_UART_Init+0x62>
|
|||
|
|
{
|
|||
|
|
UART_AdvFeatureConfig(huart);
|
|||
|
|
8005f0e: 687b ldr r3, [r7, #4]
|
|||
|
|
8005f10: 0018 movs r0, r3
|
|||
|
|
8005f12: f000 fdad bl 8006a70 <UART_AdvFeatureConfig>
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
/* In asynchronous mode, the following bits must be kept cleared:
|
|||
|
|
- LINEN and CLKEN bits in the USART_CR2 register,
|
|||
|
|
- SCEN, HDSEL and IREN bits in the USART_CR3 register.*/
|
|||
|
|
CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
|
|||
|
|
8005f16: 687b ldr r3, [r7, #4]
|
|||
|
|
8005f18: 681b ldr r3, [r3, #0]
|
|||
|
|
8005f1a: 687a ldr r2, [r7, #4]
|
|||
|
|
8005f1c: 6812 ldr r2, [r2, #0]
|
|||
|
|
8005f1e: 6852 ldr r2, [r2, #4]
|
|||
|
|
8005f20: 490d ldr r1, [pc, #52] ; (8005f58 <HAL_UART_Init+0xa4>)
|
|||
|
|
8005f22: 400a ands r2, r1
|
|||
|
|
8005f24: 605a str r2, [r3, #4]
|
|||
|
|
CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN));
|
|||
|
|
8005f26: 687b ldr r3, [r7, #4]
|
|||
|
|
8005f28: 681b ldr r3, [r3, #0]
|
|||
|
|
8005f2a: 687a ldr r2, [r7, #4]
|
|||
|
|
8005f2c: 6812 ldr r2, [r2, #0]
|
|||
|
|
8005f2e: 6892 ldr r2, [r2, #8]
|
|||
|
|
8005f30: 212a movs r1, #42 ; 0x2a
|
|||
|
|
8005f32: 438a bics r2, r1
|
|||
|
|
8005f34: 609a str r2, [r3, #8]
|
|||
|
|
|
|||
|
|
__HAL_UART_ENABLE(huart);
|
|||
|
|
8005f36: 687b ldr r3, [r7, #4]
|
|||
|
|
8005f38: 681b ldr r3, [r3, #0]
|
|||
|
|
8005f3a: 687a ldr r2, [r7, #4]
|
|||
|
|
8005f3c: 6812 ldr r2, [r2, #0]
|
|||
|
|
8005f3e: 6812 ldr r2, [r2, #0]
|
|||
|
|
8005f40: 2101 movs r1, #1
|
|||
|
|
8005f42: 430a orrs r2, r1
|
|||
|
|
8005f44: 601a str r2, [r3, #0]
|
|||
|
|
|
|||
|
|
/* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */
|
|||
|
|
return (UART_CheckIdleState(huart));
|
|||
|
|
8005f46: 687b ldr r3, [r7, #4]
|
|||
|
|
8005f48: 0018 movs r0, r3
|
|||
|
|
8005f4a: f000 fe3d bl 8006bc8 <UART_CheckIdleState>
|
|||
|
|
8005f4e: 0003 movs r3, r0
|
|||
|
|
}
|
|||
|
|
8005f50: 0018 movs r0, r3
|
|||
|
|
8005f52: 46bd mov sp, r7
|
|||
|
|
8005f54: b002 add sp, #8
|
|||
|
|
8005f56: bd80 pop {r7, pc}
|
|||
|
|
8005f58: ffffb7ff .word 0xffffb7ff
|
|||
|
|
|
|||
|
|
08005f5c <HAL_UART_DeInit>:
|
|||
|
|
* @brief DeInitialize the UART peripheral.
|
|||
|
|
* @param huart UART handle.
|
|||
|
|
* @retval HAL status
|
|||
|
|
*/
|
|||
|
|
HAL_StatusTypeDef HAL_UART_DeInit(UART_HandleTypeDef *huart)
|
|||
|
|
{
|
|||
|
|
8005f5c: b580 push {r7, lr}
|
|||
|
|
8005f5e: b082 sub sp, #8
|
|||
|
|
8005f60: af00 add r7, sp, #0
|
|||
|
|
8005f62: 6078 str r0, [r7, #4]
|
|||
|
|
/* Check the UART handle allocation */
|
|||
|
|
if (huart == NULL)
|
|||
|
|
8005f64: 687b ldr r3, [r7, #4]
|
|||
|
|
8005f66: 2b00 cmp r3, #0
|
|||
|
|
8005f68: d101 bne.n 8005f6e <HAL_UART_DeInit+0x12>
|
|||
|
|
{
|
|||
|
|
return HAL_ERROR;
|
|||
|
|
8005f6a: 2301 movs r3, #1
|
|||
|
|
8005f6c: e02c b.n 8005fc8 <HAL_UART_DeInit+0x6c>
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
/* Check the parameters */
|
|||
|
|
assert_param((IS_UART_INSTANCE(huart->Instance)) || (IS_LPUART_INSTANCE(huart->Instance)));
|
|||
|
|
|
|||
|
|
huart->gState = HAL_UART_STATE_BUSY;
|
|||
|
|
8005f6e: 687b ldr r3, [r7, #4]
|
|||
|
|
8005f70: 2224 movs r2, #36 ; 0x24
|
|||
|
|
8005f72: 679a str r2, [r3, #120] ; 0x78
|
|||
|
|
|
|||
|
|
__HAL_UART_DISABLE(huart);
|
|||
|
|
8005f74: 687b ldr r3, [r7, #4]
|
|||
|
|
8005f76: 681b ldr r3, [r3, #0]
|
|||
|
|
8005f78: 687a ldr r2, [r7, #4]
|
|||
|
|
8005f7a: 6812 ldr r2, [r2, #0]
|
|||
|
|
8005f7c: 6812 ldr r2, [r2, #0]
|
|||
|
|
8005f7e: 2101 movs r1, #1
|
|||
|
|
8005f80: 438a bics r2, r1
|
|||
|
|
8005f82: 601a str r2, [r3, #0]
|
|||
|
|
|
|||
|
|
huart->Instance->CR1 = 0x0U;
|
|||
|
|
8005f84: 687b ldr r3, [r7, #4]
|
|||
|
|
8005f86: 681b ldr r3, [r3, #0]
|
|||
|
|
8005f88: 2200 movs r2, #0
|
|||
|
|
8005f8a: 601a str r2, [r3, #0]
|
|||
|
|
huart->Instance->CR2 = 0x0U;
|
|||
|
|
8005f8c: 687b ldr r3, [r7, #4]
|
|||
|
|
8005f8e: 681b ldr r3, [r3, #0]
|
|||
|
|
8005f90: 2200 movs r2, #0
|
|||
|
|
8005f92: 605a str r2, [r3, #4]
|
|||
|
|
huart->Instance->CR3 = 0x0U;
|
|||
|
|
8005f94: 687b ldr r3, [r7, #4]
|
|||
|
|
8005f96: 681b ldr r3, [r3, #0]
|
|||
|
|
8005f98: 2200 movs r2, #0
|
|||
|
|
8005f9a: 609a str r2, [r3, #8]
|
|||
|
|
}
|
|||
|
|
/* DeInit the low level hardware */
|
|||
|
|
huart->MspDeInitCallback(huart);
|
|||
|
|
#else
|
|||
|
|
/* DeInit the low level hardware */
|
|||
|
|
HAL_UART_MspDeInit(huart);
|
|||
|
|
8005f9c: 687b ldr r3, [r7, #4]
|
|||
|
|
8005f9e: 0018 movs r0, r3
|
|||
|
|
8005fa0: f7fc fb2c bl 80025fc <HAL_UART_MspDeInit>
|
|||
|
|
#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
|
|||
|
|
|
|||
|
|
huart->ErrorCode = HAL_UART_ERROR_NONE;
|
|||
|
|
8005fa4: 687b ldr r3, [r7, #4]
|
|||
|
|
8005fa6: 2280 movs r2, #128 ; 0x80
|
|||
|
|
8005fa8: 2100 movs r1, #0
|
|||
|
|
8005faa: 5099 str r1, [r3, r2]
|
|||
|
|
huart->gState = HAL_UART_STATE_RESET;
|
|||
|
|
8005fac: 687b ldr r3, [r7, #4]
|
|||
|
|
8005fae: 2200 movs r2, #0
|
|||
|
|
8005fb0: 679a str r2, [r3, #120] ; 0x78
|
|||
|
|
huart->RxState = HAL_UART_STATE_RESET;
|
|||
|
|
8005fb2: 687b ldr r3, [r7, #4]
|
|||
|
|
8005fb4: 2200 movs r2, #0
|
|||
|
|
8005fb6: 67da str r2, [r3, #124] ; 0x7c
|
|||
|
|
huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
|
|||
|
|
8005fb8: 687b ldr r3, [r7, #4]
|
|||
|
|
8005fba: 2200 movs r2, #0
|
|||
|
|
8005fbc: 661a str r2, [r3, #96] ; 0x60
|
|||
|
|
|
|||
|
|
__HAL_UNLOCK(huart);
|
|||
|
|
8005fbe: 687b ldr r3, [r7, #4]
|
|||
|
|
8005fc0: 2274 movs r2, #116 ; 0x74
|
|||
|
|
8005fc2: 2100 movs r1, #0
|
|||
|
|
8005fc4: 5499 strb r1, [r3, r2]
|
|||
|
|
|
|||
|
|
return HAL_OK;
|
|||
|
|
8005fc6: 2300 movs r3, #0
|
|||
|
|
}
|
|||
|
|
8005fc8: 0018 movs r0, r3
|
|||
|
|
8005fca: 46bd mov sp, r7
|
|||
|
|
8005fcc: b002 add sp, #8
|
|||
|
|
8005fce: bd80 pop {r7, pc}
|
|||
|
|
|
|||
|
|
08005fd0 <HAL_UART_Transmit_IT>:
|
|||
|
|
* @param pData Pointer to data buffer (u8 or u16 data elements).
|
|||
|
|
* @param Size Amount of data elements (u8 or u16) to be sent.
|
|||
|
|
* @retval HAL status
|
|||
|
|
*/
|
|||
|
|
HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
|
|||
|
|
{
|
|||
|
|
8005fd0: b580 push {r7, lr}
|
|||
|
|
8005fd2: b084 sub sp, #16
|
|||
|
|
8005fd4: af00 add r7, sp, #0
|
|||
|
|
8005fd6: 60f8 str r0, [r7, #12]
|
|||
|
|
8005fd8: 60b9 str r1, [r7, #8]
|
|||
|
|
8005fda: 1dbb adds r3, r7, #6
|
|||
|
|
8005fdc: 801a strh r2, [r3, #0]
|
|||
|
|
/* Check that a Tx process is not already ongoing */
|
|||
|
|
if (huart->gState == HAL_UART_STATE_READY)
|
|||
|
|
8005fde: 68fb ldr r3, [r7, #12]
|
|||
|
|
8005fe0: 6f9b ldr r3, [r3, #120] ; 0x78
|
|||
|
|
8005fe2: 2b20 cmp r3, #32
|
|||
|
|
8005fe4: d159 bne.n 800609a <HAL_UART_Transmit_IT+0xca>
|
|||
|
|
{
|
|||
|
|
if ((pData == NULL) || (Size == 0U))
|
|||
|
|
8005fe6: 68bb ldr r3, [r7, #8]
|
|||
|
|
8005fe8: 2b00 cmp r3, #0
|
|||
|
|
8005fea: d003 beq.n 8005ff4 <HAL_UART_Transmit_IT+0x24>
|
|||
|
|
8005fec: 1dbb adds r3, r7, #6
|
|||
|
|
8005fee: 881b ldrh r3, [r3, #0]
|
|||
|
|
8005ff0: 2b00 cmp r3, #0
|
|||
|
|
8005ff2: d101 bne.n 8005ff8 <HAL_UART_Transmit_IT+0x28>
|
|||
|
|
{
|
|||
|
|
return HAL_ERROR;
|
|||
|
|
8005ff4: 2301 movs r3, #1
|
|||
|
|
8005ff6: e051 b.n 800609c <HAL_UART_Transmit_IT+0xcc>
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
/* In case of 9bits/No Parity transfer, pData buffer provided as input parameter
|
|||
|
|
should be aligned on a u16 frontier, as data to be filled into TDR will be
|
|||
|
|
handled through a u16 cast. */
|
|||
|
|
if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
|
|||
|
|
8005ff8: 68fb ldr r3, [r7, #12]
|
|||
|
|
8005ffa: 689a ldr r2, [r3, #8]
|
|||
|
|
8005ffc: 2380 movs r3, #128 ; 0x80
|
|||
|
|
8005ffe: 015b lsls r3, r3, #5
|
|||
|
|
8006000: 429a cmp r2, r3
|
|||
|
|
8006002: d109 bne.n 8006018 <HAL_UART_Transmit_IT+0x48>
|
|||
|
|
8006004: 68fb ldr r3, [r7, #12]
|
|||
|
|
8006006: 691b ldr r3, [r3, #16]
|
|||
|
|
8006008: 2b00 cmp r3, #0
|
|||
|
|
800600a: d105 bne.n 8006018 <HAL_UART_Transmit_IT+0x48>
|
|||
|
|
{
|
|||
|
|
if ((((uint32_t)pData) & 1U) != 0U)
|
|||
|
|
800600c: 68bb ldr r3, [r7, #8]
|
|||
|
|
800600e: 2201 movs r2, #1
|
|||
|
|
8006010: 4013 ands r3, r2
|
|||
|
|
8006012: d001 beq.n 8006018 <HAL_UART_Transmit_IT+0x48>
|
|||
|
|
{
|
|||
|
|
return HAL_ERROR;
|
|||
|
|
8006014: 2301 movs r3, #1
|
|||
|
|
8006016: e041 b.n 800609c <HAL_UART_Transmit_IT+0xcc>
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
__HAL_LOCK(huart);
|
|||
|
|
8006018: 68fb ldr r3, [r7, #12]
|
|||
|
|
800601a: 2274 movs r2, #116 ; 0x74
|
|||
|
|
800601c: 5c9b ldrb r3, [r3, r2]
|
|||
|
|
800601e: 2b01 cmp r3, #1
|
|||
|
|
8006020: d101 bne.n 8006026 <HAL_UART_Transmit_IT+0x56>
|
|||
|
|
8006022: 2302 movs r3, #2
|
|||
|
|
8006024: e03a b.n 800609c <HAL_UART_Transmit_IT+0xcc>
|
|||
|
|
8006026: 68fb ldr r3, [r7, #12]
|
|||
|
|
8006028: 2274 movs r2, #116 ; 0x74
|
|||
|
|
800602a: 2101 movs r1, #1
|
|||
|
|
800602c: 5499 strb r1, [r3, r2]
|
|||
|
|
|
|||
|
|
huart->pTxBuffPtr = pData;
|
|||
|
|
800602e: 68fb ldr r3, [r7, #12]
|
|||
|
|
8006030: 68ba ldr r2, [r7, #8]
|
|||
|
|
8006032: 64da str r2, [r3, #76] ; 0x4c
|
|||
|
|
huart->TxXferSize = Size;
|
|||
|
|
8006034: 68fb ldr r3, [r7, #12]
|
|||
|
|
8006036: 1dba adds r2, r7, #6
|
|||
|
|
8006038: 2150 movs r1, #80 ; 0x50
|
|||
|
|
800603a: 8812 ldrh r2, [r2, #0]
|
|||
|
|
800603c: 525a strh r2, [r3, r1]
|
|||
|
|
huart->TxXferCount = Size;
|
|||
|
|
800603e: 68fb ldr r3, [r7, #12]
|
|||
|
|
8006040: 1dba adds r2, r7, #6
|
|||
|
|
8006042: 2152 movs r1, #82 ; 0x52
|
|||
|
|
8006044: 8812 ldrh r2, [r2, #0]
|
|||
|
|
8006046: 525a strh r2, [r3, r1]
|
|||
|
|
huart->TxISR = NULL;
|
|||
|
|
8006048: 68fb ldr r3, [r7, #12]
|
|||
|
|
800604a: 2200 movs r2, #0
|
|||
|
|
800604c: 669a str r2, [r3, #104] ; 0x68
|
|||
|
|
|
|||
|
|
huart->ErrorCode = HAL_UART_ERROR_NONE;
|
|||
|
|
800604e: 68fb ldr r3, [r7, #12]
|
|||
|
|
8006050: 2280 movs r2, #128 ; 0x80
|
|||
|
|
8006052: 2100 movs r1, #0
|
|||
|
|
8006054: 5099 str r1, [r3, r2]
|
|||
|
|
huart->gState = HAL_UART_STATE_BUSY_TX;
|
|||
|
|
8006056: 68fb ldr r3, [r7, #12]
|
|||
|
|
8006058: 2221 movs r2, #33 ; 0x21
|
|||
|
|
800605a: 679a str r2, [r3, #120] ; 0x78
|
|||
|
|
|
|||
|
|
/* Set the Tx ISR function pointer according to the data word length */
|
|||
|
|
if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
|
|||
|
|
800605c: 68fb ldr r3, [r7, #12]
|
|||
|
|
800605e: 689a ldr r2, [r3, #8]
|
|||
|
|
8006060: 2380 movs r3, #128 ; 0x80
|
|||
|
|
8006062: 015b lsls r3, r3, #5
|
|||
|
|
8006064: 429a cmp r2, r3
|
|||
|
|
8006066: d107 bne.n 8006078 <HAL_UART_Transmit_IT+0xa8>
|
|||
|
|
8006068: 68fb ldr r3, [r7, #12]
|
|||
|
|
800606a: 691b ldr r3, [r3, #16]
|
|||
|
|
800606c: 2b00 cmp r3, #0
|
|||
|
|
800606e: d103 bne.n 8006078 <HAL_UART_Transmit_IT+0xa8>
|
|||
|
|
{
|
|||
|
|
huart->TxISR = UART_TxISR_16BIT;
|
|||
|
|
8006070: 68fb ldr r3, [r7, #12]
|
|||
|
|
8006072: 4a0c ldr r2, [pc, #48] ; (80060a4 <HAL_UART_Transmit_IT+0xd4>)
|
|||
|
|
8006074: 669a str r2, [r3, #104] ; 0x68
|
|||
|
|
8006076: e002 b.n 800607e <HAL_UART_Transmit_IT+0xae>
|
|||
|
|
}
|
|||
|
|
else
|
|||
|
|
{
|
|||
|
|
huart->TxISR = UART_TxISR_8BIT;
|
|||
|
|
8006078: 68fb ldr r3, [r7, #12]
|
|||
|
|
800607a: 4a0b ldr r2, [pc, #44] ; (80060a8 <HAL_UART_Transmit_IT+0xd8>)
|
|||
|
|
800607c: 669a str r2, [r3, #104] ; 0x68
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
__HAL_UNLOCK(huart);
|
|||
|
|
800607e: 68fb ldr r3, [r7, #12]
|
|||
|
|
8006080: 2274 movs r2, #116 ; 0x74
|
|||
|
|
8006082: 2100 movs r1, #0
|
|||
|
|
8006084: 5499 strb r1, [r3, r2]
|
|||
|
|
|
|||
|
|
/* Enable the Transmit Data Register Empty interrupt */
|
|||
|
|
SET_BIT(huart->Instance->CR1, USART_CR1_TXEIE);
|
|||
|
|
8006086: 68fb ldr r3, [r7, #12]
|
|||
|
|
8006088: 681b ldr r3, [r3, #0]
|
|||
|
|
800608a: 68fa ldr r2, [r7, #12]
|
|||
|
|
800608c: 6812 ldr r2, [r2, #0]
|
|||
|
|
800608e: 6812 ldr r2, [r2, #0]
|
|||
|
|
8006090: 2180 movs r1, #128 ; 0x80
|
|||
|
|
8006092: 430a orrs r2, r1
|
|||
|
|
8006094: 601a str r2, [r3, #0]
|
|||
|
|
|
|||
|
|
return HAL_OK;
|
|||
|
|
8006096: 2300 movs r3, #0
|
|||
|
|
8006098: e000 b.n 800609c <HAL_UART_Transmit_IT+0xcc>
|
|||
|
|
}
|
|||
|
|
else
|
|||
|
|
{
|
|||
|
|
return HAL_BUSY;
|
|||
|
|
800609a: 2302 movs r3, #2
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
800609c: 0018 movs r0, r3
|
|||
|
|
800609e: 46bd mov sp, r7
|
|||
|
|
80060a0: b004 add sp, #16
|
|||
|
|
80060a2: bd80 pop {r7, pc}
|
|||
|
|
80060a4: 08006e55 .word 0x08006e55
|
|||
|
|
80060a8: 08006de7 .word 0x08006de7
|
|||
|
|
|
|||
|
|
080060ac <HAL_UART_IRQHandler>:
|
|||
|
|
* @brief Handle UART interrupt request.
|
|||
|
|
* @param huart UART handle.
|
|||
|
|
* @retval None
|
|||
|
|
*/
|
|||
|
|
void HAL_UART_IRQHandler(UART_HandleTypeDef *huart)
|
|||
|
|
{
|
|||
|
|
80060ac: b580 push {r7, lr}
|
|||
|
|
80060ae: b088 sub sp, #32
|
|||
|
|
80060b0: af00 add r7, sp, #0
|
|||
|
|
80060b2: 6078 str r0, [r7, #4]
|
|||
|
|
uint32_t isrflags = READ_REG(huart->Instance->ISR);
|
|||
|
|
80060b4: 687b ldr r3, [r7, #4]
|
|||
|
|
80060b6: 681b ldr r3, [r3, #0]
|
|||
|
|
80060b8: 69db ldr r3, [r3, #28]
|
|||
|
|
80060ba: 61fb str r3, [r7, #28]
|
|||
|
|
uint32_t cr1its = READ_REG(huart->Instance->CR1);
|
|||
|
|
80060bc: 687b ldr r3, [r7, #4]
|
|||
|
|
80060be: 681b ldr r3, [r3, #0]
|
|||
|
|
80060c0: 681b ldr r3, [r3, #0]
|
|||
|
|
80060c2: 61bb str r3, [r7, #24]
|
|||
|
|
uint32_t cr3its = READ_REG(huart->Instance->CR3);
|
|||
|
|
80060c4: 687b ldr r3, [r7, #4]
|
|||
|
|
80060c6: 681b ldr r3, [r3, #0]
|
|||
|
|
80060c8: 689b ldr r3, [r3, #8]
|
|||
|
|
80060ca: 617b str r3, [r7, #20]
|
|||
|
|
|
|||
|
|
uint32_t errorflags;
|
|||
|
|
uint32_t errorcode;
|
|||
|
|
|
|||
|
|
/* If no error occurs */
|
|||
|
|
errorflags = (isrflags & (uint32_t)(USART_ISR_PE | USART_ISR_FE | USART_ISR_ORE | USART_ISR_NE | USART_ISR_RTOF));
|
|||
|
|
80060cc: 69fb ldr r3, [r7, #28]
|
|||
|
|
80060ce: 4ab7 ldr r2, [pc, #732] ; (80063ac <HAL_UART_IRQHandler+0x300>)
|
|||
|
|
80060d0: 4013 ands r3, r2
|
|||
|
|
80060d2: 613b str r3, [r7, #16]
|
|||
|
|
if (errorflags == 0U)
|
|||
|
|
80060d4: 693b ldr r3, [r7, #16]
|
|||
|
|
80060d6: 2b00 cmp r3, #0
|
|||
|
|
80060d8: d112 bne.n 8006100 <HAL_UART_IRQHandler+0x54>
|
|||
|
|
{
|
|||
|
|
/* UART in mode Receiver ---------------------------------------------------*/
|
|||
|
|
if (((isrflags & USART_ISR_RXNE) != 0U)
|
|||
|
|
80060da: 69fb ldr r3, [r7, #28]
|
|||
|
|
80060dc: 2220 movs r2, #32
|
|||
|
|
80060de: 4013 ands r3, r2
|
|||
|
|
80060e0: d00e beq.n 8006100 <HAL_UART_IRQHandler+0x54>
|
|||
|
|
&& ((cr1its & USART_CR1_RXNEIE) != 0U))
|
|||
|
|
80060e2: 69bb ldr r3, [r7, #24]
|
|||
|
|
80060e4: 2220 movs r2, #32
|
|||
|
|
80060e6: 4013 ands r3, r2
|
|||
|
|
80060e8: d00a beq.n 8006100 <HAL_UART_IRQHandler+0x54>
|
|||
|
|
{
|
|||
|
|
if (huart->RxISR != NULL)
|
|||
|
|
80060ea: 687b ldr r3, [r7, #4]
|
|||
|
|
80060ec: 6e5b ldr r3, [r3, #100] ; 0x64
|
|||
|
|
80060ee: 2b00 cmp r3, #0
|
|||
|
|
80060f0: d100 bne.n 80060f4 <HAL_UART_IRQHandler+0x48>
|
|||
|
|
80060f2: e1d8 b.n 80064a6 <HAL_UART_IRQHandler+0x3fa>
|
|||
|
|
{
|
|||
|
|
huart->RxISR(huart);
|
|||
|
|
80060f4: 687b ldr r3, [r7, #4]
|
|||
|
|
80060f6: 6e5b ldr r3, [r3, #100] ; 0x64
|
|||
|
|
80060f8: 687a ldr r2, [r7, #4]
|
|||
|
|
80060fa: 0010 movs r0, r2
|
|||
|
|
80060fc: 4798 blx r3
|
|||
|
|
}
|
|||
|
|
return;
|
|||
|
|
80060fe: e1d2 b.n 80064a6 <HAL_UART_IRQHandler+0x3fa>
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
/* If some errors occur */
|
|||
|
|
if ((errorflags != 0U)
|
|||
|
|
8006100: 693b ldr r3, [r7, #16]
|
|||
|
|
8006102: 2b00 cmp r3, #0
|
|||
|
|
8006104: d100 bne.n 8006108 <HAL_UART_IRQHandler+0x5c>
|
|||
|
|
8006106: e0d9 b.n 80062bc <HAL_UART_IRQHandler+0x210>
|
|||
|
|
&& (((cr3its & USART_CR3_EIE) != 0U)
|
|||
|
|
8006108: 697b ldr r3, [r7, #20]
|
|||
|
|
800610a: 2201 movs r2, #1
|
|||
|
|
800610c: 4013 ands r3, r2
|
|||
|
|
800610e: d104 bne.n 800611a <HAL_UART_IRQHandler+0x6e>
|
|||
|
|
|| ((cr1its & (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_RTOIE)) != 0U)))
|
|||
|
|
8006110: 69bb ldr r3, [r7, #24]
|
|||
|
|
8006112: 4aa7 ldr r2, [pc, #668] ; (80063b0 <HAL_UART_IRQHandler+0x304>)
|
|||
|
|
8006114: 4013 ands r3, r2
|
|||
|
|
8006116: d100 bne.n 800611a <HAL_UART_IRQHandler+0x6e>
|
|||
|
|
8006118: e0d0 b.n 80062bc <HAL_UART_IRQHandler+0x210>
|
|||
|
|
{
|
|||
|
|
/* UART parity error interrupt occurred -------------------------------------*/
|
|||
|
|
if (((isrflags & USART_ISR_PE) != 0U) && ((cr1its & USART_CR1_PEIE) != 0U))
|
|||
|
|
800611a: 69fb ldr r3, [r7, #28]
|
|||
|
|
800611c: 2201 movs r2, #1
|
|||
|
|
800611e: 4013 ands r3, r2
|
|||
|
|
8006120: d010 beq.n 8006144 <HAL_UART_IRQHandler+0x98>
|
|||
|
|
8006122: 69ba ldr r2, [r7, #24]
|
|||
|
|
8006124: 2380 movs r3, #128 ; 0x80
|
|||
|
|
8006126: 005b lsls r3, r3, #1
|
|||
|
|
8006128: 4013 ands r3, r2
|
|||
|
|
800612a: d00b beq.n 8006144 <HAL_UART_IRQHandler+0x98>
|
|||
|
|
{
|
|||
|
|
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_PEF);
|
|||
|
|
800612c: 687b ldr r3, [r7, #4]
|
|||
|
|
800612e: 681b ldr r3, [r3, #0]
|
|||
|
|
8006130: 2201 movs r2, #1
|
|||
|
|
8006132: 621a str r2, [r3, #32]
|
|||
|
|
|
|||
|
|
huart->ErrorCode |= HAL_UART_ERROR_PE;
|
|||
|
|
8006134: 687b ldr r3, [r7, #4]
|
|||
|
|
8006136: 2280 movs r2, #128 ; 0x80
|
|||
|
|
8006138: 589b ldr r3, [r3, r2]
|
|||
|
|
800613a: 2201 movs r2, #1
|
|||
|
|
800613c: 431a orrs r2, r3
|
|||
|
|
800613e: 687b ldr r3, [r7, #4]
|
|||
|
|
8006140: 2180 movs r1, #128 ; 0x80
|
|||
|
|
8006142: 505a str r2, [r3, r1]
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
/* UART frame error interrupt occurred --------------------------------------*/
|
|||
|
|
if (((isrflags & USART_ISR_FE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U))
|
|||
|
|
8006144: 69fb ldr r3, [r7, #28]
|
|||
|
|
8006146: 2202 movs r2, #2
|
|||
|
|
8006148: 4013 ands r3, r2
|
|||
|
|
800614a: d00f beq.n 800616c <HAL_UART_IRQHandler+0xc0>
|
|||
|
|
800614c: 697b ldr r3, [r7, #20]
|
|||
|
|
800614e: 2201 movs r2, #1
|
|||
|
|
8006150: 4013 ands r3, r2
|
|||
|
|
8006152: d00b beq.n 800616c <HAL_UART_IRQHandler+0xc0>
|
|||
|
|
{
|
|||
|
|
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_FEF);
|
|||
|
|
8006154: 687b ldr r3, [r7, #4]
|
|||
|
|
8006156: 681b ldr r3, [r3, #0]
|
|||
|
|
8006158: 2202 movs r2, #2
|
|||
|
|
800615a: 621a str r2, [r3, #32]
|
|||
|
|
|
|||
|
|
huart->ErrorCode |= HAL_UART_ERROR_FE;
|
|||
|
|
800615c: 687b ldr r3, [r7, #4]
|
|||
|
|
800615e: 2280 movs r2, #128 ; 0x80
|
|||
|
|
8006160: 589b ldr r3, [r3, r2]
|
|||
|
|
8006162: 2204 movs r2, #4
|
|||
|
|
8006164: 431a orrs r2, r3
|
|||
|
|
8006166: 687b ldr r3, [r7, #4]
|
|||
|
|
8006168: 2180 movs r1, #128 ; 0x80
|
|||
|
|
800616a: 505a str r2, [r3, r1]
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
/* UART noise error interrupt occurred --------------------------------------*/
|
|||
|
|
if (((isrflags & USART_ISR_NE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U))
|
|||
|
|
800616c: 69fb ldr r3, [r7, #28]
|
|||
|
|
800616e: 2204 movs r2, #4
|
|||
|
|
8006170: 4013 ands r3, r2
|
|||
|
|
8006172: d00f beq.n 8006194 <HAL_UART_IRQHandler+0xe8>
|
|||
|
|
8006174: 697b ldr r3, [r7, #20]
|
|||
|
|
8006176: 2201 movs r2, #1
|
|||
|
|
8006178: 4013 ands r3, r2
|
|||
|
|
800617a: d00b beq.n 8006194 <HAL_UART_IRQHandler+0xe8>
|
|||
|
|
{
|
|||
|
|
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_NEF);
|
|||
|
|
800617c: 687b ldr r3, [r7, #4]
|
|||
|
|
800617e: 681b ldr r3, [r3, #0]
|
|||
|
|
8006180: 2204 movs r2, #4
|
|||
|
|
8006182: 621a str r2, [r3, #32]
|
|||
|
|
|
|||
|
|
huart->ErrorCode |= HAL_UART_ERROR_NE;
|
|||
|
|
8006184: 687b ldr r3, [r7, #4]
|
|||
|
|
8006186: 2280 movs r2, #128 ; 0x80
|
|||
|
|
8006188: 589b ldr r3, [r3, r2]
|
|||
|
|
800618a: 2202 movs r2, #2
|
|||
|
|
800618c: 431a orrs r2, r3
|
|||
|
|
800618e: 687b ldr r3, [r7, #4]
|
|||
|
|
8006190: 2180 movs r1, #128 ; 0x80
|
|||
|
|
8006192: 505a str r2, [r3, r1]
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
/* UART Over-Run interrupt occurred -----------------------------------------*/
|
|||
|
|
if (((isrflags & USART_ISR_ORE) != 0U)
|
|||
|
|
8006194: 69fb ldr r3, [r7, #28]
|
|||
|
|
8006196: 2208 movs r2, #8
|
|||
|
|
8006198: 4013 ands r3, r2
|
|||
|
|
800619a: d013 beq.n 80061c4 <HAL_UART_IRQHandler+0x118>
|
|||
|
|
&& (((cr1its & USART_CR1_RXNEIE) != 0U) ||
|
|||
|
|
800619c: 69bb ldr r3, [r7, #24]
|
|||
|
|
800619e: 2220 movs r2, #32
|
|||
|
|
80061a0: 4013 ands r3, r2
|
|||
|
|
80061a2: d103 bne.n 80061ac <HAL_UART_IRQHandler+0x100>
|
|||
|
|
((cr3its & USART_CR3_EIE) != 0U)))
|
|||
|
|
80061a4: 697b ldr r3, [r7, #20]
|
|||
|
|
80061a6: 2201 movs r2, #1
|
|||
|
|
80061a8: 4013 ands r3, r2
|
|||
|
|
&& (((cr1its & USART_CR1_RXNEIE) != 0U) ||
|
|||
|
|
80061aa: d00b beq.n 80061c4 <HAL_UART_IRQHandler+0x118>
|
|||
|
|
{
|
|||
|
|
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF);
|
|||
|
|
80061ac: 687b ldr r3, [r7, #4]
|
|||
|
|
80061ae: 681b ldr r3, [r3, #0]
|
|||
|
|
80061b0: 2208 movs r2, #8
|
|||
|
|
80061b2: 621a str r2, [r3, #32]
|
|||
|
|
|
|||
|
|
huart->ErrorCode |= HAL_UART_ERROR_ORE;
|
|||
|
|
80061b4: 687b ldr r3, [r7, #4]
|
|||
|
|
80061b6: 2280 movs r2, #128 ; 0x80
|
|||
|
|
80061b8: 589b ldr r3, [r3, r2]
|
|||
|
|
80061ba: 2208 movs r2, #8
|
|||
|
|
80061bc: 431a orrs r2, r3
|
|||
|
|
80061be: 687b ldr r3, [r7, #4]
|
|||
|
|
80061c0: 2180 movs r1, #128 ; 0x80
|
|||
|
|
80061c2: 505a str r2, [r3, r1]
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
/* UART Receiver Timeout interrupt occurred ---------------------------------*/
|
|||
|
|
if (((isrflags & USART_ISR_RTOF) != 0U) && ((cr1its & USART_CR1_RTOIE) != 0U))
|
|||
|
|
80061c4: 69fa ldr r2, [r7, #28]
|
|||
|
|
80061c6: 2380 movs r3, #128 ; 0x80
|
|||
|
|
80061c8: 011b lsls r3, r3, #4
|
|||
|
|
80061ca: 4013 ands r3, r2
|
|||
|
|
80061cc: d011 beq.n 80061f2 <HAL_UART_IRQHandler+0x146>
|
|||
|
|
80061ce: 69ba ldr r2, [r7, #24]
|
|||
|
|
80061d0: 2380 movs r3, #128 ; 0x80
|
|||
|
|
80061d2: 04db lsls r3, r3, #19
|
|||
|
|
80061d4: 4013 ands r3, r2
|
|||
|
|
80061d6: d00c beq.n 80061f2 <HAL_UART_IRQHandler+0x146>
|
|||
|
|
{
|
|||
|
|
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_RTOF);
|
|||
|
|
80061d8: 687b ldr r3, [r7, #4]
|
|||
|
|
80061da: 681b ldr r3, [r3, #0]
|
|||
|
|
80061dc: 2280 movs r2, #128 ; 0x80
|
|||
|
|
80061de: 0112 lsls r2, r2, #4
|
|||
|
|
80061e0: 621a str r2, [r3, #32]
|
|||
|
|
|
|||
|
|
huart->ErrorCode |= HAL_UART_ERROR_RTO;
|
|||
|
|
80061e2: 687b ldr r3, [r7, #4]
|
|||
|
|
80061e4: 2280 movs r2, #128 ; 0x80
|
|||
|
|
80061e6: 589b ldr r3, [r3, r2]
|
|||
|
|
80061e8: 2220 movs r2, #32
|
|||
|
|
80061ea: 431a orrs r2, r3
|
|||
|
|
80061ec: 687b ldr r3, [r7, #4]
|
|||
|
|
80061ee: 2180 movs r1, #128 ; 0x80
|
|||
|
|
80061f0: 505a str r2, [r3, r1]
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
/* Call UART Error Call back function if need be ----------------------------*/
|
|||
|
|
if (huart->ErrorCode != HAL_UART_ERROR_NONE)
|
|||
|
|
80061f2: 687b ldr r3, [r7, #4]
|
|||
|
|
80061f4: 2280 movs r2, #128 ; 0x80
|
|||
|
|
80061f6: 589b ldr r3, [r3, r2]
|
|||
|
|
80061f8: 2b00 cmp r3, #0
|
|||
|
|
80061fa: d100 bne.n 80061fe <HAL_UART_IRQHandler+0x152>
|
|||
|
|
80061fc: e155 b.n 80064aa <HAL_UART_IRQHandler+0x3fe>
|
|||
|
|
{
|
|||
|
|
/* UART in mode Receiver --------------------------------------------------*/
|
|||
|
|
if (((isrflags & USART_ISR_RXNE) != 0U)
|
|||
|
|
80061fe: 69fb ldr r3, [r7, #28]
|
|||
|
|
8006200: 2220 movs r2, #32
|
|||
|
|
8006202: 4013 ands r3, r2
|
|||
|
|
8006204: d00c beq.n 8006220 <HAL_UART_IRQHandler+0x174>
|
|||
|
|
&& ((cr1its & USART_CR1_RXNEIE) != 0U))
|
|||
|
|
8006206: 69bb ldr r3, [r7, #24]
|
|||
|
|
8006208: 2220 movs r2, #32
|
|||
|
|
800620a: 4013 ands r3, r2
|
|||
|
|
800620c: d008 beq.n 8006220 <HAL_UART_IRQHandler+0x174>
|
|||
|
|
{
|
|||
|
|
if (huart->RxISR != NULL)
|
|||
|
|
800620e: 687b ldr r3, [r7, #4]
|
|||
|
|
8006210: 6e5b ldr r3, [r3, #100] ; 0x64
|
|||
|
|
8006212: 2b00 cmp r3, #0
|
|||
|
|
8006214: d004 beq.n 8006220 <HAL_UART_IRQHandler+0x174>
|
|||
|
|
{
|
|||
|
|
huart->RxISR(huart);
|
|||
|
|
8006216: 687b ldr r3, [r7, #4]
|
|||
|
|
8006218: 6e5b ldr r3, [r3, #100] ; 0x64
|
|||
|
|
800621a: 687a ldr r2, [r7, #4]
|
|||
|
|
800621c: 0010 movs r0, r2
|
|||
|
|
800621e: 4798 blx r3
|
|||
|
|
/* If Error is to be considered as blocking :
|
|||
|
|
- Receiver Timeout error in Reception
|
|||
|
|
- Overrun error in Reception
|
|||
|
|
- any error occurs in DMA mode reception
|
|||
|
|
*/
|
|||
|
|
errorcode = huart->ErrorCode;
|
|||
|
|
8006220: 687b ldr r3, [r7, #4]
|
|||
|
|
8006222: 2280 movs r2, #128 ; 0x80
|
|||
|
|
8006224: 589b ldr r3, [r3, r2]
|
|||
|
|
8006226: 60fb str r3, [r7, #12]
|
|||
|
|
if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) ||
|
|||
|
|
8006228: 687b ldr r3, [r7, #4]
|
|||
|
|
800622a: 681b ldr r3, [r3, #0]
|
|||
|
|
800622c: 689b ldr r3, [r3, #8]
|
|||
|
|
800622e: 2240 movs r2, #64 ; 0x40
|
|||
|
|
8006230: 4013 ands r3, r2
|
|||
|
|
8006232: 2b40 cmp r3, #64 ; 0x40
|
|||
|
|
8006234: d003 beq.n 800623e <HAL_UART_IRQHandler+0x192>
|
|||
|
|
((errorcode & (HAL_UART_ERROR_RTO | HAL_UART_ERROR_ORE)) != 0U))
|
|||
|
|
8006236: 68fb ldr r3, [r7, #12]
|
|||
|
|
8006238: 2228 movs r2, #40 ; 0x28
|
|||
|
|
800623a: 4013 ands r3, r2
|
|||
|
|
if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) ||
|
|||
|
|
800623c: d033 beq.n 80062a6 <HAL_UART_IRQHandler+0x1fa>
|
|||
|
|
{
|
|||
|
|
/* Blocking error : transfer is aborted
|
|||
|
|
Set the UART state ready to be able to start again the process,
|
|||
|
|
Disable Rx Interrupts, and disable Rx DMA request, if ongoing */
|
|||
|
|
UART_EndRxTransfer(huart);
|
|||
|
|
800623e: 687b ldr r3, [r7, #4]
|
|||
|
|
8006240: 0018 movs r0, r3
|
|||
|
|
8006242: f000 fd89 bl 8006d58 <UART_EndRxTransfer>
|
|||
|
|
|
|||
|
|
/* Disable the UART DMA Rx request if enabled */
|
|||
|
|
if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
|
|||
|
|
8006246: 687b ldr r3, [r7, #4]
|
|||
|
|
8006248: 681b ldr r3, [r3, #0]
|
|||
|
|
800624a: 689b ldr r3, [r3, #8]
|
|||
|
|
800624c: 2240 movs r2, #64 ; 0x40
|
|||
|
|
800624e: 4013 ands r3, r2
|
|||
|
|
8006250: 2b40 cmp r3, #64 ; 0x40
|
|||
|
|
8006252: d123 bne.n 800629c <HAL_UART_IRQHandler+0x1f0>
|
|||
|
|
{
|
|||
|
|
CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
|
|||
|
|
8006254: 687b ldr r3, [r7, #4]
|
|||
|
|
8006256: 681b ldr r3, [r3, #0]
|
|||
|
|
8006258: 687a ldr r2, [r7, #4]
|
|||
|
|
800625a: 6812 ldr r2, [r2, #0]
|
|||
|
|
800625c: 6892 ldr r2, [r2, #8]
|
|||
|
|
800625e: 2140 movs r1, #64 ; 0x40
|
|||
|
|
8006260: 438a bics r2, r1
|
|||
|
|
8006262: 609a str r2, [r3, #8]
|
|||
|
|
|
|||
|
|
/* Abort the UART DMA Rx channel */
|
|||
|
|
if (huart->hdmarx != NULL)
|
|||
|
|
8006264: 687b ldr r3, [r7, #4]
|
|||
|
|
8006266: 6f1b ldr r3, [r3, #112] ; 0x70
|
|||
|
|
8006268: 2b00 cmp r3, #0
|
|||
|
|
800626a: d012 beq.n 8006292 <HAL_UART_IRQHandler+0x1e6>
|
|||
|
|
{
|
|||
|
|
/* Set the UART DMA Abort callback :
|
|||
|
|
will lead to call HAL_UART_ErrorCallback() at end of DMA abort procedure */
|
|||
|
|
huart->hdmarx->XferAbortCallback = UART_DMAAbortOnError;
|
|||
|
|
800626c: 687b ldr r3, [r7, #4]
|
|||
|
|
800626e: 6f1b ldr r3, [r3, #112] ; 0x70
|
|||
|
|
8006270: 4a50 ldr r2, [pc, #320] ; (80063b4 <HAL_UART_IRQHandler+0x308>)
|
|||
|
|
8006272: 639a str r2, [r3, #56] ; 0x38
|
|||
|
|
|
|||
|
|
/* Abort DMA RX */
|
|||
|
|
if (HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK)
|
|||
|
|
8006274: 687b ldr r3, [r7, #4]
|
|||
|
|
8006276: 6f1b ldr r3, [r3, #112] ; 0x70
|
|||
|
|
8006278: 0018 movs r0, r3
|
|||
|
|
800627a: f7fd ffb0 bl 80041de <HAL_DMA_Abort_IT>
|
|||
|
|
800627e: 1e03 subs r3, r0, #0
|
|||
|
|
8006280: d01a beq.n 80062b8 <HAL_UART_IRQHandler+0x20c>
|
|||
|
|
{
|
|||
|
|
/* Call Directly huart->hdmarx->XferAbortCallback function in case of error */
|
|||
|
|
huart->hdmarx->XferAbortCallback(huart->hdmarx);
|
|||
|
|
8006282: 687b ldr r3, [r7, #4]
|
|||
|
|
8006284: 6f1b ldr r3, [r3, #112] ; 0x70
|
|||
|
|
8006286: 6b9a ldr r2, [r3, #56] ; 0x38
|
|||
|
|
8006288: 687b ldr r3, [r7, #4]
|
|||
|
|
800628a: 6f1b ldr r3, [r3, #112] ; 0x70
|
|||
|
|
800628c: 0018 movs r0, r3
|
|||
|
|
800628e: 4790 blx r2
|
|||
|
|
if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
|
|||
|
|
8006290: e012 b.n 80062b8 <HAL_UART_IRQHandler+0x20c>
|
|||
|
|
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
|
|||
|
|
/*Call registered error callback*/
|
|||
|
|
huart->ErrorCallback(huart);
|
|||
|
|
#else
|
|||
|
|
/*Call legacy weak error callback*/
|
|||
|
|
HAL_UART_ErrorCallback(huart);
|
|||
|
|
8006292: 687b ldr r3, [r7, #4]
|
|||
|
|
8006294: 0018 movs r0, r3
|
|||
|
|
8006296: f000 f915 bl 80064c4 <HAL_UART_ErrorCallback>
|
|||
|
|
if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
|
|||
|
|
800629a: e00d b.n 80062b8 <HAL_UART_IRQHandler+0x20c>
|
|||
|
|
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
|
|||
|
|
/*Call registered error callback*/
|
|||
|
|
huart->ErrorCallback(huart);
|
|||
|
|
#else
|
|||
|
|
/*Call legacy weak error callback*/
|
|||
|
|
HAL_UART_ErrorCallback(huart);
|
|||
|
|
800629c: 687b ldr r3, [r7, #4]
|
|||
|
|
800629e: 0018 movs r0, r3
|
|||
|
|
80062a0: f000 f910 bl 80064c4 <HAL_UART_ErrorCallback>
|
|||
|
|
if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
|
|||
|
|
80062a4: e008 b.n 80062b8 <HAL_UART_IRQHandler+0x20c>
|
|||
|
|
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
|
|||
|
|
/*Call registered error callback*/
|
|||
|
|
huart->ErrorCallback(huart);
|
|||
|
|
#else
|
|||
|
|
/*Call legacy weak error callback*/
|
|||
|
|
HAL_UART_ErrorCallback(huart);
|
|||
|
|
80062a6: 687b ldr r3, [r7, #4]
|
|||
|
|
80062a8: 0018 movs r0, r3
|
|||
|
|
80062aa: f000 f90b bl 80064c4 <HAL_UART_ErrorCallback>
|
|||
|
|
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
|
|||
|
|
huart->ErrorCode = HAL_UART_ERROR_NONE;
|
|||
|
|
80062ae: 687b ldr r3, [r7, #4]
|
|||
|
|
80062b0: 2280 movs r2, #128 ; 0x80
|
|||
|
|
80062b2: 2100 movs r1, #0
|
|||
|
|
80062b4: 5099 str r1, [r3, r2]
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
return;
|
|||
|
|
80062b6: e0f8 b.n 80064aa <HAL_UART_IRQHandler+0x3fe>
|
|||
|
|
if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
|
|||
|
|
80062b8: 46c0 nop ; (mov r8, r8)
|
|||
|
|
return;
|
|||
|
|
80062ba: e0f6 b.n 80064aa <HAL_UART_IRQHandler+0x3fe>
|
|||
|
|
|
|||
|
|
} /* End if some error occurs */
|
|||
|
|
|
|||
|
|
/* Check current reception Mode :
|
|||
|
|
If Reception till IDLE event has been selected : */
|
|||
|
|
if ( (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
|
|||
|
|
80062bc: 687b ldr r3, [r7, #4]
|
|||
|
|
80062be: 6e1b ldr r3, [r3, #96] ; 0x60
|
|||
|
|
80062c0: 2b01 cmp r3, #1
|
|||
|
|
80062c2: d000 beq.n 80062c6 <HAL_UART_IRQHandler+0x21a>
|
|||
|
|
80062c4: e0bb b.n 800643e <HAL_UART_IRQHandler+0x392>
|
|||
|
|
&&((isrflags & USART_ISR_IDLE) != 0U)
|
|||
|
|
80062c6: 69fb ldr r3, [r7, #28]
|
|||
|
|
80062c8: 2210 movs r2, #16
|
|||
|
|
80062ca: 4013 ands r3, r2
|
|||
|
|
80062cc: d100 bne.n 80062d0 <HAL_UART_IRQHandler+0x224>
|
|||
|
|
80062ce: e0b6 b.n 800643e <HAL_UART_IRQHandler+0x392>
|
|||
|
|
&&((cr1its & USART_ISR_IDLE) != 0U))
|
|||
|
|
80062d0: 69bb ldr r3, [r7, #24]
|
|||
|
|
80062d2: 2210 movs r2, #16
|
|||
|
|
80062d4: 4013 ands r3, r2
|
|||
|
|
80062d6: d100 bne.n 80062da <HAL_UART_IRQHandler+0x22e>
|
|||
|
|
80062d8: e0b1 b.n 800643e <HAL_UART_IRQHandler+0x392>
|
|||
|
|
{
|
|||
|
|
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF);
|
|||
|
|
80062da: 687b ldr r3, [r7, #4]
|
|||
|
|
80062dc: 681b ldr r3, [r3, #0]
|
|||
|
|
80062de: 2210 movs r2, #16
|
|||
|
|
80062e0: 621a str r2, [r3, #32]
|
|||
|
|
|
|||
|
|
/* Check if DMA mode is enabled in UART */
|
|||
|
|
if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
|
|||
|
|
80062e2: 687b ldr r3, [r7, #4]
|
|||
|
|
80062e4: 681b ldr r3, [r3, #0]
|
|||
|
|
80062e6: 689b ldr r3, [r3, #8]
|
|||
|
|
80062e8: 2240 movs r2, #64 ; 0x40
|
|||
|
|
80062ea: 4013 ands r3, r2
|
|||
|
|
80062ec: 2b40 cmp r3, #64 ; 0x40
|
|||
|
|
80062ee: d165 bne.n 80063bc <HAL_UART_IRQHandler+0x310>
|
|||
|
|
{
|
|||
|
|
/* DMA mode enabled */
|
|||
|
|
/* Check received length : If all expected data are received, do nothing,
|
|||
|
|
(DMA cplt callback will be called).
|
|||
|
|
Otherwise, if at least one data has already been received, IDLE event is to be notified to user */
|
|||
|
|
uint16_t nb_remaining_rx_data = (uint16_t) __HAL_DMA_GET_COUNTER(huart->hdmarx);
|
|||
|
|
80062f0: 687b ldr r3, [r7, #4]
|
|||
|
|
80062f2: 6f1b ldr r3, [r3, #112] ; 0x70
|
|||
|
|
80062f4: 681b ldr r3, [r3, #0]
|
|||
|
|
80062f6: 685a ldr r2, [r3, #4]
|
|||
|
|
80062f8: 230a movs r3, #10
|
|||
|
|
80062fa: 18fb adds r3, r7, r3
|
|||
|
|
80062fc: 801a strh r2, [r3, #0]
|
|||
|
|
if ( (nb_remaining_rx_data > 0U)
|
|||
|
|
80062fe: 230a movs r3, #10
|
|||
|
|
8006300: 18fb adds r3, r7, r3
|
|||
|
|
8006302: 881b ldrh r3, [r3, #0]
|
|||
|
|
8006304: 2b00 cmp r3, #0
|
|||
|
|
8006306: d100 bne.n 800630a <HAL_UART_IRQHandler+0x25e>
|
|||
|
|
8006308: e0d1 b.n 80064ae <HAL_UART_IRQHandler+0x402>
|
|||
|
|
&&(nb_remaining_rx_data < huart->RxXferSize))
|
|||
|
|
800630a: 687b ldr r3, [r7, #4]
|
|||
|
|
800630c: 2258 movs r2, #88 ; 0x58
|
|||
|
|
800630e: 5a9b ldrh r3, [r3, r2]
|
|||
|
|
8006310: 220a movs r2, #10
|
|||
|
|
8006312: 18ba adds r2, r7, r2
|
|||
|
|
8006314: 8812 ldrh r2, [r2, #0]
|
|||
|
|
8006316: 429a cmp r2, r3
|
|||
|
|
8006318: d300 bcc.n 800631c <HAL_UART_IRQHandler+0x270>
|
|||
|
|
800631a: e0c8 b.n 80064ae <HAL_UART_IRQHandler+0x402>
|
|||
|
|
{
|
|||
|
|
/* Reception is not complete */
|
|||
|
|
huart->RxXferCount = nb_remaining_rx_data;
|
|||
|
|
800631c: 687b ldr r3, [r7, #4]
|
|||
|
|
800631e: 220a movs r2, #10
|
|||
|
|
8006320: 18ba adds r2, r7, r2
|
|||
|
|
8006322: 215a movs r1, #90 ; 0x5a
|
|||
|
|
8006324: 8812 ldrh r2, [r2, #0]
|
|||
|
|
8006326: 525a strh r2, [r3, r1]
|
|||
|
|
|
|||
|
|
/* In Normal mode, end DMA xfer and HAL UART Rx process*/
|
|||
|
|
if (HAL_IS_BIT_CLR(huart->hdmarx->Instance->CCR, DMA_CCR_CIRC))
|
|||
|
|
8006328: 687b ldr r3, [r7, #4]
|
|||
|
|
800632a: 6f1b ldr r3, [r3, #112] ; 0x70
|
|||
|
|
800632c: 681b ldr r3, [r3, #0]
|
|||
|
|
800632e: 681b ldr r3, [r3, #0]
|
|||
|
|
8006330: 2220 movs r2, #32
|
|||
|
|
8006332: 4013 ands r3, r2
|
|||
|
|
8006334: d12a bne.n 800638c <HAL_UART_IRQHandler+0x2e0>
|
|||
|
|
{
|
|||
|
|
/* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */
|
|||
|
|
CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE);
|
|||
|
|
8006336: 687b ldr r3, [r7, #4]
|
|||
|
|
8006338: 681b ldr r3, [r3, #0]
|
|||
|
|
800633a: 687a ldr r2, [r7, #4]
|
|||
|
|
800633c: 6812 ldr r2, [r2, #0]
|
|||
|
|
800633e: 6812 ldr r2, [r2, #0]
|
|||
|
|
8006340: 491d ldr r1, [pc, #116] ; (80063b8 <HAL_UART_IRQHandler+0x30c>)
|
|||
|
|
8006342: 400a ands r2, r1
|
|||
|
|
8006344: 601a str r2, [r3, #0]
|
|||
|
|
CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
|
|||
|
|
8006346: 687b ldr r3, [r7, #4]
|
|||
|
|
8006348: 681b ldr r3, [r3, #0]
|
|||
|
|
800634a: 687a ldr r2, [r7, #4]
|
|||
|
|
800634c: 6812 ldr r2, [r2, #0]
|
|||
|
|
800634e: 6892 ldr r2, [r2, #8]
|
|||
|
|
8006350: 2101 movs r1, #1
|
|||
|
|
8006352: 438a bics r2, r1
|
|||
|
|
8006354: 609a str r2, [r3, #8]
|
|||
|
|
|
|||
|
|
/* Disable the DMA transfer for the receiver request by resetting the DMAR bit
|
|||
|
|
in the UART CR3 register */
|
|||
|
|
CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
|
|||
|
|
8006356: 687b ldr r3, [r7, #4]
|
|||
|
|
8006358: 681b ldr r3, [r3, #0]
|
|||
|
|
800635a: 687a ldr r2, [r7, #4]
|
|||
|
|
800635c: 6812 ldr r2, [r2, #0]
|
|||
|
|
800635e: 6892 ldr r2, [r2, #8]
|
|||
|
|
8006360: 2140 movs r1, #64 ; 0x40
|
|||
|
|
8006362: 438a bics r2, r1
|
|||
|
|
8006364: 609a str r2, [r3, #8]
|
|||
|
|
|
|||
|
|
/* At end of Rx process, restore huart->RxState to Ready */
|
|||
|
|
huart->RxState = HAL_UART_STATE_READY;
|
|||
|
|
8006366: 687b ldr r3, [r7, #4]
|
|||
|
|
8006368: 2220 movs r2, #32
|
|||
|
|
800636a: 67da str r2, [r3, #124] ; 0x7c
|
|||
|
|
huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
|
|||
|
|
800636c: 687b ldr r3, [r7, #4]
|
|||
|
|
800636e: 2200 movs r2, #0
|
|||
|
|
8006370: 661a str r2, [r3, #96] ; 0x60
|
|||
|
|
|
|||
|
|
CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
|
|||
|
|
8006372: 687b ldr r3, [r7, #4]
|
|||
|
|
8006374: 681b ldr r3, [r3, #0]
|
|||
|
|
8006376: 687a ldr r2, [r7, #4]
|
|||
|
|
8006378: 6812 ldr r2, [r2, #0]
|
|||
|
|
800637a: 6812 ldr r2, [r2, #0]
|
|||
|
|
800637c: 2110 movs r1, #16
|
|||
|
|
800637e: 438a bics r2, r1
|
|||
|
|
8006380: 601a str r2, [r3, #0]
|
|||
|
|
|
|||
|
|
/* Last bytes received, so no need as the abort is immediate */
|
|||
|
|
(void)HAL_DMA_Abort(huart->hdmarx);
|
|||
|
|
8006382: 687b ldr r3, [r7, #4]
|
|||
|
|
8006384: 6f1b ldr r3, [r3, #112] ; 0x70
|
|||
|
|
8006386: 0018 movs r0, r3
|
|||
|
|
8006388: f7fd fee9 bl 800415e <HAL_DMA_Abort>
|
|||
|
|
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
|
|||
|
|
/*Call registered Rx Event callback*/
|
|||
|
|
huart->RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount));
|
|||
|
|
#else
|
|||
|
|
/*Call legacy weak Rx Event callback*/
|
|||
|
|
HAL_UARTEx_RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount));
|
|||
|
|
800638c: 687b ldr r3, [r7, #4]
|
|||
|
|
800638e: 2258 movs r2, #88 ; 0x58
|
|||
|
|
8006390: 5a9a ldrh r2, [r3, r2]
|
|||
|
|
8006392: 687b ldr r3, [r7, #4]
|
|||
|
|
8006394: 215a movs r1, #90 ; 0x5a
|
|||
|
|
8006396: 5a5b ldrh r3, [r3, r1]
|
|||
|
|
8006398: b29b uxth r3, r3
|
|||
|
|
800639a: 1ad3 subs r3, r2, r3
|
|||
|
|
800639c: b29a uxth r2, r3
|
|||
|
|
800639e: 687b ldr r3, [r7, #4]
|
|||
|
|
80063a0: 0011 movs r1, r2
|
|||
|
|
80063a2: 0018 movs r0, r3
|
|||
|
|
80063a4: f000 f896 bl 80064d4 <HAL_UARTEx_RxEventCallback>
|
|||
|
|
#endif
|
|||
|
|
}
|
|||
|
|
return;
|
|||
|
|
80063a8: e081 b.n 80064ae <HAL_UART_IRQHandler+0x402>
|
|||
|
|
80063aa: 46c0 nop ; (mov r8, r8)
|
|||
|
|
80063ac: 0000080f .word 0x0000080f
|
|||
|
|
80063b0: 04000120 .word 0x04000120
|
|||
|
|
80063b4: 08006db9 .word 0x08006db9
|
|||
|
|
80063b8: fffffeff .word 0xfffffeff
|
|||
|
|
else
|
|||
|
|
{
|
|||
|
|
/* DMA mode not enabled */
|
|||
|
|
/* Check received length : If all expected data are received, do nothing.
|
|||
|
|
Otherwise, if at least one data has already been received, IDLE event is to be notified to user */
|
|||
|
|
uint16_t nb_rx_data = huart->RxXferSize - huart->RxXferCount;
|
|||
|
|
80063bc: 687b ldr r3, [r7, #4]
|
|||
|
|
80063be: 2258 movs r2, #88 ; 0x58
|
|||
|
|
80063c0: 5a99 ldrh r1, [r3, r2]
|
|||
|
|
80063c2: 687b ldr r3, [r7, #4]
|
|||
|
|
80063c4: 225a movs r2, #90 ; 0x5a
|
|||
|
|
80063c6: 5a9b ldrh r3, [r3, r2]
|
|||
|
|
80063c8: b29a uxth r2, r3
|
|||
|
|
80063ca: 2308 movs r3, #8
|
|||
|
|
80063cc: 18fb adds r3, r7, r3
|
|||
|
|
80063ce: 1a8a subs r2, r1, r2
|
|||
|
|
80063d0: 801a strh r2, [r3, #0]
|
|||
|
|
if ( (huart->RxXferCount > 0U)
|
|||
|
|
80063d2: 687b ldr r3, [r7, #4]
|
|||
|
|
80063d4: 225a movs r2, #90 ; 0x5a
|
|||
|
|
80063d6: 5a9b ldrh r3, [r3, r2]
|
|||
|
|
80063d8: b29b uxth r3, r3
|
|||
|
|
80063da: 2b00 cmp r3, #0
|
|||
|
|
80063dc: d100 bne.n 80063e0 <HAL_UART_IRQHandler+0x334>
|
|||
|
|
80063de: e068 b.n 80064b2 <HAL_UART_IRQHandler+0x406>
|
|||
|
|
&&(nb_rx_data > 0U) )
|
|||
|
|
80063e0: 2308 movs r3, #8
|
|||
|
|
80063e2: 18fb adds r3, r7, r3
|
|||
|
|
80063e4: 881b ldrh r3, [r3, #0]
|
|||
|
|
80063e6: 2b00 cmp r3, #0
|
|||
|
|
80063e8: d063 beq.n 80064b2 <HAL_UART_IRQHandler+0x406>
|
|||
|
|
{
|
|||
|
|
/* Disable the UART Parity Error Interrupt and RXNE interrupts */
|
|||
|
|
CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
|
|||
|
|
80063ea: 687b ldr r3, [r7, #4]
|
|||
|
|
80063ec: 681b ldr r3, [r3, #0]
|
|||
|
|
80063ee: 687a ldr r2, [r7, #4]
|
|||
|
|
80063f0: 6812 ldr r2, [r2, #0]
|
|||
|
|
80063f2: 6812 ldr r2, [r2, #0]
|
|||
|
|
80063f4: 4932 ldr r1, [pc, #200] ; (80064c0 <HAL_UART_IRQHandler+0x414>)
|
|||
|
|
80063f6: 400a ands r2, r1
|
|||
|
|
80063f8: 601a str r2, [r3, #0]
|
|||
|
|
|
|||
|
|
/* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */
|
|||
|
|
CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
|
|||
|
|
80063fa: 687b ldr r3, [r7, #4]
|
|||
|
|
80063fc: 681b ldr r3, [r3, #0]
|
|||
|
|
80063fe: 687a ldr r2, [r7, #4]
|
|||
|
|
8006400: 6812 ldr r2, [r2, #0]
|
|||
|
|
8006402: 6892 ldr r2, [r2, #8]
|
|||
|
|
8006404: 2101 movs r1, #1
|
|||
|
|
8006406: 438a bics r2, r1
|
|||
|
|
8006408: 609a str r2, [r3, #8]
|
|||
|
|
|
|||
|
|
/* Rx process is completed, restore huart->RxState to Ready */
|
|||
|
|
huart->RxState = HAL_UART_STATE_READY;
|
|||
|
|
800640a: 687b ldr r3, [r7, #4]
|
|||
|
|
800640c: 2220 movs r2, #32
|
|||
|
|
800640e: 67da str r2, [r3, #124] ; 0x7c
|
|||
|
|
huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
|
|||
|
|
8006410: 687b ldr r3, [r7, #4]
|
|||
|
|
8006412: 2200 movs r2, #0
|
|||
|
|
8006414: 661a str r2, [r3, #96] ; 0x60
|
|||
|
|
|
|||
|
|
/* Clear RxISR function pointer */
|
|||
|
|
huart->RxISR = NULL;
|
|||
|
|
8006416: 687b ldr r3, [r7, #4]
|
|||
|
|
8006418: 2200 movs r2, #0
|
|||
|
|
800641a: 665a str r2, [r3, #100] ; 0x64
|
|||
|
|
|
|||
|
|
CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
|
|||
|
|
800641c: 687b ldr r3, [r7, #4]
|
|||
|
|
800641e: 681b ldr r3, [r3, #0]
|
|||
|
|
8006420: 687a ldr r2, [r7, #4]
|
|||
|
|
8006422: 6812 ldr r2, [r2, #0]
|
|||
|
|
8006424: 6812 ldr r2, [r2, #0]
|
|||
|
|
8006426: 2110 movs r1, #16
|
|||
|
|
8006428: 438a bics r2, r1
|
|||
|
|
800642a: 601a str r2, [r3, #0]
|
|||
|
|
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
|
|||
|
|
/*Call registered Rx complete callback*/
|
|||
|
|
huart->RxEventCallback(huart, nb_rx_data);
|
|||
|
|
#else
|
|||
|
|
/*Call legacy weak Rx Event callback*/
|
|||
|
|
HAL_UARTEx_RxEventCallback(huart, nb_rx_data);
|
|||
|
|
800642c: 2308 movs r3, #8
|
|||
|
|
800642e: 18fb adds r3, r7, r3
|
|||
|
|
8006430: 881a ldrh r2, [r3, #0]
|
|||
|
|
8006432: 687b ldr r3, [r7, #4]
|
|||
|
|
8006434: 0011 movs r1, r2
|
|||
|
|
8006436: 0018 movs r0, r3
|
|||
|
|
8006438: f000 f84c bl 80064d4 <HAL_UARTEx_RxEventCallback>
|
|||
|
|
#endif
|
|||
|
|
}
|
|||
|
|
return;
|
|||
|
|
800643c: e039 b.n 80064b2 <HAL_UART_IRQHandler+0x406>
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
/* UART wakeup from Stop mode interrupt occurred ---------------------------*/
|
|||
|
|
if (((isrflags & USART_ISR_WUF) != 0U) && ((cr3its & USART_CR3_WUFIE) != 0U))
|
|||
|
|
800643e: 69fa ldr r2, [r7, #28]
|
|||
|
|
8006440: 2380 movs r3, #128 ; 0x80
|
|||
|
|
8006442: 035b lsls r3, r3, #13
|
|||
|
|
8006444: 4013 ands r3, r2
|
|||
|
|
8006446: d00e beq.n 8006466 <HAL_UART_IRQHandler+0x3ba>
|
|||
|
|
8006448: 697a ldr r2, [r7, #20]
|
|||
|
|
800644a: 2380 movs r3, #128 ; 0x80
|
|||
|
|
800644c: 03db lsls r3, r3, #15
|
|||
|
|
800644e: 4013 ands r3, r2
|
|||
|
|
8006450: d009 beq.n 8006466 <HAL_UART_IRQHandler+0x3ba>
|
|||
|
|
{
|
|||
|
|
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_WUF);
|
|||
|
|
8006452: 687b ldr r3, [r7, #4]
|
|||
|
|
8006454: 681b ldr r3, [r3, #0]
|
|||
|
|
8006456: 2280 movs r2, #128 ; 0x80
|
|||
|
|
8006458: 0352 lsls r2, r2, #13
|
|||
|
|
800645a: 621a str r2, [r3, #32]
|
|||
|
|
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
|
|||
|
|
/* Call registered Wakeup Callback */
|
|||
|
|
huart->WakeupCallback(huart);
|
|||
|
|
#else
|
|||
|
|
/* Call legacy weak Wakeup Callback */
|
|||
|
|
HAL_UARTEx_WakeupCallback(huart);
|
|||
|
|
800645c: 687b ldr r3, [r7, #4]
|
|||
|
|
800645e: 0018 movs r0, r3
|
|||
|
|
8006460: f000 fd4d bl 8006efe <HAL_UARTEx_WakeupCallback>
|
|||
|
|
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
|
|||
|
|
return;
|
|||
|
|
8006464: e028 b.n 80064b8 <HAL_UART_IRQHandler+0x40c>
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
/* UART in mode Transmitter ------------------------------------------------*/
|
|||
|
|
if (((isrflags & USART_ISR_TXE) != 0U)
|
|||
|
|
8006466: 69fb ldr r3, [r7, #28]
|
|||
|
|
8006468: 2280 movs r2, #128 ; 0x80
|
|||
|
|
800646a: 4013 ands r3, r2
|
|||
|
|
800646c: d00d beq.n 800648a <HAL_UART_IRQHandler+0x3de>
|
|||
|
|
&& ((cr1its & USART_CR1_TXEIE) != 0U))
|
|||
|
|
800646e: 69bb ldr r3, [r7, #24]
|
|||
|
|
8006470: 2280 movs r2, #128 ; 0x80
|
|||
|
|
8006472: 4013 ands r3, r2
|
|||
|
|
8006474: d009 beq.n 800648a <HAL_UART_IRQHandler+0x3de>
|
|||
|
|
{
|
|||
|
|
if (huart->TxISR != NULL)
|
|||
|
|
8006476: 687b ldr r3, [r7, #4]
|
|||
|
|
8006478: 6e9b ldr r3, [r3, #104] ; 0x68
|
|||
|
|
800647a: 2b00 cmp r3, #0
|
|||
|
|
800647c: d01b beq.n 80064b6 <HAL_UART_IRQHandler+0x40a>
|
|||
|
|
{
|
|||
|
|
huart->TxISR(huart);
|
|||
|
|
800647e: 687b ldr r3, [r7, #4]
|
|||
|
|
8006480: 6e9b ldr r3, [r3, #104] ; 0x68
|
|||
|
|
8006482: 687a ldr r2, [r7, #4]
|
|||
|
|
8006484: 0010 movs r0, r2
|
|||
|
|
8006486: 4798 blx r3
|
|||
|
|
}
|
|||
|
|
return;
|
|||
|
|
8006488: e015 b.n 80064b6 <HAL_UART_IRQHandler+0x40a>
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
/* UART in mode Transmitter (transmission end) -----------------------------*/
|
|||
|
|
if (((isrflags & USART_ISR_TC) != 0U) && ((cr1its & USART_CR1_TCIE) != 0U))
|
|||
|
|
800648a: 69fb ldr r3, [r7, #28]
|
|||
|
|
800648c: 2240 movs r2, #64 ; 0x40
|
|||
|
|
800648e: 4013 ands r3, r2
|
|||
|
|
8006490: d012 beq.n 80064b8 <HAL_UART_IRQHandler+0x40c>
|
|||
|
|
8006492: 69bb ldr r3, [r7, #24]
|
|||
|
|
8006494: 2240 movs r2, #64 ; 0x40
|
|||
|
|
8006496: 4013 ands r3, r2
|
|||
|
|
8006498: d00e beq.n 80064b8 <HAL_UART_IRQHandler+0x40c>
|
|||
|
|
{
|
|||
|
|
UART_EndTransmit_IT(huart);
|
|||
|
|
800649a: 687b ldr r3, [r7, #4]
|
|||
|
|
800649c: 0018 movs r0, r3
|
|||
|
|
800649e: f000 fd14 bl 8006eca <UART_EndTransmit_IT>
|
|||
|
|
return;
|
|||
|
|
80064a2: 46c0 nop ; (mov r8, r8)
|
|||
|
|
80064a4: e008 b.n 80064b8 <HAL_UART_IRQHandler+0x40c>
|
|||
|
|
return;
|
|||
|
|
80064a6: 46c0 nop ; (mov r8, r8)
|
|||
|
|
80064a8: e006 b.n 80064b8 <HAL_UART_IRQHandler+0x40c>
|
|||
|
|
return;
|
|||
|
|
80064aa: 46c0 nop ; (mov r8, r8)
|
|||
|
|
80064ac: e004 b.n 80064b8 <HAL_UART_IRQHandler+0x40c>
|
|||
|
|
return;
|
|||
|
|
80064ae: 46c0 nop ; (mov r8, r8)
|
|||
|
|
80064b0: e002 b.n 80064b8 <HAL_UART_IRQHandler+0x40c>
|
|||
|
|
return;
|
|||
|
|
80064b2: 46c0 nop ; (mov r8, r8)
|
|||
|
|
80064b4: e000 b.n 80064b8 <HAL_UART_IRQHandler+0x40c>
|
|||
|
|
return;
|
|||
|
|
80064b6: 46c0 nop ; (mov r8, r8)
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
}
|
|||
|
|
80064b8: 46bd mov sp, r7
|
|||
|
|
80064ba: b008 add sp, #32
|
|||
|
|
80064bc: bd80 pop {r7, pc}
|
|||
|
|
80064be: 46c0 nop ; (mov r8, r8)
|
|||
|
|
80064c0: fffffedf .word 0xfffffedf
|
|||
|
|
|
|||
|
|
080064c4 <HAL_UART_ErrorCallback>:
|
|||
|
|
* @brief UART error callback.
|
|||
|
|
* @param huart UART handle.
|
|||
|
|
* @retval None
|
|||
|
|
*/
|
|||
|
|
__weak void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart)
|
|||
|
|
{
|
|||
|
|
80064c4: b580 push {r7, lr}
|
|||
|
|
80064c6: b082 sub sp, #8
|
|||
|
|
80064c8: af00 add r7, sp, #0
|
|||
|
|
80064ca: 6078 str r0, [r7, #4]
|
|||
|
|
UNUSED(huart);
|
|||
|
|
|
|||
|
|
/* NOTE : This function should not be modified, when the callback is needed,
|
|||
|
|
the HAL_UART_ErrorCallback can be implemented in the user file.
|
|||
|
|
*/
|
|||
|
|
}
|
|||
|
|
80064cc: 46c0 nop ; (mov r8, r8)
|
|||
|
|
80064ce: 46bd mov sp, r7
|
|||
|
|
80064d0: b002 add sp, #8
|
|||
|
|
80064d2: bd80 pop {r7, pc}
|
|||
|
|
|
|||
|
|
080064d4 <HAL_UARTEx_RxEventCallback>:
|
|||
|
|
* @param Size Number of data available in application reception buffer (indicates a position in
|
|||
|
|
* reception buffer until which, data are available)
|
|||
|
|
* @retval None
|
|||
|
|
*/
|
|||
|
|
__weak void HAL_UARTEx_RxEventCallback(UART_HandleTypeDef *huart, uint16_t Size)
|
|||
|
|
{
|
|||
|
|
80064d4: b580 push {r7, lr}
|
|||
|
|
80064d6: b082 sub sp, #8
|
|||
|
|
80064d8: af00 add r7, sp, #0
|
|||
|
|
80064da: 6078 str r0, [r7, #4]
|
|||
|
|
80064dc: 000a movs r2, r1
|
|||
|
|
80064de: 1cbb adds r3, r7, #2
|
|||
|
|
80064e0: 801a strh r2, [r3, #0]
|
|||
|
|
UNUSED(Size);
|
|||
|
|
|
|||
|
|
/* NOTE : This function should not be modified, when the callback is needed,
|
|||
|
|
the HAL_UARTEx_RxEventCallback can be implemented in the user file.
|
|||
|
|
*/
|
|||
|
|
}
|
|||
|
|
80064e2: 46c0 nop ; (mov r8, r8)
|
|||
|
|
80064e4: 46bd mov sp, r7
|
|||
|
|
80064e6: b002 add sp, #8
|
|||
|
|
80064e8: bd80 pop {r7, pc}
|
|||
|
|
...
|
|||
|
|
|
|||
|
|
080064ec <UART_SetConfig>:
|
|||
|
|
* @brief Configure the UART peripheral.
|
|||
|
|
* @param huart UART handle.
|
|||
|
|
* @retval HAL status
|
|||
|
|
*/
|
|||
|
|
HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart)
|
|||
|
|
{
|
|||
|
|
80064ec: b5b0 push {r4, r5, r7, lr}
|
|||
|
|
80064ee: b08e sub sp, #56 ; 0x38
|
|||
|
|
80064f0: af00 add r7, sp, #0
|
|||
|
|
80064f2: 61f8 str r0, [r7, #28]
|
|||
|
|
uint32_t tmpreg;
|
|||
|
|
uint16_t brrtemp;
|
|||
|
|
UART_ClockSourceTypeDef clocksource;
|
|||
|
|
uint32_t usartdiv;
|
|||
|
|
HAL_StatusTypeDef ret = HAL_OK;
|
|||
|
|
80064f4: 231a movs r3, #26
|
|||
|
|
80064f6: 2218 movs r2, #24
|
|||
|
|
80064f8: 4694 mov ip, r2
|
|||
|
|
80064fa: 44bc add ip, r7
|
|||
|
|
80064fc: 4463 add r3, ip
|
|||
|
|
80064fe: 2200 movs r2, #0
|
|||
|
|
8006500: 701a strb r2, [r3, #0]
|
|||
|
|
* the UART Word Length, Parity, Mode and oversampling:
|
|||
|
|
* set the M bits according to huart->Init.WordLength value
|
|||
|
|
* set PCE and PS bits according to huart->Init.Parity value
|
|||
|
|
* set TE and RE bits according to huart->Init.Mode value
|
|||
|
|
* set OVER8 bit according to huart->Init.OverSampling value */
|
|||
|
|
tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.OverSampling ;
|
|||
|
|
8006502: 69fb ldr r3, [r7, #28]
|
|||
|
|
8006504: 689a ldr r2, [r3, #8]
|
|||
|
|
8006506: 69fb ldr r3, [r7, #28]
|
|||
|
|
8006508: 691b ldr r3, [r3, #16]
|
|||
|
|
800650a: 431a orrs r2, r3
|
|||
|
|
800650c: 69fb ldr r3, [r7, #28]
|
|||
|
|
800650e: 695b ldr r3, [r3, #20]
|
|||
|
|
8006510: 431a orrs r2, r3
|
|||
|
|
8006512: 69fb ldr r3, [r7, #28]
|
|||
|
|
8006514: 69db ldr r3, [r3, #28]
|
|||
|
|
8006516: 4313 orrs r3, r2
|
|||
|
|
8006518: 637b str r3, [r7, #52] ; 0x34
|
|||
|
|
MODIFY_REG(huart->Instance->CR1, USART_CR1_FIELDS, tmpreg);
|
|||
|
|
800651a: 69fb ldr r3, [r7, #28]
|
|||
|
|
800651c: 681b ldr r3, [r3, #0]
|
|||
|
|
800651e: 69fa ldr r2, [r7, #28]
|
|||
|
|
8006520: 6812 ldr r2, [r2, #0]
|
|||
|
|
8006522: 6812 ldr r2, [r2, #0]
|
|||
|
|
8006524: 49c8 ldr r1, [pc, #800] ; (8006848 <UART_SetConfig+0x35c>)
|
|||
|
|
8006526: 4011 ands r1, r2
|
|||
|
|
8006528: 6b7a ldr r2, [r7, #52] ; 0x34
|
|||
|
|
800652a: 430a orrs r2, r1
|
|||
|
|
800652c: 601a str r2, [r3, #0]
|
|||
|
|
|
|||
|
|
/*-------------------------- USART CR2 Configuration -----------------------*/
|
|||
|
|
/* Configure the UART Stop Bits: Set STOP[13:12] bits according
|
|||
|
|
* to huart->Init.StopBits value */
|
|||
|
|
MODIFY_REG(huart->Instance->CR2, USART_CR2_STOP, huart->Init.StopBits);
|
|||
|
|
800652e: 69fb ldr r3, [r7, #28]
|
|||
|
|
8006530: 681b ldr r3, [r3, #0]
|
|||
|
|
8006532: 69fa ldr r2, [r7, #28]
|
|||
|
|
8006534: 6812 ldr r2, [r2, #0]
|
|||
|
|
8006536: 6852 ldr r2, [r2, #4]
|
|||
|
|
8006538: 49c4 ldr r1, [pc, #784] ; (800684c <UART_SetConfig+0x360>)
|
|||
|
|
800653a: 4011 ands r1, r2
|
|||
|
|
800653c: 69fa ldr r2, [r7, #28]
|
|||
|
|
800653e: 68d2 ldr r2, [r2, #12]
|
|||
|
|
8006540: 430a orrs r2, r1
|
|||
|
|
8006542: 605a str r2, [r3, #4]
|
|||
|
|
/* Configure
|
|||
|
|
* - UART HardWare Flow Control: set CTSE and RTSE bits according
|
|||
|
|
* to huart->Init.HwFlowCtl value
|
|||
|
|
* - one-bit sampling method versus three samples' majority rule according
|
|||
|
|
* to huart->Init.OneBitSampling (not applicable to LPUART) */
|
|||
|
|
tmpreg = (uint32_t)huart->Init.HwFlowCtl;
|
|||
|
|
8006544: 69fb ldr r3, [r7, #28]
|
|||
|
|
8006546: 699b ldr r3, [r3, #24]
|
|||
|
|
8006548: 637b str r3, [r7, #52] ; 0x34
|
|||
|
|
|
|||
|
|
if (!(UART_INSTANCE_LOWPOWER(huart)))
|
|||
|
|
800654a: 69fb ldr r3, [r7, #28]
|
|||
|
|
800654c: 681b ldr r3, [r3, #0]
|
|||
|
|
800654e: 4ac0 ldr r2, [pc, #768] ; (8006850 <UART_SetConfig+0x364>)
|
|||
|
|
8006550: 4293 cmp r3, r2
|
|||
|
|
8006552: d004 beq.n 800655e <UART_SetConfig+0x72>
|
|||
|
|
{
|
|||
|
|
tmpreg |= huart->Init.OneBitSampling;
|
|||
|
|
8006554: 69fb ldr r3, [r7, #28]
|
|||
|
|
8006556: 6a1b ldr r3, [r3, #32]
|
|||
|
|
8006558: 6b7a ldr r2, [r7, #52] ; 0x34
|
|||
|
|
800655a: 4313 orrs r3, r2
|
|||
|
|
800655c: 637b str r3, [r7, #52] ; 0x34
|
|||
|
|
}
|
|||
|
|
MODIFY_REG(huart->Instance->CR3, USART_CR3_FIELDS, tmpreg);
|
|||
|
|
800655e: 69fb ldr r3, [r7, #28]
|
|||
|
|
8006560: 681b ldr r3, [r3, #0]
|
|||
|
|
8006562: 69fa ldr r2, [r7, #28]
|
|||
|
|
8006564: 6812 ldr r2, [r2, #0]
|
|||
|
|
8006566: 6892 ldr r2, [r2, #8]
|
|||
|
|
8006568: 49ba ldr r1, [pc, #744] ; (8006854 <UART_SetConfig+0x368>)
|
|||
|
|
800656a: 4011 ands r1, r2
|
|||
|
|
800656c: 6b7a ldr r2, [r7, #52] ; 0x34
|
|||
|
|
800656e: 430a orrs r2, r1
|
|||
|
|
8006570: 609a str r2, [r3, #8]
|
|||
|
|
|
|||
|
|
|
|||
|
|
/*-------------------------- USART BRR Configuration -----------------------*/
|
|||
|
|
UART_GETCLOCKSOURCE(huart, clocksource);
|
|||
|
|
8006572: 69fb ldr r3, [r7, #28]
|
|||
|
|
8006574: 681b ldr r3, [r3, #0]
|
|||
|
|
8006576: 4ab8 ldr r2, [pc, #736] ; (8006858 <UART_SetConfig+0x36c>)
|
|||
|
|
8006578: 4293 cmp r3, r2
|
|||
|
|
800657a: d134 bne.n 80065e6 <UART_SetConfig+0xfa>
|
|||
|
|
800657c: 4bb7 ldr r3, [pc, #732] ; (800685c <UART_SetConfig+0x370>)
|
|||
|
|
800657e: 6cdb ldr r3, [r3, #76] ; 0x4c
|
|||
|
|
8006580: 2203 movs r2, #3
|
|||
|
|
8006582: 4013 ands r3, r2
|
|||
|
|
8006584: 2b01 cmp r3, #1
|
|||
|
|
8006586: d015 beq.n 80065b4 <UART_SetConfig+0xc8>
|
|||
|
|
8006588: d304 bcc.n 8006594 <UART_SetConfig+0xa8>
|
|||
|
|
800658a: 2b02 cmp r3, #2
|
|||
|
|
800658c: d00a beq.n 80065a4 <UART_SetConfig+0xb8>
|
|||
|
|
800658e: 2b03 cmp r3, #3
|
|||
|
|
8006590: d018 beq.n 80065c4 <UART_SetConfig+0xd8>
|
|||
|
|
8006592: e01f b.n 80065d4 <UART_SetConfig+0xe8>
|
|||
|
|
8006594: 231b movs r3, #27
|
|||
|
|
8006596: 2218 movs r2, #24
|
|||
|
|
8006598: 4694 mov ip, r2
|
|||
|
|
800659a: 44bc add ip, r7
|
|||
|
|
800659c: 4463 add r3, ip
|
|||
|
|
800659e: 2201 movs r2, #1
|
|||
|
|
80065a0: 701a strb r2, [r3, #0]
|
|||
|
|
80065a2: e0c5 b.n 8006730 <UART_SetConfig+0x244>
|
|||
|
|
80065a4: 231b movs r3, #27
|
|||
|
|
80065a6: 2218 movs r2, #24
|
|||
|
|
80065a8: 4694 mov ip, r2
|
|||
|
|
80065aa: 44bc add ip, r7
|
|||
|
|
80065ac: 4463 add r3, ip
|
|||
|
|
80065ae: 2202 movs r2, #2
|
|||
|
|
80065b0: 701a strb r2, [r3, #0]
|
|||
|
|
80065b2: e0bd b.n 8006730 <UART_SetConfig+0x244>
|
|||
|
|
80065b4: 231b movs r3, #27
|
|||
|
|
80065b6: 2218 movs r2, #24
|
|||
|
|
80065b8: 4694 mov ip, r2
|
|||
|
|
80065ba: 44bc add ip, r7
|
|||
|
|
80065bc: 4463 add r3, ip
|
|||
|
|
80065be: 2204 movs r2, #4
|
|||
|
|
80065c0: 701a strb r2, [r3, #0]
|
|||
|
|
80065c2: e0b5 b.n 8006730 <UART_SetConfig+0x244>
|
|||
|
|
80065c4: 231b movs r3, #27
|
|||
|
|
80065c6: 2218 movs r2, #24
|
|||
|
|
80065c8: 4694 mov ip, r2
|
|||
|
|
80065ca: 44bc add ip, r7
|
|||
|
|
80065cc: 4463 add r3, ip
|
|||
|
|
80065ce: 2208 movs r2, #8
|
|||
|
|
80065d0: 701a strb r2, [r3, #0]
|
|||
|
|
80065d2: e0ad b.n 8006730 <UART_SetConfig+0x244>
|
|||
|
|
80065d4: 231b movs r3, #27
|
|||
|
|
80065d6: 2218 movs r2, #24
|
|||
|
|
80065d8: 4694 mov ip, r2
|
|||
|
|
80065da: 44bc add ip, r7
|
|||
|
|
80065dc: 4463 add r3, ip
|
|||
|
|
80065de: 2210 movs r2, #16
|
|||
|
|
80065e0: 701a strb r2, [r3, #0]
|
|||
|
|
80065e2: 46c0 nop ; (mov r8, r8)
|
|||
|
|
80065e4: e0a4 b.n 8006730 <UART_SetConfig+0x244>
|
|||
|
|
80065e6: 69fb ldr r3, [r7, #28]
|
|||
|
|
80065e8: 681b ldr r3, [r3, #0]
|
|||
|
|
80065ea: 4a9d ldr r2, [pc, #628] ; (8006860 <UART_SetConfig+0x374>)
|
|||
|
|
80065ec: 4293 cmp r3, r2
|
|||
|
|
80065ee: d137 bne.n 8006660 <UART_SetConfig+0x174>
|
|||
|
|
80065f0: 4b9a ldr r3, [pc, #616] ; (800685c <UART_SetConfig+0x370>)
|
|||
|
|
80065f2: 6cdb ldr r3, [r3, #76] ; 0x4c
|
|||
|
|
80065f4: 220c movs r2, #12
|
|||
|
|
80065f6: 4013 ands r3, r2
|
|||
|
|
80065f8: 2b04 cmp r3, #4
|
|||
|
|
80065fa: d018 beq.n 800662e <UART_SetConfig+0x142>
|
|||
|
|
80065fc: d802 bhi.n 8006604 <UART_SetConfig+0x118>
|
|||
|
|
80065fe: 2b00 cmp r3, #0
|
|||
|
|
8006600: d005 beq.n 800660e <UART_SetConfig+0x122>
|
|||
|
|
8006602: e024 b.n 800664e <UART_SetConfig+0x162>
|
|||
|
|
8006604: 2b08 cmp r3, #8
|
|||
|
|
8006606: d00a beq.n 800661e <UART_SetConfig+0x132>
|
|||
|
|
8006608: 2b0c cmp r3, #12
|
|||
|
|
800660a: d018 beq.n 800663e <UART_SetConfig+0x152>
|
|||
|
|
800660c: e01f b.n 800664e <UART_SetConfig+0x162>
|
|||
|
|
800660e: 231b movs r3, #27
|
|||
|
|
8006610: 2218 movs r2, #24
|
|||
|
|
8006612: 4694 mov ip, r2
|
|||
|
|
8006614: 44bc add ip, r7
|
|||
|
|
8006616: 4463 add r3, ip
|
|||
|
|
8006618: 2200 movs r2, #0
|
|||
|
|
800661a: 701a strb r2, [r3, #0]
|
|||
|
|
800661c: e088 b.n 8006730 <UART_SetConfig+0x244>
|
|||
|
|
800661e: 231b movs r3, #27
|
|||
|
|
8006620: 2218 movs r2, #24
|
|||
|
|
8006622: 4694 mov ip, r2
|
|||
|
|
8006624: 44bc add ip, r7
|
|||
|
|
8006626: 4463 add r3, ip
|
|||
|
|
8006628: 2202 movs r2, #2
|
|||
|
|
800662a: 701a strb r2, [r3, #0]
|
|||
|
|
800662c: e080 b.n 8006730 <UART_SetConfig+0x244>
|
|||
|
|
800662e: 231b movs r3, #27
|
|||
|
|
8006630: 2218 movs r2, #24
|
|||
|
|
8006632: 4694 mov ip, r2
|
|||
|
|
8006634: 44bc add ip, r7
|
|||
|
|
8006636: 4463 add r3, ip
|
|||
|
|
8006638: 2204 movs r2, #4
|
|||
|
|
800663a: 701a strb r2, [r3, #0]
|
|||
|
|
800663c: e078 b.n 8006730 <UART_SetConfig+0x244>
|
|||
|
|
800663e: 231b movs r3, #27
|
|||
|
|
8006640: 2218 movs r2, #24
|
|||
|
|
8006642: 4694 mov ip, r2
|
|||
|
|
8006644: 44bc add ip, r7
|
|||
|
|
8006646: 4463 add r3, ip
|
|||
|
|
8006648: 2208 movs r2, #8
|
|||
|
|
800664a: 701a strb r2, [r3, #0]
|
|||
|
|
800664c: e070 b.n 8006730 <UART_SetConfig+0x244>
|
|||
|
|
800664e: 231b movs r3, #27
|
|||
|
|
8006650: 2218 movs r2, #24
|
|||
|
|
8006652: 4694 mov ip, r2
|
|||
|
|
8006654: 44bc add ip, r7
|
|||
|
|
8006656: 4463 add r3, ip
|
|||
|
|
8006658: 2210 movs r2, #16
|
|||
|
|
800665a: 701a strb r2, [r3, #0]
|
|||
|
|
800665c: 46c0 nop ; (mov r8, r8)
|
|||
|
|
800665e: e067 b.n 8006730 <UART_SetConfig+0x244>
|
|||
|
|
8006660: 69fb ldr r3, [r7, #28]
|
|||
|
|
8006662: 681b ldr r3, [r3, #0]
|
|||
|
|
8006664: 4a7f ldr r2, [pc, #508] ; (8006864 <UART_SetConfig+0x378>)
|
|||
|
|
8006666: 4293 cmp r3, r2
|
|||
|
|
8006668: d107 bne.n 800667a <UART_SetConfig+0x18e>
|
|||
|
|
800666a: 231b movs r3, #27
|
|||
|
|
800666c: 2218 movs r2, #24
|
|||
|
|
800666e: 4694 mov ip, r2
|
|||
|
|
8006670: 44bc add ip, r7
|
|||
|
|
8006672: 4463 add r3, ip
|
|||
|
|
8006674: 2200 movs r2, #0
|
|||
|
|
8006676: 701a strb r2, [r3, #0]
|
|||
|
|
8006678: e05a b.n 8006730 <UART_SetConfig+0x244>
|
|||
|
|
800667a: 69fb ldr r3, [r7, #28]
|
|||
|
|
800667c: 681b ldr r3, [r3, #0]
|
|||
|
|
800667e: 4a7a ldr r2, [pc, #488] ; (8006868 <UART_SetConfig+0x37c>)
|
|||
|
|
8006680: 4293 cmp r3, r2
|
|||
|
|
8006682: d107 bne.n 8006694 <UART_SetConfig+0x1a8>
|
|||
|
|
8006684: 231b movs r3, #27
|
|||
|
|
8006686: 2218 movs r2, #24
|
|||
|
|
8006688: 4694 mov ip, r2
|
|||
|
|
800668a: 44bc add ip, r7
|
|||
|
|
800668c: 4463 add r3, ip
|
|||
|
|
800668e: 2200 movs r2, #0
|
|||
|
|
8006690: 701a strb r2, [r3, #0]
|
|||
|
|
8006692: e04d b.n 8006730 <UART_SetConfig+0x244>
|
|||
|
|
8006694: 69fb ldr r3, [r7, #28]
|
|||
|
|
8006696: 681b ldr r3, [r3, #0]
|
|||
|
|
8006698: 4a6d ldr r2, [pc, #436] ; (8006850 <UART_SetConfig+0x364>)
|
|||
|
|
800669a: 4293 cmp r3, r2
|
|||
|
|
800669c: d141 bne.n 8006722 <UART_SetConfig+0x236>
|
|||
|
|
800669e: 4b6f ldr r3, [pc, #444] ; (800685c <UART_SetConfig+0x370>)
|
|||
|
|
80066a0: 6cda ldr r2, [r3, #76] ; 0x4c
|
|||
|
|
80066a2: 23c0 movs r3, #192 ; 0xc0
|
|||
|
|
80066a4: 011b lsls r3, r3, #4
|
|||
|
|
80066a6: 4013 ands r3, r2
|
|||
|
|
80066a8: 2280 movs r2, #128 ; 0x80
|
|||
|
|
80066aa: 00d2 lsls r2, r2, #3
|
|||
|
|
80066ac: 4293 cmp r3, r2
|
|||
|
|
80066ae: d01f beq.n 80066f0 <UART_SetConfig+0x204>
|
|||
|
|
80066b0: 2280 movs r2, #128 ; 0x80
|
|||
|
|
80066b2: 00d2 lsls r2, r2, #3
|
|||
|
|
80066b4: 4293 cmp r3, r2
|
|||
|
|
80066b6: d802 bhi.n 80066be <UART_SetConfig+0x1d2>
|
|||
|
|
80066b8: 2b00 cmp r3, #0
|
|||
|
|
80066ba: d009 beq.n 80066d0 <UART_SetConfig+0x1e4>
|
|||
|
|
80066bc: e028 b.n 8006710 <UART_SetConfig+0x224>
|
|||
|
|
80066be: 2280 movs r2, #128 ; 0x80
|
|||
|
|
80066c0: 0112 lsls r2, r2, #4
|
|||
|
|
80066c2: 4293 cmp r3, r2
|
|||
|
|
80066c4: d00c beq.n 80066e0 <UART_SetConfig+0x1f4>
|
|||
|
|
80066c6: 22c0 movs r2, #192 ; 0xc0
|
|||
|
|
80066c8: 0112 lsls r2, r2, #4
|
|||
|
|
80066ca: 4293 cmp r3, r2
|
|||
|
|
80066cc: d018 beq.n 8006700 <UART_SetConfig+0x214>
|
|||
|
|
80066ce: e01f b.n 8006710 <UART_SetConfig+0x224>
|
|||
|
|
80066d0: 231b movs r3, #27
|
|||
|
|
80066d2: 2218 movs r2, #24
|
|||
|
|
80066d4: 4694 mov ip, r2
|
|||
|
|
80066d6: 44bc add ip, r7
|
|||
|
|
80066d8: 4463 add r3, ip
|
|||
|
|
80066da: 2200 movs r2, #0
|
|||
|
|
80066dc: 701a strb r2, [r3, #0]
|
|||
|
|
80066de: e027 b.n 8006730 <UART_SetConfig+0x244>
|
|||
|
|
80066e0: 231b movs r3, #27
|
|||
|
|
80066e2: 2218 movs r2, #24
|
|||
|
|
80066e4: 4694 mov ip, r2
|
|||
|
|
80066e6: 44bc add ip, r7
|
|||
|
|
80066e8: 4463 add r3, ip
|
|||
|
|
80066ea: 2202 movs r2, #2
|
|||
|
|
80066ec: 701a strb r2, [r3, #0]
|
|||
|
|
80066ee: e01f b.n 8006730 <UART_SetConfig+0x244>
|
|||
|
|
80066f0: 231b movs r3, #27
|
|||
|
|
80066f2: 2218 movs r2, #24
|
|||
|
|
80066f4: 4694 mov ip, r2
|
|||
|
|
80066f6: 44bc add ip, r7
|
|||
|
|
80066f8: 4463 add r3, ip
|
|||
|
|
80066fa: 2204 movs r2, #4
|
|||
|
|
80066fc: 701a strb r2, [r3, #0]
|
|||
|
|
80066fe: e017 b.n 8006730 <UART_SetConfig+0x244>
|
|||
|
|
8006700: 231b movs r3, #27
|
|||
|
|
8006702: 2218 movs r2, #24
|
|||
|
|
8006704: 4694 mov ip, r2
|
|||
|
|
8006706: 44bc add ip, r7
|
|||
|
|
8006708: 4463 add r3, ip
|
|||
|
|
800670a: 2208 movs r2, #8
|
|||
|
|
800670c: 701a strb r2, [r3, #0]
|
|||
|
|
800670e: e00f b.n 8006730 <UART_SetConfig+0x244>
|
|||
|
|
8006710: 231b movs r3, #27
|
|||
|
|
8006712: 2218 movs r2, #24
|
|||
|
|
8006714: 4694 mov ip, r2
|
|||
|
|
8006716: 44bc add ip, r7
|
|||
|
|
8006718: 4463 add r3, ip
|
|||
|
|
800671a: 2210 movs r2, #16
|
|||
|
|
800671c: 701a strb r2, [r3, #0]
|
|||
|
|
800671e: 46c0 nop ; (mov r8, r8)
|
|||
|
|
8006720: e006 b.n 8006730 <UART_SetConfig+0x244>
|
|||
|
|
8006722: 231b movs r3, #27
|
|||
|
|
8006724: 2218 movs r2, #24
|
|||
|
|
8006726: 4694 mov ip, r2
|
|||
|
|
8006728: 44bc add ip, r7
|
|||
|
|
800672a: 4463 add r3, ip
|
|||
|
|
800672c: 2210 movs r2, #16
|
|||
|
|
800672e: 701a strb r2, [r3, #0]
|
|||
|
|
|
|||
|
|
/* Check LPUART instance */
|
|||
|
|
if (UART_INSTANCE_LOWPOWER(huart))
|
|||
|
|
8006730: 69fb ldr r3, [r7, #28]
|
|||
|
|
8006732: 681b ldr r3, [r3, #0]
|
|||
|
|
8006734: 4a46 ldr r2, [pc, #280] ; (8006850 <UART_SetConfig+0x364>)
|
|||
|
|
8006736: 4293 cmp r3, r2
|
|||
|
|
8006738: d000 beq.n 800673c <UART_SetConfig+0x250>
|
|||
|
|
800673a: e09f b.n 800687c <UART_SetConfig+0x390>
|
|||
|
|
{
|
|||
|
|
/* Retrieve frequency clock */
|
|||
|
|
switch (clocksource)
|
|||
|
|
800673c: 231b movs r3, #27
|
|||
|
|
800673e: 2218 movs r2, #24
|
|||
|
|
8006740: 4694 mov ip, r2
|
|||
|
|
8006742: 44bc add ip, r7
|
|||
|
|
8006744: 4463 add r3, ip
|
|||
|
|
8006746: 781b ldrb r3, [r3, #0]
|
|||
|
|
8006748: 2b02 cmp r3, #2
|
|||
|
|
800674a: d00d beq.n 8006768 <UART_SetConfig+0x27c>
|
|||
|
|
800674c: dc02 bgt.n 8006754 <UART_SetConfig+0x268>
|
|||
|
|
800674e: 2b00 cmp r3, #0
|
|||
|
|
8006750: d005 beq.n 800675e <UART_SetConfig+0x272>
|
|||
|
|
8006752: e01d b.n 8006790 <UART_SetConfig+0x2a4>
|
|||
|
|
8006754: 2b04 cmp r3, #4
|
|||
|
|
8006756: d012 beq.n 800677e <UART_SetConfig+0x292>
|
|||
|
|
8006758: 2b08 cmp r3, #8
|
|||
|
|
800675a: d015 beq.n 8006788 <UART_SetConfig+0x29c>
|
|||
|
|
800675c: e018 b.n 8006790 <UART_SetConfig+0x2a4>
|
|||
|
|
{
|
|||
|
|
case UART_CLOCKSOURCE_PCLK1:
|
|||
|
|
pclk = HAL_RCC_GetPCLK1Freq();
|
|||
|
|
800675e: f7fe ffd5 bl 800570c <HAL_RCC_GetPCLK1Freq>
|
|||
|
|
8006762: 0003 movs r3, r0
|
|||
|
|
8006764: 62fb str r3, [r7, #44] ; 0x2c
|
|||
|
|
break;
|
|||
|
|
8006766: e01d b.n 80067a4 <UART_SetConfig+0x2b8>
|
|||
|
|
case UART_CLOCKSOURCE_HSI:
|
|||
|
|
if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U)
|
|||
|
|
8006768: 4b3c ldr r3, [pc, #240] ; (800685c <UART_SetConfig+0x370>)
|
|||
|
|
800676a: 681b ldr r3, [r3, #0]
|
|||
|
|
800676c: 2210 movs r2, #16
|
|||
|
|
800676e: 4013 ands r3, r2
|
|||
|
|
8006770: d002 beq.n 8006778 <UART_SetConfig+0x28c>
|
|||
|
|
{
|
|||
|
|
pclk = (uint32_t)(HSI_VALUE >> 2U);
|
|||
|
|
8006772: 4b3e ldr r3, [pc, #248] ; (800686c <UART_SetConfig+0x380>)
|
|||
|
|
8006774: 62fb str r3, [r7, #44] ; 0x2c
|
|||
|
|
}
|
|||
|
|
else
|
|||
|
|
{
|
|||
|
|
pclk = (uint32_t) HSI_VALUE;
|
|||
|
|
}
|
|||
|
|
break;
|
|||
|
|
8006776: e015 b.n 80067a4 <UART_SetConfig+0x2b8>
|
|||
|
|
pclk = (uint32_t) HSI_VALUE;
|
|||
|
|
8006778: 4b3d ldr r3, [pc, #244] ; (8006870 <UART_SetConfig+0x384>)
|
|||
|
|
800677a: 62fb str r3, [r7, #44] ; 0x2c
|
|||
|
|
break;
|
|||
|
|
800677c: e012 b.n 80067a4 <UART_SetConfig+0x2b8>
|
|||
|
|
case UART_CLOCKSOURCE_SYSCLK:
|
|||
|
|
pclk = HAL_RCC_GetSysClockFreq();
|
|||
|
|
800677e: f7fe ff19 bl 80055b4 <HAL_RCC_GetSysClockFreq>
|
|||
|
|
8006782: 0003 movs r3, r0
|
|||
|
|
8006784: 62fb str r3, [r7, #44] ; 0x2c
|
|||
|
|
break;
|
|||
|
|
8006786: e00d b.n 80067a4 <UART_SetConfig+0x2b8>
|
|||
|
|
case UART_CLOCKSOURCE_LSE:
|
|||
|
|
pclk = (uint32_t) LSE_VALUE;
|
|||
|
|
8006788: 2380 movs r3, #128 ; 0x80
|
|||
|
|
800678a: 021b lsls r3, r3, #8
|
|||
|
|
800678c: 62fb str r3, [r7, #44] ; 0x2c
|
|||
|
|
break;
|
|||
|
|
800678e: e009 b.n 80067a4 <UART_SetConfig+0x2b8>
|
|||
|
|
default:
|
|||
|
|
pclk = 0U;
|
|||
|
|
8006790: 2300 movs r3, #0
|
|||
|
|
8006792: 62fb str r3, [r7, #44] ; 0x2c
|
|||
|
|
ret = HAL_ERROR;
|
|||
|
|
8006794: 231a movs r3, #26
|
|||
|
|
8006796: 2218 movs r2, #24
|
|||
|
|
8006798: 4694 mov ip, r2
|
|||
|
|
800679a: 44bc add ip, r7
|
|||
|
|
800679c: 4463 add r3, ip
|
|||
|
|
800679e: 2201 movs r2, #1
|
|||
|
|
80067a0: 701a strb r2, [r3, #0]
|
|||
|
|
break;
|
|||
|
|
80067a2: 46c0 nop ; (mov r8, r8)
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
/* If proper clock source reported */
|
|||
|
|
if (pclk != 0U)
|
|||
|
|
80067a4: 6afb ldr r3, [r7, #44] ; 0x2c
|
|||
|
|
80067a6: 2b00 cmp r3, #0
|
|||
|
|
80067a8: d100 bne.n 80067ac <UART_SetConfig+0x2c0>
|
|||
|
|
80067aa: e145 b.n 8006a38 <UART_SetConfig+0x54c>
|
|||
|
|
{
|
|||
|
|
/* No Prescaler applicable */
|
|||
|
|
/* Ensure that Frequency clock is in the range [3 * baudrate, 4096 * baudrate] */
|
|||
|
|
if ((pclk < (3U * huart->Init.BaudRate)) ||
|
|||
|
|
80067ac: 69fb ldr r3, [r7, #28]
|
|||
|
|
80067ae: 685a ldr r2, [r3, #4]
|
|||
|
|
80067b0: 0013 movs r3, r2
|
|||
|
|
80067b2: 005b lsls r3, r3, #1
|
|||
|
|
80067b4: 189a adds r2, r3, r2
|
|||
|
|
80067b6: 6afb ldr r3, [r7, #44] ; 0x2c
|
|||
|
|
80067b8: 429a cmp r2, r3
|
|||
|
|
80067ba: d805 bhi.n 80067c8 <UART_SetConfig+0x2dc>
|
|||
|
|
(pclk > (4096U * huart->Init.BaudRate)))
|
|||
|
|
80067bc: 69fb ldr r3, [r7, #28]
|
|||
|
|
80067be: 685b ldr r3, [r3, #4]
|
|||
|
|
80067c0: 031a lsls r2, r3, #12
|
|||
|
|
if ((pclk < (3U * huart->Init.BaudRate)) ||
|
|||
|
|
80067c2: 6afb ldr r3, [r7, #44] ; 0x2c
|
|||
|
|
80067c4: 429a cmp r2, r3
|
|||
|
|
80067c6: d207 bcs.n 80067d8 <UART_SetConfig+0x2ec>
|
|||
|
|
{
|
|||
|
|
ret = HAL_ERROR;
|
|||
|
|
80067c8: 231a movs r3, #26
|
|||
|
|
80067ca: 2218 movs r2, #24
|
|||
|
|
80067cc: 4694 mov ip, r2
|
|||
|
|
80067ce: 44bc add ip, r7
|
|||
|
|
80067d0: 4463 add r3, ip
|
|||
|
|
80067d2: 2201 movs r2, #1
|
|||
|
|
80067d4: 701a strb r2, [r3, #0]
|
|||
|
|
80067d6: e12f b.n 8006a38 <UART_SetConfig+0x54c>
|
|||
|
|
}
|
|||
|
|
else
|
|||
|
|
{
|
|||
|
|
usartdiv = (uint32_t)(UART_DIV_LPUART(pclk, huart->Init.BaudRate));
|
|||
|
|
80067d8: 6afb ldr r3, [r7, #44] ; 0x2c
|
|||
|
|
80067da: 613b str r3, [r7, #16]
|
|||
|
|
80067dc: 2300 movs r3, #0
|
|||
|
|
80067de: 617b str r3, [r7, #20]
|
|||
|
|
80067e0: 6939 ldr r1, [r7, #16]
|
|||
|
|
80067e2: 697a ldr r2, [r7, #20]
|
|||
|
|
80067e4: 000b movs r3, r1
|
|||
|
|
80067e6: 0e1b lsrs r3, r3, #24
|
|||
|
|
80067e8: 0010 movs r0, r2
|
|||
|
|
80067ea: 0205 lsls r5, r0, #8
|
|||
|
|
80067ec: 431d orrs r5, r3
|
|||
|
|
80067ee: 000b movs r3, r1
|
|||
|
|
80067f0: 021c lsls r4, r3, #8
|
|||
|
|
80067f2: 69fb ldr r3, [r7, #28]
|
|||
|
|
80067f4: 685b ldr r3, [r3, #4]
|
|||
|
|
80067f6: 085b lsrs r3, r3, #1
|
|||
|
|
80067f8: 60bb str r3, [r7, #8]
|
|||
|
|
80067fa: 2300 movs r3, #0
|
|||
|
|
80067fc: 60fb str r3, [r7, #12]
|
|||
|
|
80067fe: 68b8 ldr r0, [r7, #8]
|
|||
|
|
8006800: 68f9 ldr r1, [r7, #12]
|
|||
|
|
8006802: 1900 adds r0, r0, r4
|
|||
|
|
8006804: 4169 adcs r1, r5
|
|||
|
|
8006806: 69fb ldr r3, [r7, #28]
|
|||
|
|
8006808: 685b ldr r3, [r3, #4]
|
|||
|
|
800680a: 603b str r3, [r7, #0]
|
|||
|
|
800680c: 2300 movs r3, #0
|
|||
|
|
800680e: 607b str r3, [r7, #4]
|
|||
|
|
8006810: 683a ldr r2, [r7, #0]
|
|||
|
|
8006812: 687b ldr r3, [r7, #4]
|
|||
|
|
8006814: f7f9 fd7c bl 8000310 <__aeabi_uldivmod>
|
|||
|
|
8006818: 0003 movs r3, r0
|
|||
|
|
800681a: 000c movs r4, r1
|
|||
|
|
800681c: 62bb str r3, [r7, #40] ; 0x28
|
|||
|
|
if ((usartdiv >= LPUART_BRR_MIN) && (usartdiv <= LPUART_BRR_MAX))
|
|||
|
|
800681e: 6abb ldr r3, [r7, #40] ; 0x28
|
|||
|
|
8006820: 4a14 ldr r2, [pc, #80] ; (8006874 <UART_SetConfig+0x388>)
|
|||
|
|
8006822: 4293 cmp r3, r2
|
|||
|
|
8006824: d908 bls.n 8006838 <UART_SetConfig+0x34c>
|
|||
|
|
8006826: 6abb ldr r3, [r7, #40] ; 0x28
|
|||
|
|
8006828: 4a13 ldr r2, [pc, #76] ; (8006878 <UART_SetConfig+0x38c>)
|
|||
|
|
800682a: 4293 cmp r3, r2
|
|||
|
|
800682c: d804 bhi.n 8006838 <UART_SetConfig+0x34c>
|
|||
|
|
{
|
|||
|
|
huart->Instance->BRR = usartdiv;
|
|||
|
|
800682e: 69fb ldr r3, [r7, #28]
|
|||
|
|
8006830: 681b ldr r3, [r3, #0]
|
|||
|
|
8006832: 6aba ldr r2, [r7, #40] ; 0x28
|
|||
|
|
8006834: 60da str r2, [r3, #12]
|
|||
|
|
8006836: e0ff b.n 8006a38 <UART_SetConfig+0x54c>
|
|||
|
|
}
|
|||
|
|
else
|
|||
|
|
{
|
|||
|
|
ret = HAL_ERROR;
|
|||
|
|
8006838: 231a movs r3, #26
|
|||
|
|
800683a: 2218 movs r2, #24
|
|||
|
|
800683c: 4694 mov ip, r2
|
|||
|
|
800683e: 44bc add ip, r7
|
|||
|
|
8006840: 4463 add r3, ip
|
|||
|
|
8006842: 2201 movs r2, #1
|
|||
|
|
8006844: 701a strb r2, [r3, #0]
|
|||
|
|
8006846: e0f7 b.n 8006a38 <UART_SetConfig+0x54c>
|
|||
|
|
8006848: efff69f3 .word 0xefff69f3
|
|||
|
|
800684c: ffffcfff .word 0xffffcfff
|
|||
|
|
8006850: 40004800 .word 0x40004800
|
|||
|
|
8006854: fffff4ff .word 0xfffff4ff
|
|||
|
|
8006858: 40013800 .word 0x40013800
|
|||
|
|
800685c: 40021000 .word 0x40021000
|
|||
|
|
8006860: 40004400 .word 0x40004400
|
|||
|
|
8006864: 40004c00 .word 0x40004c00
|
|||
|
|
8006868: 40005000 .word 0x40005000
|
|||
|
|
800686c: 003d0900 .word 0x003d0900
|
|||
|
|
8006870: 00f42400 .word 0x00f42400
|
|||
|
|
8006874: 000002ff .word 0x000002ff
|
|||
|
|
8006878: 000fffff .word 0x000fffff
|
|||
|
|
}
|
|||
|
|
} /* if ( (pclk < (3 * huart->Init.BaudRate) ) || (pclk > (4096 * huart->Init.BaudRate) )) */
|
|||
|
|
} /* if (pclk != 0) */
|
|||
|
|
}
|
|||
|
|
/* Check UART Over Sampling to set Baud Rate Register */
|
|||
|
|
else if (huart->Init.OverSampling == UART_OVERSAMPLING_8)
|
|||
|
|
800687c: 69fb ldr r3, [r7, #28]
|
|||
|
|
800687e: 69da ldr r2, [r3, #28]
|
|||
|
|
8006880: 2380 movs r3, #128 ; 0x80
|
|||
|
|
8006882: 021b lsls r3, r3, #8
|
|||
|
|
8006884: 429a cmp r2, r3
|
|||
|
|
8006886: d000 beq.n 800688a <UART_SetConfig+0x39e>
|
|||
|
|
8006888: e07d b.n 8006986 <UART_SetConfig+0x49a>
|
|||
|
|
{
|
|||
|
|
switch (clocksource)
|
|||
|
|
800688a: 231b movs r3, #27
|
|||
|
|
800688c: 2218 movs r2, #24
|
|||
|
|
800688e: 4694 mov ip, r2
|
|||
|
|
8006890: 44bc add ip, r7
|
|||
|
|
8006892: 4463 add r3, ip
|
|||
|
|
8006894: 781b ldrb r3, [r3, #0]
|
|||
|
|
8006896: 2b08 cmp r3, #8
|
|||
|
|
8006898: d822 bhi.n 80068e0 <UART_SetConfig+0x3f4>
|
|||
|
|
800689a: 009a lsls r2, r3, #2
|
|||
|
|
800689c: 4b6e ldr r3, [pc, #440] ; (8006a58 <UART_SetConfig+0x56c>)
|
|||
|
|
800689e: 18d3 adds r3, r2, r3
|
|||
|
|
80068a0: 681b ldr r3, [r3, #0]
|
|||
|
|
80068a2: 469f mov pc, r3
|
|||
|
|
{
|
|||
|
|
case UART_CLOCKSOURCE_PCLK1:
|
|||
|
|
pclk = HAL_RCC_GetPCLK1Freq();
|
|||
|
|
80068a4: f7fe ff32 bl 800570c <HAL_RCC_GetPCLK1Freq>
|
|||
|
|
80068a8: 0003 movs r3, r0
|
|||
|
|
80068aa: 62fb str r3, [r7, #44] ; 0x2c
|
|||
|
|
break;
|
|||
|
|
80068ac: e022 b.n 80068f4 <UART_SetConfig+0x408>
|
|||
|
|
case UART_CLOCKSOURCE_PCLK2:
|
|||
|
|
pclk = HAL_RCC_GetPCLK2Freq();
|
|||
|
|
80068ae: f7fe ff43 bl 8005738 <HAL_RCC_GetPCLK2Freq>
|
|||
|
|
80068b2: 0003 movs r3, r0
|
|||
|
|
80068b4: 62fb str r3, [r7, #44] ; 0x2c
|
|||
|
|
break;
|
|||
|
|
80068b6: e01d b.n 80068f4 <UART_SetConfig+0x408>
|
|||
|
|
case UART_CLOCKSOURCE_HSI:
|
|||
|
|
if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U)
|
|||
|
|
80068b8: 4b68 ldr r3, [pc, #416] ; (8006a5c <UART_SetConfig+0x570>)
|
|||
|
|
80068ba: 681b ldr r3, [r3, #0]
|
|||
|
|
80068bc: 2210 movs r2, #16
|
|||
|
|
80068be: 4013 ands r3, r2
|
|||
|
|
80068c0: d002 beq.n 80068c8 <UART_SetConfig+0x3dc>
|
|||
|
|
{
|
|||
|
|
pclk = (uint32_t)(HSI_VALUE >> 2U);
|
|||
|
|
80068c2: 4b67 ldr r3, [pc, #412] ; (8006a60 <UART_SetConfig+0x574>)
|
|||
|
|
80068c4: 62fb str r3, [r7, #44] ; 0x2c
|
|||
|
|
}
|
|||
|
|
else
|
|||
|
|
{
|
|||
|
|
pclk = (uint32_t) HSI_VALUE;
|
|||
|
|
}
|
|||
|
|
break;
|
|||
|
|
80068c6: e015 b.n 80068f4 <UART_SetConfig+0x408>
|
|||
|
|
pclk = (uint32_t) HSI_VALUE;
|
|||
|
|
80068c8: 4b66 ldr r3, [pc, #408] ; (8006a64 <UART_SetConfig+0x578>)
|
|||
|
|
80068ca: 62fb str r3, [r7, #44] ; 0x2c
|
|||
|
|
break;
|
|||
|
|
80068cc: e012 b.n 80068f4 <UART_SetConfig+0x408>
|
|||
|
|
case UART_CLOCKSOURCE_SYSCLK:
|
|||
|
|
pclk = HAL_RCC_GetSysClockFreq();
|
|||
|
|
80068ce: f7fe fe71 bl 80055b4 <HAL_RCC_GetSysClockFreq>
|
|||
|
|
80068d2: 0003 movs r3, r0
|
|||
|
|
80068d4: 62fb str r3, [r7, #44] ; 0x2c
|
|||
|
|
break;
|
|||
|
|
80068d6: e00d b.n 80068f4 <UART_SetConfig+0x408>
|
|||
|
|
case UART_CLOCKSOURCE_LSE:
|
|||
|
|
pclk = (uint32_t) LSE_VALUE;
|
|||
|
|
80068d8: 2380 movs r3, #128 ; 0x80
|
|||
|
|
80068da: 021b lsls r3, r3, #8
|
|||
|
|
80068dc: 62fb str r3, [r7, #44] ; 0x2c
|
|||
|
|
break;
|
|||
|
|
80068de: e009 b.n 80068f4 <UART_SetConfig+0x408>
|
|||
|
|
default:
|
|||
|
|
pclk = 0U;
|
|||
|
|
80068e0: 2300 movs r3, #0
|
|||
|
|
80068e2: 62fb str r3, [r7, #44] ; 0x2c
|
|||
|
|
ret = HAL_ERROR;
|
|||
|
|
80068e4: 231a movs r3, #26
|
|||
|
|
80068e6: 2218 movs r2, #24
|
|||
|
|
80068e8: 4694 mov ip, r2
|
|||
|
|
80068ea: 44bc add ip, r7
|
|||
|
|
80068ec: 4463 add r3, ip
|
|||
|
|
80068ee: 2201 movs r2, #1
|
|||
|
|
80068f0: 701a strb r2, [r3, #0]
|
|||
|
|
break;
|
|||
|
|
80068f2: 46c0 nop ; (mov r8, r8)
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
/* USARTDIV must be greater than or equal to 0d16 */
|
|||
|
|
if (pclk != 0U)
|
|||
|
|
80068f4: 6afb ldr r3, [r7, #44] ; 0x2c
|
|||
|
|
80068f6: 2b00 cmp r3, #0
|
|||
|
|
80068f8: d100 bne.n 80068fc <UART_SetConfig+0x410>
|
|||
|
|
80068fa: e09d b.n 8006a38 <UART_SetConfig+0x54c>
|
|||
|
|
{
|
|||
|
|
usartdiv = (uint16_t)(UART_DIV_SAMPLING8(pclk, huart->Init.BaudRate));
|
|||
|
|
80068fc: 6afb ldr r3, [r7, #44] ; 0x2c
|
|||
|
|
80068fe: 005a lsls r2, r3, #1
|
|||
|
|
8006900: 69fb ldr r3, [r7, #28]
|
|||
|
|
8006902: 685b ldr r3, [r3, #4]
|
|||
|
|
8006904: 085b lsrs r3, r3, #1
|
|||
|
|
8006906: 18d2 adds r2, r2, r3
|
|||
|
|
8006908: 69fb ldr r3, [r7, #28]
|
|||
|
|
800690a: 685b ldr r3, [r3, #4]
|
|||
|
|
800690c: 0019 movs r1, r3
|
|||
|
|
800690e: 0010 movs r0, r2
|
|||
|
|
8006910: f7f9 fbfa bl 8000108 <__udivsi3>
|
|||
|
|
8006914: 0003 movs r3, r0
|
|||
|
|
8006916: b29b uxth r3, r3
|
|||
|
|
8006918: 62bb str r3, [r7, #40] ; 0x28
|
|||
|
|
if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX))
|
|||
|
|
800691a: 6abb ldr r3, [r7, #40] ; 0x28
|
|||
|
|
800691c: 2b0f cmp r3, #15
|
|||
|
|
800691e: d92a bls.n 8006976 <UART_SetConfig+0x48a>
|
|||
|
|
8006920: 6abb ldr r3, [r7, #40] ; 0x28
|
|||
|
|
8006922: 4a51 ldr r2, [pc, #324] ; (8006a68 <UART_SetConfig+0x57c>)
|
|||
|
|
8006924: 4293 cmp r3, r2
|
|||
|
|
8006926: d826 bhi.n 8006976 <UART_SetConfig+0x48a>
|
|||
|
|
{
|
|||
|
|
brrtemp = (uint16_t)(usartdiv & 0xFFF0U);
|
|||
|
|
8006928: 6abb ldr r3, [r7, #40] ; 0x28
|
|||
|
|
800692a: b29a uxth r2, r3
|
|||
|
|
800692c: 230e movs r3, #14
|
|||
|
|
800692e: 2118 movs r1, #24
|
|||
|
|
8006930: 468c mov ip, r1
|
|||
|
|
8006932: 44bc add ip, r7
|
|||
|
|
8006934: 4463 add r3, ip
|
|||
|
|
8006936: 210f movs r1, #15
|
|||
|
|
8006938: 438a bics r2, r1
|
|||
|
|
800693a: 801a strh r2, [r3, #0]
|
|||
|
|
brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000FU) >> 1U);
|
|||
|
|
800693c: 6abb ldr r3, [r7, #40] ; 0x28
|
|||
|
|
800693e: 085b lsrs r3, r3, #1
|
|||
|
|
8006940: b29b uxth r3, r3
|
|||
|
|
8006942: 2207 movs r2, #7
|
|||
|
|
8006944: 4013 ands r3, r2
|
|||
|
|
8006946: b299 uxth r1, r3
|
|||
|
|
8006948: 230e movs r3, #14
|
|||
|
|
800694a: 2218 movs r2, #24
|
|||
|
|
800694c: 4694 mov ip, r2
|
|||
|
|
800694e: 44bc add ip, r7
|
|||
|
|
8006950: 4463 add r3, ip
|
|||
|
|
8006952: 220e movs r2, #14
|
|||
|
|
8006954: 2018 movs r0, #24
|
|||
|
|
8006956: 4684 mov ip, r0
|
|||
|
|
8006958: 44bc add ip, r7
|
|||
|
|
800695a: 4462 add r2, ip
|
|||
|
|
800695c: 8812 ldrh r2, [r2, #0]
|
|||
|
|
800695e: 430a orrs r2, r1
|
|||
|
|
8006960: 801a strh r2, [r3, #0]
|
|||
|
|
huart->Instance->BRR = brrtemp;
|
|||
|
|
8006962: 69fb ldr r3, [r7, #28]
|
|||
|
|
8006964: 681b ldr r3, [r3, #0]
|
|||
|
|
8006966: 220e movs r2, #14
|
|||
|
|
8006968: 2118 movs r1, #24
|
|||
|
|
800696a: 468c mov ip, r1
|
|||
|
|
800696c: 44bc add ip, r7
|
|||
|
|
800696e: 4462 add r2, ip
|
|||
|
|
8006970: 8812 ldrh r2, [r2, #0]
|
|||
|
|
8006972: 60da str r2, [r3, #12]
|
|||
|
|
8006974: e060 b.n 8006a38 <UART_SetConfig+0x54c>
|
|||
|
|
}
|
|||
|
|
else
|
|||
|
|
{
|
|||
|
|
ret = HAL_ERROR;
|
|||
|
|
8006976: 231a movs r3, #26
|
|||
|
|
8006978: 2218 movs r2, #24
|
|||
|
|
800697a: 4694 mov ip, r2
|
|||
|
|
800697c: 44bc add ip, r7
|
|||
|
|
800697e: 4463 add r3, ip
|
|||
|
|
8006980: 2201 movs r2, #1
|
|||
|
|
8006982: 701a strb r2, [r3, #0]
|
|||
|
|
8006984: e058 b.n 8006a38 <UART_SetConfig+0x54c>
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
else
|
|||
|
|
{
|
|||
|
|
switch (clocksource)
|
|||
|
|
8006986: 231b movs r3, #27
|
|||
|
|
8006988: 2218 movs r2, #24
|
|||
|
|
800698a: 4694 mov ip, r2
|
|||
|
|
800698c: 44bc add ip, r7
|
|||
|
|
800698e: 4463 add r3, ip
|
|||
|
|
8006990: 781b ldrb r3, [r3, #0]
|
|||
|
|
8006992: 2b08 cmp r3, #8
|
|||
|
|
8006994: d822 bhi.n 80069dc <UART_SetConfig+0x4f0>
|
|||
|
|
8006996: 009a lsls r2, r3, #2
|
|||
|
|
8006998: 4b34 ldr r3, [pc, #208] ; (8006a6c <UART_SetConfig+0x580>)
|
|||
|
|
800699a: 18d3 adds r3, r2, r3
|
|||
|
|
800699c: 681b ldr r3, [r3, #0]
|
|||
|
|
800699e: 469f mov pc, r3
|
|||
|
|
{
|
|||
|
|
case UART_CLOCKSOURCE_PCLK1:
|
|||
|
|
pclk = HAL_RCC_GetPCLK1Freq();
|
|||
|
|
80069a0: f7fe feb4 bl 800570c <HAL_RCC_GetPCLK1Freq>
|
|||
|
|
80069a4: 0003 movs r3, r0
|
|||
|
|
80069a6: 62fb str r3, [r7, #44] ; 0x2c
|
|||
|
|
break;
|
|||
|
|
80069a8: e022 b.n 80069f0 <UART_SetConfig+0x504>
|
|||
|
|
case UART_CLOCKSOURCE_PCLK2:
|
|||
|
|
pclk = HAL_RCC_GetPCLK2Freq();
|
|||
|
|
80069aa: f7fe fec5 bl 8005738 <HAL_RCC_GetPCLK2Freq>
|
|||
|
|
80069ae: 0003 movs r3, r0
|
|||
|
|
80069b0: 62fb str r3, [r7, #44] ; 0x2c
|
|||
|
|
break;
|
|||
|
|
80069b2: e01d b.n 80069f0 <UART_SetConfig+0x504>
|
|||
|
|
case UART_CLOCKSOURCE_HSI:
|
|||
|
|
if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U)
|
|||
|
|
80069b4: 4b29 ldr r3, [pc, #164] ; (8006a5c <UART_SetConfig+0x570>)
|
|||
|
|
80069b6: 681b ldr r3, [r3, #0]
|
|||
|
|
80069b8: 2210 movs r2, #16
|
|||
|
|
80069ba: 4013 ands r3, r2
|
|||
|
|
80069bc: d002 beq.n 80069c4 <UART_SetConfig+0x4d8>
|
|||
|
|
{
|
|||
|
|
pclk = (uint32_t)(HSI_VALUE >> 2U);
|
|||
|
|
80069be: 4b28 ldr r3, [pc, #160] ; (8006a60 <UART_SetConfig+0x574>)
|
|||
|
|
80069c0: 62fb str r3, [r7, #44] ; 0x2c
|
|||
|
|
}
|
|||
|
|
else
|
|||
|
|
{
|
|||
|
|
pclk = (uint32_t) HSI_VALUE;
|
|||
|
|
}
|
|||
|
|
break;
|
|||
|
|
80069c2: e015 b.n 80069f0 <UART_SetConfig+0x504>
|
|||
|
|
pclk = (uint32_t) HSI_VALUE;
|
|||
|
|
80069c4: 4b27 ldr r3, [pc, #156] ; (8006a64 <UART_SetConfig+0x578>)
|
|||
|
|
80069c6: 62fb str r3, [r7, #44] ; 0x2c
|
|||
|
|
break;
|
|||
|
|
80069c8: e012 b.n 80069f0 <UART_SetConfig+0x504>
|
|||
|
|
case UART_CLOCKSOURCE_SYSCLK:
|
|||
|
|
pclk = HAL_RCC_GetSysClockFreq();
|
|||
|
|
80069ca: f7fe fdf3 bl 80055b4 <HAL_RCC_GetSysClockFreq>
|
|||
|
|
80069ce: 0003 movs r3, r0
|
|||
|
|
80069d0: 62fb str r3, [r7, #44] ; 0x2c
|
|||
|
|
break;
|
|||
|
|
80069d2: e00d b.n 80069f0 <UART_SetConfig+0x504>
|
|||
|
|
case UART_CLOCKSOURCE_LSE:
|
|||
|
|
pclk = (uint32_t) LSE_VALUE;
|
|||
|
|
80069d4: 2380 movs r3, #128 ; 0x80
|
|||
|
|
80069d6: 021b lsls r3, r3, #8
|
|||
|
|
80069d8: 62fb str r3, [r7, #44] ; 0x2c
|
|||
|
|
break;
|
|||
|
|
80069da: e009 b.n 80069f0 <UART_SetConfig+0x504>
|
|||
|
|
default:
|
|||
|
|
pclk = 0U;
|
|||
|
|
80069dc: 2300 movs r3, #0
|
|||
|
|
80069de: 62fb str r3, [r7, #44] ; 0x2c
|
|||
|
|
ret = HAL_ERROR;
|
|||
|
|
80069e0: 231a movs r3, #26
|
|||
|
|
80069e2: 2218 movs r2, #24
|
|||
|
|
80069e4: 4694 mov ip, r2
|
|||
|
|
80069e6: 44bc add ip, r7
|
|||
|
|
80069e8: 4463 add r3, ip
|
|||
|
|
80069ea: 2201 movs r2, #1
|
|||
|
|
80069ec: 701a strb r2, [r3, #0]
|
|||
|
|
break;
|
|||
|
|
80069ee: 46c0 nop ; (mov r8, r8)
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
if (pclk != 0U)
|
|||
|
|
80069f0: 6afb ldr r3, [r7, #44] ; 0x2c
|
|||
|
|
80069f2: 2b00 cmp r3, #0
|
|||
|
|
80069f4: d020 beq.n 8006a38 <UART_SetConfig+0x54c>
|
|||
|
|
{
|
|||
|
|
/* USARTDIV must be greater than or equal to 0d16 */
|
|||
|
|
usartdiv = (uint16_t)(UART_DIV_SAMPLING16(pclk, huart->Init.BaudRate));
|
|||
|
|
80069f6: 69fb ldr r3, [r7, #28]
|
|||
|
|
80069f8: 685b ldr r3, [r3, #4]
|
|||
|
|
80069fa: 085a lsrs r2, r3, #1
|
|||
|
|
80069fc: 6afb ldr r3, [r7, #44] ; 0x2c
|
|||
|
|
80069fe: 18d2 adds r2, r2, r3
|
|||
|
|
8006a00: 69fb ldr r3, [r7, #28]
|
|||
|
|
8006a02: 685b ldr r3, [r3, #4]
|
|||
|
|
8006a04: 0019 movs r1, r3
|
|||
|
|
8006a06: 0010 movs r0, r2
|
|||
|
|
8006a08: f7f9 fb7e bl 8000108 <__udivsi3>
|
|||
|
|
8006a0c: 0003 movs r3, r0
|
|||
|
|
8006a0e: b29b uxth r3, r3
|
|||
|
|
8006a10: 62bb str r3, [r7, #40] ; 0x28
|
|||
|
|
if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX))
|
|||
|
|
8006a12: 6abb ldr r3, [r7, #40] ; 0x28
|
|||
|
|
8006a14: 2b0f cmp r3, #15
|
|||
|
|
8006a16: d908 bls.n 8006a2a <UART_SetConfig+0x53e>
|
|||
|
|
8006a18: 6abb ldr r3, [r7, #40] ; 0x28
|
|||
|
|
8006a1a: 4a13 ldr r2, [pc, #76] ; (8006a68 <UART_SetConfig+0x57c>)
|
|||
|
|
8006a1c: 4293 cmp r3, r2
|
|||
|
|
8006a1e: d804 bhi.n 8006a2a <UART_SetConfig+0x53e>
|
|||
|
|
{
|
|||
|
|
huart->Instance->BRR = usartdiv;
|
|||
|
|
8006a20: 69fb ldr r3, [r7, #28]
|
|||
|
|
8006a22: 681b ldr r3, [r3, #0]
|
|||
|
|
8006a24: 6aba ldr r2, [r7, #40] ; 0x28
|
|||
|
|
8006a26: 60da str r2, [r3, #12]
|
|||
|
|
8006a28: e006 b.n 8006a38 <UART_SetConfig+0x54c>
|
|||
|
|
}
|
|||
|
|
else
|
|||
|
|
{
|
|||
|
|
ret = HAL_ERROR;
|
|||
|
|
8006a2a: 231a movs r3, #26
|
|||
|
|
8006a2c: 2218 movs r2, #24
|
|||
|
|
8006a2e: 4694 mov ip, r2
|
|||
|
|
8006a30: 44bc add ip, r7
|
|||
|
|
8006a32: 4463 add r3, ip
|
|||
|
|
8006a34: 2201 movs r2, #1
|
|||
|
|
8006a36: 701a strb r2, [r3, #0]
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
|
|||
|
|
/* Clear ISR function pointers */
|
|||
|
|
huart->RxISR = NULL;
|
|||
|
|
8006a38: 69fb ldr r3, [r7, #28]
|
|||
|
|
8006a3a: 2200 movs r2, #0
|
|||
|
|
8006a3c: 665a str r2, [r3, #100] ; 0x64
|
|||
|
|
huart->TxISR = NULL;
|
|||
|
|
8006a3e: 69fb ldr r3, [r7, #28]
|
|||
|
|
8006a40: 2200 movs r2, #0
|
|||
|
|
8006a42: 669a str r2, [r3, #104] ; 0x68
|
|||
|
|
|
|||
|
|
return ret;
|
|||
|
|
8006a44: 231a movs r3, #26
|
|||
|
|
8006a46: 2218 movs r2, #24
|
|||
|
|
8006a48: 4694 mov ip, r2
|
|||
|
|
8006a4a: 44bc add ip, r7
|
|||
|
|
8006a4c: 4463 add r3, ip
|
|||
|
|
8006a4e: 781b ldrb r3, [r3, #0]
|
|||
|
|
}
|
|||
|
|
8006a50: 0018 movs r0, r3
|
|||
|
|
8006a52: 46bd mov sp, r7
|
|||
|
|
8006a54: b00e add sp, #56 ; 0x38
|
|||
|
|
8006a56: bdb0 pop {r4, r5, r7, pc}
|
|||
|
|
8006a58: 08007444 .word 0x08007444
|
|||
|
|
8006a5c: 40021000 .word 0x40021000
|
|||
|
|
8006a60: 003d0900 .word 0x003d0900
|
|||
|
|
8006a64: 00f42400 .word 0x00f42400
|
|||
|
|
8006a68: 0000ffff .word 0x0000ffff
|
|||
|
|
8006a6c: 08007468 .word 0x08007468
|
|||
|
|
|
|||
|
|
08006a70 <UART_AdvFeatureConfig>:
|
|||
|
|
* @brief Configure the UART peripheral advanced features.
|
|||
|
|
* @param huart UART handle.
|
|||
|
|
* @retval None
|
|||
|
|
*/
|
|||
|
|
void UART_AdvFeatureConfig(UART_HandleTypeDef *huart)
|
|||
|
|
{
|
|||
|
|
8006a70: b580 push {r7, lr}
|
|||
|
|
8006a72: b082 sub sp, #8
|
|||
|
|
8006a74: af00 add r7, sp, #0
|
|||
|
|
8006a76: 6078 str r0, [r7, #4]
|
|||
|
|
/* Check whether the set of advanced features to configure is properly set */
|
|||
|
|
assert_param(IS_UART_ADVFEATURE_INIT(huart->AdvancedInit.AdvFeatureInit));
|
|||
|
|
|
|||
|
|
/* if required, configure TX pin active level inversion */
|
|||
|
|
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_TXINVERT_INIT))
|
|||
|
|
8006a78: 687b ldr r3, [r7, #4]
|
|||
|
|
8006a7a: 6a5b ldr r3, [r3, #36] ; 0x24
|
|||
|
|
8006a7c: 2201 movs r2, #1
|
|||
|
|
8006a7e: 4013 ands r3, r2
|
|||
|
|
8006a80: d00a beq.n 8006a98 <UART_AdvFeatureConfig+0x28>
|
|||
|
|
{
|
|||
|
|
assert_param(IS_UART_ADVFEATURE_TXINV(huart->AdvancedInit.TxPinLevelInvert));
|
|||
|
|
MODIFY_REG(huart->Instance->CR2, USART_CR2_TXINV, huart->AdvancedInit.TxPinLevelInvert);
|
|||
|
|
8006a82: 687b ldr r3, [r7, #4]
|
|||
|
|
8006a84: 681b ldr r3, [r3, #0]
|
|||
|
|
8006a86: 687a ldr r2, [r7, #4]
|
|||
|
|
8006a88: 6812 ldr r2, [r2, #0]
|
|||
|
|
8006a8a: 6852 ldr r2, [r2, #4]
|
|||
|
|
8006a8c: 4945 ldr r1, [pc, #276] ; (8006ba4 <UART_AdvFeatureConfig+0x134>)
|
|||
|
|
8006a8e: 4011 ands r1, r2
|
|||
|
|
8006a90: 687a ldr r2, [r7, #4]
|
|||
|
|
8006a92: 6a92 ldr r2, [r2, #40] ; 0x28
|
|||
|
|
8006a94: 430a orrs r2, r1
|
|||
|
|
8006a96: 605a str r2, [r3, #4]
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
/* if required, configure RX pin active level inversion */
|
|||
|
|
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXINVERT_INIT))
|
|||
|
|
8006a98: 687b ldr r3, [r7, #4]
|
|||
|
|
8006a9a: 6a5b ldr r3, [r3, #36] ; 0x24
|
|||
|
|
8006a9c: 2202 movs r2, #2
|
|||
|
|
8006a9e: 4013 ands r3, r2
|
|||
|
|
8006aa0: d00a beq.n 8006ab8 <UART_AdvFeatureConfig+0x48>
|
|||
|
|
{
|
|||
|
|
assert_param(IS_UART_ADVFEATURE_RXINV(huart->AdvancedInit.RxPinLevelInvert));
|
|||
|
|
MODIFY_REG(huart->Instance->CR2, USART_CR2_RXINV, huart->AdvancedInit.RxPinLevelInvert);
|
|||
|
|
8006aa2: 687b ldr r3, [r7, #4]
|
|||
|
|
8006aa4: 681b ldr r3, [r3, #0]
|
|||
|
|
8006aa6: 687a ldr r2, [r7, #4]
|
|||
|
|
8006aa8: 6812 ldr r2, [r2, #0]
|
|||
|
|
8006aaa: 6852 ldr r2, [r2, #4]
|
|||
|
|
8006aac: 493e ldr r1, [pc, #248] ; (8006ba8 <UART_AdvFeatureConfig+0x138>)
|
|||
|
|
8006aae: 4011 ands r1, r2
|
|||
|
|
8006ab0: 687a ldr r2, [r7, #4]
|
|||
|
|
8006ab2: 6ad2 ldr r2, [r2, #44] ; 0x2c
|
|||
|
|
8006ab4: 430a orrs r2, r1
|
|||
|
|
8006ab6: 605a str r2, [r3, #4]
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
/* if required, configure data inversion */
|
|||
|
|
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DATAINVERT_INIT))
|
|||
|
|
8006ab8: 687b ldr r3, [r7, #4]
|
|||
|
|
8006aba: 6a5b ldr r3, [r3, #36] ; 0x24
|
|||
|
|
8006abc: 2204 movs r2, #4
|
|||
|
|
8006abe: 4013 ands r3, r2
|
|||
|
|
8006ac0: d00a beq.n 8006ad8 <UART_AdvFeatureConfig+0x68>
|
|||
|
|
{
|
|||
|
|
assert_param(IS_UART_ADVFEATURE_DATAINV(huart->AdvancedInit.DataInvert));
|
|||
|
|
MODIFY_REG(huart->Instance->CR2, USART_CR2_DATAINV, huart->AdvancedInit.DataInvert);
|
|||
|
|
8006ac2: 687b ldr r3, [r7, #4]
|
|||
|
|
8006ac4: 681b ldr r3, [r3, #0]
|
|||
|
|
8006ac6: 687a ldr r2, [r7, #4]
|
|||
|
|
8006ac8: 6812 ldr r2, [r2, #0]
|
|||
|
|
8006aca: 6852 ldr r2, [r2, #4]
|
|||
|
|
8006acc: 4937 ldr r1, [pc, #220] ; (8006bac <UART_AdvFeatureConfig+0x13c>)
|
|||
|
|
8006ace: 4011 ands r1, r2
|
|||
|
|
8006ad0: 687a ldr r2, [r7, #4]
|
|||
|
|
8006ad2: 6b12 ldr r2, [r2, #48] ; 0x30
|
|||
|
|
8006ad4: 430a orrs r2, r1
|
|||
|
|
8006ad6: 605a str r2, [r3, #4]
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
/* if required, configure RX/TX pins swap */
|
|||
|
|
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_SWAP_INIT))
|
|||
|
|
8006ad8: 687b ldr r3, [r7, #4]
|
|||
|
|
8006ada: 6a5b ldr r3, [r3, #36] ; 0x24
|
|||
|
|
8006adc: 2208 movs r2, #8
|
|||
|
|
8006ade: 4013 ands r3, r2
|
|||
|
|
8006ae0: d00a beq.n 8006af8 <UART_AdvFeatureConfig+0x88>
|
|||
|
|
{
|
|||
|
|
assert_param(IS_UART_ADVFEATURE_SWAP(huart->AdvancedInit.Swap));
|
|||
|
|
MODIFY_REG(huart->Instance->CR2, USART_CR2_SWAP, huart->AdvancedInit.Swap);
|
|||
|
|
8006ae2: 687b ldr r3, [r7, #4]
|
|||
|
|
8006ae4: 681b ldr r3, [r3, #0]
|
|||
|
|
8006ae6: 687a ldr r2, [r7, #4]
|
|||
|
|
8006ae8: 6812 ldr r2, [r2, #0]
|
|||
|
|
8006aea: 6852 ldr r2, [r2, #4]
|
|||
|
|
8006aec: 4930 ldr r1, [pc, #192] ; (8006bb0 <UART_AdvFeatureConfig+0x140>)
|
|||
|
|
8006aee: 4011 ands r1, r2
|
|||
|
|
8006af0: 687a ldr r2, [r7, #4]
|
|||
|
|
8006af2: 6b52 ldr r2, [r2, #52] ; 0x34
|
|||
|
|
8006af4: 430a orrs r2, r1
|
|||
|
|
8006af6: 605a str r2, [r3, #4]
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
/* if required, configure RX overrun detection disabling */
|
|||
|
|
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXOVERRUNDISABLE_INIT))
|
|||
|
|
8006af8: 687b ldr r3, [r7, #4]
|
|||
|
|
8006afa: 6a5b ldr r3, [r3, #36] ; 0x24
|
|||
|
|
8006afc: 2210 movs r2, #16
|
|||
|
|
8006afe: 4013 ands r3, r2
|
|||
|
|
8006b00: d00a beq.n 8006b18 <UART_AdvFeatureConfig+0xa8>
|
|||
|
|
{
|
|||
|
|
assert_param(IS_UART_OVERRUN(huart->AdvancedInit.OverrunDisable));
|
|||
|
|
MODIFY_REG(huart->Instance->CR3, USART_CR3_OVRDIS, huart->AdvancedInit.OverrunDisable);
|
|||
|
|
8006b02: 687b ldr r3, [r7, #4]
|
|||
|
|
8006b04: 681b ldr r3, [r3, #0]
|
|||
|
|
8006b06: 687a ldr r2, [r7, #4]
|
|||
|
|
8006b08: 6812 ldr r2, [r2, #0]
|
|||
|
|
8006b0a: 6892 ldr r2, [r2, #8]
|
|||
|
|
8006b0c: 4929 ldr r1, [pc, #164] ; (8006bb4 <UART_AdvFeatureConfig+0x144>)
|
|||
|
|
8006b0e: 4011 ands r1, r2
|
|||
|
|
8006b10: 687a ldr r2, [r7, #4]
|
|||
|
|
8006b12: 6b92 ldr r2, [r2, #56] ; 0x38
|
|||
|
|
8006b14: 430a orrs r2, r1
|
|||
|
|
8006b16: 609a str r2, [r3, #8]
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
/* if required, configure DMA disabling on reception error */
|
|||
|
|
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DMADISABLEONERROR_INIT))
|
|||
|
|
8006b18: 687b ldr r3, [r7, #4]
|
|||
|
|
8006b1a: 6a5b ldr r3, [r3, #36] ; 0x24
|
|||
|
|
8006b1c: 2220 movs r2, #32
|
|||
|
|
8006b1e: 4013 ands r3, r2
|
|||
|
|
8006b20: d00a beq.n 8006b38 <UART_AdvFeatureConfig+0xc8>
|
|||
|
|
{
|
|||
|
|
assert_param(IS_UART_ADVFEATURE_DMAONRXERROR(huart->AdvancedInit.DMADisableonRxError));
|
|||
|
|
MODIFY_REG(huart->Instance->CR3, USART_CR3_DDRE, huart->AdvancedInit.DMADisableonRxError);
|
|||
|
|
8006b22: 687b ldr r3, [r7, #4]
|
|||
|
|
8006b24: 681b ldr r3, [r3, #0]
|
|||
|
|
8006b26: 687a ldr r2, [r7, #4]
|
|||
|
|
8006b28: 6812 ldr r2, [r2, #0]
|
|||
|
|
8006b2a: 6892 ldr r2, [r2, #8]
|
|||
|
|
8006b2c: 4922 ldr r1, [pc, #136] ; (8006bb8 <UART_AdvFeatureConfig+0x148>)
|
|||
|
|
8006b2e: 4011 ands r1, r2
|
|||
|
|
8006b30: 687a ldr r2, [r7, #4]
|
|||
|
|
8006b32: 6bd2 ldr r2, [r2, #60] ; 0x3c
|
|||
|
|
8006b34: 430a orrs r2, r1
|
|||
|
|
8006b36: 609a str r2, [r3, #8]
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
/* if required, configure auto Baud rate detection scheme */
|
|||
|
|
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_AUTOBAUDRATE_INIT))
|
|||
|
|
8006b38: 687b ldr r3, [r7, #4]
|
|||
|
|
8006b3a: 6a5b ldr r3, [r3, #36] ; 0x24
|
|||
|
|
8006b3c: 2240 movs r2, #64 ; 0x40
|
|||
|
|
8006b3e: 4013 ands r3, r2
|
|||
|
|
8006b40: d01b beq.n 8006b7a <UART_AdvFeatureConfig+0x10a>
|
|||
|
|
{
|
|||
|
|
assert_param(IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(huart->Instance));
|
|||
|
|
assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATE(huart->AdvancedInit.AutoBaudRateEnable));
|
|||
|
|
MODIFY_REG(huart->Instance->CR2, USART_CR2_ABREN, huart->AdvancedInit.AutoBaudRateEnable);
|
|||
|
|
8006b42: 687b ldr r3, [r7, #4]
|
|||
|
|
8006b44: 681b ldr r3, [r3, #0]
|
|||
|
|
8006b46: 687a ldr r2, [r7, #4]
|
|||
|
|
8006b48: 6812 ldr r2, [r2, #0]
|
|||
|
|
8006b4a: 6852 ldr r2, [r2, #4]
|
|||
|
|
8006b4c: 491b ldr r1, [pc, #108] ; (8006bbc <UART_AdvFeatureConfig+0x14c>)
|
|||
|
|
8006b4e: 4011 ands r1, r2
|
|||
|
|
8006b50: 687a ldr r2, [r7, #4]
|
|||
|
|
8006b52: 6c12 ldr r2, [r2, #64] ; 0x40
|
|||
|
|
8006b54: 430a orrs r2, r1
|
|||
|
|
8006b56: 605a str r2, [r3, #4]
|
|||
|
|
/* set auto Baudrate detection parameters if detection is enabled */
|
|||
|
|
if (huart->AdvancedInit.AutoBaudRateEnable == UART_ADVFEATURE_AUTOBAUDRATE_ENABLE)
|
|||
|
|
8006b58: 687b ldr r3, [r7, #4]
|
|||
|
|
8006b5a: 6c1a ldr r2, [r3, #64] ; 0x40
|
|||
|
|
8006b5c: 2380 movs r3, #128 ; 0x80
|
|||
|
|
8006b5e: 035b lsls r3, r3, #13
|
|||
|
|
8006b60: 429a cmp r2, r3
|
|||
|
|
8006b62: d10a bne.n 8006b7a <UART_AdvFeatureConfig+0x10a>
|
|||
|
|
{
|
|||
|
|
assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATEMODE(huart->AdvancedInit.AutoBaudRateMode));
|
|||
|
|
MODIFY_REG(huart->Instance->CR2, USART_CR2_ABRMODE, huart->AdvancedInit.AutoBaudRateMode);
|
|||
|
|
8006b64: 687b ldr r3, [r7, #4]
|
|||
|
|
8006b66: 681b ldr r3, [r3, #0]
|
|||
|
|
8006b68: 687a ldr r2, [r7, #4]
|
|||
|
|
8006b6a: 6812 ldr r2, [r2, #0]
|
|||
|
|
8006b6c: 6852 ldr r2, [r2, #4]
|
|||
|
|
8006b6e: 4914 ldr r1, [pc, #80] ; (8006bc0 <UART_AdvFeatureConfig+0x150>)
|
|||
|
|
8006b70: 4011 ands r1, r2
|
|||
|
|
8006b72: 687a ldr r2, [r7, #4]
|
|||
|
|
8006b74: 6c52 ldr r2, [r2, #68] ; 0x44
|
|||
|
|
8006b76: 430a orrs r2, r1
|
|||
|
|
8006b78: 605a str r2, [r3, #4]
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
/* if required, configure MSB first on communication line */
|
|||
|
|
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_MSBFIRST_INIT))
|
|||
|
|
8006b7a: 687b ldr r3, [r7, #4]
|
|||
|
|
8006b7c: 6a5b ldr r3, [r3, #36] ; 0x24
|
|||
|
|
8006b7e: 2280 movs r2, #128 ; 0x80
|
|||
|
|
8006b80: 4013 ands r3, r2
|
|||
|
|
8006b82: d00a beq.n 8006b9a <UART_AdvFeatureConfig+0x12a>
|
|||
|
|
{
|
|||
|
|
assert_param(IS_UART_ADVFEATURE_MSBFIRST(huart->AdvancedInit.MSBFirst));
|
|||
|
|
MODIFY_REG(huart->Instance->CR2, USART_CR2_MSBFIRST, huart->AdvancedInit.MSBFirst);
|
|||
|
|
8006b84: 687b ldr r3, [r7, #4]
|
|||
|
|
8006b86: 681b ldr r3, [r3, #0]
|
|||
|
|
8006b88: 687a ldr r2, [r7, #4]
|
|||
|
|
8006b8a: 6812 ldr r2, [r2, #0]
|
|||
|
|
8006b8c: 6852 ldr r2, [r2, #4]
|
|||
|
|
8006b8e: 490d ldr r1, [pc, #52] ; (8006bc4 <UART_AdvFeatureConfig+0x154>)
|
|||
|
|
8006b90: 4011 ands r1, r2
|
|||
|
|
8006b92: 687a ldr r2, [r7, #4]
|
|||
|
|
8006b94: 6c92 ldr r2, [r2, #72] ; 0x48
|
|||
|
|
8006b96: 430a orrs r2, r1
|
|||
|
|
8006b98: 605a str r2, [r3, #4]
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
8006b9a: 46c0 nop ; (mov r8, r8)
|
|||
|
|
8006b9c: 46bd mov sp, r7
|
|||
|
|
8006b9e: b002 add sp, #8
|
|||
|
|
8006ba0: bd80 pop {r7, pc}
|
|||
|
|
8006ba2: 46c0 nop ; (mov r8, r8)
|
|||
|
|
8006ba4: fffdffff .word 0xfffdffff
|
|||
|
|
8006ba8: fffeffff .word 0xfffeffff
|
|||
|
|
8006bac: fffbffff .word 0xfffbffff
|
|||
|
|
8006bb0: ffff7fff .word 0xffff7fff
|
|||
|
|
8006bb4: ffffefff .word 0xffffefff
|
|||
|
|
8006bb8: ffffdfff .word 0xffffdfff
|
|||
|
|
8006bbc: ffefffff .word 0xffefffff
|
|||
|
|
8006bc0: ff9fffff .word 0xff9fffff
|
|||
|
|
8006bc4: fff7ffff .word 0xfff7ffff
|
|||
|
|
|
|||
|
|
08006bc8 <UART_CheckIdleState>:
|
|||
|
|
* @brief Check the UART Idle State.
|
|||
|
|
* @param huart UART handle.
|
|||
|
|
* @retval HAL status
|
|||
|
|
*/
|
|||
|
|
HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart)
|
|||
|
|
{
|
|||
|
|
8006bc8: b580 push {r7, lr}
|
|||
|
|
8006bca: b086 sub sp, #24
|
|||
|
|
8006bcc: af02 add r7, sp, #8
|
|||
|
|
8006bce: 6078 str r0, [r7, #4]
|
|||
|
|
uint32_t tickstart;
|
|||
|
|
|
|||
|
|
/* Initialize the UART ErrorCode */
|
|||
|
|
huart->ErrorCode = HAL_UART_ERROR_NONE;
|
|||
|
|
8006bd0: 687b ldr r3, [r7, #4]
|
|||
|
|
8006bd2: 2280 movs r2, #128 ; 0x80
|
|||
|
|
8006bd4: 2100 movs r1, #0
|
|||
|
|
8006bd6: 5099 str r1, [r3, r2]
|
|||
|
|
|
|||
|
|
/* Init tickstart for timeout management */
|
|||
|
|
tickstart = HAL_GetTick();
|
|||
|
|
8006bd8: f7fd f9a8 bl 8003f2c <HAL_GetTick>
|
|||
|
|
8006bdc: 0003 movs r3, r0
|
|||
|
|
8006bde: 60fb str r3, [r7, #12]
|
|||
|
|
|
|||
|
|
/* Check if the Transmitter is enabled */
|
|||
|
|
if ((huart->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE)
|
|||
|
|
8006be0: 687b ldr r3, [r7, #4]
|
|||
|
|
8006be2: 681b ldr r3, [r3, #0]
|
|||
|
|
8006be4: 681b ldr r3, [r3, #0]
|
|||
|
|
8006be6: 2208 movs r2, #8
|
|||
|
|
8006be8: 4013 ands r3, r2
|
|||
|
|
8006bea: 2b08 cmp r3, #8
|
|||
|
|
8006bec: d10d bne.n 8006c0a <UART_CheckIdleState+0x42>
|
|||
|
|
{
|
|||
|
|
/* Wait until TEACK flag is set */
|
|||
|
|
if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_TEACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK)
|
|||
|
|
8006bee: 68fa ldr r2, [r7, #12]
|
|||
|
|
8006bf0: 2380 movs r3, #128 ; 0x80
|
|||
|
|
8006bf2: 0399 lsls r1, r3, #14
|
|||
|
|
8006bf4: 6878 ldr r0, [r7, #4]
|
|||
|
|
8006bf6: 4b18 ldr r3, [pc, #96] ; (8006c58 <UART_CheckIdleState+0x90>)
|
|||
|
|
8006bf8: 9300 str r3, [sp, #0]
|
|||
|
|
8006bfa: 0013 movs r3, r2
|
|||
|
|
8006bfc: 2200 movs r2, #0
|
|||
|
|
8006bfe: f000 f82d bl 8006c5c <UART_WaitOnFlagUntilTimeout>
|
|||
|
|
8006c02: 1e03 subs r3, r0, #0
|
|||
|
|
8006c04: d001 beq.n 8006c0a <UART_CheckIdleState+0x42>
|
|||
|
|
{
|
|||
|
|
/* Timeout occurred */
|
|||
|
|
return HAL_TIMEOUT;
|
|||
|
|
8006c06: 2303 movs r3, #3
|
|||
|
|
8006c08: e022 b.n 8006c50 <UART_CheckIdleState+0x88>
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
/* Check if the Receiver is enabled */
|
|||
|
|
if ((huart->Instance->CR1 & USART_CR1_RE) == USART_CR1_RE)
|
|||
|
|
8006c0a: 687b ldr r3, [r7, #4]
|
|||
|
|
8006c0c: 681b ldr r3, [r3, #0]
|
|||
|
|
8006c0e: 681b ldr r3, [r3, #0]
|
|||
|
|
8006c10: 2204 movs r2, #4
|
|||
|
|
8006c12: 4013 ands r3, r2
|
|||
|
|
8006c14: 2b04 cmp r3, #4
|
|||
|
|
8006c16: d10d bne.n 8006c34 <UART_CheckIdleState+0x6c>
|
|||
|
|
{
|
|||
|
|
/* Wait until REACK flag is set */
|
|||
|
|
if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_REACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK)
|
|||
|
|
8006c18: 68fa ldr r2, [r7, #12]
|
|||
|
|
8006c1a: 2380 movs r3, #128 ; 0x80
|
|||
|
|
8006c1c: 03d9 lsls r1, r3, #15
|
|||
|
|
8006c1e: 6878 ldr r0, [r7, #4]
|
|||
|
|
8006c20: 4b0d ldr r3, [pc, #52] ; (8006c58 <UART_CheckIdleState+0x90>)
|
|||
|
|
8006c22: 9300 str r3, [sp, #0]
|
|||
|
|
8006c24: 0013 movs r3, r2
|
|||
|
|
8006c26: 2200 movs r2, #0
|
|||
|
|
8006c28: f000 f818 bl 8006c5c <UART_WaitOnFlagUntilTimeout>
|
|||
|
|
8006c2c: 1e03 subs r3, r0, #0
|
|||
|
|
8006c2e: d001 beq.n 8006c34 <UART_CheckIdleState+0x6c>
|
|||
|
|
{
|
|||
|
|
/* Timeout occurred */
|
|||
|
|
return HAL_TIMEOUT;
|
|||
|
|
8006c30: 2303 movs r3, #3
|
|||
|
|
8006c32: e00d b.n 8006c50 <UART_CheckIdleState+0x88>
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
/* Initialize the UART State */
|
|||
|
|
huart->gState = HAL_UART_STATE_READY;
|
|||
|
|
8006c34: 687b ldr r3, [r7, #4]
|
|||
|
|
8006c36: 2220 movs r2, #32
|
|||
|
|
8006c38: 679a str r2, [r3, #120] ; 0x78
|
|||
|
|
huart->RxState = HAL_UART_STATE_READY;
|
|||
|
|
8006c3a: 687b ldr r3, [r7, #4]
|
|||
|
|
8006c3c: 2220 movs r2, #32
|
|||
|
|
8006c3e: 67da str r2, [r3, #124] ; 0x7c
|
|||
|
|
huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
|
|||
|
|
8006c40: 687b ldr r3, [r7, #4]
|
|||
|
|
8006c42: 2200 movs r2, #0
|
|||
|
|
8006c44: 661a str r2, [r3, #96] ; 0x60
|
|||
|
|
|
|||
|
|
__HAL_UNLOCK(huart);
|
|||
|
|
8006c46: 687b ldr r3, [r7, #4]
|
|||
|
|
8006c48: 2274 movs r2, #116 ; 0x74
|
|||
|
|
8006c4a: 2100 movs r1, #0
|
|||
|
|
8006c4c: 5499 strb r1, [r3, r2]
|
|||
|
|
|
|||
|
|
return HAL_OK;
|
|||
|
|
8006c4e: 2300 movs r3, #0
|
|||
|
|
}
|
|||
|
|
8006c50: 0018 movs r0, r3
|
|||
|
|
8006c52: 46bd mov sp, r7
|
|||
|
|
8006c54: b004 add sp, #16
|
|||
|
|
8006c56: bd80 pop {r7, pc}
|
|||
|
|
8006c58: 01ffffff .word 0x01ffffff
|
|||
|
|
|
|||
|
|
08006c5c <UART_WaitOnFlagUntilTimeout>:
|
|||
|
|
* @param Timeout Timeout duration
|
|||
|
|
* @retval HAL status
|
|||
|
|
*/
|
|||
|
|
HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status,
|
|||
|
|
uint32_t Tickstart, uint32_t Timeout)
|
|||
|
|
{
|
|||
|
|
8006c5c: b580 push {r7, lr}
|
|||
|
|
8006c5e: b084 sub sp, #16
|
|||
|
|
8006c60: af00 add r7, sp, #0
|
|||
|
|
8006c62: 60f8 str r0, [r7, #12]
|
|||
|
|
8006c64: 60b9 str r1, [r7, #8]
|
|||
|
|
8006c66: 603b str r3, [r7, #0]
|
|||
|
|
8006c68: 1dfb adds r3, r7, #7
|
|||
|
|
8006c6a: 701a strb r2, [r3, #0]
|
|||
|
|
/* Wait until flag is set */
|
|||
|
|
while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status)
|
|||
|
|
8006c6c: e05e b.n 8006d2c <UART_WaitOnFlagUntilTimeout+0xd0>
|
|||
|
|
{
|
|||
|
|
/* Check for the Timeout */
|
|||
|
|
if (Timeout != HAL_MAX_DELAY)
|
|||
|
|
8006c6e: 69bb ldr r3, [r7, #24]
|
|||
|
|
8006c70: 3301 adds r3, #1
|
|||
|
|
8006c72: d05b beq.n 8006d2c <UART_WaitOnFlagUntilTimeout+0xd0>
|
|||
|
|
{
|
|||
|
|
if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
|
|||
|
|
8006c74: f7fd f95a bl 8003f2c <HAL_GetTick>
|
|||
|
|
8006c78: 0002 movs r2, r0
|
|||
|
|
8006c7a: 683b ldr r3, [r7, #0]
|
|||
|
|
8006c7c: 1ad2 subs r2, r2, r3
|
|||
|
|
8006c7e: 69bb ldr r3, [r7, #24]
|
|||
|
|
8006c80: 429a cmp r2, r3
|
|||
|
|
8006c82: d802 bhi.n 8006c8a <UART_WaitOnFlagUntilTimeout+0x2e>
|
|||
|
|
8006c84: 69bb ldr r3, [r7, #24]
|
|||
|
|
8006c86: 2b00 cmp r3, #0
|
|||
|
|
8006c88: d11b bne.n 8006cc2 <UART_WaitOnFlagUntilTimeout+0x66>
|
|||
|
|
{
|
|||
|
|
/* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error)
|
|||
|
|
interrupts for the interrupt process */
|
|||
|
|
CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE));
|
|||
|
|
8006c8a: 68fb ldr r3, [r7, #12]
|
|||
|
|
8006c8c: 681b ldr r3, [r3, #0]
|
|||
|
|
8006c8e: 68fa ldr r2, [r7, #12]
|
|||
|
|
8006c90: 6812 ldr r2, [r2, #0]
|
|||
|
|
8006c92: 6812 ldr r2, [r2, #0]
|
|||
|
|
8006c94: 492f ldr r1, [pc, #188] ; (8006d54 <UART_WaitOnFlagUntilTimeout+0xf8>)
|
|||
|
|
8006c96: 400a ands r2, r1
|
|||
|
|
8006c98: 601a str r2, [r3, #0]
|
|||
|
|
CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
|
|||
|
|
8006c9a: 68fb ldr r3, [r7, #12]
|
|||
|
|
8006c9c: 681b ldr r3, [r3, #0]
|
|||
|
|
8006c9e: 68fa ldr r2, [r7, #12]
|
|||
|
|
8006ca0: 6812 ldr r2, [r2, #0]
|
|||
|
|
8006ca2: 6892 ldr r2, [r2, #8]
|
|||
|
|
8006ca4: 2101 movs r1, #1
|
|||
|
|
8006ca6: 438a bics r2, r1
|
|||
|
|
8006ca8: 609a str r2, [r3, #8]
|
|||
|
|
|
|||
|
|
huart->gState = HAL_UART_STATE_READY;
|
|||
|
|
8006caa: 68fb ldr r3, [r7, #12]
|
|||
|
|
8006cac: 2220 movs r2, #32
|
|||
|
|
8006cae: 679a str r2, [r3, #120] ; 0x78
|
|||
|
|
huart->RxState = HAL_UART_STATE_READY;
|
|||
|
|
8006cb0: 68fb ldr r3, [r7, #12]
|
|||
|
|
8006cb2: 2220 movs r2, #32
|
|||
|
|
8006cb4: 67da str r2, [r3, #124] ; 0x7c
|
|||
|
|
|
|||
|
|
__HAL_UNLOCK(huart);
|
|||
|
|
8006cb6: 68fb ldr r3, [r7, #12]
|
|||
|
|
8006cb8: 2274 movs r2, #116 ; 0x74
|
|||
|
|
8006cba: 2100 movs r1, #0
|
|||
|
|
8006cbc: 5499 strb r1, [r3, r2]
|
|||
|
|
|
|||
|
|
return HAL_TIMEOUT;
|
|||
|
|
8006cbe: 2303 movs r3, #3
|
|||
|
|
8006cc0: e044 b.n 8006d4c <UART_WaitOnFlagUntilTimeout+0xf0>
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
if (READ_BIT(huart->Instance->CR1, USART_CR1_RE) != 0U)
|
|||
|
|
8006cc2: 68fb ldr r3, [r7, #12]
|
|||
|
|
8006cc4: 681b ldr r3, [r3, #0]
|
|||
|
|
8006cc6: 681b ldr r3, [r3, #0]
|
|||
|
|
8006cc8: 2204 movs r2, #4
|
|||
|
|
8006cca: 4013 ands r3, r2
|
|||
|
|
8006ccc: d02e beq.n 8006d2c <UART_WaitOnFlagUntilTimeout+0xd0>
|
|||
|
|
{
|
|||
|
|
if (__HAL_UART_GET_FLAG(huart, UART_FLAG_RTOF) == SET)
|
|||
|
|
8006cce: 68fb ldr r3, [r7, #12]
|
|||
|
|
8006cd0: 681b ldr r3, [r3, #0]
|
|||
|
|
8006cd2: 69da ldr r2, [r3, #28]
|
|||
|
|
8006cd4: 2380 movs r3, #128 ; 0x80
|
|||
|
|
8006cd6: 011b lsls r3, r3, #4
|
|||
|
|
8006cd8: 401a ands r2, r3
|
|||
|
|
8006cda: 2380 movs r3, #128 ; 0x80
|
|||
|
|
8006cdc: 011b lsls r3, r3, #4
|
|||
|
|
8006cde: 429a cmp r2, r3
|
|||
|
|
8006ce0: d124 bne.n 8006d2c <UART_WaitOnFlagUntilTimeout+0xd0>
|
|||
|
|
{
|
|||
|
|
/* Clear Receiver Timeout flag*/
|
|||
|
|
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_RTOF);
|
|||
|
|
8006ce2: 68fb ldr r3, [r7, #12]
|
|||
|
|
8006ce4: 681b ldr r3, [r3, #0]
|
|||
|
|
8006ce6: 2280 movs r2, #128 ; 0x80
|
|||
|
|
8006ce8: 0112 lsls r2, r2, #4
|
|||
|
|
8006cea: 621a str r2, [r3, #32]
|
|||
|
|
|
|||
|
|
/* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error)
|
|||
|
|
interrupts for the interrupt process */
|
|||
|
|
CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE));
|
|||
|
|
8006cec: 68fb ldr r3, [r7, #12]
|
|||
|
|
8006cee: 681b ldr r3, [r3, #0]
|
|||
|
|
8006cf0: 68fa ldr r2, [r7, #12]
|
|||
|
|
8006cf2: 6812 ldr r2, [r2, #0]
|
|||
|
|
8006cf4: 6812 ldr r2, [r2, #0]
|
|||
|
|
8006cf6: 4917 ldr r1, [pc, #92] ; (8006d54 <UART_WaitOnFlagUntilTimeout+0xf8>)
|
|||
|
|
8006cf8: 400a ands r2, r1
|
|||
|
|
8006cfa: 601a str r2, [r3, #0]
|
|||
|
|
CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
|
|||
|
|
8006cfc: 68fb ldr r3, [r7, #12]
|
|||
|
|
8006cfe: 681b ldr r3, [r3, #0]
|
|||
|
|
8006d00: 68fa ldr r2, [r7, #12]
|
|||
|
|
8006d02: 6812 ldr r2, [r2, #0]
|
|||
|
|
8006d04: 6892 ldr r2, [r2, #8]
|
|||
|
|
8006d06: 2101 movs r1, #1
|
|||
|
|
8006d08: 438a bics r2, r1
|
|||
|
|
8006d0a: 609a str r2, [r3, #8]
|
|||
|
|
|
|||
|
|
huart->gState = HAL_UART_STATE_READY;
|
|||
|
|
8006d0c: 68fb ldr r3, [r7, #12]
|
|||
|
|
8006d0e: 2220 movs r2, #32
|
|||
|
|
8006d10: 679a str r2, [r3, #120] ; 0x78
|
|||
|
|
huart->RxState = HAL_UART_STATE_READY;
|
|||
|
|
8006d12: 68fb ldr r3, [r7, #12]
|
|||
|
|
8006d14: 2220 movs r2, #32
|
|||
|
|
8006d16: 67da str r2, [r3, #124] ; 0x7c
|
|||
|
|
huart->ErrorCode = HAL_UART_ERROR_RTO;
|
|||
|
|
8006d18: 68fb ldr r3, [r7, #12]
|
|||
|
|
8006d1a: 2280 movs r2, #128 ; 0x80
|
|||
|
|
8006d1c: 2120 movs r1, #32
|
|||
|
|
8006d1e: 5099 str r1, [r3, r2]
|
|||
|
|
|
|||
|
|
/* Process Unlocked */
|
|||
|
|
__HAL_UNLOCK(huart);
|
|||
|
|
8006d20: 68fb ldr r3, [r7, #12]
|
|||
|
|
8006d22: 2274 movs r2, #116 ; 0x74
|
|||
|
|
8006d24: 2100 movs r1, #0
|
|||
|
|
8006d26: 5499 strb r1, [r3, r2]
|
|||
|
|
|
|||
|
|
return HAL_TIMEOUT;
|
|||
|
|
8006d28: 2303 movs r3, #3
|
|||
|
|
8006d2a: e00f b.n 8006d4c <UART_WaitOnFlagUntilTimeout+0xf0>
|
|||
|
|
while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status)
|
|||
|
|
8006d2c: 68fb ldr r3, [r7, #12]
|
|||
|
|
8006d2e: 681b ldr r3, [r3, #0]
|
|||
|
|
8006d30: 69db ldr r3, [r3, #28]
|
|||
|
|
8006d32: 68ba ldr r2, [r7, #8]
|
|||
|
|
8006d34: 401a ands r2, r3
|
|||
|
|
8006d36: 68bb ldr r3, [r7, #8]
|
|||
|
|
8006d38: 1ad3 subs r3, r2, r3
|
|||
|
|
8006d3a: 425a negs r2, r3
|
|||
|
|
8006d3c: 4153 adcs r3, r2
|
|||
|
|
8006d3e: b2db uxtb r3, r3
|
|||
|
|
8006d40: 001a movs r2, r3
|
|||
|
|
8006d42: 1dfb adds r3, r7, #7
|
|||
|
|
8006d44: 781b ldrb r3, [r3, #0]
|
|||
|
|
8006d46: 429a cmp r2, r3
|
|||
|
|
8006d48: d091 beq.n 8006c6e <UART_WaitOnFlagUntilTimeout+0x12>
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
return HAL_OK;
|
|||
|
|
8006d4a: 2300 movs r3, #0
|
|||
|
|
}
|
|||
|
|
8006d4c: 0018 movs r0, r3
|
|||
|
|
8006d4e: 46bd mov sp, r7
|
|||
|
|
8006d50: b004 add sp, #16
|
|||
|
|
8006d52: bd80 pop {r7, pc}
|
|||
|
|
8006d54: fffffe5f .word 0xfffffe5f
|
|||
|
|
|
|||
|
|
08006d58 <UART_EndRxTransfer>:
|
|||
|
|
* @brief End ongoing Rx transfer on UART peripheral (following error detection or Reception completion).
|
|||
|
|
* @param huart UART handle.
|
|||
|
|
* @retval None
|
|||
|
|
*/
|
|||
|
|
static void UART_EndRxTransfer(UART_HandleTypeDef *huart)
|
|||
|
|
{
|
|||
|
|
8006d58: b580 push {r7, lr}
|
|||
|
|
8006d5a: b082 sub sp, #8
|
|||
|
|
8006d5c: af00 add r7, sp, #0
|
|||
|
|
8006d5e: 6078 str r0, [r7, #4]
|
|||
|
|
/* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
|
|||
|
|
CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
|
|||
|
|
8006d60: 687b ldr r3, [r7, #4]
|
|||
|
|
8006d62: 681b ldr r3, [r3, #0]
|
|||
|
|
8006d64: 687a ldr r2, [r7, #4]
|
|||
|
|
8006d66: 6812 ldr r2, [r2, #0]
|
|||
|
|
8006d68: 6812 ldr r2, [r2, #0]
|
|||
|
|
8006d6a: 4912 ldr r1, [pc, #72] ; (8006db4 <UART_EndRxTransfer+0x5c>)
|
|||
|
|
8006d6c: 400a ands r2, r1
|
|||
|
|
8006d6e: 601a str r2, [r3, #0]
|
|||
|
|
CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
|
|||
|
|
8006d70: 687b ldr r3, [r7, #4]
|
|||
|
|
8006d72: 681b ldr r3, [r3, #0]
|
|||
|
|
8006d74: 687a ldr r2, [r7, #4]
|
|||
|
|
8006d76: 6812 ldr r2, [r2, #0]
|
|||
|
|
8006d78: 6892 ldr r2, [r2, #8]
|
|||
|
|
8006d7a: 2101 movs r1, #1
|
|||
|
|
8006d7c: 438a bics r2, r1
|
|||
|
|
8006d7e: 609a str r2, [r3, #8]
|
|||
|
|
|
|||
|
|
/* In case of reception waiting for IDLE event, disable also the IDLE IE interrupt source */
|
|||
|
|
if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
|
|||
|
|
8006d80: 687b ldr r3, [r7, #4]
|
|||
|
|
8006d82: 6e1b ldr r3, [r3, #96] ; 0x60
|
|||
|
|
8006d84: 2b01 cmp r3, #1
|
|||
|
|
8006d86: d107 bne.n 8006d98 <UART_EndRxTransfer+0x40>
|
|||
|
|
{
|
|||
|
|
CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
|
|||
|
|
8006d88: 687b ldr r3, [r7, #4]
|
|||
|
|
8006d8a: 681b ldr r3, [r3, #0]
|
|||
|
|
8006d8c: 687a ldr r2, [r7, #4]
|
|||
|
|
8006d8e: 6812 ldr r2, [r2, #0]
|
|||
|
|
8006d90: 6812 ldr r2, [r2, #0]
|
|||
|
|
8006d92: 2110 movs r1, #16
|
|||
|
|
8006d94: 438a bics r2, r1
|
|||
|
|
8006d96: 601a str r2, [r3, #0]
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
/* At end of Rx process, restore huart->RxState to Ready */
|
|||
|
|
huart->RxState = HAL_UART_STATE_READY;
|
|||
|
|
8006d98: 687b ldr r3, [r7, #4]
|
|||
|
|
8006d9a: 2220 movs r2, #32
|
|||
|
|
8006d9c: 67da str r2, [r3, #124] ; 0x7c
|
|||
|
|
huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
|
|||
|
|
8006d9e: 687b ldr r3, [r7, #4]
|
|||
|
|
8006da0: 2200 movs r2, #0
|
|||
|
|
8006da2: 661a str r2, [r3, #96] ; 0x60
|
|||
|
|
|
|||
|
|
/* Reset RxIsr function pointer */
|
|||
|
|
huart->RxISR = NULL;
|
|||
|
|
8006da4: 687b ldr r3, [r7, #4]
|
|||
|
|
8006da6: 2200 movs r2, #0
|
|||
|
|
8006da8: 665a str r2, [r3, #100] ; 0x64
|
|||
|
|
}
|
|||
|
|
8006daa: 46c0 nop ; (mov r8, r8)
|
|||
|
|
8006dac: 46bd mov sp, r7
|
|||
|
|
8006dae: b002 add sp, #8
|
|||
|
|
8006db0: bd80 pop {r7, pc}
|
|||
|
|
8006db2: 46c0 nop ; (mov r8, r8)
|
|||
|
|
8006db4: fffffedf .word 0xfffffedf
|
|||
|
|
|
|||
|
|
08006db8 <UART_DMAAbortOnError>:
|
|||
|
|
* (To be called at end of DMA Abort procedure following error occurrence).
|
|||
|
|
* @param hdma DMA handle.
|
|||
|
|
* @retval None
|
|||
|
|
*/
|
|||
|
|
static void UART_DMAAbortOnError(DMA_HandleTypeDef *hdma)
|
|||
|
|
{
|
|||
|
|
8006db8: b580 push {r7, lr}
|
|||
|
|
8006dba: b084 sub sp, #16
|
|||
|
|
8006dbc: af00 add r7, sp, #0
|
|||
|
|
8006dbe: 6078 str r0, [r7, #4]
|
|||
|
|
UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent);
|
|||
|
|
8006dc0: 687b ldr r3, [r7, #4]
|
|||
|
|
8006dc2: 6a9b ldr r3, [r3, #40] ; 0x28
|
|||
|
|
8006dc4: 60fb str r3, [r7, #12]
|
|||
|
|
huart->RxXferCount = 0U;
|
|||
|
|
8006dc6: 68fb ldr r3, [r7, #12]
|
|||
|
|
8006dc8: 225a movs r2, #90 ; 0x5a
|
|||
|
|
8006dca: 2100 movs r1, #0
|
|||
|
|
8006dcc: 5299 strh r1, [r3, r2]
|
|||
|
|
huart->TxXferCount = 0U;
|
|||
|
|
8006dce: 68fb ldr r3, [r7, #12]
|
|||
|
|
8006dd0: 2252 movs r2, #82 ; 0x52
|
|||
|
|
8006dd2: 2100 movs r1, #0
|
|||
|
|
8006dd4: 5299 strh r1, [r3, r2]
|
|||
|
|
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
|
|||
|
|
/*Call registered error callback*/
|
|||
|
|
huart->ErrorCallback(huart);
|
|||
|
|
#else
|
|||
|
|
/*Call legacy weak error callback*/
|
|||
|
|
HAL_UART_ErrorCallback(huart);
|
|||
|
|
8006dd6: 68fb ldr r3, [r7, #12]
|
|||
|
|
8006dd8: 0018 movs r0, r3
|
|||
|
|
8006dda: f7ff fb73 bl 80064c4 <HAL_UART_ErrorCallback>
|
|||
|
|
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
|
|||
|
|
}
|
|||
|
|
8006dde: 46c0 nop ; (mov r8, r8)
|
|||
|
|
8006de0: 46bd mov sp, r7
|
|||
|
|
8006de2: b004 add sp, #16
|
|||
|
|
8006de4: bd80 pop {r7, pc}
|
|||
|
|
|
|||
|
|
08006de6 <UART_TxISR_8BIT>:
|
|||
|
|
* interruptions have been enabled by HAL_UART_Transmit_IT().
|
|||
|
|
* @param huart UART handle.
|
|||
|
|
* @retval None
|
|||
|
|
*/
|
|||
|
|
static void UART_TxISR_8BIT(UART_HandleTypeDef *huart)
|
|||
|
|
{
|
|||
|
|
8006de6: b580 push {r7, lr}
|
|||
|
|
8006de8: b082 sub sp, #8
|
|||
|
|
8006dea: af00 add r7, sp, #0
|
|||
|
|
8006dec: 6078 str r0, [r7, #4]
|
|||
|
|
/* Check that a Tx process is ongoing */
|
|||
|
|
if (huart->gState == HAL_UART_STATE_BUSY_TX)
|
|||
|
|
8006dee: 687b ldr r3, [r7, #4]
|
|||
|
|
8006df0: 6f9b ldr r3, [r3, #120] ; 0x78
|
|||
|
|
8006df2: 2b21 cmp r3, #33 ; 0x21
|
|||
|
|
8006df4: d12a bne.n 8006e4c <UART_TxISR_8BIT+0x66>
|
|||
|
|
{
|
|||
|
|
if (huart->TxXferCount == 0U)
|
|||
|
|
8006df6: 687b ldr r3, [r7, #4]
|
|||
|
|
8006df8: 2252 movs r2, #82 ; 0x52
|
|||
|
|
8006dfa: 5a9b ldrh r3, [r3, r2]
|
|||
|
|
8006dfc: b29b uxth r3, r3
|
|||
|
|
8006dfe: 2b00 cmp r3, #0
|
|||
|
|
8006e00: d110 bne.n 8006e24 <UART_TxISR_8BIT+0x3e>
|
|||
|
|
{
|
|||
|
|
/* Disable the UART Transmit Data Register Empty Interrupt */
|
|||
|
|
CLEAR_BIT(huart->Instance->CR1, USART_CR1_TXEIE);
|
|||
|
|
8006e02: 687b ldr r3, [r7, #4]
|
|||
|
|
8006e04: 681b ldr r3, [r3, #0]
|
|||
|
|
8006e06: 687a ldr r2, [r7, #4]
|
|||
|
|
8006e08: 6812 ldr r2, [r2, #0]
|
|||
|
|
8006e0a: 6812 ldr r2, [r2, #0]
|
|||
|
|
8006e0c: 2180 movs r1, #128 ; 0x80
|
|||
|
|
8006e0e: 438a bics r2, r1
|
|||
|
|
8006e10: 601a str r2, [r3, #0]
|
|||
|
|
|
|||
|
|
/* Enable the UART Transmit Complete Interrupt */
|
|||
|
|
SET_BIT(huart->Instance->CR1, USART_CR1_TCIE);
|
|||
|
|
8006e12: 687b ldr r3, [r7, #4]
|
|||
|
|
8006e14: 681b ldr r3, [r3, #0]
|
|||
|
|
8006e16: 687a ldr r2, [r7, #4]
|
|||
|
|
8006e18: 6812 ldr r2, [r2, #0]
|
|||
|
|
8006e1a: 6812 ldr r2, [r2, #0]
|
|||
|
|
8006e1c: 2140 movs r1, #64 ; 0x40
|
|||
|
|
8006e1e: 430a orrs r2, r1
|
|||
|
|
8006e20: 601a str r2, [r3, #0]
|
|||
|
|
huart->Instance->TDR = (uint8_t)(*huart->pTxBuffPtr & (uint8_t)0xFF);
|
|||
|
|
huart->pTxBuffPtr++;
|
|||
|
|
huart->TxXferCount--;
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
8006e22: e013 b.n 8006e4c <UART_TxISR_8BIT+0x66>
|
|||
|
|
huart->Instance->TDR = (uint8_t)(*huart->pTxBuffPtr & (uint8_t)0xFF);
|
|||
|
|
8006e24: 687b ldr r3, [r7, #4]
|
|||
|
|
8006e26: 681b ldr r3, [r3, #0]
|
|||
|
|
8006e28: 687a ldr r2, [r7, #4]
|
|||
|
|
8006e2a: 6cd2 ldr r2, [r2, #76] ; 0x4c
|
|||
|
|
8006e2c: 7812 ldrb r2, [r2, #0]
|
|||
|
|
8006e2e: 629a str r2, [r3, #40] ; 0x28
|
|||
|
|
huart->pTxBuffPtr++;
|
|||
|
|
8006e30: 687b ldr r3, [r7, #4]
|
|||
|
|
8006e32: 6cdb ldr r3, [r3, #76] ; 0x4c
|
|||
|
|
8006e34: 1c5a adds r2, r3, #1
|
|||
|
|
8006e36: 687b ldr r3, [r7, #4]
|
|||
|
|
8006e38: 64da str r2, [r3, #76] ; 0x4c
|
|||
|
|
huart->TxXferCount--;
|
|||
|
|
8006e3a: 687b ldr r3, [r7, #4]
|
|||
|
|
8006e3c: 2252 movs r2, #82 ; 0x52
|
|||
|
|
8006e3e: 5a9b ldrh r3, [r3, r2]
|
|||
|
|
8006e40: b29b uxth r3, r3
|
|||
|
|
8006e42: 3b01 subs r3, #1
|
|||
|
|
8006e44: b299 uxth r1, r3
|
|||
|
|
8006e46: 687b ldr r3, [r7, #4]
|
|||
|
|
8006e48: 2252 movs r2, #82 ; 0x52
|
|||
|
|
8006e4a: 5299 strh r1, [r3, r2]
|
|||
|
|
}
|
|||
|
|
8006e4c: 46c0 nop ; (mov r8, r8)
|
|||
|
|
8006e4e: 46bd mov sp, r7
|
|||
|
|
8006e50: b002 add sp, #8
|
|||
|
|
8006e52: bd80 pop {r7, pc}
|
|||
|
|
|
|||
|
|
08006e54 <UART_TxISR_16BIT>:
|
|||
|
|
* interruptions have been enabled by HAL_UART_Transmit_IT().
|
|||
|
|
* @param huart UART handle.
|
|||
|
|
* @retval None
|
|||
|
|
*/
|
|||
|
|
static void UART_TxISR_16BIT(UART_HandleTypeDef *huart)
|
|||
|
|
{
|
|||
|
|
8006e54: b580 push {r7, lr}
|
|||
|
|
8006e56: b084 sub sp, #16
|
|||
|
|
8006e58: af00 add r7, sp, #0
|
|||
|
|
8006e5a: 6078 str r0, [r7, #4]
|
|||
|
|
uint16_t *tmp;
|
|||
|
|
|
|||
|
|
/* Check that a Tx process is ongoing */
|
|||
|
|
if (huart->gState == HAL_UART_STATE_BUSY_TX)
|
|||
|
|
8006e5c: 687b ldr r3, [r7, #4]
|
|||
|
|
8006e5e: 6f9b ldr r3, [r3, #120] ; 0x78
|
|||
|
|
8006e60: 2b21 cmp r3, #33 ; 0x21
|
|||
|
|
8006e62: d12e bne.n 8006ec2 <UART_TxISR_16BIT+0x6e>
|
|||
|
|
{
|
|||
|
|
if (huart->TxXferCount == 0U)
|
|||
|
|
8006e64: 687b ldr r3, [r7, #4]
|
|||
|
|
8006e66: 2252 movs r2, #82 ; 0x52
|
|||
|
|
8006e68: 5a9b ldrh r3, [r3, r2]
|
|||
|
|
8006e6a: b29b uxth r3, r3
|
|||
|
|
8006e6c: 2b00 cmp r3, #0
|
|||
|
|
8006e6e: d110 bne.n 8006e92 <UART_TxISR_16BIT+0x3e>
|
|||
|
|
{
|
|||
|
|
/* Disable the UART Transmit Data Register Empty Interrupt */
|
|||
|
|
CLEAR_BIT(huart->Instance->CR1, USART_CR1_TXEIE);
|
|||
|
|
8006e70: 687b ldr r3, [r7, #4]
|
|||
|
|
8006e72: 681b ldr r3, [r3, #0]
|
|||
|
|
8006e74: 687a ldr r2, [r7, #4]
|
|||
|
|
8006e76: 6812 ldr r2, [r2, #0]
|
|||
|
|
8006e78: 6812 ldr r2, [r2, #0]
|
|||
|
|
8006e7a: 2180 movs r1, #128 ; 0x80
|
|||
|
|
8006e7c: 438a bics r2, r1
|
|||
|
|
8006e7e: 601a str r2, [r3, #0]
|
|||
|
|
|
|||
|
|
/* Enable the UART Transmit Complete Interrupt */
|
|||
|
|
SET_BIT(huart->Instance->CR1, USART_CR1_TCIE);
|
|||
|
|
8006e80: 687b ldr r3, [r7, #4]
|
|||
|
|
8006e82: 681b ldr r3, [r3, #0]
|
|||
|
|
8006e84: 687a ldr r2, [r7, #4]
|
|||
|
|
8006e86: 6812 ldr r2, [r2, #0]
|
|||
|
|
8006e88: 6812 ldr r2, [r2, #0]
|
|||
|
|
8006e8a: 2140 movs r1, #64 ; 0x40
|
|||
|
|
8006e8c: 430a orrs r2, r1
|
|||
|
|
8006e8e: 601a str r2, [r3, #0]
|
|||
|
|
huart->Instance->TDR = (((uint32_t)(*tmp)) & 0x01FFUL);
|
|||
|
|
huart->pTxBuffPtr += 2U;
|
|||
|
|
huart->TxXferCount--;
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
8006e90: e017 b.n 8006ec2 <UART_TxISR_16BIT+0x6e>
|
|||
|
|
tmp = (uint16_t *) huart->pTxBuffPtr;
|
|||
|
|
8006e92: 687b ldr r3, [r7, #4]
|
|||
|
|
8006e94: 6cdb ldr r3, [r3, #76] ; 0x4c
|
|||
|
|
8006e96: 60fb str r3, [r7, #12]
|
|||
|
|
huart->Instance->TDR = (((uint32_t)(*tmp)) & 0x01FFUL);
|
|||
|
|
8006e98: 687b ldr r3, [r7, #4]
|
|||
|
|
8006e9a: 681b ldr r3, [r3, #0]
|
|||
|
|
8006e9c: 68fa ldr r2, [r7, #12]
|
|||
|
|
8006e9e: 8812 ldrh r2, [r2, #0]
|
|||
|
|
8006ea0: 05d2 lsls r2, r2, #23
|
|||
|
|
8006ea2: 0dd2 lsrs r2, r2, #23
|
|||
|
|
8006ea4: 629a str r2, [r3, #40] ; 0x28
|
|||
|
|
huart->pTxBuffPtr += 2U;
|
|||
|
|
8006ea6: 687b ldr r3, [r7, #4]
|
|||
|
|
8006ea8: 6cdb ldr r3, [r3, #76] ; 0x4c
|
|||
|
|
8006eaa: 1c9a adds r2, r3, #2
|
|||
|
|
8006eac: 687b ldr r3, [r7, #4]
|
|||
|
|
8006eae: 64da str r2, [r3, #76] ; 0x4c
|
|||
|
|
huart->TxXferCount--;
|
|||
|
|
8006eb0: 687b ldr r3, [r7, #4]
|
|||
|
|
8006eb2: 2252 movs r2, #82 ; 0x52
|
|||
|
|
8006eb4: 5a9b ldrh r3, [r3, r2]
|
|||
|
|
8006eb6: b29b uxth r3, r3
|
|||
|
|
8006eb8: 3b01 subs r3, #1
|
|||
|
|
8006eba: b299 uxth r1, r3
|
|||
|
|
8006ebc: 687b ldr r3, [r7, #4]
|
|||
|
|
8006ebe: 2252 movs r2, #82 ; 0x52
|
|||
|
|
8006ec0: 5299 strh r1, [r3, r2]
|
|||
|
|
}
|
|||
|
|
8006ec2: 46c0 nop ; (mov r8, r8)
|
|||
|
|
8006ec4: 46bd mov sp, r7
|
|||
|
|
8006ec6: b004 add sp, #16
|
|||
|
|
8006ec8: bd80 pop {r7, pc}
|
|||
|
|
|
|||
|
|
08006eca <UART_EndTransmit_IT>:
|
|||
|
|
* @param huart pointer to a UART_HandleTypeDef structure that contains
|
|||
|
|
* the configuration information for the specified UART module.
|
|||
|
|
* @retval None
|
|||
|
|
*/
|
|||
|
|
static void UART_EndTransmit_IT(UART_HandleTypeDef *huart)
|
|||
|
|
{
|
|||
|
|
8006eca: b580 push {r7, lr}
|
|||
|
|
8006ecc: b082 sub sp, #8
|
|||
|
|
8006ece: af00 add r7, sp, #0
|
|||
|
|
8006ed0: 6078 str r0, [r7, #4]
|
|||
|
|
/* Disable the UART Transmit Complete Interrupt */
|
|||
|
|
CLEAR_BIT(huart->Instance->CR1, USART_CR1_TCIE);
|
|||
|
|
8006ed2: 687b ldr r3, [r7, #4]
|
|||
|
|
8006ed4: 681b ldr r3, [r3, #0]
|
|||
|
|
8006ed6: 687a ldr r2, [r7, #4]
|
|||
|
|
8006ed8: 6812 ldr r2, [r2, #0]
|
|||
|
|
8006eda: 6812 ldr r2, [r2, #0]
|
|||
|
|
8006edc: 2140 movs r1, #64 ; 0x40
|
|||
|
|
8006ede: 438a bics r2, r1
|
|||
|
|
8006ee0: 601a str r2, [r3, #0]
|
|||
|
|
|
|||
|
|
/* Tx process is ended, restore huart->gState to Ready */
|
|||
|
|
huart->gState = HAL_UART_STATE_READY;
|
|||
|
|
8006ee2: 687b ldr r3, [r7, #4]
|
|||
|
|
8006ee4: 2220 movs r2, #32
|
|||
|
|
8006ee6: 679a str r2, [r3, #120] ; 0x78
|
|||
|
|
|
|||
|
|
/* Cleat TxISR function pointer */
|
|||
|
|
huart->TxISR = NULL;
|
|||
|
|
8006ee8: 687b ldr r3, [r7, #4]
|
|||
|
|
8006eea: 2200 movs r2, #0
|
|||
|
|
8006eec: 669a str r2, [r3, #104] ; 0x68
|
|||
|
|
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
|
|||
|
|
/*Call registered Tx complete callback*/
|
|||
|
|
huart->TxCpltCallback(huart);
|
|||
|
|
#else
|
|||
|
|
/*Call legacy weak Tx complete callback*/
|
|||
|
|
HAL_UART_TxCpltCallback(huart);
|
|||
|
|
8006eee: 687b ldr r3, [r7, #4]
|
|||
|
|
8006ef0: 0018 movs r0, r3
|
|||
|
|
8006ef2: f7fc febf bl 8003c74 <HAL_UART_TxCpltCallback>
|
|||
|
|
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
|
|||
|
|
}
|
|||
|
|
8006ef6: 46c0 nop ; (mov r8, r8)
|
|||
|
|
8006ef8: 46bd mov sp, r7
|
|||
|
|
8006efa: b002 add sp, #8
|
|||
|
|
8006efc: bd80 pop {r7, pc}
|
|||
|
|
|
|||
|
|
08006efe <HAL_UARTEx_WakeupCallback>:
|
|||
|
|
* @brief UART wakeup from Stop mode callback.
|
|||
|
|
* @param huart UART handle.
|
|||
|
|
* @retval None
|
|||
|
|
*/
|
|||
|
|
__weak void HAL_UARTEx_WakeupCallback(UART_HandleTypeDef *huart)
|
|||
|
|
{
|
|||
|
|
8006efe: b580 push {r7, lr}
|
|||
|
|
8006f00: b082 sub sp, #8
|
|||
|
|
8006f02: af00 add r7, sp, #0
|
|||
|
|
8006f04: 6078 str r0, [r7, #4]
|
|||
|
|
UNUSED(huart);
|
|||
|
|
|
|||
|
|
/* NOTE : This function should not be modified, when the callback is needed,
|
|||
|
|
the HAL_UARTEx_WakeupCallback can be implemented in the user file.
|
|||
|
|
*/
|
|||
|
|
}
|
|||
|
|
8006f06: 46c0 nop ; (mov r8, r8)
|
|||
|
|
8006f08: 46bd mov sp, r7
|
|||
|
|
8006f0a: b002 add sp, #8
|
|||
|
|
8006f0c: bd80 pop {r7, pc}
|
|||
|
|
...
|
|||
|
|
|
|||
|
|
08006f10 <Reset_Handler>:
|
|||
|
|
|
|||
|
|
.section .text.Reset_Handler
|
|||
|
|
.weak Reset_Handler
|
|||
|
|
.type Reset_Handler, %function
|
|||
|
|
Reset_Handler:
|
|||
|
|
ldr r0, =_estack
|
|||
|
|
8006f10: 480d ldr r0, [pc, #52] ; (8006f48 <LoopForever+0x2>)
|
|||
|
|
mov sp, r0 /* set stack pointer */
|
|||
|
|
8006f12: 4685 mov sp, r0
|
|||
|
|
|
|||
|
|
/* Copy the data segment initializers from flash to SRAM */
|
|||
|
|
ldr r0, =_sdata
|
|||
|
|
8006f14: 480d ldr r0, [pc, #52] ; (8006f4c <LoopForever+0x6>)
|
|||
|
|
ldr r1, =_edata
|
|||
|
|
8006f16: 490e ldr r1, [pc, #56] ; (8006f50 <LoopForever+0xa>)
|
|||
|
|
ldr r2, =_sidata
|
|||
|
|
8006f18: 4a0e ldr r2, [pc, #56] ; (8006f54 <LoopForever+0xe>)
|
|||
|
|
movs r3, #0
|
|||
|
|
8006f1a: 2300 movs r3, #0
|
|||
|
|
b LoopCopyDataInit
|
|||
|
|
8006f1c: e002 b.n 8006f24 <LoopCopyDataInit>
|
|||
|
|
|
|||
|
|
08006f1e <CopyDataInit>:
|
|||
|
|
|
|||
|
|
CopyDataInit:
|
|||
|
|
ldr r4, [r2, r3]
|
|||
|
|
8006f1e: 58d4 ldr r4, [r2, r3]
|
|||
|
|
str r4, [r0, r3]
|
|||
|
|
8006f20: 50c4 str r4, [r0, r3]
|
|||
|
|
adds r3, r3, #4
|
|||
|
|
8006f22: 3304 adds r3, #4
|
|||
|
|
|
|||
|
|
08006f24 <LoopCopyDataInit>:
|
|||
|
|
|
|||
|
|
LoopCopyDataInit:
|
|||
|
|
adds r4, r0, r3
|
|||
|
|
8006f24: 18c4 adds r4, r0, r3
|
|||
|
|
cmp r4, r1
|
|||
|
|
8006f26: 428c cmp r4, r1
|
|||
|
|
bcc CopyDataInit
|
|||
|
|
8006f28: d3f9 bcc.n 8006f1e <CopyDataInit>
|
|||
|
|
|
|||
|
|
/* Zero fill the bss segment. */
|
|||
|
|
ldr r2, =_sbss
|
|||
|
|
8006f2a: 4a0b ldr r2, [pc, #44] ; (8006f58 <LoopForever+0x12>)
|
|||
|
|
ldr r4, =_ebss
|
|||
|
|
8006f2c: 4c0b ldr r4, [pc, #44] ; (8006f5c <LoopForever+0x16>)
|
|||
|
|
movs r3, #0
|
|||
|
|
8006f2e: 2300 movs r3, #0
|
|||
|
|
b LoopFillZerobss
|
|||
|
|
8006f30: e001 b.n 8006f36 <LoopFillZerobss>
|
|||
|
|
|
|||
|
|
08006f32 <FillZerobss>:
|
|||
|
|
|
|||
|
|
FillZerobss:
|
|||
|
|
str r3, [r2]
|
|||
|
|
8006f32: 6013 str r3, [r2, #0]
|
|||
|
|
adds r2, r2, #4
|
|||
|
|
8006f34: 3204 adds r2, #4
|
|||
|
|
|
|||
|
|
08006f36 <LoopFillZerobss>:
|
|||
|
|
|
|||
|
|
LoopFillZerobss:
|
|||
|
|
cmp r2, r4
|
|||
|
|
8006f36: 42a2 cmp r2, r4
|
|||
|
|
bcc FillZerobss
|
|||
|
|
8006f38: d3fb bcc.n 8006f32 <FillZerobss>
|
|||
|
|
|
|||
|
|
/* Call the clock system intitialization function.*/
|
|||
|
|
bl SystemInit
|
|||
|
|
8006f3a: f7fb f9df bl 80022fc <SystemInit>
|
|||
|
|
/* Call static constructors */
|
|||
|
|
bl __libc_init_array
|
|||
|
|
8006f3e: f000 f811 bl 8006f64 <__libc_init_array>
|
|||
|
|
/* Call the application's entry point.*/
|
|||
|
|
bl main
|
|||
|
|
8006f42: f7fb f89b bl 800207c <main>
|
|||
|
|
|
|||
|
|
08006f46 <LoopForever>:
|
|||
|
|
|
|||
|
|
LoopForever:
|
|||
|
|
b LoopForever
|
|||
|
|
8006f46: e7fe b.n 8006f46 <LoopForever>
|
|||
|
|
ldr r0, =_estack
|
|||
|
|
8006f48: 20005000 .word 0x20005000
|
|||
|
|
ldr r0, =_sdata
|
|||
|
|
8006f4c: 20000000 .word 0x20000000
|
|||
|
|
ldr r1, =_edata
|
|||
|
|
8006f50: 20000010 .word 0x20000010
|
|||
|
|
ldr r2, =_sidata
|
|||
|
|
8006f54: 0800749c .word 0x0800749c
|
|||
|
|
ldr r2, =_sbss
|
|||
|
|
8006f58: 20000010 .word 0x20000010
|
|||
|
|
ldr r4, =_ebss
|
|||
|
|
8006f5c: 200003a8 .word 0x200003a8
|
|||
|
|
|
|||
|
|
08006f60 <ADC1_COMP_IRQHandler>:
|
|||
|
|
* @retval : None
|
|||
|
|
*/
|
|||
|
|
.section .text.Default_Handler,"ax",%progbits
|
|||
|
|
Default_Handler:
|
|||
|
|
Infinite_Loop:
|
|||
|
|
b Infinite_Loop
|
|||
|
|
8006f60: e7fe b.n 8006f60 <ADC1_COMP_IRQHandler>
|
|||
|
|
...
|
|||
|
|
|
|||
|
|
08006f64 <__libc_init_array>:
|
|||
|
|
8006f64: b570 push {r4, r5, r6, lr}
|
|||
|
|
8006f66: 2600 movs r6, #0
|
|||
|
|
8006f68: 4d0c ldr r5, [pc, #48] ; (8006f9c <__libc_init_array+0x38>)
|
|||
|
|
8006f6a: 4c0d ldr r4, [pc, #52] ; (8006fa0 <__libc_init_array+0x3c>)
|
|||
|
|
8006f6c: 1b64 subs r4, r4, r5
|
|||
|
|
8006f6e: 10a4 asrs r4, r4, #2
|
|||
|
|
8006f70: 42a6 cmp r6, r4
|
|||
|
|
8006f72: d109 bne.n 8006f88 <__libc_init_array+0x24>
|
|||
|
|
8006f74: 2600 movs r6, #0
|
|||
|
|
8006f76: f000 f82b bl 8006fd0 <_init>
|
|||
|
|
8006f7a: 4d0a ldr r5, [pc, #40] ; (8006fa4 <__libc_init_array+0x40>)
|
|||
|
|
8006f7c: 4c0a ldr r4, [pc, #40] ; (8006fa8 <__libc_init_array+0x44>)
|
|||
|
|
8006f7e: 1b64 subs r4, r4, r5
|
|||
|
|
8006f80: 10a4 asrs r4, r4, #2
|
|||
|
|
8006f82: 42a6 cmp r6, r4
|
|||
|
|
8006f84: d105 bne.n 8006f92 <__libc_init_array+0x2e>
|
|||
|
|
8006f86: bd70 pop {r4, r5, r6, pc}
|
|||
|
|
8006f88: 00b3 lsls r3, r6, #2
|
|||
|
|
8006f8a: 58eb ldr r3, [r5, r3]
|
|||
|
|
8006f8c: 4798 blx r3
|
|||
|
|
8006f8e: 3601 adds r6, #1
|
|||
|
|
8006f90: e7ee b.n 8006f70 <__libc_init_array+0xc>
|
|||
|
|
8006f92: 00b3 lsls r3, r6, #2
|
|||
|
|
8006f94: 58eb ldr r3, [r5, r3]
|
|||
|
|
8006f96: 4798 blx r3
|
|||
|
|
8006f98: 3601 adds r6, #1
|
|||
|
|
8006f9a: e7f2 b.n 8006f82 <__libc_init_array+0x1e>
|
|||
|
|
8006f9c: 08007494 .word 0x08007494
|
|||
|
|
8006fa0: 08007494 .word 0x08007494
|
|||
|
|
8006fa4: 08007494 .word 0x08007494
|
|||
|
|
8006fa8: 08007498 .word 0x08007498
|
|||
|
|
|
|||
|
|
08006fac <memcpy>:
|
|||
|
|
8006fac: 2300 movs r3, #0
|
|||
|
|
8006fae: b510 push {r4, lr}
|
|||
|
|
8006fb0: 429a cmp r2, r3
|
|||
|
|
8006fb2: d100 bne.n 8006fb6 <memcpy+0xa>
|
|||
|
|
8006fb4: bd10 pop {r4, pc}
|
|||
|
|
8006fb6: 5ccc ldrb r4, [r1, r3]
|
|||
|
|
8006fb8: 54c4 strb r4, [r0, r3]
|
|||
|
|
8006fba: 3301 adds r3, #1
|
|||
|
|
8006fbc: e7f8 b.n 8006fb0 <memcpy+0x4>
|
|||
|
|
|
|||
|
|
08006fbe <memset>:
|
|||
|
|
8006fbe: 0003 movs r3, r0
|
|||
|
|
8006fc0: 1882 adds r2, r0, r2
|
|||
|
|
8006fc2: 4293 cmp r3, r2
|
|||
|
|
8006fc4: d100 bne.n 8006fc8 <memset+0xa>
|
|||
|
|
8006fc6: 4770 bx lr
|
|||
|
|
8006fc8: 7019 strb r1, [r3, #0]
|
|||
|
|
8006fca: 3301 adds r3, #1
|
|||
|
|
8006fcc: e7f9 b.n 8006fc2 <memset+0x4>
|
|||
|
|
...
|
|||
|
|
|
|||
|
|
08006fd0 <_init>:
|
|||
|
|
8006fd0: b5f8 push {r3, r4, r5, r6, r7, lr}
|
|||
|
|
8006fd2: 46c0 nop ; (mov r8, r8)
|
|||
|
|
8006fd4: bcf8 pop {r3, r4, r5, r6, r7}
|
|||
|
|
8006fd6: bc08 pop {r3}
|
|||
|
|
8006fd8: 469e mov lr, r3
|
|||
|
|
8006fda: 4770 bx lr
|
|||
|
|
|
|||
|
|
08006fdc <_fini>:
|
|||
|
|
8006fdc: b5f8 push {r3, r4, r5, r6, r7, lr}
|
|||
|
|
8006fde: 46c0 nop ; (mov r8, r8)
|
|||
|
|
8006fe0: bcf8 pop {r3, r4, r5, r6, r7}
|
|||
|
|
8006fe2: bc08 pop {r3}
|
|||
|
|
8006fe4: 469e mov lr, r3
|
|||
|
|
8006fe6: 4770 bx lr
|