8185 lines
308 KiB
Plaintext
8185 lines
308 KiB
Plaintext
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Amplifier.elf: file format elf32-littlearm
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Sections:
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Idx Name Size VMA LMA File off Algn
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0 .isr_vector 000000c0 08000000 08000000 00010000 2**0
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CONTENTS, ALLOC, LOAD, READONLY, DATA
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1 .text 00002cd0 080000c0 080000c0 000100c0 2**2
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CONTENTS, ALLOC, LOAD, READONLY, CODE
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2 .rodata 0000006c 08002d90 08002d90 00012d90 2**2
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CONTENTS, ALLOC, LOAD, READONLY, DATA
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3 .ARM 00000008 08002dfc 08002dfc 00012dfc 2**2
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CONTENTS, ALLOC, LOAD, READONLY, DATA
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4 .init_array 00000004 08002e04 08002e04 00012e04 2**2
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CONTENTS, ALLOC, LOAD, DATA
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5 .fini_array 00000004 08002e08 08002e08 00012e08 2**2
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CONTENTS, ALLOC, LOAD, DATA
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6 .data 0000000c 20000000 08002e0c 00020000 2**2
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CONTENTS, ALLOC, LOAD, DATA
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7 .bss 000000a4 2000000c 08002e18 0002000c 2**2
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ALLOC
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8 ._user_heap_stack 00000600 200000b0 08002e18 000200b0 2**0
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ALLOC
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9 .ARM.attributes 00000028 00000000 00000000 0002000c 2**0
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CONTENTS, READONLY
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10 .debug_info 000079f6 00000000 00000000 00020034 2**0
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CONTENTS, READONLY, DEBUGGING
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11 .debug_abbrev 000017f9 00000000 00000000 00027a2a 2**0
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CONTENTS, READONLY, DEBUGGING
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12 .debug_aranges 000007d8 00000000 00000000 00029228 2**3
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CONTENTS, READONLY, DEBUGGING
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13 .debug_ranges 00000720 00000000 00000000 00029a00 2**3
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CONTENTS, READONLY, DEBUGGING
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14 .debug_line 00003b49 00000000 00000000 0002a120 2**0
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CONTENTS, READONLY, DEBUGGING
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15 .debug_str 0000266c 00000000 00000000 0002dc69 2**0
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CONTENTS, READONLY, DEBUGGING
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16 .comment 0000007c 00000000 00000000 000302d5 2**0
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CONTENTS, READONLY
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17 .debug_frame 00001a5c 00000000 00000000 00030354 2**2
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CONTENTS, READONLY, DEBUGGING
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Disassembly of section .text:
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080000c0 <__do_global_dtors_aux>:
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80000c0: b510 push {r4, lr}
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80000c2: 4c06 ldr r4, [pc, #24] ; (80000dc <__do_global_dtors_aux+0x1c>)
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80000c4: 7823 ldrb r3, [r4, #0]
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80000c6: 2b00 cmp r3, #0
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80000c8: d107 bne.n 80000da <__do_global_dtors_aux+0x1a>
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80000ca: 4b05 ldr r3, [pc, #20] ; (80000e0 <__do_global_dtors_aux+0x20>)
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80000cc: 2b00 cmp r3, #0
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80000ce: d002 beq.n 80000d6 <__do_global_dtors_aux+0x16>
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80000d0: 4804 ldr r0, [pc, #16] ; (80000e4 <__do_global_dtors_aux+0x24>)
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80000d2: e000 b.n 80000d6 <__do_global_dtors_aux+0x16>
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80000d4: bf00 nop
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80000d6: 2301 movs r3, #1
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80000d8: 7023 strb r3, [r4, #0]
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80000da: bd10 pop {r4, pc}
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80000dc: 2000000c .word 0x2000000c
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80000e0: 00000000 .word 0x00000000
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80000e4: 08002d78 .word 0x08002d78
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080000e8 <frame_dummy>:
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80000e8: 4b04 ldr r3, [pc, #16] ; (80000fc <frame_dummy+0x14>)
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80000ea: b510 push {r4, lr}
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80000ec: 2b00 cmp r3, #0
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80000ee: d003 beq.n 80000f8 <frame_dummy+0x10>
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80000f0: 4903 ldr r1, [pc, #12] ; (8000100 <frame_dummy+0x18>)
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80000f2: 4804 ldr r0, [pc, #16] ; (8000104 <frame_dummy+0x1c>)
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80000f4: e000 b.n 80000f8 <frame_dummy+0x10>
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80000f6: bf00 nop
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80000f8: bd10 pop {r4, pc}
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80000fa: 46c0 nop ; (mov r8, r8)
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80000fc: 00000000 .word 0x00000000
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8000100: 20000010 .word 0x20000010
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8000104: 08002d78 .word 0x08002d78
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08000108 <__udivsi3>:
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8000108: 2200 movs r2, #0
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800010a: 0843 lsrs r3, r0, #1
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800010c: 428b cmp r3, r1
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800010e: d374 bcc.n 80001fa <__udivsi3+0xf2>
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8000110: 0903 lsrs r3, r0, #4
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8000112: 428b cmp r3, r1
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8000114: d35f bcc.n 80001d6 <__udivsi3+0xce>
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8000116: 0a03 lsrs r3, r0, #8
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8000118: 428b cmp r3, r1
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800011a: d344 bcc.n 80001a6 <__udivsi3+0x9e>
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800011c: 0b03 lsrs r3, r0, #12
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800011e: 428b cmp r3, r1
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8000120: d328 bcc.n 8000174 <__udivsi3+0x6c>
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8000122: 0c03 lsrs r3, r0, #16
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8000124: 428b cmp r3, r1
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8000126: d30d bcc.n 8000144 <__udivsi3+0x3c>
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8000128: 22ff movs r2, #255 ; 0xff
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800012a: 0209 lsls r1, r1, #8
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800012c: ba12 rev r2, r2
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800012e: 0c03 lsrs r3, r0, #16
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8000130: 428b cmp r3, r1
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8000132: d302 bcc.n 800013a <__udivsi3+0x32>
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8000134: 1212 asrs r2, r2, #8
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8000136: 0209 lsls r1, r1, #8
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8000138: d065 beq.n 8000206 <__udivsi3+0xfe>
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800013a: 0b03 lsrs r3, r0, #12
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800013c: 428b cmp r3, r1
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800013e: d319 bcc.n 8000174 <__udivsi3+0x6c>
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8000140: e000 b.n 8000144 <__udivsi3+0x3c>
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8000142: 0a09 lsrs r1, r1, #8
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8000144: 0bc3 lsrs r3, r0, #15
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8000146: 428b cmp r3, r1
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8000148: d301 bcc.n 800014e <__udivsi3+0x46>
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800014a: 03cb lsls r3, r1, #15
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800014c: 1ac0 subs r0, r0, r3
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800014e: 4152 adcs r2, r2
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8000150: 0b83 lsrs r3, r0, #14
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8000152: 428b cmp r3, r1
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8000154: d301 bcc.n 800015a <__udivsi3+0x52>
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8000156: 038b lsls r3, r1, #14
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8000158: 1ac0 subs r0, r0, r3
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800015a: 4152 adcs r2, r2
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800015c: 0b43 lsrs r3, r0, #13
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800015e: 428b cmp r3, r1
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8000160: d301 bcc.n 8000166 <__udivsi3+0x5e>
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8000162: 034b lsls r3, r1, #13
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8000164: 1ac0 subs r0, r0, r3
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8000166: 4152 adcs r2, r2
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8000168: 0b03 lsrs r3, r0, #12
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800016a: 428b cmp r3, r1
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800016c: d301 bcc.n 8000172 <__udivsi3+0x6a>
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800016e: 030b lsls r3, r1, #12
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8000170: 1ac0 subs r0, r0, r3
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8000172: 4152 adcs r2, r2
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8000174: 0ac3 lsrs r3, r0, #11
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8000176: 428b cmp r3, r1
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8000178: d301 bcc.n 800017e <__udivsi3+0x76>
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800017a: 02cb lsls r3, r1, #11
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800017c: 1ac0 subs r0, r0, r3
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800017e: 4152 adcs r2, r2
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8000180: 0a83 lsrs r3, r0, #10
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8000182: 428b cmp r3, r1
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8000184: d301 bcc.n 800018a <__udivsi3+0x82>
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8000186: 028b lsls r3, r1, #10
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8000188: 1ac0 subs r0, r0, r3
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800018a: 4152 adcs r2, r2
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800018c: 0a43 lsrs r3, r0, #9
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800018e: 428b cmp r3, r1
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8000190: d301 bcc.n 8000196 <__udivsi3+0x8e>
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8000192: 024b lsls r3, r1, #9
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8000194: 1ac0 subs r0, r0, r3
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8000196: 4152 adcs r2, r2
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8000198: 0a03 lsrs r3, r0, #8
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800019a: 428b cmp r3, r1
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800019c: d301 bcc.n 80001a2 <__udivsi3+0x9a>
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800019e: 020b lsls r3, r1, #8
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80001a0: 1ac0 subs r0, r0, r3
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80001a2: 4152 adcs r2, r2
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80001a4: d2cd bcs.n 8000142 <__udivsi3+0x3a>
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80001a6: 09c3 lsrs r3, r0, #7
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80001a8: 428b cmp r3, r1
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80001aa: d301 bcc.n 80001b0 <__udivsi3+0xa8>
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80001ac: 01cb lsls r3, r1, #7
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80001ae: 1ac0 subs r0, r0, r3
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80001b0: 4152 adcs r2, r2
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80001b2: 0983 lsrs r3, r0, #6
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80001b4: 428b cmp r3, r1
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80001b6: d301 bcc.n 80001bc <__udivsi3+0xb4>
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80001b8: 018b lsls r3, r1, #6
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80001ba: 1ac0 subs r0, r0, r3
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80001bc: 4152 adcs r2, r2
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80001be: 0943 lsrs r3, r0, #5
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80001c0: 428b cmp r3, r1
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80001c2: d301 bcc.n 80001c8 <__udivsi3+0xc0>
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80001c4: 014b lsls r3, r1, #5
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80001c6: 1ac0 subs r0, r0, r3
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80001c8: 4152 adcs r2, r2
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80001ca: 0903 lsrs r3, r0, #4
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80001cc: 428b cmp r3, r1
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80001ce: d301 bcc.n 80001d4 <__udivsi3+0xcc>
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80001d0: 010b lsls r3, r1, #4
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80001d2: 1ac0 subs r0, r0, r3
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80001d4: 4152 adcs r2, r2
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80001d6: 08c3 lsrs r3, r0, #3
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80001d8: 428b cmp r3, r1
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80001da: d301 bcc.n 80001e0 <__udivsi3+0xd8>
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80001dc: 00cb lsls r3, r1, #3
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80001de: 1ac0 subs r0, r0, r3
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80001e0: 4152 adcs r2, r2
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80001e2: 0883 lsrs r3, r0, #2
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80001e4: 428b cmp r3, r1
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80001e6: d301 bcc.n 80001ec <__udivsi3+0xe4>
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80001e8: 008b lsls r3, r1, #2
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80001ea: 1ac0 subs r0, r0, r3
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80001ec: 4152 adcs r2, r2
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80001ee: 0843 lsrs r3, r0, #1
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80001f0: 428b cmp r3, r1
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80001f2: d301 bcc.n 80001f8 <__udivsi3+0xf0>
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80001f4: 004b lsls r3, r1, #1
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80001f6: 1ac0 subs r0, r0, r3
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80001f8: 4152 adcs r2, r2
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80001fa: 1a41 subs r1, r0, r1
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80001fc: d200 bcs.n 8000200 <__udivsi3+0xf8>
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80001fe: 4601 mov r1, r0
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8000200: 4152 adcs r2, r2
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8000202: 4610 mov r0, r2
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8000204: 4770 bx lr
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8000206: e7ff b.n 8000208 <__udivsi3+0x100>
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8000208: b501 push {r0, lr}
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800020a: 2000 movs r0, #0
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800020c: f000 f806 bl 800021c <__aeabi_idiv0>
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8000210: bd02 pop {r1, pc}
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8000212: 46c0 nop ; (mov r8, r8)
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08000214 <__aeabi_uidivmod>:
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8000214: 2900 cmp r1, #0
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8000216: d0f7 beq.n 8000208 <__udivsi3+0x100>
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8000218: e776 b.n 8000108 <__udivsi3>
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800021a: 4770 bx lr
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0800021c <__aeabi_idiv0>:
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800021c: 4770 bx lr
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800021e: 46c0 nop ; (mov r8, r8)
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08000220 <__aeabi_uldivmod>:
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8000220: 2b00 cmp r3, #0
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8000222: d111 bne.n 8000248 <__aeabi_uldivmod+0x28>
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8000224: 2a00 cmp r2, #0
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8000226: d10f bne.n 8000248 <__aeabi_uldivmod+0x28>
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8000228: 2900 cmp r1, #0
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800022a: d100 bne.n 800022e <__aeabi_uldivmod+0xe>
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800022c: 2800 cmp r0, #0
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800022e: d002 beq.n 8000236 <__aeabi_uldivmod+0x16>
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8000230: 2100 movs r1, #0
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8000232: 43c9 mvns r1, r1
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8000234: 1c08 adds r0, r1, #0
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8000236: b407 push {r0, r1, r2}
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8000238: 4802 ldr r0, [pc, #8] ; (8000244 <__aeabi_uldivmod+0x24>)
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800023a: a102 add r1, pc, #8 ; (adr r1, 8000244 <__aeabi_uldivmod+0x24>)
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800023c: 1840 adds r0, r0, r1
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800023e: 9002 str r0, [sp, #8]
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8000240: bd03 pop {r0, r1, pc}
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8000242: 46c0 nop ; (mov r8, r8)
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8000244: ffffffd9 .word 0xffffffd9
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8000248: b403 push {r0, r1}
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800024a: 4668 mov r0, sp
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800024c: b501 push {r0, lr}
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800024e: 9802 ldr r0, [sp, #8]
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8000250: f000 f830 bl 80002b4 <__udivmoddi4>
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8000254: 9b01 ldr r3, [sp, #4]
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8000256: 469e mov lr, r3
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8000258: b002 add sp, #8
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800025a: bc0c pop {r2, r3}
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800025c: 4770 bx lr
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800025e: 46c0 nop ; (mov r8, r8)
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08000260 <__aeabi_lmul>:
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8000260: b5f0 push {r4, r5, r6, r7, lr}
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8000262: 46ce mov lr, r9
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8000264: 4647 mov r7, r8
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8000266: 0415 lsls r5, r2, #16
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8000268: 0c2d lsrs r5, r5, #16
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800026a: 002e movs r6, r5
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800026c: b580 push {r7, lr}
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800026e: 0407 lsls r7, r0, #16
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8000270: 0c14 lsrs r4, r2, #16
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8000272: 0c3f lsrs r7, r7, #16
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8000274: 4699 mov r9, r3
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8000276: 0c03 lsrs r3, r0, #16
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8000278: 437e muls r6, r7
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|
800027a: 435d muls r5, r3
|
||
|
|
800027c: 4367 muls r7, r4
|
||
|
|
800027e: 4363 muls r3, r4
|
||
|
|
8000280: 197f adds r7, r7, r5
|
||
|
|
8000282: 0c34 lsrs r4, r6, #16
|
||
|
|
8000284: 19e4 adds r4, r4, r7
|
||
|
|
8000286: 469c mov ip, r3
|
||
|
|
8000288: 42a5 cmp r5, r4
|
||
|
|
800028a: d903 bls.n 8000294 <__aeabi_lmul+0x34>
|
||
|
|
800028c: 2380 movs r3, #128 ; 0x80
|
||
|
|
800028e: 025b lsls r3, r3, #9
|
||
|
|
8000290: 4698 mov r8, r3
|
||
|
|
8000292: 44c4 add ip, r8
|
||
|
|
8000294: 464b mov r3, r9
|
||
|
|
8000296: 4351 muls r1, r2
|
||
|
|
8000298: 4343 muls r3, r0
|
||
|
|
800029a: 0436 lsls r6, r6, #16
|
||
|
|
800029c: 0c36 lsrs r6, r6, #16
|
||
|
|
800029e: 0c25 lsrs r5, r4, #16
|
||
|
|
80002a0: 0424 lsls r4, r4, #16
|
||
|
|
80002a2: 4465 add r5, ip
|
||
|
|
80002a4: 19a4 adds r4, r4, r6
|
||
|
|
80002a6: 1859 adds r1, r3, r1
|
||
|
|
80002a8: 1949 adds r1, r1, r5
|
||
|
|
80002aa: 0020 movs r0, r4
|
||
|
|
80002ac: bc0c pop {r2, r3}
|
||
|
|
80002ae: 4690 mov r8, r2
|
||
|
|
80002b0: 4699 mov r9, r3
|
||
|
|
80002b2: bdf0 pop {r4, r5, r6, r7, pc}
|
||
|
|
|
||
|
|
080002b4 <__udivmoddi4>:
|
||
|
|
80002b4: b5f0 push {r4, r5, r6, r7, lr}
|
||
|
|
80002b6: 4657 mov r7, sl
|
||
|
|
80002b8: 464e mov r6, r9
|
||
|
|
80002ba: 4645 mov r5, r8
|
||
|
|
80002bc: 46de mov lr, fp
|
||
|
|
80002be: b5e0 push {r5, r6, r7, lr}
|
||
|
|
80002c0: 0004 movs r4, r0
|
||
|
|
80002c2: b083 sub sp, #12
|
||
|
|
80002c4: 000d movs r5, r1
|
||
|
|
80002c6: 4692 mov sl, r2
|
||
|
|
80002c8: 4699 mov r9, r3
|
||
|
|
80002ca: 428b cmp r3, r1
|
||
|
|
80002cc: d82f bhi.n 800032e <__udivmoddi4+0x7a>
|
||
|
|
80002ce: d02c beq.n 800032a <__udivmoddi4+0x76>
|
||
|
|
80002d0: 4649 mov r1, r9
|
||
|
|
80002d2: 4650 mov r0, sl
|
||
|
|
80002d4: f000 f8ae bl 8000434 <__clzdi2>
|
||
|
|
80002d8: 0029 movs r1, r5
|
||
|
|
80002da: 0006 movs r6, r0
|
||
|
|
80002dc: 0020 movs r0, r4
|
||
|
|
80002de: f000 f8a9 bl 8000434 <__clzdi2>
|
||
|
|
80002e2: 1a33 subs r3, r6, r0
|
||
|
|
80002e4: 4698 mov r8, r3
|
||
|
|
80002e6: 3b20 subs r3, #32
|
||
|
|
80002e8: 469b mov fp, r3
|
||
|
|
80002ea: d500 bpl.n 80002ee <__udivmoddi4+0x3a>
|
||
|
|
80002ec: e074 b.n 80003d8 <__udivmoddi4+0x124>
|
||
|
|
80002ee: 4653 mov r3, sl
|
||
|
|
80002f0: 465a mov r2, fp
|
||
|
|
80002f2: 4093 lsls r3, r2
|
||
|
|
80002f4: 001f movs r7, r3
|
||
|
|
80002f6: 4653 mov r3, sl
|
||
|
|
80002f8: 4642 mov r2, r8
|
||
|
|
80002fa: 4093 lsls r3, r2
|
||
|
|
80002fc: 001e movs r6, r3
|
||
|
|
80002fe: 42af cmp r7, r5
|
||
|
|
8000300: d829 bhi.n 8000356 <__udivmoddi4+0xa2>
|
||
|
|
8000302: d026 beq.n 8000352 <__udivmoddi4+0x9e>
|
||
|
|
8000304: 465b mov r3, fp
|
||
|
|
8000306: 1ba4 subs r4, r4, r6
|
||
|
|
8000308: 41bd sbcs r5, r7
|
||
|
|
800030a: 2b00 cmp r3, #0
|
||
|
|
800030c: da00 bge.n 8000310 <__udivmoddi4+0x5c>
|
||
|
|
800030e: e079 b.n 8000404 <__udivmoddi4+0x150>
|
||
|
|
8000310: 2200 movs r2, #0
|
||
|
|
8000312: 2300 movs r3, #0
|
||
|
|
8000314: 9200 str r2, [sp, #0]
|
||
|
|
8000316: 9301 str r3, [sp, #4]
|
||
|
|
8000318: 2301 movs r3, #1
|
||
|
|
800031a: 465a mov r2, fp
|
||
|
|
800031c: 4093 lsls r3, r2
|
||
|
|
800031e: 9301 str r3, [sp, #4]
|
||
|
|
8000320: 2301 movs r3, #1
|
||
|
|
8000322: 4642 mov r2, r8
|
||
|
|
8000324: 4093 lsls r3, r2
|
||
|
|
8000326: 9300 str r3, [sp, #0]
|
||
|
|
8000328: e019 b.n 800035e <__udivmoddi4+0xaa>
|
||
|
|
800032a: 4282 cmp r2, r0
|
||
|
|
800032c: d9d0 bls.n 80002d0 <__udivmoddi4+0x1c>
|
||
|
|
800032e: 2200 movs r2, #0
|
||
|
|
8000330: 2300 movs r3, #0
|
||
|
|
8000332: 9200 str r2, [sp, #0]
|
||
|
|
8000334: 9301 str r3, [sp, #4]
|
||
|
|
8000336: 9b0c ldr r3, [sp, #48] ; 0x30
|
||
|
|
8000338: 2b00 cmp r3, #0
|
||
|
|
800033a: d001 beq.n 8000340 <__udivmoddi4+0x8c>
|
||
|
|
800033c: 601c str r4, [r3, #0]
|
||
|
|
800033e: 605d str r5, [r3, #4]
|
||
|
|
8000340: 9800 ldr r0, [sp, #0]
|
||
|
|
8000342: 9901 ldr r1, [sp, #4]
|
||
|
|
8000344: b003 add sp, #12
|
||
|
|
8000346: bc3c pop {r2, r3, r4, r5}
|
||
|
|
8000348: 4690 mov r8, r2
|
||
|
|
800034a: 4699 mov r9, r3
|
||
|
|
800034c: 46a2 mov sl, r4
|
||
|
|
800034e: 46ab mov fp, r5
|
||
|
|
8000350: bdf0 pop {r4, r5, r6, r7, pc}
|
||
|
|
8000352: 42a3 cmp r3, r4
|
||
|
|
8000354: d9d6 bls.n 8000304 <__udivmoddi4+0x50>
|
||
|
|
8000356: 2200 movs r2, #0
|
||
|
|
8000358: 2300 movs r3, #0
|
||
|
|
800035a: 9200 str r2, [sp, #0]
|
||
|
|
800035c: 9301 str r3, [sp, #4]
|
||
|
|
800035e: 4643 mov r3, r8
|
||
|
|
8000360: 2b00 cmp r3, #0
|
||
|
|
8000362: d0e8 beq.n 8000336 <__udivmoddi4+0x82>
|
||
|
|
8000364: 07fb lsls r3, r7, #31
|
||
|
|
8000366: 0872 lsrs r2, r6, #1
|
||
|
|
8000368: 431a orrs r2, r3
|
||
|
|
800036a: 4646 mov r6, r8
|
||
|
|
800036c: 087b lsrs r3, r7, #1
|
||
|
|
800036e: e00e b.n 800038e <__udivmoddi4+0xda>
|
||
|
|
8000370: 42ab cmp r3, r5
|
||
|
|
8000372: d101 bne.n 8000378 <__udivmoddi4+0xc4>
|
||
|
|
8000374: 42a2 cmp r2, r4
|
||
|
|
8000376: d80c bhi.n 8000392 <__udivmoddi4+0xde>
|
||
|
|
8000378: 1aa4 subs r4, r4, r2
|
||
|
|
800037a: 419d sbcs r5, r3
|
||
|
|
800037c: 2001 movs r0, #1
|
||
|
|
800037e: 1924 adds r4, r4, r4
|
||
|
|
8000380: 416d adcs r5, r5
|
||
|
|
8000382: 2100 movs r1, #0
|
||
|
|
8000384: 3e01 subs r6, #1
|
||
|
|
8000386: 1824 adds r4, r4, r0
|
||
|
|
8000388: 414d adcs r5, r1
|
||
|
|
800038a: 2e00 cmp r6, #0
|
||
|
|
800038c: d006 beq.n 800039c <__udivmoddi4+0xe8>
|
||
|
|
800038e: 42ab cmp r3, r5
|
||
|
|
8000390: d9ee bls.n 8000370 <__udivmoddi4+0xbc>
|
||
|
|
8000392: 3e01 subs r6, #1
|
||
|
|
8000394: 1924 adds r4, r4, r4
|
||
|
|
8000396: 416d adcs r5, r5
|
||
|
|
8000398: 2e00 cmp r6, #0
|
||
|
|
800039a: d1f8 bne.n 800038e <__udivmoddi4+0xda>
|
||
|
|
800039c: 465b mov r3, fp
|
||
|
|
800039e: 9800 ldr r0, [sp, #0]
|
||
|
|
80003a0: 9901 ldr r1, [sp, #4]
|
||
|
|
80003a2: 1900 adds r0, r0, r4
|
||
|
|
80003a4: 4169 adcs r1, r5
|
||
|
|
80003a6: 2b00 cmp r3, #0
|
||
|
|
80003a8: db22 blt.n 80003f0 <__udivmoddi4+0x13c>
|
||
|
|
80003aa: 002b movs r3, r5
|
||
|
|
80003ac: 465a mov r2, fp
|
||
|
|
80003ae: 40d3 lsrs r3, r2
|
||
|
|
80003b0: 002a movs r2, r5
|
||
|
|
80003b2: 4644 mov r4, r8
|
||
|
|
80003b4: 40e2 lsrs r2, r4
|
||
|
|
80003b6: 001c movs r4, r3
|
||
|
|
80003b8: 465b mov r3, fp
|
||
|
|
80003ba: 0015 movs r5, r2
|
||
|
|
80003bc: 2b00 cmp r3, #0
|
||
|
|
80003be: db2c blt.n 800041a <__udivmoddi4+0x166>
|
||
|
|
80003c0: 0026 movs r6, r4
|
||
|
|
80003c2: 409e lsls r6, r3
|
||
|
|
80003c4: 0033 movs r3, r6
|
||
|
|
80003c6: 0026 movs r6, r4
|
||
|
|
80003c8: 4647 mov r7, r8
|
||
|
|
80003ca: 40be lsls r6, r7
|
||
|
|
80003cc: 0032 movs r2, r6
|
||
|
|
80003ce: 1a80 subs r0, r0, r2
|
||
|
|
80003d0: 4199 sbcs r1, r3
|
||
|
|
80003d2: 9000 str r0, [sp, #0]
|
||
|
|
80003d4: 9101 str r1, [sp, #4]
|
||
|
|
80003d6: e7ae b.n 8000336 <__udivmoddi4+0x82>
|
||
|
|
80003d8: 4642 mov r2, r8
|
||
|
|
80003da: 2320 movs r3, #32
|
||
|
|
80003dc: 1a9b subs r3, r3, r2
|
||
|
|
80003de: 4652 mov r2, sl
|
||
|
|
80003e0: 40da lsrs r2, r3
|
||
|
|
80003e2: 4641 mov r1, r8
|
||
|
|
80003e4: 0013 movs r3, r2
|
||
|
|
80003e6: 464a mov r2, r9
|
||
|
|
80003e8: 408a lsls r2, r1
|
||
|
|
80003ea: 0017 movs r7, r2
|
||
|
|
80003ec: 431f orrs r7, r3
|
||
|
|
80003ee: e782 b.n 80002f6 <__udivmoddi4+0x42>
|
||
|
|
80003f0: 4642 mov r2, r8
|
||
|
|
80003f2: 2320 movs r3, #32
|
||
|
|
80003f4: 1a9b subs r3, r3, r2
|
||
|
|
80003f6: 002a movs r2, r5
|
||
|
|
80003f8: 4646 mov r6, r8
|
||
|
|
80003fa: 409a lsls r2, r3
|
||
|
|
80003fc: 0023 movs r3, r4
|
||
|
|
80003fe: 40f3 lsrs r3, r6
|
||
|
|
8000400: 4313 orrs r3, r2
|
||
|
|
8000402: e7d5 b.n 80003b0 <__udivmoddi4+0xfc>
|
||
|
|
8000404: 4642 mov r2, r8
|
||
|
|
8000406: 2320 movs r3, #32
|
||
|
|
8000408: 2100 movs r1, #0
|
||
|
|
800040a: 1a9b subs r3, r3, r2
|
||
|
|
800040c: 2200 movs r2, #0
|
||
|
|
800040e: 9100 str r1, [sp, #0]
|
||
|
|
8000410: 9201 str r2, [sp, #4]
|
||
|
|
8000412: 2201 movs r2, #1
|
||
|
|
8000414: 40da lsrs r2, r3
|
||
|
|
8000416: 9201 str r2, [sp, #4]
|
||
|
|
8000418: e782 b.n 8000320 <__udivmoddi4+0x6c>
|
||
|
|
800041a: 4642 mov r2, r8
|
||
|
|
800041c: 2320 movs r3, #32
|
||
|
|
800041e: 0026 movs r6, r4
|
||
|
|
8000420: 1a9b subs r3, r3, r2
|
||
|
|
8000422: 40de lsrs r6, r3
|
||
|
|
8000424: 002f movs r7, r5
|
||
|
|
8000426: 46b4 mov ip, r6
|
||
|
|
8000428: 4097 lsls r7, r2
|
||
|
|
800042a: 4666 mov r6, ip
|
||
|
|
800042c: 003b movs r3, r7
|
||
|
|
800042e: 4333 orrs r3, r6
|
||
|
|
8000430: e7c9 b.n 80003c6 <__udivmoddi4+0x112>
|
||
|
|
8000432: 46c0 nop ; (mov r8, r8)
|
||
|
|
|
||
|
|
08000434 <__clzdi2>:
|
||
|
|
8000434: b510 push {r4, lr}
|
||
|
|
8000436: 2900 cmp r1, #0
|
||
|
|
8000438: d103 bne.n 8000442 <__clzdi2+0xe>
|
||
|
|
800043a: f000 f807 bl 800044c <__clzsi2>
|
||
|
|
800043e: 3020 adds r0, #32
|
||
|
|
8000440: e002 b.n 8000448 <__clzdi2+0x14>
|
||
|
|
8000442: 1c08 adds r0, r1, #0
|
||
|
|
8000444: f000 f802 bl 800044c <__clzsi2>
|
||
|
|
8000448: bd10 pop {r4, pc}
|
||
|
|
800044a: 46c0 nop ; (mov r8, r8)
|
||
|
|
|
||
|
|
0800044c <__clzsi2>:
|
||
|
|
800044c: 211c movs r1, #28
|
||
|
|
800044e: 2301 movs r3, #1
|
||
|
|
8000450: 041b lsls r3, r3, #16
|
||
|
|
8000452: 4298 cmp r0, r3
|
||
|
|
8000454: d301 bcc.n 800045a <__clzsi2+0xe>
|
||
|
|
8000456: 0c00 lsrs r0, r0, #16
|
||
|
|
8000458: 3910 subs r1, #16
|
||
|
|
800045a: 0a1b lsrs r3, r3, #8
|
||
|
|
800045c: 4298 cmp r0, r3
|
||
|
|
800045e: d301 bcc.n 8000464 <__clzsi2+0x18>
|
||
|
|
8000460: 0a00 lsrs r0, r0, #8
|
||
|
|
8000462: 3908 subs r1, #8
|
||
|
|
8000464: 091b lsrs r3, r3, #4
|
||
|
|
8000466: 4298 cmp r0, r3
|
||
|
|
8000468: d301 bcc.n 800046e <__clzsi2+0x22>
|
||
|
|
800046a: 0900 lsrs r0, r0, #4
|
||
|
|
800046c: 3904 subs r1, #4
|
||
|
|
800046e: a202 add r2, pc, #8 ; (adr r2, 8000478 <__clzsi2+0x2c>)
|
||
|
|
8000470: 5c10 ldrb r0, [r2, r0]
|
||
|
|
8000472: 1840 adds r0, r0, r1
|
||
|
|
8000474: 4770 bx lr
|
||
|
|
8000476: 46c0 nop ; (mov r8, r8)
|
||
|
|
8000478: 02020304 .word 0x02020304
|
||
|
|
800047c: 01010101 .word 0x01010101
|
||
|
|
...
|
||
|
|
|
||
|
|
08000488 <MX_GPIO_Init>:
|
||
|
|
* Output
|
||
|
|
* EVENT_OUT
|
||
|
|
* EXTI
|
||
|
|
*/
|
||
|
|
void MX_GPIO_Init(void)
|
||
|
|
{
|
||
|
|
8000488: b580 push {r7, lr}
|
||
|
|
800048a: b088 sub sp, #32
|
||
|
|
800048c: af00 add r7, sp, #0
|
||
|
|
|
||
|
|
GPIO_InitTypeDef GPIO_InitStruct = {0};
|
||
|
|
800048e: 230c movs r3, #12
|
||
|
|
8000490: 18fb adds r3, r7, r3
|
||
|
|
8000492: 0018 movs r0, r3
|
||
|
|
8000494: 2314 movs r3, #20
|
||
|
|
8000496: 001a movs r2, r3
|
||
|
|
8000498: 2100 movs r1, #0
|
||
|
|
800049a: f002 fc65 bl 8002d68 <memset>
|
||
|
|
|
||
|
|
/* GPIO Ports Clock Enable */
|
||
|
|
__HAL_RCC_GPIOA_CLK_ENABLE();
|
||
|
|
800049e: 4b5a ldr r3, [pc, #360] ; (8000608 <MX_GPIO_Init+0x180>)
|
||
|
|
80004a0: 4a59 ldr r2, [pc, #356] ; (8000608 <MX_GPIO_Init+0x180>)
|
||
|
|
80004a2: 6ad2 ldr r2, [r2, #44] ; 0x2c
|
||
|
|
80004a4: 2101 movs r1, #1
|
||
|
|
80004a6: 430a orrs r2, r1
|
||
|
|
80004a8: 62da str r2, [r3, #44] ; 0x2c
|
||
|
|
80004aa: 4b57 ldr r3, [pc, #348] ; (8000608 <MX_GPIO_Init+0x180>)
|
||
|
|
80004ac: 6adb ldr r3, [r3, #44] ; 0x2c
|
||
|
|
80004ae: 2201 movs r2, #1
|
||
|
|
80004b0: 4013 ands r3, r2
|
||
|
|
80004b2: 60bb str r3, [r7, #8]
|
||
|
|
80004b4: 68bb ldr r3, [r7, #8]
|
||
|
|
__HAL_RCC_GPIOB_CLK_ENABLE();
|
||
|
|
80004b6: 4b54 ldr r3, [pc, #336] ; (8000608 <MX_GPIO_Init+0x180>)
|
||
|
|
80004b8: 4a53 ldr r2, [pc, #332] ; (8000608 <MX_GPIO_Init+0x180>)
|
||
|
|
80004ba: 6ad2 ldr r2, [r2, #44] ; 0x2c
|
||
|
|
80004bc: 2102 movs r1, #2
|
||
|
|
80004be: 430a orrs r2, r1
|
||
|
|
80004c0: 62da str r2, [r3, #44] ; 0x2c
|
||
|
|
80004c2: 4b51 ldr r3, [pc, #324] ; (8000608 <MX_GPIO_Init+0x180>)
|
||
|
|
80004c4: 6adb ldr r3, [r3, #44] ; 0x2c
|
||
|
|
80004c6: 2202 movs r2, #2
|
||
|
|
80004c8: 4013 ands r3, r2
|
||
|
|
80004ca: 607b str r3, [r7, #4]
|
||
|
|
80004cc: 687b ldr r3, [r7, #4]
|
||
|
|
|
||
|
|
/*Configure GPIO pin Output Level */
|
||
|
|
HAL_GPIO_WritePin(GPIOA, PER_Pin|RE_Pin, GPIO_PIN_RESET);
|
||
|
|
80004ce: 2388 movs r3, #136 ; 0x88
|
||
|
|
80004d0: 0059 lsls r1, r3, #1
|
||
|
|
80004d2: 23a0 movs r3, #160 ; 0xa0
|
||
|
|
80004d4: 05db lsls r3, r3, #23
|
||
|
|
80004d6: 2200 movs r2, #0
|
||
|
|
80004d8: 0018 movs r0, r3
|
||
|
|
80004da: f000 fd53 bl 8000f84 <HAL_GPIO_WritePin>
|
||
|
|
|
||
|
|
/*Configure GPIO pin Output Level */
|
||
|
|
HAL_GPIO_WritePin(GPIOB, A0_Pin|A1_Pin|A2_Pin|A10_Pin
|
||
|
|
80004de: 494b ldr r1, [pc, #300] ; (800060c <MX_GPIO_Init+0x184>)
|
||
|
|
80004e0: 4b4b ldr r3, [pc, #300] ; (8000610 <MX_GPIO_Init+0x188>)
|
||
|
|
80004e2: 2200 movs r2, #0
|
||
|
|
80004e4: 0018 movs r0, r3
|
||
|
|
80004e6: f000 fd4d bl 8000f84 <HAL_GPIO_WritePin>
|
||
|
|
|A11_Pin|A12_Pin|A3_Pin|A4_Pin
|
||
|
|
|A5_Pin|A6_Pin|A7_Pin|A8_Pin
|
||
|
|
|A9_Pin, GPIO_PIN_RESET);
|
||
|
|
|
||
|
|
/*Configure GPIO pin Output Level */
|
||
|
|
HAL_GPIO_WritePin(GPIOB, FL_Pin|STD_Pin|SCK_Pin, GPIO_PIN_SET);
|
||
|
|
80004ea: 23e0 movs r3, #224 ; 0xe0
|
||
|
|
80004ec: 021b lsls r3, r3, #8
|
||
|
|
80004ee: 4848 ldr r0, [pc, #288] ; (8000610 <MX_GPIO_Init+0x188>)
|
||
|
|
80004f0: 2201 movs r2, #1
|
||
|
|
80004f2: 0019 movs r1, r3
|
||
|
|
80004f4: f000 fd46 bl 8000f84 <HAL_GPIO_WritePin>
|
||
|
|
|
||
|
|
/*Configure GPIO pins : PAPin PAPin PAPin */
|
||
|
|
GPIO_InitStruct.Pin = UPER_Pin|OP_Pin|KZ_Pin;
|
||
|
|
80004f8: 230c movs r3, #12
|
||
|
|
80004fa: 18fb adds r3, r7, r3
|
||
|
|
80004fc: 2207 movs r2, #7
|
||
|
|
80004fe: 601a str r2, [r3, #0]
|
||
|
|
GPIO_InitStruct.Mode = GPIO_MODE_IT_RISING;
|
||
|
|
8000500: 230c movs r3, #12
|
||
|
|
8000502: 18fb adds r3, r7, r3
|
||
|
|
8000504: 4a43 ldr r2, [pc, #268] ; (8000614 <MX_GPIO_Init+0x18c>)
|
||
|
|
8000506: 605a str r2, [r3, #4]
|
||
|
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
||
|
|
8000508: 230c movs r3, #12
|
||
|
|
800050a: 18fb adds r3, r7, r3
|
||
|
|
800050c: 2200 movs r2, #0
|
||
|
|
800050e: 609a str r2, [r3, #8]
|
||
|
|
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
|
||
|
|
8000510: 230c movs r3, #12
|
||
|
|
8000512: 18fa adds r2, r7, r3
|
||
|
|
8000514: 23a0 movs r3, #160 ; 0xa0
|
||
|
|
8000516: 05db lsls r3, r3, #23
|
||
|
|
8000518: 0011 movs r1, r2
|
||
|
|
800051a: 0018 movs r0, r3
|
||
|
|
800051c: f000 fbb4 bl 8000c88 <HAL_GPIO_Init>
|
||
|
|
|
||
|
|
/*Configure GPIO pin : PtPin */
|
||
|
|
GPIO_InitStruct.Pin = PER_Pin;
|
||
|
|
8000520: 230c movs r3, #12
|
||
|
|
8000522: 18fb adds r3, r7, r3
|
||
|
|
8000524: 2210 movs r2, #16
|
||
|
|
8000526: 601a str r2, [r3, #0]
|
||
|
|
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
|
||
|
|
8000528: 230c movs r3, #12
|
||
|
|
800052a: 18fb adds r3, r7, r3
|
||
|
|
800052c: 2201 movs r2, #1
|
||
|
|
800052e: 605a str r2, [r3, #4]
|
||
|
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
||
|
|
8000530: 230c movs r3, #12
|
||
|
|
8000532: 18fb adds r3, r7, r3
|
||
|
|
8000534: 2200 movs r2, #0
|
||
|
|
8000536: 609a str r2, [r3, #8]
|
||
|
|
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
|
||
|
|
8000538: 230c movs r3, #12
|
||
|
|
800053a: 18fb adds r3, r7, r3
|
||
|
|
800053c: 2202 movs r2, #2
|
||
|
|
800053e: 60da str r2, [r3, #12]
|
||
|
|
HAL_GPIO_Init(PER_GPIO_Port, &GPIO_InitStruct);
|
||
|
|
8000540: 230c movs r3, #12
|
||
|
|
8000542: 18fa adds r2, r7, r3
|
||
|
|
8000544: 23a0 movs r3, #160 ; 0xa0
|
||
|
|
8000546: 05db lsls r3, r3, #23
|
||
|
|
8000548: 0011 movs r1, r2
|
||
|
|
800054a: 0018 movs r0, r3
|
||
|
|
800054c: f000 fb9c bl 8000c88 <HAL_GPIO_Init>
|
||
|
|
|
||
|
|
/*Configure GPIO pins : PBPin PBPin PBPin PBPin
|
||
|
|
PBPin PBPin PBPin PBPin
|
||
|
|
PBPin PBPin PBPin PBPin
|
||
|
|
PBPin */
|
||
|
|
GPIO_InitStruct.Pin = A0_Pin|A1_Pin|A2_Pin|A10_Pin
|
||
|
|
8000550: 230c movs r3, #12
|
||
|
|
8000552: 18fb adds r3, r7, r3
|
||
|
|
8000554: 4a2d ldr r2, [pc, #180] ; (800060c <MX_GPIO_Init+0x184>)
|
||
|
|
8000556: 601a str r2, [r3, #0]
|
||
|
|
|A11_Pin|A12_Pin|A3_Pin|A4_Pin
|
||
|
|
|A5_Pin|A6_Pin|A7_Pin|A8_Pin
|
||
|
|
|A9_Pin;
|
||
|
|
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
|
||
|
|
8000558: 230c movs r3, #12
|
||
|
|
800055a: 18fb adds r3, r7, r3
|
||
|
|
800055c: 2201 movs r2, #1
|
||
|
|
800055e: 605a str r2, [r3, #4]
|
||
|
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
||
|
|
8000560: 230c movs r3, #12
|
||
|
|
8000562: 18fb adds r3, r7, r3
|
||
|
|
8000564: 2200 movs r2, #0
|
||
|
|
8000566: 609a str r2, [r3, #8]
|
||
|
|
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
|
||
|
|
8000568: 230c movs r3, #12
|
||
|
|
800056a: 18fb adds r3, r7, r3
|
||
|
|
800056c: 2200 movs r2, #0
|
||
|
|
800056e: 60da str r2, [r3, #12]
|
||
|
|
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
|
||
|
|
8000570: 230c movs r3, #12
|
||
|
|
8000572: 18fb adds r3, r7, r3
|
||
|
|
8000574: 4a26 ldr r2, [pc, #152] ; (8000610 <MX_GPIO_Init+0x188>)
|
||
|
|
8000576: 0019 movs r1, r3
|
||
|
|
8000578: 0010 movs r0, r2
|
||
|
|
800057a: f000 fb85 bl 8000c88 <HAL_GPIO_Init>
|
||
|
|
|
||
|
|
/*Configure GPIO pins : PBPin PBPin PBPin */
|
||
|
|
GPIO_InitStruct.Pin = FL_Pin|STD_Pin|SCK_Pin;
|
||
|
|
800057e: 230c movs r3, #12
|
||
|
|
8000580: 18fb adds r3, r7, r3
|
||
|
|
8000582: 22e0 movs r2, #224 ; 0xe0
|
||
|
|
8000584: 0212 lsls r2, r2, #8
|
||
|
|
8000586: 601a str r2, [r3, #0]
|
||
|
|
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
|
||
|
|
8000588: 230c movs r3, #12
|
||
|
|
800058a: 18fb adds r3, r7, r3
|
||
|
|
800058c: 2201 movs r2, #1
|
||
|
|
800058e: 605a str r2, [r3, #4]
|
||
|
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
||
|
|
8000590: 230c movs r3, #12
|
||
|
|
8000592: 18fb adds r3, r7, r3
|
||
|
|
8000594: 2200 movs r2, #0
|
||
|
|
8000596: 609a str r2, [r3, #8]
|
||
|
|
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
|
||
|
|
8000598: 230c movs r3, #12
|
||
|
|
800059a: 18fb adds r3, r7, r3
|
||
|
|
800059c: 2203 movs r2, #3
|
||
|
|
800059e: 60da str r2, [r3, #12]
|
||
|
|
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
|
||
|
|
80005a0: 230c movs r3, #12
|
||
|
|
80005a2: 18fb adds r3, r7, r3
|
||
|
|
80005a4: 4a1a ldr r2, [pc, #104] ; (8000610 <MX_GPIO_Init+0x188>)
|
||
|
|
80005a6: 0019 movs r1, r3
|
||
|
|
80005a8: 0010 movs r0, r2
|
||
|
|
80005aa: f000 fb6d bl 8000c88 <HAL_GPIO_Init>
|
||
|
|
|
||
|
|
/*Configure GPIO pin : PtPin */
|
||
|
|
GPIO_InitStruct.Pin = RE_Pin;
|
||
|
|
80005ae: 230c movs r3, #12
|
||
|
|
80005b0: 18fb adds r3, r7, r3
|
||
|
|
80005b2: 2280 movs r2, #128 ; 0x80
|
||
|
|
80005b4: 0052 lsls r2, r2, #1
|
||
|
|
80005b6: 601a str r2, [r3, #0]
|
||
|
|
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
|
||
|
|
80005b8: 230c movs r3, #12
|
||
|
|
80005ba: 18fb adds r3, r7, r3
|
||
|
|
80005bc: 2201 movs r2, #1
|
||
|
|
80005be: 605a str r2, [r3, #4]
|
||
|
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
||
|
|
80005c0: 230c movs r3, #12
|
||
|
|
80005c2: 18fb adds r3, r7, r3
|
||
|
|
80005c4: 2200 movs r2, #0
|
||
|
|
80005c6: 609a str r2, [r3, #8]
|
||
|
|
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
|
||
|
|
80005c8: 230c movs r3, #12
|
||
|
|
80005ca: 18fb adds r3, r7, r3
|
||
|
|
80005cc: 2203 movs r2, #3
|
||
|
|
80005ce: 60da str r2, [r3, #12]
|
||
|
|
HAL_GPIO_Init(RE_GPIO_Port, &GPIO_InitStruct);
|
||
|
|
80005d0: 230c movs r3, #12
|
||
|
|
80005d2: 18fa adds r2, r7, r3
|
||
|
|
80005d4: 23a0 movs r3, #160 ; 0xa0
|
||
|
|
80005d6: 05db lsls r3, r3, #23
|
||
|
|
80005d8: 0011 movs r1, r2
|
||
|
|
80005da: 0018 movs r0, r3
|
||
|
|
80005dc: f000 fb54 bl 8000c88 <HAL_GPIO_Init>
|
||
|
|
|
||
|
|
/* EXTI interrupt init*/
|
||
|
|
HAL_NVIC_SetPriority(EXTI0_1_IRQn, 1, 0);
|
||
|
|
80005e0: 2200 movs r2, #0
|
||
|
|
80005e2: 2101 movs r1, #1
|
||
|
|
80005e4: 2005 movs r0, #5
|
||
|
|
80005e6: f000 fa93 bl 8000b10 <HAL_NVIC_SetPriority>
|
||
|
|
HAL_NVIC_EnableIRQ(EXTI0_1_IRQn);
|
||
|
|
80005ea: 2005 movs r0, #5
|
||
|
|
80005ec: f000 faa6 bl 8000b3c <HAL_NVIC_EnableIRQ>
|
||
|
|
|
||
|
|
HAL_NVIC_SetPriority(EXTI2_3_IRQn, 1, 0);
|
||
|
|
80005f0: 2200 movs r2, #0
|
||
|
|
80005f2: 2101 movs r1, #1
|
||
|
|
80005f4: 2006 movs r0, #6
|
||
|
|
80005f6: f000 fa8b bl 8000b10 <HAL_NVIC_SetPriority>
|
||
|
|
HAL_NVIC_EnableIRQ(EXTI2_3_IRQn);
|
||
|
|
80005fa: 2006 movs r0, #6
|
||
|
|
80005fc: f000 fa9e bl 8000b3c <HAL_NVIC_EnableIRQ>
|
||
|
|
|
||
|
|
}
|
||
|
|
8000600: 46c0 nop ; (mov r8, r8)
|
||
|
|
8000602: 46bd mov sp, r7
|
||
|
|
8000604: b008 add sp, #32
|
||
|
|
8000606: bd80 pop {r7, pc}
|
||
|
|
8000608: 40021000 .word 0x40021000
|
||
|
|
800060c: 00001fff .word 0x00001fff
|
||
|
|
8000610: 50000400 .word 0x50000400
|
||
|
|
8000614: 10110000 .word 0x10110000
|
||
|
|
|
||
|
|
08000618 <main>:
|
||
|
|
/**
|
||
|
|
* @brief The application entry point.
|
||
|
|
* @retval int
|
||
|
|
*/
|
||
|
|
int main(void)
|
||
|
|
{
|
||
|
|
8000618: b580 push {r7, lr}
|
||
|
|
800061a: af00 add r7, sp, #0
|
||
|
|
HAL_Init();
|
||
|
|
800061c: f000 f95c bl 80008d8 <HAL_Init>
|
||
|
|
|
||
|
|
SystemClock_Config();
|
||
|
|
8000620: f000 f806 bl 8000630 <SystemClock_Config>
|
||
|
|
|
||
|
|
MX_GPIO_Init();
|
||
|
|
8000624: f7ff ff30 bl 8000488 <MX_GPIO_Init>
|
||
|
|
MX_USART1_UART_Init();
|
||
|
|
8000628: f000 f8d4 bl 80007d4 <MX_USART1_UART_Init>
|
||
|
|
|
||
|
|
while (1)
|
||
|
|
800062c: e7fe b.n 800062c <main+0x14>
|
||
|
|
...
|
||
|
|
|
||
|
|
08000630 <SystemClock_Config>:
|
||
|
|
/**
|
||
|
|
* @brief System Clock Configuration
|
||
|
|
* @retval None
|
||
|
|
*/
|
||
|
|
void SystemClock_Config(void)
|
||
|
|
{
|
||
|
|
8000630: b580 push {r7, lr}
|
||
|
|
8000632: b09c sub sp, #112 ; 0x70
|
||
|
|
8000634: af00 add r7, sp, #0
|
||
|
|
RCC_OscInitTypeDef RCC_OscInitStruct = {0};
|
||
|
|
8000636: 2338 movs r3, #56 ; 0x38
|
||
|
|
8000638: 18fb adds r3, r7, r3
|
||
|
|
800063a: 0018 movs r0, r3
|
||
|
|
800063c: 2338 movs r3, #56 ; 0x38
|
||
|
|
800063e: 001a movs r2, r3
|
||
|
|
8000640: 2100 movs r1, #0
|
||
|
|
8000642: f002 fb91 bl 8002d68 <memset>
|
||
|
|
RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
|
||
|
|
8000646: 2324 movs r3, #36 ; 0x24
|
||
|
|
8000648: 18fb adds r3, r7, r3
|
||
|
|
800064a: 0018 movs r0, r3
|
||
|
|
800064c: 2314 movs r3, #20
|
||
|
|
800064e: 001a movs r2, r3
|
||
|
|
8000650: 2100 movs r1, #0
|
||
|
|
8000652: f002 fb89 bl 8002d68 <memset>
|
||
|
|
RCC_PeriphCLKInitTypeDef PeriphClkInit = {0};
|
||
|
|
8000656: 003b movs r3, r7
|
||
|
|
8000658: 0018 movs r0, r3
|
||
|
|
800065a: 2324 movs r3, #36 ; 0x24
|
||
|
|
800065c: 001a movs r2, r3
|
||
|
|
800065e: 2100 movs r1, #0
|
||
|
|
8000660: f002 fb82 bl 8002d68 <memset>
|
||
|
|
|
||
|
|
/** Configure the main internal regulator output voltage
|
||
|
|
*/
|
||
|
|
__HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
|
||
|
|
8000664: 4b2f ldr r3, [pc, #188] ; (8000724 <SystemClock_Config+0xf4>)
|
||
|
|
8000666: 4a2f ldr r2, [pc, #188] ; (8000724 <SystemClock_Config+0xf4>)
|
||
|
|
8000668: 6812 ldr r2, [r2, #0]
|
||
|
|
800066a: 492f ldr r1, [pc, #188] ; (8000728 <SystemClock_Config+0xf8>)
|
||
|
|
800066c: 400a ands r2, r1
|
||
|
|
800066e: 2180 movs r1, #128 ; 0x80
|
||
|
|
8000670: 0109 lsls r1, r1, #4
|
||
|
|
8000672: 430a orrs r2, r1
|
||
|
|
8000674: 601a str r2, [r3, #0]
|
||
|
|
/** Initializes the RCC Oscillators according to the specified parameters
|
||
|
|
* in the RCC_OscInitTypeDef structure.
|
||
|
|
*/
|
||
|
|
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;
|
||
|
|
8000676: 2338 movs r3, #56 ; 0x38
|
||
|
|
8000678: 18fb adds r3, r7, r3
|
||
|
|
800067a: 2202 movs r2, #2
|
||
|
|
800067c: 601a str r2, [r3, #0]
|
||
|
|
RCC_OscInitStruct.HSIState = RCC_HSI_ON;
|
||
|
|
800067e: 2338 movs r3, #56 ; 0x38
|
||
|
|
8000680: 18fb adds r3, r7, r3
|
||
|
|
8000682: 2201 movs r2, #1
|
||
|
|
8000684: 60da str r2, [r3, #12]
|
||
|
|
RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
|
||
|
|
8000686: 2338 movs r3, #56 ; 0x38
|
||
|
|
8000688: 18fb adds r3, r7, r3
|
||
|
|
800068a: 2210 movs r2, #16
|
||
|
|
800068c: 611a str r2, [r3, #16]
|
||
|
|
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
|
||
|
|
800068e: 2338 movs r3, #56 ; 0x38
|
||
|
|
8000690: 18fb adds r3, r7, r3
|
||
|
|
8000692: 2202 movs r2, #2
|
||
|
|
8000694: 629a str r2, [r3, #40] ; 0x28
|
||
|
|
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
|
||
|
|
8000696: 2338 movs r3, #56 ; 0x38
|
||
|
|
8000698: 18fb adds r3, r7, r3
|
||
|
|
800069a: 2200 movs r2, #0
|
||
|
|
800069c: 62da str r2, [r3, #44] ; 0x2c
|
||
|
|
RCC_OscInitStruct.PLL.PLLMUL = RCC_PLLMUL_3;
|
||
|
|
800069e: 2338 movs r3, #56 ; 0x38
|
||
|
|
80006a0: 18fb adds r3, r7, r3
|
||
|
|
80006a2: 2200 movs r2, #0
|
||
|
|
80006a4: 631a str r2, [r3, #48] ; 0x30
|
||
|
|
RCC_OscInitStruct.PLL.PLLDIV = RCC_PLLDIV_3;
|
||
|
|
80006a6: 2338 movs r3, #56 ; 0x38
|
||
|
|
80006a8: 18fb adds r3, r7, r3
|
||
|
|
80006aa: 2280 movs r2, #128 ; 0x80
|
||
|
|
80006ac: 0412 lsls r2, r2, #16
|
||
|
|
80006ae: 635a str r2, [r3, #52] ; 0x34
|
||
|
|
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
|
||
|
|
80006b0: 2338 movs r3, #56 ; 0x38
|
||
|
|
80006b2: 18fb adds r3, r7, r3
|
||
|
|
80006b4: 0018 movs r0, r3
|
||
|
|
80006b6: f000 fca9 bl 800100c <HAL_RCC_OscConfig>
|
||
|
|
80006ba: 1e03 subs r3, r0, #0
|
||
|
|
80006bc: d001 beq.n 80006c2 <SystemClock_Config+0x92>
|
||
|
|
{
|
||
|
|
Error_Handler();
|
||
|
|
80006be: f000 f835 bl 800072c <Error_Handler>
|
||
|
|
}
|
||
|
|
/** Initializes the CPU, AHB and APB buses clocks
|
||
|
|
*/
|
||
|
|
RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
|
||
|
|
80006c2: 2324 movs r3, #36 ; 0x24
|
||
|
|
80006c4: 18fb adds r3, r7, r3
|
||
|
|
80006c6: 220f movs r2, #15
|
||
|
|
80006c8: 601a str r2, [r3, #0]
|
||
|
|
|RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
|
||
|
|
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
|
||
|
|
80006ca: 2324 movs r3, #36 ; 0x24
|
||
|
|
80006cc: 18fb adds r3, r7, r3
|
||
|
|
80006ce: 2203 movs r2, #3
|
||
|
|
80006d0: 605a str r2, [r3, #4]
|
||
|
|
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV2;
|
||
|
|
80006d2: 2324 movs r3, #36 ; 0x24
|
||
|
|
80006d4: 18fb adds r3, r7, r3
|
||
|
|
80006d6: 2280 movs r2, #128 ; 0x80
|
||
|
|
80006d8: 609a str r2, [r3, #8]
|
||
|
|
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
|
||
|
|
80006da: 2324 movs r3, #36 ; 0x24
|
||
|
|
80006dc: 18fb adds r3, r7, r3
|
||
|
|
80006de: 2200 movs r2, #0
|
||
|
|
80006e0: 60da str r2, [r3, #12]
|
||
|
|
RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
|
||
|
|
80006e2: 2324 movs r3, #36 ; 0x24
|
||
|
|
80006e4: 18fb adds r3, r7, r3
|
||
|
|
80006e6: 2200 movs r2, #0
|
||
|
|
80006e8: 611a str r2, [r3, #16]
|
||
|
|
|
||
|
|
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0) != HAL_OK)
|
||
|
|
80006ea: 2324 movs r3, #36 ; 0x24
|
||
|
|
80006ec: 18fb adds r3, r7, r3
|
||
|
|
80006ee: 2100 movs r1, #0
|
||
|
|
80006f0: 0018 movs r0, r3
|
||
|
|
80006f2: f001 f85d bl 80017b0 <HAL_RCC_ClockConfig>
|
||
|
|
80006f6: 1e03 subs r3, r0, #0
|
||
|
|
80006f8: d001 beq.n 80006fe <SystemClock_Config+0xce>
|
||
|
|
{
|
||
|
|
Error_Handler();
|
||
|
|
80006fa: f000 f817 bl 800072c <Error_Handler>
|
||
|
|
}
|
||
|
|
PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USART1;
|
||
|
|
80006fe: 003b movs r3, r7
|
||
|
|
8000700: 2201 movs r2, #1
|
||
|
|
8000702: 601a str r2, [r3, #0]
|
||
|
|
PeriphClkInit.Usart1ClockSelection = RCC_USART1CLKSOURCE_PCLK2;
|
||
|
|
8000704: 003b movs r3, r7
|
||
|
|
8000706: 2200 movs r2, #0
|
||
|
|
8000708: 609a str r2, [r3, #8]
|
||
|
|
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK)
|
||
|
|
800070a: 003b movs r3, r7
|
||
|
|
800070c: 0018 movs r0, r3
|
||
|
|
800070e: f001 fa6f bl 8001bf0 <HAL_RCCEx_PeriphCLKConfig>
|
||
|
|
8000712: 1e03 subs r3, r0, #0
|
||
|
|
8000714: d001 beq.n 800071a <SystemClock_Config+0xea>
|
||
|
|
{
|
||
|
|
Error_Handler();
|
||
|
|
8000716: f000 f809 bl 800072c <Error_Handler>
|
||
|
|
}
|
||
|
|
}
|
||
|
|
800071a: 46c0 nop ; (mov r8, r8)
|
||
|
|
800071c: 46bd mov sp, r7
|
||
|
|
800071e: b01c add sp, #112 ; 0x70
|
||
|
|
8000720: bd80 pop {r7, pc}
|
||
|
|
8000722: 46c0 nop ; (mov r8, r8)
|
||
|
|
8000724: 40007000 .word 0x40007000
|
||
|
|
8000728: ffffe7ff .word 0xffffe7ff
|
||
|
|
|
||
|
|
0800072c <Error_Handler>:
|
||
|
|
/**
|
||
|
|
* @brief This function is executed in case of error occurrence.
|
||
|
|
* @retval None
|
||
|
|
*/
|
||
|
|
void Error_Handler(void)
|
||
|
|
{
|
||
|
|
800072c: b580 push {r7, lr}
|
||
|
|
800072e: af00 add r7, sp, #0
|
||
|
|
\details Disables IRQ interrupts by setting the I-bit in the CPSR.
|
||
|
|
Can only be executed in Privileged modes.
|
||
|
|
*/
|
||
|
|
__STATIC_FORCEINLINE void __disable_irq(void)
|
||
|
|
{
|
||
|
|
__ASM volatile ("cpsid i" : : : "memory");
|
||
|
|
8000730: b672 cpsid i
|
||
|
|
/* USER CODE BEGIN Error_Handler_Debug */
|
||
|
|
/* User can add his own implementation to report the HAL error return state */
|
||
|
|
__disable_irq();
|
||
|
|
while (1)
|
||
|
|
8000732: e7fe b.n 8000732 <Error_Handler+0x6>
|
||
|
|
|
||
|
|
08000734 <HAL_MspInit>:
|
||
|
|
/* USER CODE END 0 */
|
||
|
|
/**
|
||
|
|
* Initializes the Global MSP.
|
||
|
|
*/
|
||
|
|
void HAL_MspInit(void)
|
||
|
|
{
|
||
|
|
8000734: b580 push {r7, lr}
|
||
|
|
8000736: af00 add r7, sp, #0
|
||
|
|
/* USER CODE BEGIN MspInit 0 */
|
||
|
|
|
||
|
|
/* USER CODE END MspInit 0 */
|
||
|
|
|
||
|
|
__HAL_RCC_SYSCFG_CLK_ENABLE();
|
||
|
|
8000738: 4b07 ldr r3, [pc, #28] ; (8000758 <HAL_MspInit+0x24>)
|
||
|
|
800073a: 4a07 ldr r2, [pc, #28] ; (8000758 <HAL_MspInit+0x24>)
|
||
|
|
800073c: 6b52 ldr r2, [r2, #52] ; 0x34
|
||
|
|
800073e: 2101 movs r1, #1
|
||
|
|
8000740: 430a orrs r2, r1
|
||
|
|
8000742: 635a str r2, [r3, #52] ; 0x34
|
||
|
|
__HAL_RCC_PWR_CLK_ENABLE();
|
||
|
|
8000744: 4b04 ldr r3, [pc, #16] ; (8000758 <HAL_MspInit+0x24>)
|
||
|
|
8000746: 4a04 ldr r2, [pc, #16] ; (8000758 <HAL_MspInit+0x24>)
|
||
|
|
8000748: 6b92 ldr r2, [r2, #56] ; 0x38
|
||
|
|
800074a: 2180 movs r1, #128 ; 0x80
|
||
|
|
800074c: 0549 lsls r1, r1, #21
|
||
|
|
800074e: 430a orrs r2, r1
|
||
|
|
8000750: 639a str r2, [r3, #56] ; 0x38
|
||
|
|
/* System interrupt init*/
|
||
|
|
|
||
|
|
/* USER CODE BEGIN MspInit 1 */
|
||
|
|
|
||
|
|
/* USER CODE END MspInit 1 */
|
||
|
|
}
|
||
|
|
8000752: 46c0 nop ; (mov r8, r8)
|
||
|
|
8000754: 46bd mov sp, r7
|
||
|
|
8000756: bd80 pop {r7, pc}
|
||
|
|
8000758: 40021000 .word 0x40021000
|
||
|
|
|
||
|
|
0800075c <NMI_Handler>:
|
||
|
|
/******************************************************************************/
|
||
|
|
/**
|
||
|
|
* @brief This function handles Non maskable Interrupt.
|
||
|
|
*/
|
||
|
|
void NMI_Handler(void)
|
||
|
|
{
|
||
|
|
800075c: b580 push {r7, lr}
|
||
|
|
800075e: af00 add r7, sp, #0
|
||
|
|
/* USER CODE BEGIN NonMaskableInt_IRQn 0 */
|
||
|
|
|
||
|
|
/* USER CODE END NonMaskableInt_IRQn 0 */
|
||
|
|
/* USER CODE BEGIN NonMaskableInt_IRQn 1 */
|
||
|
|
while (1)
|
||
|
|
8000760: e7fe b.n 8000760 <NMI_Handler+0x4>
|
||
|
|
|
||
|
|
08000762 <HardFault_Handler>:
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @brief This function handles Hard fault interrupt.
|
||
|
|
*/
|
||
|
|
void HardFault_Handler(void)
|
||
|
|
{
|
||
|
|
8000762: b580 push {r7, lr}
|
||
|
|
8000764: af00 add r7, sp, #0
|
||
|
|
/* USER CODE BEGIN HardFault_IRQn 0 */
|
||
|
|
|
||
|
|
/* USER CODE END HardFault_IRQn 0 */
|
||
|
|
while (1)
|
||
|
|
8000766: e7fe b.n 8000766 <HardFault_Handler+0x4>
|
||
|
|
|
||
|
|
08000768 <SVC_Handler>:
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @brief This function handles System service call via SWI instruction.
|
||
|
|
*/
|
||
|
|
void SVC_Handler(void)
|
||
|
|
{
|
||
|
|
8000768: b580 push {r7, lr}
|
||
|
|
800076a: af00 add r7, sp, #0
|
||
|
|
|
||
|
|
/* USER CODE END SVC_IRQn 0 */
|
||
|
|
/* USER CODE BEGIN SVC_IRQn 1 */
|
||
|
|
|
||
|
|
/* USER CODE END SVC_IRQn 1 */
|
||
|
|
}
|
||
|
|
800076c: 46c0 nop ; (mov r8, r8)
|
||
|
|
800076e: 46bd mov sp, r7
|
||
|
|
8000770: bd80 pop {r7, pc}
|
||
|
|
|
||
|
|
08000772 <PendSV_Handler>:
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @brief This function handles Pendable request for system service.
|
||
|
|
*/
|
||
|
|
void PendSV_Handler(void)
|
||
|
|
{
|
||
|
|
8000772: b580 push {r7, lr}
|
||
|
|
8000774: af00 add r7, sp, #0
|
||
|
|
|
||
|
|
/* USER CODE END PendSV_IRQn 0 */
|
||
|
|
/* USER CODE BEGIN PendSV_IRQn 1 */
|
||
|
|
|
||
|
|
/* USER CODE END PendSV_IRQn 1 */
|
||
|
|
}
|
||
|
|
8000776: 46c0 nop ; (mov r8, r8)
|
||
|
|
8000778: 46bd mov sp, r7
|
||
|
|
800077a: bd80 pop {r7, pc}
|
||
|
|
|
||
|
|
0800077c <SysTick_Handler>:
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @brief This function handles System tick timer.
|
||
|
|
*/
|
||
|
|
void SysTick_Handler(void)
|
||
|
|
{
|
||
|
|
800077c: b580 push {r7, lr}
|
||
|
|
800077e: af00 add r7, sp, #0
|
||
|
|
/* USER CODE BEGIN SysTick_IRQn 0 */
|
||
|
|
|
||
|
|
/* USER CODE END SysTick_IRQn 0 */
|
||
|
|
HAL_IncTick();
|
||
|
|
8000780: f000 f8fe bl 8000980 <HAL_IncTick>
|
||
|
|
/* USER CODE BEGIN SysTick_IRQn 1 */
|
||
|
|
|
||
|
|
/* USER CODE END SysTick_IRQn 1 */
|
||
|
|
}
|
||
|
|
8000784: 46c0 nop ; (mov r8, r8)
|
||
|
|
8000786: 46bd mov sp, r7
|
||
|
|
8000788: bd80 pop {r7, pc}
|
||
|
|
|
||
|
|
0800078a <EXTI0_1_IRQHandler>:
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @brief This function handles EXTI line 0 and line 1 interrupts.
|
||
|
|
*/
|
||
|
|
void EXTI0_1_IRQHandler(void)
|
||
|
|
{
|
||
|
|
800078a: b580 push {r7, lr}
|
||
|
|
800078c: af00 add r7, sp, #0
|
||
|
|
/* USER CODE BEGIN EXTI0_1_IRQn 0 */
|
||
|
|
|
||
|
|
/* USER CODE END EXTI0_1_IRQn 0 */
|
||
|
|
HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_0);
|
||
|
|
800078e: 2001 movs r0, #1
|
||
|
|
8000790: f000 fc16 bl 8000fc0 <HAL_GPIO_EXTI_IRQHandler>
|
||
|
|
HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_1);
|
||
|
|
8000794: 2002 movs r0, #2
|
||
|
|
8000796: f000 fc13 bl 8000fc0 <HAL_GPIO_EXTI_IRQHandler>
|
||
|
|
/* USER CODE BEGIN EXTI0_1_IRQn 1 */
|
||
|
|
|
||
|
|
/* USER CODE END EXTI0_1_IRQn 1 */
|
||
|
|
}
|
||
|
|
800079a: 46c0 nop ; (mov r8, r8)
|
||
|
|
800079c: 46bd mov sp, r7
|
||
|
|
800079e: bd80 pop {r7, pc}
|
||
|
|
|
||
|
|
080007a0 <EXTI2_3_IRQHandler>:
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @brief This function handles EXTI line 2 and line 3 interrupts.
|
||
|
|
*/
|
||
|
|
void EXTI2_3_IRQHandler(void)
|
||
|
|
{
|
||
|
|
80007a0: b580 push {r7, lr}
|
||
|
|
80007a2: af00 add r7, sp, #0
|
||
|
|
/* USER CODE BEGIN EXTI2_3_IRQn 0 */
|
||
|
|
|
||
|
|
/* USER CODE END EXTI2_3_IRQn 0 */
|
||
|
|
HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_2);
|
||
|
|
80007a4: 2004 movs r0, #4
|
||
|
|
80007a6: f000 fc0b bl 8000fc0 <HAL_GPIO_EXTI_IRQHandler>
|
||
|
|
/* USER CODE BEGIN EXTI2_3_IRQn 1 */
|
||
|
|
|
||
|
|
/* USER CODE END EXTI2_3_IRQn 1 */
|
||
|
|
}
|
||
|
|
80007aa: 46c0 nop ; (mov r8, r8)
|
||
|
|
80007ac: 46bd mov sp, r7
|
||
|
|
80007ae: bd80 pop {r7, pc}
|
||
|
|
|
||
|
|
080007b0 <USART1_IRQHandler>:
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @brief This function handles USART1 global interrupt / USART1 wake-up interrupt through EXTI line 25.
|
||
|
|
*/
|
||
|
|
void USART1_IRQHandler(void)
|
||
|
|
{
|
||
|
|
80007b0: b580 push {r7, lr}
|
||
|
|
80007b2: af00 add r7, sp, #0
|
||
|
|
/* USER CODE BEGIN USART1_IRQn 0 */
|
||
|
|
|
||
|
|
/* USER CODE END USART1_IRQn 0 */
|
||
|
|
HAL_UART_IRQHandler(&huart1);
|
||
|
|
80007b4: 4b03 ldr r3, [pc, #12] ; (80007c4 <USART1_IRQHandler+0x14>)
|
||
|
|
80007b6: 0018 movs r0, r3
|
||
|
|
80007b8: f001 fbc0 bl 8001f3c <HAL_UART_IRQHandler>
|
||
|
|
/* USER CODE BEGIN USART1_IRQn 1 */
|
||
|
|
|
||
|
|
/* USER CODE END USART1_IRQn 1 */
|
||
|
|
}
|
||
|
|
80007bc: 46c0 nop ; (mov r8, r8)
|
||
|
|
80007be: 46bd mov sp, r7
|
||
|
|
80007c0: bd80 pop {r7, pc}
|
||
|
|
80007c2: 46c0 nop ; (mov r8, r8)
|
||
|
|
80007c4: 20000028 .word 0x20000028
|
||
|
|
|
||
|
|
080007c8 <SystemInit>:
|
||
|
|
* @brief Setup the microcontroller system.
|
||
|
|
* @param None
|
||
|
|
* @retval None
|
||
|
|
*/
|
||
|
|
void SystemInit (void)
|
||
|
|
{
|
||
|
|
80007c8: b580 push {r7, lr}
|
||
|
|
80007ca: af00 add r7, sp, #0
|
||
|
|
/* Configure the Vector Table location add offset address ------------------*/
|
||
|
|
#if defined (USER_VECT_TAB_ADDRESS)
|
||
|
|
SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
|
||
|
|
#endif /* USER_VECT_TAB_ADDRESS */
|
||
|
|
}
|
||
|
|
80007cc: 46c0 nop ; (mov r8, r8)
|
||
|
|
80007ce: 46bd mov sp, r7
|
||
|
|
80007d0: bd80 pop {r7, pc}
|
||
|
|
...
|
||
|
|
|
||
|
|
080007d4 <MX_USART1_UART_Init>:
|
||
|
|
UART_HandleTypeDef huart1;
|
||
|
|
|
||
|
|
/* USART1 init function */
|
||
|
|
|
||
|
|
void MX_USART1_UART_Init(void)
|
||
|
|
{
|
||
|
|
80007d4: b580 push {r7, lr}
|
||
|
|
80007d6: af00 add r7, sp, #0
|
||
|
|
/* USER CODE END USART1_Init 0 */
|
||
|
|
|
||
|
|
/* USER CODE BEGIN USART1_Init 1 */
|
||
|
|
|
||
|
|
/* USER CODE END USART1_Init 1 */
|
||
|
|
huart1.Instance = USART1;
|
||
|
|
80007d8: 4b14 ldr r3, [pc, #80] ; (800082c <MX_USART1_UART_Init+0x58>)
|
||
|
|
80007da: 4a15 ldr r2, [pc, #84] ; (8000830 <MX_USART1_UART_Init+0x5c>)
|
||
|
|
80007dc: 601a str r2, [r3, #0]
|
||
|
|
huart1.Init.BaudRate = 115200;
|
||
|
|
80007de: 4b13 ldr r3, [pc, #76] ; (800082c <MX_USART1_UART_Init+0x58>)
|
||
|
|
80007e0: 22e1 movs r2, #225 ; 0xe1
|
||
|
|
80007e2: 0252 lsls r2, r2, #9
|
||
|
|
80007e4: 605a str r2, [r3, #4]
|
||
|
|
huart1.Init.WordLength = UART_WORDLENGTH_8B;
|
||
|
|
80007e6: 4b11 ldr r3, [pc, #68] ; (800082c <MX_USART1_UART_Init+0x58>)
|
||
|
|
80007e8: 2200 movs r2, #0
|
||
|
|
80007ea: 609a str r2, [r3, #8]
|
||
|
|
huart1.Init.StopBits = UART_STOPBITS_1;
|
||
|
|
80007ec: 4b0f ldr r3, [pc, #60] ; (800082c <MX_USART1_UART_Init+0x58>)
|
||
|
|
80007ee: 2200 movs r2, #0
|
||
|
|
80007f0: 60da str r2, [r3, #12]
|
||
|
|
huart1.Init.Parity = UART_PARITY_NONE;
|
||
|
|
80007f2: 4b0e ldr r3, [pc, #56] ; (800082c <MX_USART1_UART_Init+0x58>)
|
||
|
|
80007f4: 2200 movs r2, #0
|
||
|
|
80007f6: 611a str r2, [r3, #16]
|
||
|
|
huart1.Init.Mode = UART_MODE_TX_RX;
|
||
|
|
80007f8: 4b0c ldr r3, [pc, #48] ; (800082c <MX_USART1_UART_Init+0x58>)
|
||
|
|
80007fa: 220c movs r2, #12
|
||
|
|
80007fc: 615a str r2, [r3, #20]
|
||
|
|
huart1.Init.HwFlowCtl = UART_HWCONTROL_NONE;
|
||
|
|
80007fe: 4b0b ldr r3, [pc, #44] ; (800082c <MX_USART1_UART_Init+0x58>)
|
||
|
|
8000800: 2200 movs r2, #0
|
||
|
|
8000802: 619a str r2, [r3, #24]
|
||
|
|
huart1.Init.OverSampling = UART_OVERSAMPLING_16;
|
||
|
|
8000804: 4b09 ldr r3, [pc, #36] ; (800082c <MX_USART1_UART_Init+0x58>)
|
||
|
|
8000806: 2200 movs r2, #0
|
||
|
|
8000808: 61da str r2, [r3, #28]
|
||
|
|
huart1.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE;
|
||
|
|
800080a: 4b08 ldr r3, [pc, #32] ; (800082c <MX_USART1_UART_Init+0x58>)
|
||
|
|
800080c: 2200 movs r2, #0
|
||
|
|
800080e: 621a str r2, [r3, #32]
|
||
|
|
huart1.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT;
|
||
|
|
8000810: 4b06 ldr r3, [pc, #24] ; (800082c <MX_USART1_UART_Init+0x58>)
|
||
|
|
8000812: 2200 movs r2, #0
|
||
|
|
8000814: 625a str r2, [r3, #36] ; 0x24
|
||
|
|
if (HAL_UART_Init(&huart1) != HAL_OK)
|
||
|
|
8000816: 4b05 ldr r3, [pc, #20] ; (800082c <MX_USART1_UART_Init+0x58>)
|
||
|
|
8000818: 0018 movs r0, r3
|
||
|
|
800081a: f001 fb3b bl 8001e94 <HAL_UART_Init>
|
||
|
|
800081e: 1e03 subs r3, r0, #0
|
||
|
|
8000820: d001 beq.n 8000826 <MX_USART1_UART_Init+0x52>
|
||
|
|
{
|
||
|
|
Error_Handler();
|
||
|
|
8000822: f7ff ff83 bl 800072c <Error_Handler>
|
||
|
|
}
|
||
|
|
/* USER CODE BEGIN USART1_Init 2 */
|
||
|
|
|
||
|
|
/* USER CODE END USART1_Init 2 */
|
||
|
|
|
||
|
|
}
|
||
|
|
8000826: 46c0 nop ; (mov r8, r8)
|
||
|
|
8000828: 46bd mov sp, r7
|
||
|
|
800082a: bd80 pop {r7, pc}
|
||
|
|
800082c: 20000028 .word 0x20000028
|
||
|
|
8000830: 40013800 .word 0x40013800
|
||
|
|
|
||
|
|
08000834 <HAL_UART_MspInit>:
|
||
|
|
|
||
|
|
void HAL_UART_MspInit(UART_HandleTypeDef* uartHandle)
|
||
|
|
{
|
||
|
|
8000834: b580 push {r7, lr}
|
||
|
|
8000836: b088 sub sp, #32
|
||
|
|
8000838: af00 add r7, sp, #0
|
||
|
|
800083a: 6078 str r0, [r7, #4]
|
||
|
|
|
||
|
|
GPIO_InitTypeDef GPIO_InitStruct = {0};
|
||
|
|
800083c: 230c movs r3, #12
|
||
|
|
800083e: 18fb adds r3, r7, r3
|
||
|
|
8000840: 0018 movs r0, r3
|
||
|
|
8000842: 2314 movs r3, #20
|
||
|
|
8000844: 001a movs r2, r3
|
||
|
|
8000846: 2100 movs r1, #0
|
||
|
|
8000848: f002 fa8e bl 8002d68 <memset>
|
||
|
|
if(uartHandle->Instance==USART1)
|
||
|
|
800084c: 687b ldr r3, [r7, #4]
|
||
|
|
800084e: 681b ldr r3, [r3, #0]
|
||
|
|
8000850: 4a1f ldr r2, [pc, #124] ; (80008d0 <HAL_UART_MspInit+0x9c>)
|
||
|
|
8000852: 4293 cmp r3, r2
|
||
|
|
8000854: d137 bne.n 80008c6 <HAL_UART_MspInit+0x92>
|
||
|
|
{
|
||
|
|
/* USER CODE BEGIN USART1_MspInit 0 */
|
||
|
|
|
||
|
|
/* USER CODE END USART1_MspInit 0 */
|
||
|
|
/* USART1 clock enable */
|
||
|
|
__HAL_RCC_USART1_CLK_ENABLE();
|
||
|
|
8000856: 4b1f ldr r3, [pc, #124] ; (80008d4 <HAL_UART_MspInit+0xa0>)
|
||
|
|
8000858: 4a1e ldr r2, [pc, #120] ; (80008d4 <HAL_UART_MspInit+0xa0>)
|
||
|
|
800085a: 6b52 ldr r2, [r2, #52] ; 0x34
|
||
|
|
800085c: 2180 movs r1, #128 ; 0x80
|
||
|
|
800085e: 01c9 lsls r1, r1, #7
|
||
|
|
8000860: 430a orrs r2, r1
|
||
|
|
8000862: 635a str r2, [r3, #52] ; 0x34
|
||
|
|
|
||
|
|
__HAL_RCC_GPIOA_CLK_ENABLE();
|
||
|
|
8000864: 4b1b ldr r3, [pc, #108] ; (80008d4 <HAL_UART_MspInit+0xa0>)
|
||
|
|
8000866: 4a1b ldr r2, [pc, #108] ; (80008d4 <HAL_UART_MspInit+0xa0>)
|
||
|
|
8000868: 6ad2 ldr r2, [r2, #44] ; 0x2c
|
||
|
|
800086a: 2101 movs r1, #1
|
||
|
|
800086c: 430a orrs r2, r1
|
||
|
|
800086e: 62da str r2, [r3, #44] ; 0x2c
|
||
|
|
8000870: 4b18 ldr r3, [pc, #96] ; (80008d4 <HAL_UART_MspInit+0xa0>)
|
||
|
|
8000872: 6adb ldr r3, [r3, #44] ; 0x2c
|
||
|
|
8000874: 2201 movs r2, #1
|
||
|
|
8000876: 4013 ands r3, r2
|
||
|
|
8000878: 60bb str r3, [r7, #8]
|
||
|
|
800087a: 68bb ldr r3, [r7, #8]
|
||
|
|
/**USART1 GPIO Configuration
|
||
|
|
PA9 ------> USART1_TX
|
||
|
|
PA10 ------> USART1_RX
|
||
|
|
*/
|
||
|
|
GPIO_InitStruct.Pin = GPIO_PIN_9|GPIO_PIN_10;
|
||
|
|
800087c: 230c movs r3, #12
|
||
|
|
800087e: 18fb adds r3, r7, r3
|
||
|
|
8000880: 22c0 movs r2, #192 ; 0xc0
|
||
|
|
8000882: 00d2 lsls r2, r2, #3
|
||
|
|
8000884: 601a str r2, [r3, #0]
|
||
|
|
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
|
||
|
|
8000886: 230c movs r3, #12
|
||
|
|
8000888: 18fb adds r3, r7, r3
|
||
|
|
800088a: 2202 movs r2, #2
|
||
|
|
800088c: 605a str r2, [r3, #4]
|
||
|
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
||
|
|
800088e: 230c movs r3, #12
|
||
|
|
8000890: 18fb adds r3, r7, r3
|
||
|
|
8000892: 2200 movs r2, #0
|
||
|
|
8000894: 609a str r2, [r3, #8]
|
||
|
|
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
|
||
|
|
8000896: 230c movs r3, #12
|
||
|
|
8000898: 18fb adds r3, r7, r3
|
||
|
|
800089a: 2203 movs r2, #3
|
||
|
|
800089c: 60da str r2, [r3, #12]
|
||
|
|
GPIO_InitStruct.Alternate = GPIO_AF4_USART1;
|
||
|
|
800089e: 230c movs r3, #12
|
||
|
|
80008a0: 18fb adds r3, r7, r3
|
||
|
|
80008a2: 2204 movs r2, #4
|
||
|
|
80008a4: 611a str r2, [r3, #16]
|
||
|
|
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
|
||
|
|
80008a6: 230c movs r3, #12
|
||
|
|
80008a8: 18fa adds r2, r7, r3
|
||
|
|
80008aa: 23a0 movs r3, #160 ; 0xa0
|
||
|
|
80008ac: 05db lsls r3, r3, #23
|
||
|
|
80008ae: 0011 movs r1, r2
|
||
|
|
80008b0: 0018 movs r0, r3
|
||
|
|
80008b2: f000 f9e9 bl 8000c88 <HAL_GPIO_Init>
|
||
|
|
|
||
|
|
/* USART1 interrupt Init */
|
||
|
|
HAL_NVIC_SetPriority(USART1_IRQn, 2, 0);
|
||
|
|
80008b6: 2200 movs r2, #0
|
||
|
|
80008b8: 2102 movs r1, #2
|
||
|
|
80008ba: 201b movs r0, #27
|
||
|
|
80008bc: f000 f928 bl 8000b10 <HAL_NVIC_SetPriority>
|
||
|
|
HAL_NVIC_EnableIRQ(USART1_IRQn);
|
||
|
|
80008c0: 201b movs r0, #27
|
||
|
|
80008c2: f000 f93b bl 8000b3c <HAL_NVIC_EnableIRQ>
|
||
|
|
/* USER CODE BEGIN USART1_MspInit 1 */
|
||
|
|
|
||
|
|
/* USER CODE END USART1_MspInit 1 */
|
||
|
|
}
|
||
|
|
}
|
||
|
|
80008c6: 46c0 nop ; (mov r8, r8)
|
||
|
|
80008c8: 46bd mov sp, r7
|
||
|
|
80008ca: b008 add sp, #32
|
||
|
|
80008cc: bd80 pop {r7, pc}
|
||
|
|
80008ce: 46c0 nop ; (mov r8, r8)
|
||
|
|
80008d0: 40013800 .word 0x40013800
|
||
|
|
80008d4: 40021000 .word 0x40021000
|
||
|
|
|
||
|
|
080008d8 <HAL_Init>:
|
||
|
|
* In the default implementation,Systick is used as source of time base.
|
||
|
|
* the tick variable is incremented each 1ms in its ISR.
|
||
|
|
* @retval HAL status
|
||
|
|
*/
|
||
|
|
HAL_StatusTypeDef HAL_Init(void)
|
||
|
|
{
|
||
|
|
80008d8: b580 push {r7, lr}
|
||
|
|
80008da: b082 sub sp, #8
|
||
|
|
80008dc: af00 add r7, sp, #0
|
||
|
|
HAL_StatusTypeDef status = HAL_OK;
|
||
|
|
80008de: 1dfb adds r3, r7, #7
|
||
|
|
80008e0: 2200 movs r2, #0
|
||
|
|
80008e2: 701a strb r2, [r3, #0]
|
||
|
|
#if (BUFFER_CACHE_DISABLE != 0)
|
||
|
|
__HAL_FLASH_BUFFER_CACHE_DISABLE();
|
||
|
|
#endif /* BUFFER_CACHE_DISABLE */
|
||
|
|
|
||
|
|
#if (PREREAD_ENABLE != 0)
|
||
|
|
__HAL_FLASH_PREREAD_BUFFER_ENABLE();
|
||
|
|
80008e4: 4b0b ldr r3, [pc, #44] ; (8000914 <HAL_Init+0x3c>)
|
||
|
|
80008e6: 4a0b ldr r2, [pc, #44] ; (8000914 <HAL_Init+0x3c>)
|
||
|
|
80008e8: 6812 ldr r2, [r2, #0]
|
||
|
|
80008ea: 2140 movs r1, #64 ; 0x40
|
||
|
|
80008ec: 430a orrs r2, r1
|
||
|
|
80008ee: 601a str r2, [r3, #0]
|
||
|
|
#if (PREFETCH_ENABLE != 0)
|
||
|
|
__HAL_FLASH_PREFETCH_BUFFER_ENABLE();
|
||
|
|
#endif /* PREFETCH_ENABLE */
|
||
|
|
|
||
|
|
/* Use SysTick as time base source and configure 1ms tick (default clock after Reset is MSI) */
|
||
|
|
if (HAL_InitTick(TICK_INT_PRIORITY) != HAL_OK)
|
||
|
|
80008f0: 2000 movs r0, #0
|
||
|
|
80008f2: f000 f811 bl 8000918 <HAL_InitTick>
|
||
|
|
80008f6: 1e03 subs r3, r0, #0
|
||
|
|
80008f8: d003 beq.n 8000902 <HAL_Init+0x2a>
|
||
|
|
{
|
||
|
|
status = HAL_ERROR;
|
||
|
|
80008fa: 1dfb adds r3, r7, #7
|
||
|
|
80008fc: 2201 movs r2, #1
|
||
|
|
80008fe: 701a strb r2, [r3, #0]
|
||
|
|
8000900: e001 b.n 8000906 <HAL_Init+0x2e>
|
||
|
|
}
|
||
|
|
else
|
||
|
|
{
|
||
|
|
/* Init the low level hardware */
|
||
|
|
HAL_MspInit();
|
||
|
|
8000902: f7ff ff17 bl 8000734 <HAL_MspInit>
|
||
|
|
}
|
||
|
|
|
||
|
|
/* Return function status */
|
||
|
|
return status;
|
||
|
|
8000906: 1dfb adds r3, r7, #7
|
||
|
|
8000908: 781b ldrb r3, [r3, #0]
|
||
|
|
}
|
||
|
|
800090a: 0018 movs r0, r3
|
||
|
|
800090c: 46bd mov sp, r7
|
||
|
|
800090e: b002 add sp, #8
|
||
|
|
8000910: bd80 pop {r7, pc}
|
||
|
|
8000912: 46c0 nop ; (mov r8, r8)
|
||
|
|
8000914: 40022000 .word 0x40022000
|
||
|
|
|
||
|
|
08000918 <HAL_InitTick>:
|
||
|
|
* implementation in user file.
|
||
|
|
* @param TickPriority Tick interrupt priority.
|
||
|
|
* @retval HAL status
|
||
|
|
*/
|
||
|
|
__weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
|
||
|
|
{
|
||
|
|
8000918: b590 push {r4, r7, lr}
|
||
|
|
800091a: b083 sub sp, #12
|
||
|
|
800091c: af00 add r7, sp, #0
|
||
|
|
800091e: 6078 str r0, [r7, #4]
|
||
|
|
/* Configure the SysTick to have interrupt in 1ms time basis*/
|
||
|
|
if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / uwTickFreq)) > 0U)
|
||
|
|
8000920: 4b14 ldr r3, [pc, #80] ; (8000974 <HAL_InitTick+0x5c>)
|
||
|
|
8000922: 681c ldr r4, [r3, #0]
|
||
|
|
8000924: 4b14 ldr r3, [pc, #80] ; (8000978 <HAL_InitTick+0x60>)
|
||
|
|
8000926: 781b ldrb r3, [r3, #0]
|
||
|
|
8000928: 0019 movs r1, r3
|
||
|
|
800092a: 23fa movs r3, #250 ; 0xfa
|
||
|
|
800092c: 0098 lsls r0, r3, #2
|
||
|
|
800092e: f7ff fbeb bl 8000108 <__udivsi3>
|
||
|
|
8000932: 0003 movs r3, r0
|
||
|
|
8000934: 0019 movs r1, r3
|
||
|
|
8000936: 0020 movs r0, r4
|
||
|
|
8000938: f7ff fbe6 bl 8000108 <__udivsi3>
|
||
|
|
800093c: 0003 movs r3, r0
|
||
|
|
800093e: 0018 movs r0, r3
|
||
|
|
8000940: f000 f90c bl 8000b5c <HAL_SYSTICK_Config>
|
||
|
|
8000944: 1e03 subs r3, r0, #0
|
||
|
|
8000946: d001 beq.n 800094c <HAL_InitTick+0x34>
|
||
|
|
{
|
||
|
|
return HAL_ERROR;
|
||
|
|
8000948: 2301 movs r3, #1
|
||
|
|
800094a: e00f b.n 800096c <HAL_InitTick+0x54>
|
||
|
|
}
|
||
|
|
|
||
|
|
/* Configure the SysTick IRQ priority */
|
||
|
|
if (TickPriority < (1UL << __NVIC_PRIO_BITS))
|
||
|
|
800094c: 687b ldr r3, [r7, #4]
|
||
|
|
800094e: 2b03 cmp r3, #3
|
||
|
|
8000950: d80b bhi.n 800096a <HAL_InitTick+0x52>
|
||
|
|
{
|
||
|
|
HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U);
|
||
|
|
8000952: 6879 ldr r1, [r7, #4]
|
||
|
|
8000954: 2301 movs r3, #1
|
||
|
|
8000956: 425b negs r3, r3
|
||
|
|
8000958: 2200 movs r2, #0
|
||
|
|
800095a: 0018 movs r0, r3
|
||
|
|
800095c: f000 f8d8 bl 8000b10 <HAL_NVIC_SetPriority>
|
||
|
|
uwTickPrio = TickPriority;
|
||
|
|
8000960: 4b06 ldr r3, [pc, #24] ; (800097c <HAL_InitTick+0x64>)
|
||
|
|
8000962: 687a ldr r2, [r7, #4]
|
||
|
|
8000964: 601a str r2, [r3, #0]
|
||
|
|
{
|
||
|
|
return HAL_ERROR;
|
||
|
|
}
|
||
|
|
|
||
|
|
/* Return function status */
|
||
|
|
return HAL_OK;
|
||
|
|
8000966: 2300 movs r3, #0
|
||
|
|
8000968: e000 b.n 800096c <HAL_InitTick+0x54>
|
||
|
|
return HAL_ERROR;
|
||
|
|
800096a: 2301 movs r3, #1
|
||
|
|
}
|
||
|
|
800096c: 0018 movs r0, r3
|
||
|
|
800096e: 46bd mov sp, r7
|
||
|
|
8000970: b003 add sp, #12
|
||
|
|
8000972: bd90 pop {r4, r7, pc}
|
||
|
|
8000974: 20000000 .word 0x20000000
|
||
|
|
8000978: 20000008 .word 0x20000008
|
||
|
|
800097c: 20000004 .word 0x20000004
|
||
|
|
|
||
|
|
08000980 <HAL_IncTick>:
|
||
|
|
* @note This function is declared as __weak to be overwritten in case of other
|
||
|
|
* implementations in user file.
|
||
|
|
* @retval None
|
||
|
|
*/
|
||
|
|
__weak void HAL_IncTick(void)
|
||
|
|
{
|
||
|
|
8000980: b580 push {r7, lr}
|
||
|
|
8000982: af00 add r7, sp, #0
|
||
|
|
uwTick += uwTickFreq;
|
||
|
|
8000984: 4b05 ldr r3, [pc, #20] ; (800099c <HAL_IncTick+0x1c>)
|
||
|
|
8000986: 781b ldrb r3, [r3, #0]
|
||
|
|
8000988: 001a movs r2, r3
|
||
|
|
800098a: 4b05 ldr r3, [pc, #20] ; (80009a0 <HAL_IncTick+0x20>)
|
||
|
|
800098c: 681b ldr r3, [r3, #0]
|
||
|
|
800098e: 18d2 adds r2, r2, r3
|
||
|
|
8000990: 4b03 ldr r3, [pc, #12] ; (80009a0 <HAL_IncTick+0x20>)
|
||
|
|
8000992: 601a str r2, [r3, #0]
|
||
|
|
}
|
||
|
|
8000994: 46c0 nop ; (mov r8, r8)
|
||
|
|
8000996: 46bd mov sp, r7
|
||
|
|
8000998: bd80 pop {r7, pc}
|
||
|
|
800099a: 46c0 nop ; (mov r8, r8)
|
||
|
|
800099c: 20000008 .word 0x20000008
|
||
|
|
80009a0: 200000ac .word 0x200000ac
|
||
|
|
|
||
|
|
080009a4 <HAL_GetTick>:
|
||
|
|
* @note This function is declared as __weak to be overwritten in case of other
|
||
|
|
* implementations in user file.
|
||
|
|
* @retval tick value
|
||
|
|
*/
|
||
|
|
__weak uint32_t HAL_GetTick(void)
|
||
|
|
{
|
||
|
|
80009a4: b580 push {r7, lr}
|
||
|
|
80009a6: af00 add r7, sp, #0
|
||
|
|
return uwTick;
|
||
|
|
80009a8: 4b02 ldr r3, [pc, #8] ; (80009b4 <HAL_GetTick+0x10>)
|
||
|
|
80009aa: 681b ldr r3, [r3, #0]
|
||
|
|
}
|
||
|
|
80009ac: 0018 movs r0, r3
|
||
|
|
80009ae: 46bd mov sp, r7
|
||
|
|
80009b0: bd80 pop {r7, pc}
|
||
|
|
80009b2: 46c0 nop ; (mov r8, r8)
|
||
|
|
80009b4: 200000ac .word 0x200000ac
|
||
|
|
|
||
|
|
080009b8 <__NVIC_EnableIRQ>:
|
||
|
|
\details Enables a device specific interrupt in the NVIC interrupt controller.
|
||
|
|
\param [in] IRQn Device specific interrupt number.
|
||
|
|
\note IRQn must not be negative.
|
||
|
|
*/
|
||
|
|
__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
|
||
|
|
{
|
||
|
|
80009b8: b580 push {r7, lr}
|
||
|
|
80009ba: b082 sub sp, #8
|
||
|
|
80009bc: af00 add r7, sp, #0
|
||
|
|
80009be: 0002 movs r2, r0
|
||
|
|
80009c0: 1dfb adds r3, r7, #7
|
||
|
|
80009c2: 701a strb r2, [r3, #0]
|
||
|
|
if ((int32_t)(IRQn) >= 0)
|
||
|
|
80009c4: 1dfb adds r3, r7, #7
|
||
|
|
80009c6: 781b ldrb r3, [r3, #0]
|
||
|
|
80009c8: 2b7f cmp r3, #127 ; 0x7f
|
||
|
|
80009ca: d809 bhi.n 80009e0 <__NVIC_EnableIRQ+0x28>
|
||
|
|
{
|
||
|
|
NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
|
||
|
|
80009cc: 4b06 ldr r3, [pc, #24] ; (80009e8 <__NVIC_EnableIRQ+0x30>)
|
||
|
|
80009ce: 1dfa adds r2, r7, #7
|
||
|
|
80009d0: 7812 ldrb r2, [r2, #0]
|
||
|
|
80009d2: 0011 movs r1, r2
|
||
|
|
80009d4: 221f movs r2, #31
|
||
|
|
80009d6: 400a ands r2, r1
|
||
|
|
80009d8: 2101 movs r1, #1
|
||
|
|
80009da: 4091 lsls r1, r2
|
||
|
|
80009dc: 000a movs r2, r1
|
||
|
|
80009de: 601a str r2, [r3, #0]
|
||
|
|
}
|
||
|
|
}
|
||
|
|
80009e0: 46c0 nop ; (mov r8, r8)
|
||
|
|
80009e2: 46bd mov sp, r7
|
||
|
|
80009e4: b002 add sp, #8
|
||
|
|
80009e6: bd80 pop {r7, pc}
|
||
|
|
80009e8: e000e100 .word 0xe000e100
|
||
|
|
|
||
|
|
080009ec <__NVIC_SetPriority>:
|
||
|
|
\param [in] IRQn Interrupt number.
|
||
|
|
\param [in] priority Priority to set.
|
||
|
|
\note The priority cannot be set for every processor exception.
|
||
|
|
*/
|
||
|
|
__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
|
||
|
|
{
|
||
|
|
80009ec: b5b0 push {r4, r5, r7, lr}
|
||
|
|
80009ee: b082 sub sp, #8
|
||
|
|
80009f0: af00 add r7, sp, #0
|
||
|
|
80009f2: 0002 movs r2, r0
|
||
|
|
80009f4: 6039 str r1, [r7, #0]
|
||
|
|
80009f6: 1dfb adds r3, r7, #7
|
||
|
|
80009f8: 701a strb r2, [r3, #0]
|
||
|
|
if ((int32_t)(IRQn) >= 0)
|
||
|
|
80009fa: 1dfb adds r3, r7, #7
|
||
|
|
80009fc: 781b ldrb r3, [r3, #0]
|
||
|
|
80009fe: 2b7f cmp r3, #127 ; 0x7f
|
||
|
|
8000a00: d828 bhi.n 8000a54 <__NVIC_SetPriority+0x68>
|
||
|
|
{
|
||
|
|
NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
|
||
|
|
8000a02: 4c2f ldr r4, [pc, #188] ; (8000ac0 <__NVIC_SetPriority+0xd4>)
|
||
|
|
8000a04: 1dfb adds r3, r7, #7
|
||
|
|
8000a06: 781b ldrb r3, [r3, #0]
|
||
|
|
8000a08: b25b sxtb r3, r3
|
||
|
|
8000a0a: 089b lsrs r3, r3, #2
|
||
|
|
8000a0c: 492c ldr r1, [pc, #176] ; (8000ac0 <__NVIC_SetPriority+0xd4>)
|
||
|
|
8000a0e: 1dfa adds r2, r7, #7
|
||
|
|
8000a10: 7812 ldrb r2, [r2, #0]
|
||
|
|
8000a12: b252 sxtb r2, r2
|
||
|
|
8000a14: 0892 lsrs r2, r2, #2
|
||
|
|
8000a16: 32c0 adds r2, #192 ; 0xc0
|
||
|
|
8000a18: 0092 lsls r2, r2, #2
|
||
|
|
8000a1a: 5852 ldr r2, [r2, r1]
|
||
|
|
8000a1c: 1df9 adds r1, r7, #7
|
||
|
|
8000a1e: 7809 ldrb r1, [r1, #0]
|
||
|
|
8000a20: 0008 movs r0, r1
|
||
|
|
8000a22: 2103 movs r1, #3
|
||
|
|
8000a24: 4001 ands r1, r0
|
||
|
|
8000a26: 00c9 lsls r1, r1, #3
|
||
|
|
8000a28: 20ff movs r0, #255 ; 0xff
|
||
|
|
8000a2a: 4088 lsls r0, r1
|
||
|
|
8000a2c: 0001 movs r1, r0
|
||
|
|
8000a2e: 43c9 mvns r1, r1
|
||
|
|
8000a30: 4011 ands r1, r2
|
||
|
|
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
|
||
|
|
8000a32: 683a ldr r2, [r7, #0]
|
||
|
|
8000a34: 0192 lsls r2, r2, #6
|
||
|
|
8000a36: 20ff movs r0, #255 ; 0xff
|
||
|
|
8000a38: 4010 ands r0, r2
|
||
|
|
8000a3a: 1dfa adds r2, r7, #7
|
||
|
|
8000a3c: 7812 ldrb r2, [r2, #0]
|
||
|
|
8000a3e: 0015 movs r5, r2
|
||
|
|
8000a40: 2203 movs r2, #3
|
||
|
|
8000a42: 402a ands r2, r5
|
||
|
|
8000a44: 00d2 lsls r2, r2, #3
|
||
|
|
8000a46: 4090 lsls r0, r2
|
||
|
|
8000a48: 0002 movs r2, r0
|
||
|
|
NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
|
||
|
|
8000a4a: 430a orrs r2, r1
|
||
|
|
8000a4c: 33c0 adds r3, #192 ; 0xc0
|
||
|
|
8000a4e: 009b lsls r3, r3, #2
|
||
|
|
8000a50: 511a str r2, [r3, r4]
|
||
|
|
else
|
||
|
|
{
|
||
|
|
SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
|
||
|
|
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
|
||
|
|
}
|
||
|
|
}
|
||
|
|
8000a52: e031 b.n 8000ab8 <__NVIC_SetPriority+0xcc>
|
||
|
|
SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
|
||
|
|
8000a54: 4c1b ldr r4, [pc, #108] ; (8000ac4 <__NVIC_SetPriority+0xd8>)
|
||
|
|
8000a56: 1dfb adds r3, r7, #7
|
||
|
|
8000a58: 781b ldrb r3, [r3, #0]
|
||
|
|
8000a5a: 001a movs r2, r3
|
||
|
|
8000a5c: 230f movs r3, #15
|
||
|
|
8000a5e: 4013 ands r3, r2
|
||
|
|
8000a60: 3b08 subs r3, #8
|
||
|
|
8000a62: 0899 lsrs r1, r3, #2
|
||
|
|
8000a64: 4a17 ldr r2, [pc, #92] ; (8000ac4 <__NVIC_SetPriority+0xd8>)
|
||
|
|
8000a66: 1dfb adds r3, r7, #7
|
||
|
|
8000a68: 781b ldrb r3, [r3, #0]
|
||
|
|
8000a6a: 0018 movs r0, r3
|
||
|
|
8000a6c: 230f movs r3, #15
|
||
|
|
8000a6e: 4003 ands r3, r0
|
||
|
|
8000a70: 3b08 subs r3, #8
|
||
|
|
8000a72: 089b lsrs r3, r3, #2
|
||
|
|
8000a74: 3306 adds r3, #6
|
||
|
|
8000a76: 009b lsls r3, r3, #2
|
||
|
|
8000a78: 18d3 adds r3, r2, r3
|
||
|
|
8000a7a: 3304 adds r3, #4
|
||
|
|
8000a7c: 681b ldr r3, [r3, #0]
|
||
|
|
8000a7e: 1dfa adds r2, r7, #7
|
||
|
|
8000a80: 7812 ldrb r2, [r2, #0]
|
||
|
|
8000a82: 0010 movs r0, r2
|
||
|
|
8000a84: 2203 movs r2, #3
|
||
|
|
8000a86: 4002 ands r2, r0
|
||
|
|
8000a88: 00d2 lsls r2, r2, #3
|
||
|
|
8000a8a: 20ff movs r0, #255 ; 0xff
|
||
|
|
8000a8c: 4090 lsls r0, r2
|
||
|
|
8000a8e: 0002 movs r2, r0
|
||
|
|
8000a90: 43d2 mvns r2, r2
|
||
|
|
8000a92: 401a ands r2, r3
|
||
|
|
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
|
||
|
|
8000a94: 683b ldr r3, [r7, #0]
|
||
|
|
8000a96: 019b lsls r3, r3, #6
|
||
|
|
8000a98: 20ff movs r0, #255 ; 0xff
|
||
|
|
8000a9a: 4018 ands r0, r3
|
||
|
|
8000a9c: 1dfb adds r3, r7, #7
|
||
|
|
8000a9e: 781b ldrb r3, [r3, #0]
|
||
|
|
8000aa0: 001d movs r5, r3
|
||
|
|
8000aa2: 2303 movs r3, #3
|
||
|
|
8000aa4: 402b ands r3, r5
|
||
|
|
8000aa6: 00db lsls r3, r3, #3
|
||
|
|
8000aa8: 4098 lsls r0, r3
|
||
|
|
8000aaa: 0003 movs r3, r0
|
||
|
|
SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
|
||
|
|
8000aac: 431a orrs r2, r3
|
||
|
|
8000aae: 1d8b adds r3, r1, #6
|
||
|
|
8000ab0: 009b lsls r3, r3, #2
|
||
|
|
8000ab2: 18e3 adds r3, r4, r3
|
||
|
|
8000ab4: 3304 adds r3, #4
|
||
|
|
8000ab6: 601a str r2, [r3, #0]
|
||
|
|
}
|
||
|
|
8000ab8: 46c0 nop ; (mov r8, r8)
|
||
|
|
8000aba: 46bd mov sp, r7
|
||
|
|
8000abc: b002 add sp, #8
|
||
|
|
8000abe: bdb0 pop {r4, r5, r7, pc}
|
||
|
|
8000ac0: e000e100 .word 0xe000e100
|
||
|
|
8000ac4: e000ed00 .word 0xe000ed00
|
||
|
|
|
||
|
|
08000ac8 <SysTick_Config>:
|
||
|
|
\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
|
||
|
|
function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
|
||
|
|
must contain a vendor-specific implementation of this function.
|
||
|
|
*/
|
||
|
|
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
|
||
|
|
{
|
||
|
|
8000ac8: b580 push {r7, lr}
|
||
|
|
8000aca: b082 sub sp, #8
|
||
|
|
8000acc: af00 add r7, sp, #0
|
||
|
|
8000ace: 6078 str r0, [r7, #4]
|
||
|
|
if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
|
||
|
|
8000ad0: 687b ldr r3, [r7, #4]
|
||
|
|
8000ad2: 3b01 subs r3, #1
|
||
|
|
8000ad4: 4a0c ldr r2, [pc, #48] ; (8000b08 <SysTick_Config+0x40>)
|
||
|
|
8000ad6: 4293 cmp r3, r2
|
||
|
|
8000ad8: d901 bls.n 8000ade <SysTick_Config+0x16>
|
||
|
|
{
|
||
|
|
return (1UL); /* Reload value impossible */
|
||
|
|
8000ada: 2301 movs r3, #1
|
||
|
|
8000adc: e010 b.n 8000b00 <SysTick_Config+0x38>
|
||
|
|
}
|
||
|
|
|
||
|
|
SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
|
||
|
|
8000ade: 4b0b ldr r3, [pc, #44] ; (8000b0c <SysTick_Config+0x44>)
|
||
|
|
8000ae0: 687a ldr r2, [r7, #4]
|
||
|
|
8000ae2: 3a01 subs r2, #1
|
||
|
|
8000ae4: 605a str r2, [r3, #4]
|
||
|
|
NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
|
||
|
|
8000ae6: 2301 movs r3, #1
|
||
|
|
8000ae8: 425b negs r3, r3
|
||
|
|
8000aea: 2103 movs r1, #3
|
||
|
|
8000aec: 0018 movs r0, r3
|
||
|
|
8000aee: f7ff ff7d bl 80009ec <__NVIC_SetPriority>
|
||
|
|
SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
|
||
|
|
8000af2: 4b06 ldr r3, [pc, #24] ; (8000b0c <SysTick_Config+0x44>)
|
||
|
|
8000af4: 2200 movs r2, #0
|
||
|
|
8000af6: 609a str r2, [r3, #8]
|
||
|
|
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
|
||
|
|
8000af8: 4b04 ldr r3, [pc, #16] ; (8000b0c <SysTick_Config+0x44>)
|
||
|
|
8000afa: 2207 movs r2, #7
|
||
|
|
8000afc: 601a str r2, [r3, #0]
|
||
|
|
SysTick_CTRL_TICKINT_Msk |
|
||
|
|
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
|
||
|
|
return (0UL); /* Function successful */
|
||
|
|
8000afe: 2300 movs r3, #0
|
||
|
|
}
|
||
|
|
8000b00: 0018 movs r0, r3
|
||
|
|
8000b02: 46bd mov sp, r7
|
||
|
|
8000b04: b002 add sp, #8
|
||
|
|
8000b06: bd80 pop {r7, pc}
|
||
|
|
8000b08: 00ffffff .word 0x00ffffff
|
||
|
|
8000b0c: e000e010 .word 0xe000e010
|
||
|
|
|
||
|
|
08000b10 <HAL_NVIC_SetPriority>:
|
||
|
|
* with stm32l0xx devices, this parameter is a dummy value and it is ignored, because
|
||
|
|
* no subpriority supported in Cortex M0+ based products.
|
||
|
|
* @retval None
|
||
|
|
*/
|
||
|
|
void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
|
||
|
|
{
|
||
|
|
8000b10: b580 push {r7, lr}
|
||
|
|
8000b12: b084 sub sp, #16
|
||
|
|
8000b14: af00 add r7, sp, #0
|
||
|
|
8000b16: 60b9 str r1, [r7, #8]
|
||
|
|
8000b18: 607a str r2, [r7, #4]
|
||
|
|
8000b1a: 230f movs r3, #15
|
||
|
|
8000b1c: 18fb adds r3, r7, r3
|
||
|
|
8000b1e: 1c02 adds r2, r0, #0
|
||
|
|
8000b20: 701a strb r2, [r3, #0]
|
||
|
|
/* Check the parameters */
|
||
|
|
assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority));
|
||
|
|
NVIC_SetPriority(IRQn,PreemptPriority);
|
||
|
|
8000b22: 68ba ldr r2, [r7, #8]
|
||
|
|
8000b24: 230f movs r3, #15
|
||
|
|
8000b26: 18fb adds r3, r7, r3
|
||
|
|
8000b28: 781b ldrb r3, [r3, #0]
|
||
|
|
8000b2a: b25b sxtb r3, r3
|
||
|
|
8000b2c: 0011 movs r1, r2
|
||
|
|
8000b2e: 0018 movs r0, r3
|
||
|
|
8000b30: f7ff ff5c bl 80009ec <__NVIC_SetPriority>
|
||
|
|
}
|
||
|
|
8000b34: 46c0 nop ; (mov r8, r8)
|
||
|
|
8000b36: 46bd mov sp, r7
|
||
|
|
8000b38: b004 add sp, #16
|
||
|
|
8000b3a: bd80 pop {r7, pc}
|
||
|
|
|
||
|
|
08000b3c <HAL_NVIC_EnableIRQ>:
|
||
|
|
* This parameter can be an enumerator of IRQn_Type enumeration
|
||
|
|
* (For the complete STM32 Devices IRQ Channels list, please refer to stm32l0xx.h file)
|
||
|
|
* @retval None
|
||
|
|
*/
|
||
|
|
void HAL_NVIC_EnableIRQ(IRQn_Type IRQn)
|
||
|
|
{
|
||
|
|
8000b3c: b580 push {r7, lr}
|
||
|
|
8000b3e: b082 sub sp, #8
|
||
|
|
8000b40: af00 add r7, sp, #0
|
||
|
|
8000b42: 0002 movs r2, r0
|
||
|
|
8000b44: 1dfb adds r3, r7, #7
|
||
|
|
8000b46: 701a strb r2, [r3, #0]
|
||
|
|
/* Check the parameters */
|
||
|
|
assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
|
||
|
|
|
||
|
|
/* Enable interrupt */
|
||
|
|
NVIC_EnableIRQ(IRQn);
|
||
|
|
8000b48: 1dfb adds r3, r7, #7
|
||
|
|
8000b4a: 781b ldrb r3, [r3, #0]
|
||
|
|
8000b4c: b25b sxtb r3, r3
|
||
|
|
8000b4e: 0018 movs r0, r3
|
||
|
|
8000b50: f7ff ff32 bl 80009b8 <__NVIC_EnableIRQ>
|
||
|
|
}
|
||
|
|
8000b54: 46c0 nop ; (mov r8, r8)
|
||
|
|
8000b56: 46bd mov sp, r7
|
||
|
|
8000b58: b002 add sp, #8
|
||
|
|
8000b5a: bd80 pop {r7, pc}
|
||
|
|
|
||
|
|
08000b5c <HAL_SYSTICK_Config>:
|
||
|
|
* @param TicksNumb Specifies the ticks Number of ticks between two interrupts.
|
||
|
|
* @retval status: - 0 Function succeeded.
|
||
|
|
* - 1 Function failed.
|
||
|
|
*/
|
||
|
|
uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb)
|
||
|
|
{
|
||
|
|
8000b5c: b580 push {r7, lr}
|
||
|
|
8000b5e: b082 sub sp, #8
|
||
|
|
8000b60: af00 add r7, sp, #0
|
||
|
|
8000b62: 6078 str r0, [r7, #4]
|
||
|
|
return SysTick_Config(TicksNumb);
|
||
|
|
8000b64: 687b ldr r3, [r7, #4]
|
||
|
|
8000b66: 0018 movs r0, r3
|
||
|
|
8000b68: f7ff ffae bl 8000ac8 <SysTick_Config>
|
||
|
|
8000b6c: 0003 movs r3, r0
|
||
|
|
}
|
||
|
|
8000b6e: 0018 movs r0, r3
|
||
|
|
8000b70: 46bd mov sp, r7
|
||
|
|
8000b72: b002 add sp, #8
|
||
|
|
8000b74: bd80 pop {r7, pc}
|
||
|
|
|
||
|
|
08000b76 <HAL_DMA_Abort>:
|
||
|
|
* @param hdma pointer to a DMA_HandleTypeDef structure that contains
|
||
|
|
* the configuration information for the specified DMA Channel.
|
||
|
|
* @retval HAL status
|
||
|
|
*/
|
||
|
|
HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma)
|
||
|
|
{
|
||
|
|
8000b76: b580 push {r7, lr}
|
||
|
|
8000b78: b084 sub sp, #16
|
||
|
|
8000b7a: af00 add r7, sp, #0
|
||
|
|
8000b7c: 6078 str r0, [r7, #4]
|
||
|
|
HAL_StatusTypeDef status = HAL_OK;
|
||
|
|
8000b7e: 230f movs r3, #15
|
||
|
|
8000b80: 18fb adds r3, r7, r3
|
||
|
|
8000b82: 2200 movs r2, #0
|
||
|
|
8000b84: 701a strb r2, [r3, #0]
|
||
|
|
|
||
|
|
/* Check the DMA peripheral state */
|
||
|
|
if(hdma->State != HAL_DMA_STATE_BUSY)
|
||
|
|
8000b86: 687b ldr r3, [r7, #4]
|
||
|
|
8000b88: 2225 movs r2, #37 ; 0x25
|
||
|
|
8000b8a: 5c9b ldrb r3, [r3, r2]
|
||
|
|
8000b8c: b2db uxtb r3, r3
|
||
|
|
8000b8e: 2b02 cmp r3, #2
|
||
|
|
8000b90: d008 beq.n 8000ba4 <HAL_DMA_Abort+0x2e>
|
||
|
|
{
|
||
|
|
hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
|
||
|
|
8000b92: 687b ldr r3, [r7, #4]
|
||
|
|
8000b94: 2204 movs r2, #4
|
||
|
|
8000b96: 63da str r2, [r3, #60] ; 0x3c
|
||
|
|
|
||
|
|
/* Process Unlocked */
|
||
|
|
__HAL_UNLOCK(hdma);
|
||
|
|
8000b98: 687b ldr r3, [r7, #4]
|
||
|
|
8000b9a: 2224 movs r2, #36 ; 0x24
|
||
|
|
8000b9c: 2100 movs r1, #0
|
||
|
|
8000b9e: 5499 strb r1, [r3, r2]
|
||
|
|
|
||
|
|
return HAL_ERROR;
|
||
|
|
8000ba0: 2301 movs r3, #1
|
||
|
|
8000ba2: e024 b.n 8000bee <HAL_DMA_Abort+0x78>
|
||
|
|
}
|
||
|
|
else
|
||
|
|
{
|
||
|
|
/* Disable DMA IT */
|
||
|
|
__HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));
|
||
|
|
8000ba4: 687b ldr r3, [r7, #4]
|
||
|
|
8000ba6: 681b ldr r3, [r3, #0]
|
||
|
|
8000ba8: 687a ldr r2, [r7, #4]
|
||
|
|
8000baa: 6812 ldr r2, [r2, #0]
|
||
|
|
8000bac: 6812 ldr r2, [r2, #0]
|
||
|
|
8000bae: 210e movs r1, #14
|
||
|
|
8000bb0: 438a bics r2, r1
|
||
|
|
8000bb2: 601a str r2, [r3, #0]
|
||
|
|
|
||
|
|
/* Disable the channel */
|
||
|
|
__HAL_DMA_DISABLE(hdma);
|
||
|
|
8000bb4: 687b ldr r3, [r7, #4]
|
||
|
|
8000bb6: 681b ldr r3, [r3, #0]
|
||
|
|
8000bb8: 687a ldr r2, [r7, #4]
|
||
|
|
8000bba: 6812 ldr r2, [r2, #0]
|
||
|
|
8000bbc: 6812 ldr r2, [r2, #0]
|
||
|
|
8000bbe: 2101 movs r1, #1
|
||
|
|
8000bc0: 438a bics r2, r1
|
||
|
|
8000bc2: 601a str r2, [r3, #0]
|
||
|
|
|
||
|
|
/* Clear all flags */
|
||
|
|
hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1cU));
|
||
|
|
8000bc4: 687b ldr r3, [r7, #4]
|
||
|
|
8000bc6: 6c1b ldr r3, [r3, #64] ; 0x40
|
||
|
|
8000bc8: 687a ldr r2, [r7, #4]
|
||
|
|
8000bca: 6c52 ldr r2, [r2, #68] ; 0x44
|
||
|
|
8000bcc: 211c movs r1, #28
|
||
|
|
8000bce: 400a ands r2, r1
|
||
|
|
8000bd0: 2101 movs r1, #1
|
||
|
|
8000bd2: 4091 lsls r1, r2
|
||
|
|
8000bd4: 000a movs r2, r1
|
||
|
|
8000bd6: 605a str r2, [r3, #4]
|
||
|
|
|
||
|
|
/* Change the DMA state */
|
||
|
|
hdma->State = HAL_DMA_STATE_READY;
|
||
|
|
8000bd8: 687b ldr r3, [r7, #4]
|
||
|
|
8000bda: 2225 movs r2, #37 ; 0x25
|
||
|
|
8000bdc: 2101 movs r1, #1
|
||
|
|
8000bde: 5499 strb r1, [r3, r2]
|
||
|
|
|
||
|
|
/* Process Unlocked */
|
||
|
|
__HAL_UNLOCK(hdma);
|
||
|
|
8000be0: 687b ldr r3, [r7, #4]
|
||
|
|
8000be2: 2224 movs r2, #36 ; 0x24
|
||
|
|
8000be4: 2100 movs r1, #0
|
||
|
|
8000be6: 5499 strb r1, [r3, r2]
|
||
|
|
|
||
|
|
return status;
|
||
|
|
8000be8: 230f movs r3, #15
|
||
|
|
8000bea: 18fb adds r3, r7, r3
|
||
|
|
8000bec: 781b ldrb r3, [r3, #0]
|
||
|
|
}
|
||
|
|
}
|
||
|
|
8000bee: 0018 movs r0, r3
|
||
|
|
8000bf0: 46bd mov sp, r7
|
||
|
|
8000bf2: b004 add sp, #16
|
||
|
|
8000bf4: bd80 pop {r7, pc}
|
||
|
|
|
||
|
|
08000bf6 <HAL_DMA_Abort_IT>:
|
||
|
|
* @param hdma pointer to a DMA_HandleTypeDef structure that contains
|
||
|
|
* the configuration information for the specified DMA Channel.
|
||
|
|
* @retval HAL status
|
||
|
|
*/
|
||
|
|
HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma)
|
||
|
|
{
|
||
|
|
8000bf6: b580 push {r7, lr}
|
||
|
|
8000bf8: b084 sub sp, #16
|
||
|
|
8000bfa: af00 add r7, sp, #0
|
||
|
|
8000bfc: 6078 str r0, [r7, #4]
|
||
|
|
HAL_StatusTypeDef status = HAL_OK;
|
||
|
|
8000bfe: 230f movs r3, #15
|
||
|
|
8000c00: 18fb adds r3, r7, r3
|
||
|
|
8000c02: 2200 movs r2, #0
|
||
|
|
8000c04: 701a strb r2, [r3, #0]
|
||
|
|
|
||
|
|
if(HAL_DMA_STATE_BUSY != hdma->State)
|
||
|
|
8000c06: 687b ldr r3, [r7, #4]
|
||
|
|
8000c08: 2225 movs r2, #37 ; 0x25
|
||
|
|
8000c0a: 5c9b ldrb r3, [r3, r2]
|
||
|
|
8000c0c: b2db uxtb r3, r3
|
||
|
|
8000c0e: 2b02 cmp r3, #2
|
||
|
|
8000c10: d007 beq.n 8000c22 <HAL_DMA_Abort_IT+0x2c>
|
||
|
|
{
|
||
|
|
/* no transfer ongoing */
|
||
|
|
hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
|
||
|
|
8000c12: 687b ldr r3, [r7, #4]
|
||
|
|
8000c14: 2204 movs r2, #4
|
||
|
|
8000c16: 63da str r2, [r3, #60] ; 0x3c
|
||
|
|
|
||
|
|
status = HAL_ERROR;
|
||
|
|
8000c18: 230f movs r3, #15
|
||
|
|
8000c1a: 18fb adds r3, r7, r3
|
||
|
|
8000c1c: 2201 movs r2, #1
|
||
|
|
8000c1e: 701a strb r2, [r3, #0]
|
||
|
|
8000c20: e02a b.n 8000c78 <HAL_DMA_Abort_IT+0x82>
|
||
|
|
}
|
||
|
|
else
|
||
|
|
{
|
||
|
|
/* Disable DMA IT */
|
||
|
|
__HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));
|
||
|
|
8000c22: 687b ldr r3, [r7, #4]
|
||
|
|
8000c24: 681b ldr r3, [r3, #0]
|
||
|
|
8000c26: 687a ldr r2, [r7, #4]
|
||
|
|
8000c28: 6812 ldr r2, [r2, #0]
|
||
|
|
8000c2a: 6812 ldr r2, [r2, #0]
|
||
|
|
8000c2c: 210e movs r1, #14
|
||
|
|
8000c2e: 438a bics r2, r1
|
||
|
|
8000c30: 601a str r2, [r3, #0]
|
||
|
|
|
||
|
|
/* Disable the channel */
|
||
|
|
__HAL_DMA_DISABLE(hdma);
|
||
|
|
8000c32: 687b ldr r3, [r7, #4]
|
||
|
|
8000c34: 681b ldr r3, [r3, #0]
|
||
|
|
8000c36: 687a ldr r2, [r7, #4]
|
||
|
|
8000c38: 6812 ldr r2, [r2, #0]
|
||
|
|
8000c3a: 6812 ldr r2, [r2, #0]
|
||
|
|
8000c3c: 2101 movs r1, #1
|
||
|
|
8000c3e: 438a bics r2, r1
|
||
|
|
8000c40: 601a str r2, [r3, #0]
|
||
|
|
|
||
|
|
/* Clear all flags */
|
||
|
|
hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1cU));
|
||
|
|
8000c42: 687b ldr r3, [r7, #4]
|
||
|
|
8000c44: 6c1b ldr r3, [r3, #64] ; 0x40
|
||
|
|
8000c46: 687a ldr r2, [r7, #4]
|
||
|
|
8000c48: 6c52 ldr r2, [r2, #68] ; 0x44
|
||
|
|
8000c4a: 211c movs r1, #28
|
||
|
|
8000c4c: 400a ands r2, r1
|
||
|
|
8000c4e: 2101 movs r1, #1
|
||
|
|
8000c50: 4091 lsls r1, r2
|
||
|
|
8000c52: 000a movs r2, r1
|
||
|
|
8000c54: 605a str r2, [r3, #4]
|
||
|
|
|
||
|
|
/* Change the DMA state */
|
||
|
|
hdma->State = HAL_DMA_STATE_READY;
|
||
|
|
8000c56: 687b ldr r3, [r7, #4]
|
||
|
|
8000c58: 2225 movs r2, #37 ; 0x25
|
||
|
|
8000c5a: 2101 movs r1, #1
|
||
|
|
8000c5c: 5499 strb r1, [r3, r2]
|
||
|
|
|
||
|
|
/* Process Unlocked */
|
||
|
|
__HAL_UNLOCK(hdma);
|
||
|
|
8000c5e: 687b ldr r3, [r7, #4]
|
||
|
|
8000c60: 2224 movs r2, #36 ; 0x24
|
||
|
|
8000c62: 2100 movs r1, #0
|
||
|
|
8000c64: 5499 strb r1, [r3, r2]
|
||
|
|
|
||
|
|
/* Call User Abort callback */
|
||
|
|
if(hdma->XferAbortCallback != NULL)
|
||
|
|
8000c66: 687b ldr r3, [r7, #4]
|
||
|
|
8000c68: 6b9b ldr r3, [r3, #56] ; 0x38
|
||
|
|
8000c6a: 2b00 cmp r3, #0
|
||
|
|
8000c6c: d004 beq.n 8000c78 <HAL_DMA_Abort_IT+0x82>
|
||
|
|
{
|
||
|
|
hdma->XferAbortCallback(hdma);
|
||
|
|
8000c6e: 687b ldr r3, [r7, #4]
|
||
|
|
8000c70: 6b9b ldr r3, [r3, #56] ; 0x38
|
||
|
|
8000c72: 687a ldr r2, [r7, #4]
|
||
|
|
8000c74: 0010 movs r0, r2
|
||
|
|
8000c76: 4798 blx r3
|
||
|
|
}
|
||
|
|
}
|
||
|
|
return status;
|
||
|
|
8000c78: 230f movs r3, #15
|
||
|
|
8000c7a: 18fb adds r3, r7, r3
|
||
|
|
8000c7c: 781b ldrb r3, [r3, #0]
|
||
|
|
}
|
||
|
|
8000c7e: 0018 movs r0, r3
|
||
|
|
8000c80: 46bd mov sp, r7
|
||
|
|
8000c82: b004 add sp, #16
|
||
|
|
8000c84: bd80 pop {r7, pc}
|
||
|
|
...
|
||
|
|
|
||
|
|
08000c88 <HAL_GPIO_Init>:
|
||
|
|
* @param GPIO_Init pointer to a GPIO_InitTypeDef structure that contains
|
||
|
|
* the configuration information for the specified GPIO peripheral.
|
||
|
|
* @retval None
|
||
|
|
*/
|
||
|
|
void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init)
|
||
|
|
{
|
||
|
|
8000c88: b580 push {r7, lr}
|
||
|
|
8000c8a: b086 sub sp, #24
|
||
|
|
8000c8c: af00 add r7, sp, #0
|
||
|
|
8000c8e: 6078 str r0, [r7, #4]
|
||
|
|
8000c90: 6039 str r1, [r7, #0]
|
||
|
|
uint32_t position = 0x00U;
|
||
|
|
8000c92: 2300 movs r3, #0
|
||
|
|
8000c94: 617b str r3, [r7, #20]
|
||
|
|
uint32_t iocurrent = 0x00U;
|
||
|
|
8000c96: 2300 movs r3, #0
|
||
|
|
8000c98: 60fb str r3, [r7, #12]
|
||
|
|
uint32_t temp = 0x00U;
|
||
|
|
8000c9a: 2300 movs r3, #0
|
||
|
|
8000c9c: 613b str r3, [r7, #16]
|
||
|
|
assert_param(IS_GPIO_MODE(GPIO_Init->Mode));
|
||
|
|
assert_param(IS_GPIO_PULL(GPIO_Init->Pull));
|
||
|
|
assert_param(IS_GPIO_PIN_AVAILABLE(GPIOx, (GPIO_Init->Pin)));
|
||
|
|
|
||
|
|
/* Configure the port pins */
|
||
|
|
while (((GPIO_Init->Pin) >> position) != 0)
|
||
|
|
8000c9e: e155 b.n 8000f4c <HAL_GPIO_Init+0x2c4>
|
||
|
|
{
|
||
|
|
/* Get the IO position */
|
||
|
|
iocurrent = (GPIO_Init->Pin) & (1U << position);
|
||
|
|
8000ca0: 683b ldr r3, [r7, #0]
|
||
|
|
8000ca2: 681b ldr r3, [r3, #0]
|
||
|
|
8000ca4: 2101 movs r1, #1
|
||
|
|
8000ca6: 697a ldr r2, [r7, #20]
|
||
|
|
8000ca8: 4091 lsls r1, r2
|
||
|
|
8000caa: 000a movs r2, r1
|
||
|
|
8000cac: 4013 ands r3, r2
|
||
|
|
8000cae: 60fb str r3, [r7, #12]
|
||
|
|
|
||
|
|
if (iocurrent)
|
||
|
|
8000cb0: 68fb ldr r3, [r7, #12]
|
||
|
|
8000cb2: 2b00 cmp r3, #0
|
||
|
|
8000cb4: d100 bne.n 8000cb8 <HAL_GPIO_Init+0x30>
|
||
|
|
8000cb6: e146 b.n 8000f46 <HAL_GPIO_Init+0x2be>
|
||
|
|
{
|
||
|
|
/*--------------------- GPIO Mode Configuration ------------------------*/
|
||
|
|
/* In case of Output or Alternate function mode selection */
|
||
|
|
if ((GPIO_Init->Mode == GPIO_MODE_OUTPUT_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_PP) ||
|
||
|
|
8000cb8: 683b ldr r3, [r7, #0]
|
||
|
|
8000cba: 685b ldr r3, [r3, #4]
|
||
|
|
8000cbc: 2b01 cmp r3, #1
|
||
|
|
8000cbe: d00b beq.n 8000cd8 <HAL_GPIO_Init+0x50>
|
||
|
|
8000cc0: 683b ldr r3, [r7, #0]
|
||
|
|
8000cc2: 685b ldr r3, [r3, #4]
|
||
|
|
8000cc4: 2b02 cmp r3, #2
|
||
|
|
8000cc6: d007 beq.n 8000cd8 <HAL_GPIO_Init+0x50>
|
||
|
|
(GPIO_Init->Mode == GPIO_MODE_OUTPUT_OD) || (GPIO_Init->Mode == GPIO_MODE_AF_OD))
|
||
|
|
8000cc8: 683b ldr r3, [r7, #0]
|
||
|
|
8000cca: 685b ldr r3, [r3, #4]
|
||
|
|
if ((GPIO_Init->Mode == GPIO_MODE_OUTPUT_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_PP) ||
|
||
|
|
8000ccc: 2b11 cmp r3, #17
|
||
|
|
8000cce: d003 beq.n 8000cd8 <HAL_GPIO_Init+0x50>
|
||
|
|
(GPIO_Init->Mode == GPIO_MODE_OUTPUT_OD) || (GPIO_Init->Mode == GPIO_MODE_AF_OD))
|
||
|
|
8000cd0: 683b ldr r3, [r7, #0]
|
||
|
|
8000cd2: 685b ldr r3, [r3, #4]
|
||
|
|
8000cd4: 2b12 cmp r3, #18
|
||
|
|
8000cd6: d130 bne.n 8000d3a <HAL_GPIO_Init+0xb2>
|
||
|
|
{
|
||
|
|
/* Check the Speed parameter */
|
||
|
|
assert_param(IS_GPIO_SPEED(GPIO_Init->Speed));
|
||
|
|
/* Configure the IO Speed */
|
||
|
|
temp = GPIOx->OSPEEDR;
|
||
|
|
8000cd8: 687b ldr r3, [r7, #4]
|
||
|
|
8000cda: 689b ldr r3, [r3, #8]
|
||
|
|
8000cdc: 613b str r3, [r7, #16]
|
||
|
|
temp &= ~(GPIO_OSPEEDER_OSPEED0 << (position * 2U));
|
||
|
|
8000cde: 697b ldr r3, [r7, #20]
|
||
|
|
8000ce0: 005b lsls r3, r3, #1
|
||
|
|
8000ce2: 2203 movs r2, #3
|
||
|
|
8000ce4: 409a lsls r2, r3
|
||
|
|
8000ce6: 0013 movs r3, r2
|
||
|
|
8000ce8: 43da mvns r2, r3
|
||
|
|
8000cea: 693b ldr r3, [r7, #16]
|
||
|
|
8000cec: 4013 ands r3, r2
|
||
|
|
8000cee: 613b str r3, [r7, #16]
|
||
|
|
temp |= (GPIO_Init->Speed << (position * 2U));
|
||
|
|
8000cf0: 683b ldr r3, [r7, #0]
|
||
|
|
8000cf2: 68da ldr r2, [r3, #12]
|
||
|
|
8000cf4: 697b ldr r3, [r7, #20]
|
||
|
|
8000cf6: 005b lsls r3, r3, #1
|
||
|
|
8000cf8: 409a lsls r2, r3
|
||
|
|
8000cfa: 0013 movs r3, r2
|
||
|
|
8000cfc: 693a ldr r2, [r7, #16]
|
||
|
|
8000cfe: 4313 orrs r3, r2
|
||
|
|
8000d00: 613b str r3, [r7, #16]
|
||
|
|
GPIOx->OSPEEDR = temp;
|
||
|
|
8000d02: 687b ldr r3, [r7, #4]
|
||
|
|
8000d04: 693a ldr r2, [r7, #16]
|
||
|
|
8000d06: 609a str r2, [r3, #8]
|
||
|
|
|
||
|
|
/* Configure the IO Output Type */
|
||
|
|
temp = GPIOx->OTYPER;
|
||
|
|
8000d08: 687b ldr r3, [r7, #4]
|
||
|
|
8000d0a: 685b ldr r3, [r3, #4]
|
||
|
|
8000d0c: 613b str r3, [r7, #16]
|
||
|
|
temp &= ~(GPIO_OTYPER_OT_0 << position) ;
|
||
|
|
8000d0e: 2201 movs r2, #1
|
||
|
|
8000d10: 697b ldr r3, [r7, #20]
|
||
|
|
8000d12: 409a lsls r2, r3
|
||
|
|
8000d14: 0013 movs r3, r2
|
||
|
|
8000d16: 43da mvns r2, r3
|
||
|
|
8000d18: 693b ldr r3, [r7, #16]
|
||
|
|
8000d1a: 4013 ands r3, r2
|
||
|
|
8000d1c: 613b str r3, [r7, #16]
|
||
|
|
temp |= (((GPIO_Init->Mode & GPIO_OUTPUT_TYPE) >> 4U) << position);
|
||
|
|
8000d1e: 683b ldr r3, [r7, #0]
|
||
|
|
8000d20: 685b ldr r3, [r3, #4]
|
||
|
|
8000d22: 091b lsrs r3, r3, #4
|
||
|
|
8000d24: 2201 movs r2, #1
|
||
|
|
8000d26: 401a ands r2, r3
|
||
|
|
8000d28: 697b ldr r3, [r7, #20]
|
||
|
|
8000d2a: 409a lsls r2, r3
|
||
|
|
8000d2c: 0013 movs r3, r2
|
||
|
|
8000d2e: 693a ldr r2, [r7, #16]
|
||
|
|
8000d30: 4313 orrs r3, r2
|
||
|
|
8000d32: 613b str r3, [r7, #16]
|
||
|
|
GPIOx->OTYPER = temp;
|
||
|
|
8000d34: 687b ldr r3, [r7, #4]
|
||
|
|
8000d36: 693a ldr r2, [r7, #16]
|
||
|
|
8000d38: 605a str r2, [r3, #4]
|
||
|
|
}
|
||
|
|
|
||
|
|
/* Activate the Pull-up or Pull down resistor for the current IO */
|
||
|
|
temp = GPIOx->PUPDR;
|
||
|
|
8000d3a: 687b ldr r3, [r7, #4]
|
||
|
|
8000d3c: 68db ldr r3, [r3, #12]
|
||
|
|
8000d3e: 613b str r3, [r7, #16]
|
||
|
|
temp &= ~(GPIO_PUPDR_PUPD0 << (position * 2U));
|
||
|
|
8000d40: 697b ldr r3, [r7, #20]
|
||
|
|
8000d42: 005b lsls r3, r3, #1
|
||
|
|
8000d44: 2203 movs r2, #3
|
||
|
|
8000d46: 409a lsls r2, r3
|
||
|
|
8000d48: 0013 movs r3, r2
|
||
|
|
8000d4a: 43da mvns r2, r3
|
||
|
|
8000d4c: 693b ldr r3, [r7, #16]
|
||
|
|
8000d4e: 4013 ands r3, r2
|
||
|
|
8000d50: 613b str r3, [r7, #16]
|
||
|
|
temp |= ((GPIO_Init->Pull) << (position * 2U));
|
||
|
|
8000d52: 683b ldr r3, [r7, #0]
|
||
|
|
8000d54: 689a ldr r2, [r3, #8]
|
||
|
|
8000d56: 697b ldr r3, [r7, #20]
|
||
|
|
8000d58: 005b lsls r3, r3, #1
|
||
|
|
8000d5a: 409a lsls r2, r3
|
||
|
|
8000d5c: 0013 movs r3, r2
|
||
|
|
8000d5e: 693a ldr r2, [r7, #16]
|
||
|
|
8000d60: 4313 orrs r3, r2
|
||
|
|
8000d62: 613b str r3, [r7, #16]
|
||
|
|
GPIOx->PUPDR = temp;
|
||
|
|
8000d64: 687b ldr r3, [r7, #4]
|
||
|
|
8000d66: 693a ldr r2, [r7, #16]
|
||
|
|
8000d68: 60da str r2, [r3, #12]
|
||
|
|
|
||
|
|
/* In case of Alternate function mode selection */
|
||
|
|
if ((GPIO_Init->Mode == GPIO_MODE_AF_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_OD))
|
||
|
|
8000d6a: 683b ldr r3, [r7, #0]
|
||
|
|
8000d6c: 685b ldr r3, [r3, #4]
|
||
|
|
8000d6e: 2b02 cmp r3, #2
|
||
|
|
8000d70: d003 beq.n 8000d7a <HAL_GPIO_Init+0xf2>
|
||
|
|
8000d72: 683b ldr r3, [r7, #0]
|
||
|
|
8000d74: 685b ldr r3, [r3, #4]
|
||
|
|
8000d76: 2b12 cmp r3, #18
|
||
|
|
8000d78: d123 bne.n 8000dc2 <HAL_GPIO_Init+0x13a>
|
||
|
|
/* Check the Alternate function parameters */
|
||
|
|
assert_param(IS_GPIO_AF_INSTANCE(GPIOx));
|
||
|
|
assert_param(IS_GPIO_AF(GPIO_Init->Alternate));
|
||
|
|
|
||
|
|
/* Configure Alternate function mapped with the current IO */
|
||
|
|
temp = GPIOx->AFR[position >> 3U];
|
||
|
|
8000d7a: 697b ldr r3, [r7, #20]
|
||
|
|
8000d7c: 08da lsrs r2, r3, #3
|
||
|
|
8000d7e: 687b ldr r3, [r7, #4]
|
||
|
|
8000d80: 3208 adds r2, #8
|
||
|
|
8000d82: 0092 lsls r2, r2, #2
|
||
|
|
8000d84: 58d3 ldr r3, [r2, r3]
|
||
|
|
8000d86: 613b str r3, [r7, #16]
|
||
|
|
temp &= ~(0xFUL << ((uint32_t)(position & 0x07UL) * 4U));
|
||
|
|
8000d88: 697b ldr r3, [r7, #20]
|
||
|
|
8000d8a: 2207 movs r2, #7
|
||
|
|
8000d8c: 4013 ands r3, r2
|
||
|
|
8000d8e: 009b lsls r3, r3, #2
|
||
|
|
8000d90: 220f movs r2, #15
|
||
|
|
8000d92: 409a lsls r2, r3
|
||
|
|
8000d94: 0013 movs r3, r2
|
||
|
|
8000d96: 43da mvns r2, r3
|
||
|
|
8000d98: 693b ldr r3, [r7, #16]
|
||
|
|
8000d9a: 4013 ands r3, r2
|
||
|
|
8000d9c: 613b str r3, [r7, #16]
|
||
|
|
temp |= ((uint32_t)(GPIO_Init->Alternate) << (((uint32_t)position & (uint32_t)0x07U) * 4U));
|
||
|
|
8000d9e: 683b ldr r3, [r7, #0]
|
||
|
|
8000da0: 691a ldr r2, [r3, #16]
|
||
|
|
8000da2: 697b ldr r3, [r7, #20]
|
||
|
|
8000da4: 2107 movs r1, #7
|
||
|
|
8000da6: 400b ands r3, r1
|
||
|
|
8000da8: 009b lsls r3, r3, #2
|
||
|
|
8000daa: 409a lsls r2, r3
|
||
|
|
8000dac: 0013 movs r3, r2
|
||
|
|
8000dae: 693a ldr r2, [r7, #16]
|
||
|
|
8000db0: 4313 orrs r3, r2
|
||
|
|
8000db2: 613b str r3, [r7, #16]
|
||
|
|
GPIOx->AFR[position >> 3U] = temp;
|
||
|
|
8000db4: 697b ldr r3, [r7, #20]
|
||
|
|
8000db6: 08da lsrs r2, r3, #3
|
||
|
|
8000db8: 687b ldr r3, [r7, #4]
|
||
|
|
8000dba: 3208 adds r2, #8
|
||
|
|
8000dbc: 0092 lsls r2, r2, #2
|
||
|
|
8000dbe: 6939 ldr r1, [r7, #16]
|
||
|
|
8000dc0: 50d1 str r1, [r2, r3]
|
||
|
|
}
|
||
|
|
|
||
|
|
/* Configure IO Direction mode (Input, Output, Alternate or Analog) */
|
||
|
|
temp = GPIOx->MODER;
|
||
|
|
8000dc2: 687b ldr r3, [r7, #4]
|
||
|
|
8000dc4: 681b ldr r3, [r3, #0]
|
||
|
|
8000dc6: 613b str r3, [r7, #16]
|
||
|
|
temp &= ~(GPIO_MODER_MODE0 << (position * 2U));
|
||
|
|
8000dc8: 697b ldr r3, [r7, #20]
|
||
|
|
8000dca: 005b lsls r3, r3, #1
|
||
|
|
8000dcc: 2203 movs r2, #3
|
||
|
|
8000dce: 409a lsls r2, r3
|
||
|
|
8000dd0: 0013 movs r3, r2
|
||
|
|
8000dd2: 43da mvns r2, r3
|
||
|
|
8000dd4: 693b ldr r3, [r7, #16]
|
||
|
|
8000dd6: 4013 ands r3, r2
|
||
|
|
8000dd8: 613b str r3, [r7, #16]
|
||
|
|
temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2U));
|
||
|
|
8000dda: 683b ldr r3, [r7, #0]
|
||
|
|
8000ddc: 685b ldr r3, [r3, #4]
|
||
|
|
8000dde: 2203 movs r2, #3
|
||
|
|
8000de0: 401a ands r2, r3
|
||
|
|
8000de2: 697b ldr r3, [r7, #20]
|
||
|
|
8000de4: 005b lsls r3, r3, #1
|
||
|
|
8000de6: 409a lsls r2, r3
|
||
|
|
8000de8: 0013 movs r3, r2
|
||
|
|
8000dea: 693a ldr r2, [r7, #16]
|
||
|
|
8000dec: 4313 orrs r3, r2
|
||
|
|
8000dee: 613b str r3, [r7, #16]
|
||
|
|
GPIOx->MODER = temp;
|
||
|
|
8000df0: 687b ldr r3, [r7, #4]
|
||
|
|
8000df2: 693a ldr r2, [r7, #16]
|
||
|
|
8000df4: 601a str r2, [r3, #0]
|
||
|
|
|
||
|
|
/*--------------------- EXTI Mode Configuration ------------------------*/
|
||
|
|
/* Configure the External Interrupt or event for the current IO */
|
||
|
|
if ((GPIO_Init->Mode & EXTI_MODE) == EXTI_MODE)
|
||
|
|
8000df6: 683b ldr r3, [r7, #0]
|
||
|
|
8000df8: 685a ldr r2, [r3, #4]
|
||
|
|
8000dfa: 2380 movs r3, #128 ; 0x80
|
||
|
|
8000dfc: 055b lsls r3, r3, #21
|
||
|
|
8000dfe: 4013 ands r3, r2
|
||
|
|
8000e00: d100 bne.n 8000e04 <HAL_GPIO_Init+0x17c>
|
||
|
|
8000e02: e0a0 b.n 8000f46 <HAL_GPIO_Init+0x2be>
|
||
|
|
{
|
||
|
|
/* Enable SYSCFG Clock */
|
||
|
|
__HAL_RCC_SYSCFG_CLK_ENABLE();
|
||
|
|
8000e04: 4b57 ldr r3, [pc, #348] ; (8000f64 <HAL_GPIO_Init+0x2dc>)
|
||
|
|
8000e06: 4a57 ldr r2, [pc, #348] ; (8000f64 <HAL_GPIO_Init+0x2dc>)
|
||
|
|
8000e08: 6b52 ldr r2, [r2, #52] ; 0x34
|
||
|
|
8000e0a: 2101 movs r1, #1
|
||
|
|
8000e0c: 430a orrs r2, r1
|
||
|
|
8000e0e: 635a str r2, [r3, #52] ; 0x34
|
||
|
|
|
||
|
|
temp = SYSCFG->EXTICR[position >> 2U];
|
||
|
|
8000e10: 4a55 ldr r2, [pc, #340] ; (8000f68 <HAL_GPIO_Init+0x2e0>)
|
||
|
|
8000e12: 697b ldr r3, [r7, #20]
|
||
|
|
8000e14: 089b lsrs r3, r3, #2
|
||
|
|
8000e16: 3302 adds r3, #2
|
||
|
|
8000e18: 009b lsls r3, r3, #2
|
||
|
|
8000e1a: 589b ldr r3, [r3, r2]
|
||
|
|
8000e1c: 613b str r3, [r7, #16]
|
||
|
|
CLEAR_BIT(temp, (0x0FUL) << (4U * (position & 0x03U)));
|
||
|
|
8000e1e: 697b ldr r3, [r7, #20]
|
||
|
|
8000e20: 2203 movs r2, #3
|
||
|
|
8000e22: 4013 ands r3, r2
|
||
|
|
8000e24: 009b lsls r3, r3, #2
|
||
|
|
8000e26: 220f movs r2, #15
|
||
|
|
8000e28: 409a lsls r2, r3
|
||
|
|
8000e2a: 0013 movs r3, r2
|
||
|
|
8000e2c: 43da mvns r2, r3
|
||
|
|
8000e2e: 693b ldr r3, [r7, #16]
|
||
|
|
8000e30: 4013 ands r3, r2
|
||
|
|
8000e32: 613b str r3, [r7, #16]
|
||
|
|
SET_BIT(temp, (GPIO_GET_INDEX(GPIOx)) << (4 * (position & 0x03U)));
|
||
|
|
8000e34: 687a ldr r2, [r7, #4]
|
||
|
|
8000e36: 23a0 movs r3, #160 ; 0xa0
|
||
|
|
8000e38: 05db lsls r3, r3, #23
|
||
|
|
8000e3a: 429a cmp r2, r3
|
||
|
|
8000e3c: d01f beq.n 8000e7e <HAL_GPIO_Init+0x1f6>
|
||
|
|
8000e3e: 687b ldr r3, [r7, #4]
|
||
|
|
8000e40: 4a4a ldr r2, [pc, #296] ; (8000f6c <HAL_GPIO_Init+0x2e4>)
|
||
|
|
8000e42: 4293 cmp r3, r2
|
||
|
|
8000e44: d019 beq.n 8000e7a <HAL_GPIO_Init+0x1f2>
|
||
|
|
8000e46: 687b ldr r3, [r7, #4]
|
||
|
|
8000e48: 4a49 ldr r2, [pc, #292] ; (8000f70 <HAL_GPIO_Init+0x2e8>)
|
||
|
|
8000e4a: 4293 cmp r3, r2
|
||
|
|
8000e4c: d013 beq.n 8000e76 <HAL_GPIO_Init+0x1ee>
|
||
|
|
8000e4e: 687b ldr r3, [r7, #4]
|
||
|
|
8000e50: 4a48 ldr r2, [pc, #288] ; (8000f74 <HAL_GPIO_Init+0x2ec>)
|
||
|
|
8000e52: 4293 cmp r3, r2
|
||
|
|
8000e54: d00d beq.n 8000e72 <HAL_GPIO_Init+0x1ea>
|
||
|
|
8000e56: 687b ldr r3, [r7, #4]
|
||
|
|
8000e58: 4a47 ldr r2, [pc, #284] ; (8000f78 <HAL_GPIO_Init+0x2f0>)
|
||
|
|
8000e5a: 4293 cmp r3, r2
|
||
|
|
8000e5c: d007 beq.n 8000e6e <HAL_GPIO_Init+0x1e6>
|
||
|
|
8000e5e: 687b ldr r3, [r7, #4]
|
||
|
|
8000e60: 4a46 ldr r2, [pc, #280] ; (8000f7c <HAL_GPIO_Init+0x2f4>)
|
||
|
|
8000e62: 4293 cmp r3, r2
|
||
|
|
8000e64: d101 bne.n 8000e6a <HAL_GPIO_Init+0x1e2>
|
||
|
|
8000e66: 2305 movs r3, #5
|
||
|
|
8000e68: e00a b.n 8000e80 <HAL_GPIO_Init+0x1f8>
|
||
|
|
8000e6a: 2306 movs r3, #6
|
||
|
|
8000e6c: e008 b.n 8000e80 <HAL_GPIO_Init+0x1f8>
|
||
|
|
8000e6e: 2304 movs r3, #4
|
||
|
|
8000e70: e006 b.n 8000e80 <HAL_GPIO_Init+0x1f8>
|
||
|
|
8000e72: 2303 movs r3, #3
|
||
|
|
8000e74: e004 b.n 8000e80 <HAL_GPIO_Init+0x1f8>
|
||
|
|
8000e76: 2302 movs r3, #2
|
||
|
|
8000e78: e002 b.n 8000e80 <HAL_GPIO_Init+0x1f8>
|
||
|
|
8000e7a: 2301 movs r3, #1
|
||
|
|
8000e7c: e000 b.n 8000e80 <HAL_GPIO_Init+0x1f8>
|
||
|
|
8000e7e: 2300 movs r3, #0
|
||
|
|
8000e80: 697a ldr r2, [r7, #20]
|
||
|
|
8000e82: 2103 movs r1, #3
|
||
|
|
8000e84: 400a ands r2, r1
|
||
|
|
8000e86: 0092 lsls r2, r2, #2
|
||
|
|
8000e88: 4093 lsls r3, r2
|
||
|
|
8000e8a: 693a ldr r2, [r7, #16]
|
||
|
|
8000e8c: 4313 orrs r3, r2
|
||
|
|
8000e8e: 613b str r3, [r7, #16]
|
||
|
|
SYSCFG->EXTICR[position >> 2U] = temp;
|
||
|
|
8000e90: 4935 ldr r1, [pc, #212] ; (8000f68 <HAL_GPIO_Init+0x2e0>)
|
||
|
|
8000e92: 697b ldr r3, [r7, #20]
|
||
|
|
8000e94: 089b lsrs r3, r3, #2
|
||
|
|
8000e96: 3302 adds r3, #2
|
||
|
|
8000e98: 009b lsls r3, r3, #2
|
||
|
|
8000e9a: 693a ldr r2, [r7, #16]
|
||
|
|
8000e9c: 505a str r2, [r3, r1]
|
||
|
|
|
||
|
|
/* Clear EXTI line configuration */
|
||
|
|
temp = EXTI->IMR;
|
||
|
|
8000e9e: 4b38 ldr r3, [pc, #224] ; (8000f80 <HAL_GPIO_Init+0x2f8>)
|
||
|
|
8000ea0: 681b ldr r3, [r3, #0]
|
||
|
|
8000ea2: 613b str r3, [r7, #16]
|
||
|
|
temp &= ~((uint32_t)iocurrent);
|
||
|
|
8000ea4: 68fb ldr r3, [r7, #12]
|
||
|
|
8000ea6: 43da mvns r2, r3
|
||
|
|
8000ea8: 693b ldr r3, [r7, #16]
|
||
|
|
8000eaa: 4013 ands r3, r2
|
||
|
|
8000eac: 613b str r3, [r7, #16]
|
||
|
|
if ((GPIO_Init->Mode & GPIO_MODE_IT) == GPIO_MODE_IT)
|
||
|
|
8000eae: 683b ldr r3, [r7, #0]
|
||
|
|
8000eb0: 685a ldr r2, [r3, #4]
|
||
|
|
8000eb2: 2380 movs r3, #128 ; 0x80
|
||
|
|
8000eb4: 025b lsls r3, r3, #9
|
||
|
|
8000eb6: 4013 ands r3, r2
|
||
|
|
8000eb8: d003 beq.n 8000ec2 <HAL_GPIO_Init+0x23a>
|
||
|
|
{
|
||
|
|
temp |= iocurrent;
|
||
|
|
8000eba: 693a ldr r2, [r7, #16]
|
||
|
|
8000ebc: 68fb ldr r3, [r7, #12]
|
||
|
|
8000ebe: 4313 orrs r3, r2
|
||
|
|
8000ec0: 613b str r3, [r7, #16]
|
||
|
|
}
|
||
|
|
EXTI->IMR = temp;
|
||
|
|
8000ec2: 4b2f ldr r3, [pc, #188] ; (8000f80 <HAL_GPIO_Init+0x2f8>)
|
||
|
|
8000ec4: 693a ldr r2, [r7, #16]
|
||
|
|
8000ec6: 601a str r2, [r3, #0]
|
||
|
|
|
||
|
|
temp = EXTI->EMR;
|
||
|
|
8000ec8: 4b2d ldr r3, [pc, #180] ; (8000f80 <HAL_GPIO_Init+0x2f8>)
|
||
|
|
8000eca: 685b ldr r3, [r3, #4]
|
||
|
|
8000ecc: 613b str r3, [r7, #16]
|
||
|
|
temp &= ~((uint32_t)iocurrent);
|
||
|
|
8000ece: 68fb ldr r3, [r7, #12]
|
||
|
|
8000ed0: 43da mvns r2, r3
|
||
|
|
8000ed2: 693b ldr r3, [r7, #16]
|
||
|
|
8000ed4: 4013 ands r3, r2
|
||
|
|
8000ed6: 613b str r3, [r7, #16]
|
||
|
|
if ((GPIO_Init->Mode & GPIO_MODE_EVT) == GPIO_MODE_EVT)
|
||
|
|
8000ed8: 683b ldr r3, [r7, #0]
|
||
|
|
8000eda: 685a ldr r2, [r3, #4]
|
||
|
|
8000edc: 2380 movs r3, #128 ; 0x80
|
||
|
|
8000ede: 029b lsls r3, r3, #10
|
||
|
|
8000ee0: 4013 ands r3, r2
|
||
|
|
8000ee2: d003 beq.n 8000eec <HAL_GPIO_Init+0x264>
|
||
|
|
{
|
||
|
|
temp |= iocurrent;
|
||
|
|
8000ee4: 693a ldr r2, [r7, #16]
|
||
|
|
8000ee6: 68fb ldr r3, [r7, #12]
|
||
|
|
8000ee8: 4313 orrs r3, r2
|
||
|
|
8000eea: 613b str r3, [r7, #16]
|
||
|
|
}
|
||
|
|
EXTI->EMR = temp;
|
||
|
|
8000eec: 4b24 ldr r3, [pc, #144] ; (8000f80 <HAL_GPIO_Init+0x2f8>)
|
||
|
|
8000eee: 693a ldr r2, [r7, #16]
|
||
|
|
8000ef0: 605a str r2, [r3, #4]
|
||
|
|
|
||
|
|
/* Clear Rising Falling edge configuration */
|
||
|
|
temp = EXTI->RTSR;
|
||
|
|
8000ef2: 4b23 ldr r3, [pc, #140] ; (8000f80 <HAL_GPIO_Init+0x2f8>)
|
||
|
|
8000ef4: 689b ldr r3, [r3, #8]
|
||
|
|
8000ef6: 613b str r3, [r7, #16]
|
||
|
|
temp &= ~((uint32_t)iocurrent);
|
||
|
|
8000ef8: 68fb ldr r3, [r7, #12]
|
||
|
|
8000efa: 43da mvns r2, r3
|
||
|
|
8000efc: 693b ldr r3, [r7, #16]
|
||
|
|
8000efe: 4013 ands r3, r2
|
||
|
|
8000f00: 613b str r3, [r7, #16]
|
||
|
|
if ((GPIO_Init->Mode & RISING_EDGE) == RISING_EDGE)
|
||
|
|
8000f02: 683b ldr r3, [r7, #0]
|
||
|
|
8000f04: 685a ldr r2, [r3, #4]
|
||
|
|
8000f06: 2380 movs r3, #128 ; 0x80
|
||
|
|
8000f08: 035b lsls r3, r3, #13
|
||
|
|
8000f0a: 4013 ands r3, r2
|
||
|
|
8000f0c: d003 beq.n 8000f16 <HAL_GPIO_Init+0x28e>
|
||
|
|
{
|
||
|
|
temp |= iocurrent;
|
||
|
|
8000f0e: 693a ldr r2, [r7, #16]
|
||
|
|
8000f10: 68fb ldr r3, [r7, #12]
|
||
|
|
8000f12: 4313 orrs r3, r2
|
||
|
|
8000f14: 613b str r3, [r7, #16]
|
||
|
|
}
|
||
|
|
EXTI->RTSR = temp;
|
||
|
|
8000f16: 4b1a ldr r3, [pc, #104] ; (8000f80 <HAL_GPIO_Init+0x2f8>)
|
||
|
|
8000f18: 693a ldr r2, [r7, #16]
|
||
|
|
8000f1a: 609a str r2, [r3, #8]
|
||
|
|
|
||
|
|
temp = EXTI->FTSR;
|
||
|
|
8000f1c: 4b18 ldr r3, [pc, #96] ; (8000f80 <HAL_GPIO_Init+0x2f8>)
|
||
|
|
8000f1e: 68db ldr r3, [r3, #12]
|
||
|
|
8000f20: 613b str r3, [r7, #16]
|
||
|
|
temp &= ~((uint32_t)iocurrent);
|
||
|
|
8000f22: 68fb ldr r3, [r7, #12]
|
||
|
|
8000f24: 43da mvns r2, r3
|
||
|
|
8000f26: 693b ldr r3, [r7, #16]
|
||
|
|
8000f28: 4013 ands r3, r2
|
||
|
|
8000f2a: 613b str r3, [r7, #16]
|
||
|
|
if ((GPIO_Init->Mode & FALLING_EDGE) == FALLING_EDGE)
|
||
|
|
8000f2c: 683b ldr r3, [r7, #0]
|
||
|
|
8000f2e: 685a ldr r2, [r3, #4]
|
||
|
|
8000f30: 2380 movs r3, #128 ; 0x80
|
||
|
|
8000f32: 039b lsls r3, r3, #14
|
||
|
|
8000f34: 4013 ands r3, r2
|
||
|
|
8000f36: d003 beq.n 8000f40 <HAL_GPIO_Init+0x2b8>
|
||
|
|
{
|
||
|
|
temp |= iocurrent;
|
||
|
|
8000f38: 693a ldr r2, [r7, #16]
|
||
|
|
8000f3a: 68fb ldr r3, [r7, #12]
|
||
|
|
8000f3c: 4313 orrs r3, r2
|
||
|
|
8000f3e: 613b str r3, [r7, #16]
|
||
|
|
}
|
||
|
|
EXTI->FTSR = temp;
|
||
|
|
8000f40: 4b0f ldr r3, [pc, #60] ; (8000f80 <HAL_GPIO_Init+0x2f8>)
|
||
|
|
8000f42: 693a ldr r2, [r7, #16]
|
||
|
|
8000f44: 60da str r2, [r3, #12]
|
||
|
|
}
|
||
|
|
}
|
||
|
|
position++;
|
||
|
|
8000f46: 697b ldr r3, [r7, #20]
|
||
|
|
8000f48: 3301 adds r3, #1
|
||
|
|
8000f4a: 617b str r3, [r7, #20]
|
||
|
|
while (((GPIO_Init->Pin) >> position) != 0)
|
||
|
|
8000f4c: 683b ldr r3, [r7, #0]
|
||
|
|
8000f4e: 681a ldr r2, [r3, #0]
|
||
|
|
8000f50: 697b ldr r3, [r7, #20]
|
||
|
|
8000f52: 40da lsrs r2, r3
|
||
|
|
8000f54: 1e13 subs r3, r2, #0
|
||
|
|
8000f56: d000 beq.n 8000f5a <HAL_GPIO_Init+0x2d2>
|
||
|
|
8000f58: e6a2 b.n 8000ca0 <HAL_GPIO_Init+0x18>
|
||
|
|
}
|
||
|
|
}
|
||
|
|
8000f5a: 46c0 nop ; (mov r8, r8)
|
||
|
|
8000f5c: 46bd mov sp, r7
|
||
|
|
8000f5e: b006 add sp, #24
|
||
|
|
8000f60: bd80 pop {r7, pc}
|
||
|
|
8000f62: 46c0 nop ; (mov r8, r8)
|
||
|
|
8000f64: 40021000 .word 0x40021000
|
||
|
|
8000f68: 40010000 .word 0x40010000
|
||
|
|
8000f6c: 50000400 .word 0x50000400
|
||
|
|
8000f70: 50000800 .word 0x50000800
|
||
|
|
8000f74: 50000c00 .word 0x50000c00
|
||
|
|
8000f78: 50001000 .word 0x50001000
|
||
|
|
8000f7c: 50001c00 .word 0x50001c00
|
||
|
|
8000f80: 40010400 .word 0x40010400
|
||
|
|
|
||
|
|
08000f84 <HAL_GPIO_WritePin>:
|
||
|
|
* GPIO_PIN_RESET: to clear the port pin
|
||
|
|
* GPIO_PIN_SET: to set the port pin
|
||
|
|
* @retval None
|
||
|
|
*/
|
||
|
|
void HAL_GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState)
|
||
|
|
{
|
||
|
|
8000f84: b580 push {r7, lr}
|
||
|
|
8000f86: b082 sub sp, #8
|
||
|
|
8000f88: af00 add r7, sp, #0
|
||
|
|
8000f8a: 6078 str r0, [r7, #4]
|
||
|
|
8000f8c: 0008 movs r0, r1
|
||
|
|
8000f8e: 0011 movs r1, r2
|
||
|
|
8000f90: 1cbb adds r3, r7, #2
|
||
|
|
8000f92: 1c02 adds r2, r0, #0
|
||
|
|
8000f94: 801a strh r2, [r3, #0]
|
||
|
|
8000f96: 1c7b adds r3, r7, #1
|
||
|
|
8000f98: 1c0a adds r2, r1, #0
|
||
|
|
8000f9a: 701a strb r2, [r3, #0]
|
||
|
|
/* Check the parameters */
|
||
|
|
assert_param(IS_GPIO_PIN_AVAILABLE(GPIOx, GPIO_Pin));
|
||
|
|
assert_param(IS_GPIO_PIN_ACTION(PinState));
|
||
|
|
|
||
|
|
if (PinState != GPIO_PIN_RESET)
|
||
|
|
8000f9c: 1c7b adds r3, r7, #1
|
||
|
|
8000f9e: 781b ldrb r3, [r3, #0]
|
||
|
|
8000fa0: 2b00 cmp r3, #0
|
||
|
|
8000fa2: d004 beq.n 8000fae <HAL_GPIO_WritePin+0x2a>
|
||
|
|
{
|
||
|
|
GPIOx->BSRR = GPIO_Pin;
|
||
|
|
8000fa4: 1cbb adds r3, r7, #2
|
||
|
|
8000fa6: 881a ldrh r2, [r3, #0]
|
||
|
|
8000fa8: 687b ldr r3, [r7, #4]
|
||
|
|
8000faa: 619a str r2, [r3, #24]
|
||
|
|
}
|
||
|
|
else
|
||
|
|
{
|
||
|
|
GPIOx->BRR = GPIO_Pin ;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
8000fac: e003 b.n 8000fb6 <HAL_GPIO_WritePin+0x32>
|
||
|
|
GPIOx->BRR = GPIO_Pin ;
|
||
|
|
8000fae: 1cbb adds r3, r7, #2
|
||
|
|
8000fb0: 881a ldrh r2, [r3, #0]
|
||
|
|
8000fb2: 687b ldr r3, [r7, #4]
|
||
|
|
8000fb4: 629a str r2, [r3, #40] ; 0x28
|
||
|
|
}
|
||
|
|
8000fb6: 46c0 nop ; (mov r8, r8)
|
||
|
|
8000fb8: 46bd mov sp, r7
|
||
|
|
8000fba: b002 add sp, #8
|
||
|
|
8000fbc: bd80 pop {r7, pc}
|
||
|
|
...
|
||
|
|
|
||
|
|
08000fc0 <HAL_GPIO_EXTI_IRQHandler>:
|
||
|
|
* @brief This function handles EXTI interrupt request.
|
||
|
|
* @param GPIO_Pin Specifies the pins connected to the EXTI line.
|
||
|
|
* @retval None
|
||
|
|
*/
|
||
|
|
void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin)
|
||
|
|
{
|
||
|
|
8000fc0: b580 push {r7, lr}
|
||
|
|
8000fc2: b082 sub sp, #8
|
||
|
|
8000fc4: af00 add r7, sp, #0
|
||
|
|
8000fc6: 0002 movs r2, r0
|
||
|
|
8000fc8: 1dbb adds r3, r7, #6
|
||
|
|
8000fca: 801a strh r2, [r3, #0]
|
||
|
|
/* EXTI line interrupt detected */
|
||
|
|
if (__HAL_GPIO_EXTI_GET_IT(GPIO_Pin) != RESET)
|
||
|
|
8000fcc: 4b09 ldr r3, [pc, #36] ; (8000ff4 <HAL_GPIO_EXTI_IRQHandler+0x34>)
|
||
|
|
8000fce: 695b ldr r3, [r3, #20]
|
||
|
|
8000fd0: 1dba adds r2, r7, #6
|
||
|
|
8000fd2: 8812 ldrh r2, [r2, #0]
|
||
|
|
8000fd4: 4013 ands r3, r2
|
||
|
|
8000fd6: d008 beq.n 8000fea <HAL_GPIO_EXTI_IRQHandler+0x2a>
|
||
|
|
{
|
||
|
|
__HAL_GPIO_EXTI_CLEAR_IT(GPIO_Pin);
|
||
|
|
8000fd8: 4b06 ldr r3, [pc, #24] ; (8000ff4 <HAL_GPIO_EXTI_IRQHandler+0x34>)
|
||
|
|
8000fda: 1dba adds r2, r7, #6
|
||
|
|
8000fdc: 8812 ldrh r2, [r2, #0]
|
||
|
|
8000fde: 615a str r2, [r3, #20]
|
||
|
|
HAL_GPIO_EXTI_Callback(GPIO_Pin);
|
||
|
|
8000fe0: 1dbb adds r3, r7, #6
|
||
|
|
8000fe2: 881b ldrh r3, [r3, #0]
|
||
|
|
8000fe4: 0018 movs r0, r3
|
||
|
|
8000fe6: f000 f807 bl 8000ff8 <HAL_GPIO_EXTI_Callback>
|
||
|
|
}
|
||
|
|
}
|
||
|
|
8000fea: 46c0 nop ; (mov r8, r8)
|
||
|
|
8000fec: 46bd mov sp, r7
|
||
|
|
8000fee: b002 add sp, #8
|
||
|
|
8000ff0: bd80 pop {r7, pc}
|
||
|
|
8000ff2: 46c0 nop ; (mov r8, r8)
|
||
|
|
8000ff4: 40010400 .word 0x40010400
|
||
|
|
|
||
|
|
08000ff8 <HAL_GPIO_EXTI_Callback>:
|
||
|
|
* @brief EXTI line detection callbacks.
|
||
|
|
* @param GPIO_Pin Specifies the pins connected to the EXTI line.
|
||
|
|
* @retval None
|
||
|
|
*/
|
||
|
|
__weak void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin)
|
||
|
|
{
|
||
|
|
8000ff8: b580 push {r7, lr}
|
||
|
|
8000ffa: b082 sub sp, #8
|
||
|
|
8000ffc: af00 add r7, sp, #0
|
||
|
|
8000ffe: 0002 movs r2, r0
|
||
|
|
8001000: 1dbb adds r3, r7, #6
|
||
|
|
8001002: 801a strh r2, [r3, #0]
|
||
|
|
UNUSED(GPIO_Pin);
|
||
|
|
|
||
|
|
/* NOTE: This function Should not be modified, when the callback is needed,
|
||
|
|
the HAL_GPIO_EXTI_Callback could be implemented in the user file
|
||
|
|
*/
|
||
|
|
}
|
||
|
|
8001004: 46c0 nop ; (mov r8, r8)
|
||
|
|
8001006: 46bd mov sp, r7
|
||
|
|
8001008: b002 add sp, #8
|
||
|
|
800100a: bd80 pop {r7, pc}
|
||
|
|
|
||
|
|
0800100c <HAL_RCC_OscConfig>:
|
||
|
|
* supported by this macro. User should request a transition to HSE Off
|
||
|
|
* first and then HSE On or HSE Bypass.
|
||
|
|
* @retval HAL status
|
||
|
|
*/
|
||
|
|
HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
|
||
|
|
{
|
||
|
|
800100c: b590 push {r4, r7, lr}
|
||
|
|
800100e: b08b sub sp, #44 ; 0x2c
|
||
|
|
8001010: af00 add r7, sp, #0
|
||
|
|
8001012: 6078 str r0, [r7, #4]
|
||
|
|
uint32_t hsi_state;
|
||
|
|
HAL_StatusTypeDef status;
|
||
|
|
uint32_t sysclk_source, pll_config;
|
||
|
|
|
||
|
|
/* Check Null pointer */
|
||
|
|
if(RCC_OscInitStruct == NULL)
|
||
|
|
8001014: 687b ldr r3, [r7, #4]
|
||
|
|
8001016: 2b00 cmp r3, #0
|
||
|
|
8001018: d102 bne.n 8001020 <HAL_RCC_OscConfig+0x14>
|
||
|
|
{
|
||
|
|
return HAL_ERROR;
|
||
|
|
800101a: 2301 movs r3, #1
|
||
|
|
800101c: f000 fbbe bl 800179c <HAL_RCC_OscConfig+0x790>
|
||
|
|
}
|
||
|
|
|
||
|
|
/* Check the parameters */
|
||
|
|
assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType));
|
||
|
|
|
||
|
|
sysclk_source = __HAL_RCC_GET_SYSCLK_SOURCE();
|
||
|
|
8001020: 4bc9 ldr r3, [pc, #804] ; (8001348 <HAL_RCC_OscConfig+0x33c>)
|
||
|
|
8001022: 68db ldr r3, [r3, #12]
|
||
|
|
8001024: 220c movs r2, #12
|
||
|
|
8001026: 4013 ands r3, r2
|
||
|
|
8001028: 61fb str r3, [r7, #28]
|
||
|
|
pll_config = __HAL_RCC_GET_PLL_OSCSOURCE();
|
||
|
|
800102a: 4bc7 ldr r3, [pc, #796] ; (8001348 <HAL_RCC_OscConfig+0x33c>)
|
||
|
|
800102c: 68da ldr r2, [r3, #12]
|
||
|
|
800102e: 2380 movs r3, #128 ; 0x80
|
||
|
|
8001030: 025b lsls r3, r3, #9
|
||
|
|
8001032: 4013 ands r3, r2
|
||
|
|
8001034: 61bb str r3, [r7, #24]
|
||
|
|
|
||
|
|
/*------------------------------- HSE Configuration ------------------------*/
|
||
|
|
if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)
|
||
|
|
8001036: 687b ldr r3, [r7, #4]
|
||
|
|
8001038: 681b ldr r3, [r3, #0]
|
||
|
|
800103a: 2201 movs r2, #1
|
||
|
|
800103c: 4013 ands r3, r2
|
||
|
|
800103e: d100 bne.n 8001042 <HAL_RCC_OscConfig+0x36>
|
||
|
|
8001040: e07e b.n 8001140 <HAL_RCC_OscConfig+0x134>
|
||
|
|
{
|
||
|
|
/* Check the parameters */
|
||
|
|
assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState));
|
||
|
|
|
||
|
|
/* When the HSE is used as system clock or clock source for PLL in these cases it is not allowed to be disabled */
|
||
|
|
if((sysclk_source == RCC_SYSCLKSOURCE_STATUS_HSE)
|
||
|
|
8001042: 69fb ldr r3, [r7, #28]
|
||
|
|
8001044: 2b08 cmp r3, #8
|
||
|
|
8001046: d007 beq.n 8001058 <HAL_RCC_OscConfig+0x4c>
|
||
|
|
|| ((sysclk_source == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (pll_config == RCC_PLLSOURCE_HSE)))
|
||
|
|
8001048: 69fb ldr r3, [r7, #28]
|
||
|
|
800104a: 2b0c cmp r3, #12
|
||
|
|
800104c: d112 bne.n 8001074 <HAL_RCC_OscConfig+0x68>
|
||
|
|
800104e: 69ba ldr r2, [r7, #24]
|
||
|
|
8001050: 2380 movs r3, #128 ; 0x80
|
||
|
|
8001052: 025b lsls r3, r3, #9
|
||
|
|
8001054: 429a cmp r2, r3
|
||
|
|
8001056: d10d bne.n 8001074 <HAL_RCC_OscConfig+0x68>
|
||
|
|
{
|
||
|
|
if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != 0U) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
|
||
|
|
8001058: 4bbb ldr r3, [pc, #748] ; (8001348 <HAL_RCC_OscConfig+0x33c>)
|
||
|
|
800105a: 681a ldr r2, [r3, #0]
|
||
|
|
800105c: 2380 movs r3, #128 ; 0x80
|
||
|
|
800105e: 029b lsls r3, r3, #10
|
||
|
|
8001060: 4013 ands r3, r2
|
||
|
|
8001062: d100 bne.n 8001066 <HAL_RCC_OscConfig+0x5a>
|
||
|
|
8001064: e06b b.n 800113e <HAL_RCC_OscConfig+0x132>
|
||
|
|
8001066: 687b ldr r3, [r7, #4]
|
||
|
|
8001068: 685b ldr r3, [r3, #4]
|
||
|
|
800106a: 2b00 cmp r3, #0
|
||
|
|
800106c: d167 bne.n 800113e <HAL_RCC_OscConfig+0x132>
|
||
|
|
{
|
||
|
|
return HAL_ERROR;
|
||
|
|
800106e: 2301 movs r3, #1
|
||
|
|
8001070: f000 fb94 bl 800179c <HAL_RCC_OscConfig+0x790>
|
||
|
|
}
|
||
|
|
}
|
||
|
|
else
|
||
|
|
{
|
||
|
|
/* Set the new HSE configuration ---------------------------------------*/
|
||
|
|
__HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
|
||
|
|
8001074: 687b ldr r3, [r7, #4]
|
||
|
|
8001076: 685a ldr r2, [r3, #4]
|
||
|
|
8001078: 2380 movs r3, #128 ; 0x80
|
||
|
|
800107a: 025b lsls r3, r3, #9
|
||
|
|
800107c: 429a cmp r2, r3
|
||
|
|
800107e: d107 bne.n 8001090 <HAL_RCC_OscConfig+0x84>
|
||
|
|
8001080: 4bb1 ldr r3, [pc, #708] ; (8001348 <HAL_RCC_OscConfig+0x33c>)
|
||
|
|
8001082: 4ab1 ldr r2, [pc, #708] ; (8001348 <HAL_RCC_OscConfig+0x33c>)
|
||
|
|
8001084: 6812 ldr r2, [r2, #0]
|
||
|
|
8001086: 2180 movs r1, #128 ; 0x80
|
||
|
|
8001088: 0249 lsls r1, r1, #9
|
||
|
|
800108a: 430a orrs r2, r1
|
||
|
|
800108c: 601a str r2, [r3, #0]
|
||
|
|
800108e: e027 b.n 80010e0 <HAL_RCC_OscConfig+0xd4>
|
||
|
|
8001090: 687b ldr r3, [r7, #4]
|
||
|
|
8001092: 685a ldr r2, [r3, #4]
|
||
|
|
8001094: 23a0 movs r3, #160 ; 0xa0
|
||
|
|
8001096: 02db lsls r3, r3, #11
|
||
|
|
8001098: 429a cmp r2, r3
|
||
|
|
800109a: d10e bne.n 80010ba <HAL_RCC_OscConfig+0xae>
|
||
|
|
800109c: 4baa ldr r3, [pc, #680] ; (8001348 <HAL_RCC_OscConfig+0x33c>)
|
||
|
|
800109e: 4aaa ldr r2, [pc, #680] ; (8001348 <HAL_RCC_OscConfig+0x33c>)
|
||
|
|
80010a0: 6812 ldr r2, [r2, #0]
|
||
|
|
80010a2: 2180 movs r1, #128 ; 0x80
|
||
|
|
80010a4: 02c9 lsls r1, r1, #11
|
||
|
|
80010a6: 430a orrs r2, r1
|
||
|
|
80010a8: 601a str r2, [r3, #0]
|
||
|
|
80010aa: 4ba7 ldr r3, [pc, #668] ; (8001348 <HAL_RCC_OscConfig+0x33c>)
|
||
|
|
80010ac: 4aa6 ldr r2, [pc, #664] ; (8001348 <HAL_RCC_OscConfig+0x33c>)
|
||
|
|
80010ae: 6812 ldr r2, [r2, #0]
|
||
|
|
80010b0: 2180 movs r1, #128 ; 0x80
|
||
|
|
80010b2: 0249 lsls r1, r1, #9
|
||
|
|
80010b4: 430a orrs r2, r1
|
||
|
|
80010b6: 601a str r2, [r3, #0]
|
||
|
|
80010b8: e012 b.n 80010e0 <HAL_RCC_OscConfig+0xd4>
|
||
|
|
80010ba: 4ba3 ldr r3, [pc, #652] ; (8001348 <HAL_RCC_OscConfig+0x33c>)
|
||
|
|
80010bc: 4aa2 ldr r2, [pc, #648] ; (8001348 <HAL_RCC_OscConfig+0x33c>)
|
||
|
|
80010be: 6812 ldr r2, [r2, #0]
|
||
|
|
80010c0: 49a2 ldr r1, [pc, #648] ; (800134c <HAL_RCC_OscConfig+0x340>)
|
||
|
|
80010c2: 400a ands r2, r1
|
||
|
|
80010c4: 601a str r2, [r3, #0]
|
||
|
|
80010c6: 4ba0 ldr r3, [pc, #640] ; (8001348 <HAL_RCC_OscConfig+0x33c>)
|
||
|
|
80010c8: 681a ldr r2, [r3, #0]
|
||
|
|
80010ca: 2380 movs r3, #128 ; 0x80
|
||
|
|
80010cc: 025b lsls r3, r3, #9
|
||
|
|
80010ce: 4013 ands r3, r2
|
||
|
|
80010d0: 60fb str r3, [r7, #12]
|
||
|
|
80010d2: 68fb ldr r3, [r7, #12]
|
||
|
|
80010d4: 4b9c ldr r3, [pc, #624] ; (8001348 <HAL_RCC_OscConfig+0x33c>)
|
||
|
|
80010d6: 4a9c ldr r2, [pc, #624] ; (8001348 <HAL_RCC_OscConfig+0x33c>)
|
||
|
|
80010d8: 6812 ldr r2, [r2, #0]
|
||
|
|
80010da: 499d ldr r1, [pc, #628] ; (8001350 <HAL_RCC_OscConfig+0x344>)
|
||
|
|
80010dc: 400a ands r2, r1
|
||
|
|
80010de: 601a str r2, [r3, #0]
|
||
|
|
|
||
|
|
/* Check the HSE State */
|
||
|
|
if(RCC_OscInitStruct->HSEState != RCC_HSE_OFF)
|
||
|
|
80010e0: 687b ldr r3, [r7, #4]
|
||
|
|
80010e2: 685b ldr r3, [r3, #4]
|
||
|
|
80010e4: 2b00 cmp r3, #0
|
||
|
|
80010e6: d015 beq.n 8001114 <HAL_RCC_OscConfig+0x108>
|
||
|
|
{
|
||
|
|
/* Get Start Tick */
|
||
|
|
tickstart = HAL_GetTick();
|
||
|
|
80010e8: f7ff fc5c bl 80009a4 <HAL_GetTick>
|
||
|
|
80010ec: 0003 movs r3, r0
|
||
|
|
80010ee: 617b str r3, [r7, #20]
|
||
|
|
|
||
|
|
/* Wait till HSE is ready */
|
||
|
|
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == 0U)
|
||
|
|
80010f0: e009 b.n 8001106 <HAL_RCC_OscConfig+0xfa>
|
||
|
|
{
|
||
|
|
if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
|
||
|
|
80010f2: f7ff fc57 bl 80009a4 <HAL_GetTick>
|
||
|
|
80010f6: 0002 movs r2, r0
|
||
|
|
80010f8: 697b ldr r3, [r7, #20]
|
||
|
|
80010fa: 1ad3 subs r3, r2, r3
|
||
|
|
80010fc: 2b64 cmp r3, #100 ; 0x64
|
||
|
|
80010fe: d902 bls.n 8001106 <HAL_RCC_OscConfig+0xfa>
|
||
|
|
{
|
||
|
|
return HAL_TIMEOUT;
|
||
|
|
8001100: 2303 movs r3, #3
|
||
|
|
8001102: f000 fb4b bl 800179c <HAL_RCC_OscConfig+0x790>
|
||
|
|
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == 0U)
|
||
|
|
8001106: 4b90 ldr r3, [pc, #576] ; (8001348 <HAL_RCC_OscConfig+0x33c>)
|
||
|
|
8001108: 681a ldr r2, [r3, #0]
|
||
|
|
800110a: 2380 movs r3, #128 ; 0x80
|
||
|
|
800110c: 029b lsls r3, r3, #10
|
||
|
|
800110e: 4013 ands r3, r2
|
||
|
|
8001110: d0ef beq.n 80010f2 <HAL_RCC_OscConfig+0xe6>
|
||
|
|
8001112: e015 b.n 8001140 <HAL_RCC_OscConfig+0x134>
|
||
|
|
}
|
||
|
|
}
|
||
|
|
else
|
||
|
|
{
|
||
|
|
/* Get Start Tick */
|
||
|
|
tickstart = HAL_GetTick();
|
||
|
|
8001114: f7ff fc46 bl 80009a4 <HAL_GetTick>
|
||
|
|
8001118: 0003 movs r3, r0
|
||
|
|
800111a: 617b str r3, [r7, #20]
|
||
|
|
|
||
|
|
/* Wait till HSE is disabled */
|
||
|
|
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != 0U)
|
||
|
|
800111c: e008 b.n 8001130 <HAL_RCC_OscConfig+0x124>
|
||
|
|
{
|
||
|
|
if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
|
||
|
|
800111e: f7ff fc41 bl 80009a4 <HAL_GetTick>
|
||
|
|
8001122: 0002 movs r2, r0
|
||
|
|
8001124: 697b ldr r3, [r7, #20]
|
||
|
|
8001126: 1ad3 subs r3, r2, r3
|
||
|
|
8001128: 2b64 cmp r3, #100 ; 0x64
|
||
|
|
800112a: d901 bls.n 8001130 <HAL_RCC_OscConfig+0x124>
|
||
|
|
{
|
||
|
|
return HAL_TIMEOUT;
|
||
|
|
800112c: 2303 movs r3, #3
|
||
|
|
800112e: e335 b.n 800179c <HAL_RCC_OscConfig+0x790>
|
||
|
|
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != 0U)
|
||
|
|
8001130: 4b85 ldr r3, [pc, #532] ; (8001348 <HAL_RCC_OscConfig+0x33c>)
|
||
|
|
8001132: 681a ldr r2, [r3, #0]
|
||
|
|
8001134: 2380 movs r3, #128 ; 0x80
|
||
|
|
8001136: 029b lsls r3, r3, #10
|
||
|
|
8001138: 4013 ands r3, r2
|
||
|
|
800113a: d1f0 bne.n 800111e <HAL_RCC_OscConfig+0x112>
|
||
|
|
800113c: e000 b.n 8001140 <HAL_RCC_OscConfig+0x134>
|
||
|
|
if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != 0U) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
|
||
|
|
800113e: 46c0 nop ; (mov r8, r8)
|
||
|
|
}
|
||
|
|
}
|
||
|
|
}
|
||
|
|
}
|
||
|
|
/*----------------------------- HSI Configuration --------------------------*/
|
||
|
|
if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI)
|
||
|
|
8001140: 687b ldr r3, [r7, #4]
|
||
|
|
8001142: 681b ldr r3, [r3, #0]
|
||
|
|
8001144: 2202 movs r2, #2
|
||
|
|
8001146: 4013 ands r3, r2
|
||
|
|
8001148: d100 bne.n 800114c <HAL_RCC_OscConfig+0x140>
|
||
|
|
800114a: e099 b.n 8001280 <HAL_RCC_OscConfig+0x274>
|
||
|
|
{
|
||
|
|
/* Check the parameters */
|
||
|
|
assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState));
|
||
|
|
assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue));
|
||
|
|
|
||
|
|
hsi_state = RCC_OscInitStruct->HSIState;
|
||
|
|
800114c: 687b ldr r3, [r7, #4]
|
||
|
|
800114e: 68db ldr r3, [r3, #12]
|
||
|
|
8001150: 627b str r3, [r7, #36] ; 0x24
|
||
|
|
|
||
|
|
#if defined(RCC_CR_HSIOUTEN)
|
||
|
|
if((hsi_state & RCC_HSI_OUTEN) != 0U)
|
||
|
|
8001152: 6a7b ldr r3, [r7, #36] ; 0x24
|
||
|
|
8001154: 2220 movs r2, #32
|
||
|
|
8001156: 4013 ands r3, r2
|
||
|
|
8001158: d009 beq.n 800116e <HAL_RCC_OscConfig+0x162>
|
||
|
|
{
|
||
|
|
/* HSI Output enable for timer requested */
|
||
|
|
SET_BIT(RCC->CR, RCC_CR_HSIOUTEN);
|
||
|
|
800115a: 4b7b ldr r3, [pc, #492] ; (8001348 <HAL_RCC_OscConfig+0x33c>)
|
||
|
|
800115c: 4a7a ldr r2, [pc, #488] ; (8001348 <HAL_RCC_OscConfig+0x33c>)
|
||
|
|
800115e: 6812 ldr r2, [r2, #0]
|
||
|
|
8001160: 2120 movs r1, #32
|
||
|
|
8001162: 430a orrs r2, r1
|
||
|
|
8001164: 601a str r2, [r3, #0]
|
||
|
|
|
||
|
|
hsi_state &= ~RCC_CR_HSIOUTEN;
|
||
|
|
8001166: 6a7b ldr r3, [r7, #36] ; 0x24
|
||
|
|
8001168: 2220 movs r2, #32
|
||
|
|
800116a: 4393 bics r3, r2
|
||
|
|
800116c: 627b str r3, [r7, #36] ; 0x24
|
||
|
|
}
|
||
|
|
#endif
|
||
|
|
|
||
|
|
/* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */
|
||
|
|
if((sysclk_source == RCC_SYSCLKSOURCE_STATUS_HSI)
|
||
|
|
800116e: 69fb ldr r3, [r7, #28]
|
||
|
|
8001170: 2b04 cmp r3, #4
|
||
|
|
8001172: d005 beq.n 8001180 <HAL_RCC_OscConfig+0x174>
|
||
|
|
|| ((sysclk_source == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (pll_config == RCC_PLLSOURCE_HSI)))
|
||
|
|
8001174: 69fb ldr r3, [r7, #28]
|
||
|
|
8001176: 2b0c cmp r3, #12
|
||
|
|
8001178: d13f bne.n 80011fa <HAL_RCC_OscConfig+0x1ee>
|
||
|
|
800117a: 69bb ldr r3, [r7, #24]
|
||
|
|
800117c: 2b00 cmp r3, #0
|
||
|
|
800117e: d13c bne.n 80011fa <HAL_RCC_OscConfig+0x1ee>
|
||
|
|
{
|
||
|
|
/* When HSI is used as system clock it will not disabled */
|
||
|
|
if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != 0U) && (hsi_state == RCC_HSI_OFF))
|
||
|
|
8001180: 4b71 ldr r3, [pc, #452] ; (8001348 <HAL_RCC_OscConfig+0x33c>)
|
||
|
|
8001182: 681b ldr r3, [r3, #0]
|
||
|
|
8001184: 2204 movs r2, #4
|
||
|
|
8001186: 4013 ands r3, r2
|
||
|
|
8001188: d004 beq.n 8001194 <HAL_RCC_OscConfig+0x188>
|
||
|
|
800118a: 6a7b ldr r3, [r7, #36] ; 0x24
|
||
|
|
800118c: 2b00 cmp r3, #0
|
||
|
|
800118e: d101 bne.n 8001194 <HAL_RCC_OscConfig+0x188>
|
||
|
|
{
|
||
|
|
return HAL_ERROR;
|
||
|
|
8001190: 2301 movs r3, #1
|
||
|
|
8001192: e303 b.n 800179c <HAL_RCC_OscConfig+0x790>
|
||
|
|
}
|
||
|
|
/* Otherwise, just the calibration and HSI or HSIdiv4 are allowed */
|
||
|
|
else
|
||
|
|
{
|
||
|
|
/* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
|
||
|
|
__HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
|
||
|
|
8001194: 4a6c ldr r2, [pc, #432] ; (8001348 <HAL_RCC_OscConfig+0x33c>)
|
||
|
|
8001196: 4b6c ldr r3, [pc, #432] ; (8001348 <HAL_RCC_OscConfig+0x33c>)
|
||
|
|
8001198: 685b ldr r3, [r3, #4]
|
||
|
|
800119a: 496e ldr r1, [pc, #440] ; (8001354 <HAL_RCC_OscConfig+0x348>)
|
||
|
|
800119c: 4019 ands r1, r3
|
||
|
|
800119e: 687b ldr r3, [r7, #4]
|
||
|
|
80011a0: 691b ldr r3, [r3, #16]
|
||
|
|
80011a2: 021b lsls r3, r3, #8
|
||
|
|
80011a4: 430b orrs r3, r1
|
||
|
|
80011a6: 6053 str r3, [r2, #4]
|
||
|
|
|
||
|
|
/* Enable the Internal High Speed oscillator (HSI or HSIdiv4) */
|
||
|
|
__HAL_RCC_HSI_CONFIG(hsi_state);
|
||
|
|
80011a8: 4b67 ldr r3, [pc, #412] ; (8001348 <HAL_RCC_OscConfig+0x33c>)
|
||
|
|
80011aa: 4a67 ldr r2, [pc, #412] ; (8001348 <HAL_RCC_OscConfig+0x33c>)
|
||
|
|
80011ac: 6812 ldr r2, [r2, #0]
|
||
|
|
80011ae: 2109 movs r1, #9
|
||
|
|
80011b0: 438a bics r2, r1
|
||
|
|
80011b2: 0011 movs r1, r2
|
||
|
|
80011b4: 6a7a ldr r2, [r7, #36] ; 0x24
|
||
|
|
80011b6: 430a orrs r2, r1
|
||
|
|
80011b8: 601a str r2, [r3, #0]
|
||
|
|
}
|
||
|
|
|
||
|
|
/* Update the SystemCoreClock global variable */
|
||
|
|
SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE)>> RCC_CFGR_HPRE_Pos];
|
||
|
|
80011ba: f000 fc41 bl 8001a40 <HAL_RCC_GetSysClockFreq>
|
||
|
|
80011be: 0001 movs r1, r0
|
||
|
|
80011c0: 4b61 ldr r3, [pc, #388] ; (8001348 <HAL_RCC_OscConfig+0x33c>)
|
||
|
|
80011c2: 68db ldr r3, [r3, #12]
|
||
|
|
80011c4: 091b lsrs r3, r3, #4
|
||
|
|
80011c6: 220f movs r2, #15
|
||
|
|
80011c8: 4013 ands r3, r2
|
||
|
|
80011ca: 4a63 ldr r2, [pc, #396] ; (8001358 <HAL_RCC_OscConfig+0x34c>)
|
||
|
|
80011cc: 5cd3 ldrb r3, [r2, r3]
|
||
|
|
80011ce: 000a movs r2, r1
|
||
|
|
80011d0: 40da lsrs r2, r3
|
||
|
|
80011d2: 4b62 ldr r3, [pc, #392] ; (800135c <HAL_RCC_OscConfig+0x350>)
|
||
|
|
80011d4: 601a str r2, [r3, #0]
|
||
|
|
|
||
|
|
/* Configure the source of time base considering new system clocks settings*/
|
||
|
|
status = HAL_InitTick (uwTickPrio);
|
||
|
|
80011d6: 4b62 ldr r3, [pc, #392] ; (8001360 <HAL_RCC_OscConfig+0x354>)
|
||
|
|
80011d8: 681b ldr r3, [r3, #0]
|
||
|
|
80011da: 2213 movs r2, #19
|
||
|
|
80011dc: 18bc adds r4, r7, r2
|
||
|
|
80011de: 0018 movs r0, r3
|
||
|
|
80011e0: f7ff fb9a bl 8000918 <HAL_InitTick>
|
||
|
|
80011e4: 0003 movs r3, r0
|
||
|
|
80011e6: 7023 strb r3, [r4, #0]
|
||
|
|
if(status != HAL_OK)
|
||
|
|
80011e8: 2313 movs r3, #19
|
||
|
|
80011ea: 18fb adds r3, r7, r3
|
||
|
|
80011ec: 781b ldrb r3, [r3, #0]
|
||
|
|
80011ee: 2b00 cmp r3, #0
|
||
|
|
80011f0: d046 beq.n 8001280 <HAL_RCC_OscConfig+0x274>
|
||
|
|
{
|
||
|
|
return status;
|
||
|
|
80011f2: 2313 movs r3, #19
|
||
|
|
80011f4: 18fb adds r3, r7, r3
|
||
|
|
80011f6: 781b ldrb r3, [r3, #0]
|
||
|
|
80011f8: e2d0 b.n 800179c <HAL_RCC_OscConfig+0x790>
|
||
|
|
}
|
||
|
|
}
|
||
|
|
else
|
||
|
|
{
|
||
|
|
/* Check the HSI State */
|
||
|
|
if(hsi_state != RCC_HSI_OFF)
|
||
|
|
80011fa: 6a7b ldr r3, [r7, #36] ; 0x24
|
||
|
|
80011fc: 2b00 cmp r3, #0
|
||
|
|
80011fe: d026 beq.n 800124e <HAL_RCC_OscConfig+0x242>
|
||
|
|
{
|
||
|
|
/* Enable the Internal High Speed oscillator (HSI or HSIdiv4) */
|
||
|
|
__HAL_RCC_HSI_CONFIG(hsi_state);
|
||
|
|
8001200: 4b51 ldr r3, [pc, #324] ; (8001348 <HAL_RCC_OscConfig+0x33c>)
|
||
|
|
8001202: 4a51 ldr r2, [pc, #324] ; (8001348 <HAL_RCC_OscConfig+0x33c>)
|
||
|
|
8001204: 6812 ldr r2, [r2, #0]
|
||
|
|
8001206: 2109 movs r1, #9
|
||
|
|
8001208: 438a bics r2, r1
|
||
|
|
800120a: 0011 movs r1, r2
|
||
|
|
800120c: 6a7a ldr r2, [r7, #36] ; 0x24
|
||
|
|
800120e: 430a orrs r2, r1
|
||
|
|
8001210: 601a str r2, [r3, #0]
|
||
|
|
|
||
|
|
/* Get Start Tick */
|
||
|
|
tickstart = HAL_GetTick();
|
||
|
|
8001212: f7ff fbc7 bl 80009a4 <HAL_GetTick>
|
||
|
|
8001216: 0003 movs r3, r0
|
||
|
|
8001218: 617b str r3, [r7, #20]
|
||
|
|
|
||
|
|
/* Wait till HSI is ready */
|
||
|
|
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == 0U)
|
||
|
|
800121a: e008 b.n 800122e <HAL_RCC_OscConfig+0x222>
|
||
|
|
{
|
||
|
|
if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
|
||
|
|
800121c: f7ff fbc2 bl 80009a4 <HAL_GetTick>
|
||
|
|
8001220: 0002 movs r2, r0
|
||
|
|
8001222: 697b ldr r3, [r7, #20]
|
||
|
|
8001224: 1ad3 subs r3, r2, r3
|
||
|
|
8001226: 2b02 cmp r3, #2
|
||
|
|
8001228: d901 bls.n 800122e <HAL_RCC_OscConfig+0x222>
|
||
|
|
{
|
||
|
|
return HAL_TIMEOUT;
|
||
|
|
800122a: 2303 movs r3, #3
|
||
|
|
800122c: e2b6 b.n 800179c <HAL_RCC_OscConfig+0x790>
|
||
|
|
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == 0U)
|
||
|
|
800122e: 4b46 ldr r3, [pc, #280] ; (8001348 <HAL_RCC_OscConfig+0x33c>)
|
||
|
|
8001230: 681b ldr r3, [r3, #0]
|
||
|
|
8001232: 2204 movs r2, #4
|
||
|
|
8001234: 4013 ands r3, r2
|
||
|
|
8001236: d0f1 beq.n 800121c <HAL_RCC_OscConfig+0x210>
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
/* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
|
||
|
|
__HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
|
||
|
|
8001238: 4a43 ldr r2, [pc, #268] ; (8001348 <HAL_RCC_OscConfig+0x33c>)
|
||
|
|
800123a: 4b43 ldr r3, [pc, #268] ; (8001348 <HAL_RCC_OscConfig+0x33c>)
|
||
|
|
800123c: 685b ldr r3, [r3, #4]
|
||
|
|
800123e: 4945 ldr r1, [pc, #276] ; (8001354 <HAL_RCC_OscConfig+0x348>)
|
||
|
|
8001240: 4019 ands r1, r3
|
||
|
|
8001242: 687b ldr r3, [r7, #4]
|
||
|
|
8001244: 691b ldr r3, [r3, #16]
|
||
|
|
8001246: 021b lsls r3, r3, #8
|
||
|
|
8001248: 430b orrs r3, r1
|
||
|
|
800124a: 6053 str r3, [r2, #4]
|
||
|
|
800124c: e018 b.n 8001280 <HAL_RCC_OscConfig+0x274>
|
||
|
|
}
|
||
|
|
else
|
||
|
|
{
|
||
|
|
/* Disable the Internal High Speed oscillator (HSI). */
|
||
|
|
__HAL_RCC_HSI_DISABLE();
|
||
|
|
800124e: 4b3e ldr r3, [pc, #248] ; (8001348 <HAL_RCC_OscConfig+0x33c>)
|
||
|
|
8001250: 4a3d ldr r2, [pc, #244] ; (8001348 <HAL_RCC_OscConfig+0x33c>)
|
||
|
|
8001252: 6812 ldr r2, [r2, #0]
|
||
|
|
8001254: 2101 movs r1, #1
|
||
|
|
8001256: 438a bics r2, r1
|
||
|
|
8001258: 601a str r2, [r3, #0]
|
||
|
|
|
||
|
|
/* Get Start Tick */
|
||
|
|
tickstart = HAL_GetTick();
|
||
|
|
800125a: f7ff fba3 bl 80009a4 <HAL_GetTick>
|
||
|
|
800125e: 0003 movs r3, r0
|
||
|
|
8001260: 617b str r3, [r7, #20]
|
||
|
|
|
||
|
|
/* Wait till HSI is disabled */
|
||
|
|
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != 0U)
|
||
|
|
8001262: e008 b.n 8001276 <HAL_RCC_OscConfig+0x26a>
|
||
|
|
{
|
||
|
|
if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
|
||
|
|
8001264: f7ff fb9e bl 80009a4 <HAL_GetTick>
|
||
|
|
8001268: 0002 movs r2, r0
|
||
|
|
800126a: 697b ldr r3, [r7, #20]
|
||
|
|
800126c: 1ad3 subs r3, r2, r3
|
||
|
|
800126e: 2b02 cmp r3, #2
|
||
|
|
8001270: d901 bls.n 8001276 <HAL_RCC_OscConfig+0x26a>
|
||
|
|
{
|
||
|
|
return HAL_TIMEOUT;
|
||
|
|
8001272: 2303 movs r3, #3
|
||
|
|
8001274: e292 b.n 800179c <HAL_RCC_OscConfig+0x790>
|
||
|
|
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != 0U)
|
||
|
|
8001276: 4b34 ldr r3, [pc, #208] ; (8001348 <HAL_RCC_OscConfig+0x33c>)
|
||
|
|
8001278: 681b ldr r3, [r3, #0]
|
||
|
|
800127a: 2204 movs r2, #4
|
||
|
|
800127c: 4013 ands r3, r2
|
||
|
|
800127e: d1f1 bne.n 8001264 <HAL_RCC_OscConfig+0x258>
|
||
|
|
}
|
||
|
|
}
|
||
|
|
}
|
||
|
|
}
|
||
|
|
/*----------------------------- MSI Configuration --------------------------*/
|
||
|
|
if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_MSI) == RCC_OSCILLATORTYPE_MSI)
|
||
|
|
8001280: 687b ldr r3, [r7, #4]
|
||
|
|
8001282: 681b ldr r3, [r3, #0]
|
||
|
|
8001284: 2210 movs r2, #16
|
||
|
|
8001286: 4013 ands r3, r2
|
||
|
|
8001288: d100 bne.n 800128c <HAL_RCC_OscConfig+0x280>
|
||
|
|
800128a: e0a1 b.n 80013d0 <HAL_RCC_OscConfig+0x3c4>
|
||
|
|
{
|
||
|
|
/* When the MSI is used as system clock it will not be disabled */
|
||
|
|
if(sysclk_source == RCC_CFGR_SWS_MSI)
|
||
|
|
800128c: 69fb ldr r3, [r7, #28]
|
||
|
|
800128e: 2b00 cmp r3, #0
|
||
|
|
8001290: d141 bne.n 8001316 <HAL_RCC_OscConfig+0x30a>
|
||
|
|
{
|
||
|
|
if((__HAL_RCC_GET_FLAG(RCC_FLAG_MSIRDY) != 0U) && (RCC_OscInitStruct->MSIState == RCC_MSI_OFF))
|
||
|
|
8001292: 4b2d ldr r3, [pc, #180] ; (8001348 <HAL_RCC_OscConfig+0x33c>)
|
||
|
|
8001294: 681a ldr r2, [r3, #0]
|
||
|
|
8001296: 2380 movs r3, #128 ; 0x80
|
||
|
|
8001298: 009b lsls r3, r3, #2
|
||
|
|
800129a: 4013 ands r3, r2
|
||
|
|
800129c: d005 beq.n 80012aa <HAL_RCC_OscConfig+0x29e>
|
||
|
|
800129e: 687b ldr r3, [r7, #4]
|
||
|
|
80012a0: 69db ldr r3, [r3, #28]
|
||
|
|
80012a2: 2b00 cmp r3, #0
|
||
|
|
80012a4: d101 bne.n 80012aa <HAL_RCC_OscConfig+0x29e>
|
||
|
|
{
|
||
|
|
return HAL_ERROR;
|
||
|
|
80012a6: 2301 movs r3, #1
|
||
|
|
80012a8: e278 b.n 800179c <HAL_RCC_OscConfig+0x790>
|
||
|
|
/* Check MSICalibrationValue and MSIClockRange input parameters */
|
||
|
|
assert_param(IS_RCC_MSICALIBRATION_VALUE(RCC_OscInitStruct->MSICalibrationValue));
|
||
|
|
assert_param(IS_RCC_MSI_CLOCK_RANGE(RCC_OscInitStruct->MSIClockRange));
|
||
|
|
|
||
|
|
/* Selects the Multiple Speed oscillator (MSI) clock range .*/
|
||
|
|
__HAL_RCC_MSI_RANGE_CONFIG(RCC_OscInitStruct->MSIClockRange);
|
||
|
|
80012aa: 4a27 ldr r2, [pc, #156] ; (8001348 <HAL_RCC_OscConfig+0x33c>)
|
||
|
|
80012ac: 4b26 ldr r3, [pc, #152] ; (8001348 <HAL_RCC_OscConfig+0x33c>)
|
||
|
|
80012ae: 685b ldr r3, [r3, #4]
|
||
|
|
80012b0: 492c ldr r1, [pc, #176] ; (8001364 <HAL_RCC_OscConfig+0x358>)
|
||
|
|
80012b2: 4019 ands r1, r3
|
||
|
|
80012b4: 687b ldr r3, [r7, #4]
|
||
|
|
80012b6: 6a5b ldr r3, [r3, #36] ; 0x24
|
||
|
|
80012b8: 430b orrs r3, r1
|
||
|
|
80012ba: 6053 str r3, [r2, #4]
|
||
|
|
/* Adjusts the Multiple Speed oscillator (MSI) calibration value.*/
|
||
|
|
__HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->MSICalibrationValue);
|
||
|
|
80012bc: 4a22 ldr r2, [pc, #136] ; (8001348 <HAL_RCC_OscConfig+0x33c>)
|
||
|
|
80012be: 4b22 ldr r3, [pc, #136] ; (8001348 <HAL_RCC_OscConfig+0x33c>)
|
||
|
|
80012c0: 685b ldr r3, [r3, #4]
|
||
|
|
80012c2: 021b lsls r3, r3, #8
|
||
|
|
80012c4: 0a19 lsrs r1, r3, #8
|
||
|
|
80012c6: 687b ldr r3, [r7, #4]
|
||
|
|
80012c8: 6a1b ldr r3, [r3, #32]
|
||
|
|
80012ca: 061b lsls r3, r3, #24
|
||
|
|
80012cc: 430b orrs r3, r1
|
||
|
|
80012ce: 6053 str r3, [r2, #4]
|
||
|
|
|
||
|
|
|
||
|
|
/* Update the SystemCoreClock global variable */
|
||
|
|
SystemCoreClock = (32768U * (1UL << ((RCC_OscInitStruct->MSIClockRange >> RCC_ICSCR_MSIRANGE_Pos) + 1U)))
|
||
|
|
80012d0: 687b ldr r3, [r7, #4]
|
||
|
|
80012d2: 6a5b ldr r3, [r3, #36] ; 0x24
|
||
|
|
80012d4: 0b5b lsrs r3, r3, #13
|
||
|
|
80012d6: 3301 adds r3, #1
|
||
|
|
80012d8: 2280 movs r2, #128 ; 0x80
|
||
|
|
80012da: 0212 lsls r2, r2, #8
|
||
|
|
80012dc: 409a lsls r2, r3
|
||
|
|
>> AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos)];
|
||
|
|
80012de: 4b1a ldr r3, [pc, #104] ; (8001348 <HAL_RCC_OscConfig+0x33c>)
|
||
|
|
80012e0: 68db ldr r3, [r3, #12]
|
||
|
|
80012e2: 091b lsrs r3, r3, #4
|
||
|
|
80012e4: 210f movs r1, #15
|
||
|
|
80012e6: 400b ands r3, r1
|
||
|
|
80012e8: 491b ldr r1, [pc, #108] ; (8001358 <HAL_RCC_OscConfig+0x34c>)
|
||
|
|
80012ea: 5ccb ldrb r3, [r1, r3]
|
||
|
|
80012ec: 40da lsrs r2, r3
|
||
|
|
SystemCoreClock = (32768U * (1UL << ((RCC_OscInitStruct->MSIClockRange >> RCC_ICSCR_MSIRANGE_Pos) + 1U)))
|
||
|
|
80012ee: 4b1b ldr r3, [pc, #108] ; (800135c <HAL_RCC_OscConfig+0x350>)
|
||
|
|
80012f0: 601a str r2, [r3, #0]
|
||
|
|
|
||
|
|
/* Configure the source of time base considering new system clocks settings*/
|
||
|
|
status = HAL_InitTick (uwTickPrio);
|
||
|
|
80012f2: 4b1b ldr r3, [pc, #108] ; (8001360 <HAL_RCC_OscConfig+0x354>)
|
||
|
|
80012f4: 681b ldr r3, [r3, #0]
|
||
|
|
80012f6: 2213 movs r2, #19
|
||
|
|
80012f8: 18bc adds r4, r7, r2
|
||
|
|
80012fa: 0018 movs r0, r3
|
||
|
|
80012fc: f7ff fb0c bl 8000918 <HAL_InitTick>
|
||
|
|
8001300: 0003 movs r3, r0
|
||
|
|
8001302: 7023 strb r3, [r4, #0]
|
||
|
|
if(status != HAL_OK)
|
||
|
|
8001304: 2313 movs r3, #19
|
||
|
|
8001306: 18fb adds r3, r7, r3
|
||
|
|
8001308: 781b ldrb r3, [r3, #0]
|
||
|
|
800130a: 2b00 cmp r3, #0
|
||
|
|
800130c: d060 beq.n 80013d0 <HAL_RCC_OscConfig+0x3c4>
|
||
|
|
{
|
||
|
|
return status;
|
||
|
|
800130e: 2313 movs r3, #19
|
||
|
|
8001310: 18fb adds r3, r7, r3
|
||
|
|
8001312: 781b ldrb r3, [r3, #0]
|
||
|
|
8001314: e242 b.n 800179c <HAL_RCC_OscConfig+0x790>
|
||
|
|
{
|
||
|
|
/* Check MSI State */
|
||
|
|
assert_param(IS_RCC_MSI(RCC_OscInitStruct->MSIState));
|
||
|
|
|
||
|
|
/* Check the MSI State */
|
||
|
|
if(RCC_OscInitStruct->MSIState != RCC_MSI_OFF)
|
||
|
|
8001316: 687b ldr r3, [r7, #4]
|
||
|
|
8001318: 69db ldr r3, [r3, #28]
|
||
|
|
800131a: 2b00 cmp r3, #0
|
||
|
|
800131c: d03e beq.n 800139c <HAL_RCC_OscConfig+0x390>
|
||
|
|
{
|
||
|
|
/* Enable the Multi Speed oscillator (MSI). */
|
||
|
|
__HAL_RCC_MSI_ENABLE();
|
||
|
|
800131e: 4b0a ldr r3, [pc, #40] ; (8001348 <HAL_RCC_OscConfig+0x33c>)
|
||
|
|
8001320: 4a09 ldr r2, [pc, #36] ; (8001348 <HAL_RCC_OscConfig+0x33c>)
|
||
|
|
8001322: 6812 ldr r2, [r2, #0]
|
||
|
|
8001324: 2180 movs r1, #128 ; 0x80
|
||
|
|
8001326: 0049 lsls r1, r1, #1
|
||
|
|
8001328: 430a orrs r2, r1
|
||
|
|
800132a: 601a str r2, [r3, #0]
|
||
|
|
|
||
|
|
/* Get Start Tick */
|
||
|
|
tickstart = HAL_GetTick();
|
||
|
|
800132c: f7ff fb3a bl 80009a4 <HAL_GetTick>
|
||
|
|
8001330: 0003 movs r3, r0
|
||
|
|
8001332: 617b str r3, [r7, #20]
|
||
|
|
|
||
|
|
/* Wait till MSI is ready */
|
||
|
|
while(__HAL_RCC_GET_FLAG(RCC_FLAG_MSIRDY) == 0U)
|
||
|
|
8001334: e018 b.n 8001368 <HAL_RCC_OscConfig+0x35c>
|
||
|
|
{
|
||
|
|
if((HAL_GetTick() - tickstart) > MSI_TIMEOUT_VALUE)
|
||
|
|
8001336: f7ff fb35 bl 80009a4 <HAL_GetTick>
|
||
|
|
800133a: 0002 movs r2, r0
|
||
|
|
800133c: 697b ldr r3, [r7, #20]
|
||
|
|
800133e: 1ad3 subs r3, r2, r3
|
||
|
|
8001340: 2b02 cmp r3, #2
|
||
|
|
8001342: d911 bls.n 8001368 <HAL_RCC_OscConfig+0x35c>
|
||
|
|
{
|
||
|
|
return HAL_TIMEOUT;
|
||
|
|
8001344: 2303 movs r3, #3
|
||
|
|
8001346: e229 b.n 800179c <HAL_RCC_OscConfig+0x790>
|
||
|
|
8001348: 40021000 .word 0x40021000
|
||
|
|
800134c: fffeffff .word 0xfffeffff
|
||
|
|
8001350: fffbffff .word 0xfffbffff
|
||
|
|
8001354: ffffe0ff .word 0xffffe0ff
|
||
|
|
8001358: 08002d90 .word 0x08002d90
|
||
|
|
800135c: 20000000 .word 0x20000000
|
||
|
|
8001360: 20000004 .word 0x20000004
|
||
|
|
8001364: ffff1fff .word 0xffff1fff
|
||
|
|
while(__HAL_RCC_GET_FLAG(RCC_FLAG_MSIRDY) == 0U)
|
||
|
|
8001368: 4bca ldr r3, [pc, #808] ; (8001694 <HAL_RCC_OscConfig+0x688>)
|
||
|
|
800136a: 681a ldr r2, [r3, #0]
|
||
|
|
800136c: 2380 movs r3, #128 ; 0x80
|
||
|
|
800136e: 009b lsls r3, r3, #2
|
||
|
|
8001370: 4013 ands r3, r2
|
||
|
|
8001372: d0e0 beq.n 8001336 <HAL_RCC_OscConfig+0x32a>
|
||
|
|
/* Check MSICalibrationValue and MSIClockRange input parameters */
|
||
|
|
assert_param(IS_RCC_MSICALIBRATION_VALUE(RCC_OscInitStruct->MSICalibrationValue));
|
||
|
|
assert_param(IS_RCC_MSI_CLOCK_RANGE(RCC_OscInitStruct->MSIClockRange));
|
||
|
|
|
||
|
|
/* Selects the Multiple Speed oscillator (MSI) clock range .*/
|
||
|
|
__HAL_RCC_MSI_RANGE_CONFIG(RCC_OscInitStruct->MSIClockRange);
|
||
|
|
8001374: 4ac7 ldr r2, [pc, #796] ; (8001694 <HAL_RCC_OscConfig+0x688>)
|
||
|
|
8001376: 4bc7 ldr r3, [pc, #796] ; (8001694 <HAL_RCC_OscConfig+0x688>)
|
||
|
|
8001378: 685b ldr r3, [r3, #4]
|
||
|
|
800137a: 49c7 ldr r1, [pc, #796] ; (8001698 <HAL_RCC_OscConfig+0x68c>)
|
||
|
|
800137c: 4019 ands r1, r3
|
||
|
|
800137e: 687b ldr r3, [r7, #4]
|
||
|
|
8001380: 6a5b ldr r3, [r3, #36] ; 0x24
|
||
|
|
8001382: 430b orrs r3, r1
|
||
|
|
8001384: 6053 str r3, [r2, #4]
|
||
|
|
/* Adjusts the Multiple Speed oscillator (MSI) calibration value.*/
|
||
|
|
__HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->MSICalibrationValue);
|
||
|
|
8001386: 4ac3 ldr r2, [pc, #780] ; (8001694 <HAL_RCC_OscConfig+0x688>)
|
||
|
|
8001388: 4bc2 ldr r3, [pc, #776] ; (8001694 <HAL_RCC_OscConfig+0x688>)
|
||
|
|
800138a: 685b ldr r3, [r3, #4]
|
||
|
|
800138c: 021b lsls r3, r3, #8
|
||
|
|
800138e: 0a19 lsrs r1, r3, #8
|
||
|
|
8001390: 687b ldr r3, [r7, #4]
|
||
|
|
8001392: 6a1b ldr r3, [r3, #32]
|
||
|
|
8001394: 061b lsls r3, r3, #24
|
||
|
|
8001396: 430b orrs r3, r1
|
||
|
|
8001398: 6053 str r3, [r2, #4]
|
||
|
|
800139a: e019 b.n 80013d0 <HAL_RCC_OscConfig+0x3c4>
|
||
|
|
}
|
||
|
|
else
|
||
|
|
{
|
||
|
|
/* Disable the Multi Speed oscillator (MSI). */
|
||
|
|
__HAL_RCC_MSI_DISABLE();
|
||
|
|
800139c: 4bbd ldr r3, [pc, #756] ; (8001694 <HAL_RCC_OscConfig+0x688>)
|
||
|
|
800139e: 4abd ldr r2, [pc, #756] ; (8001694 <HAL_RCC_OscConfig+0x688>)
|
||
|
|
80013a0: 6812 ldr r2, [r2, #0]
|
||
|
|
80013a2: 49be ldr r1, [pc, #760] ; (800169c <HAL_RCC_OscConfig+0x690>)
|
||
|
|
80013a4: 400a ands r2, r1
|
||
|
|
80013a6: 601a str r2, [r3, #0]
|
||
|
|
|
||
|
|
/* Get Start Tick */
|
||
|
|
tickstart = HAL_GetTick();
|
||
|
|
80013a8: f7ff fafc bl 80009a4 <HAL_GetTick>
|
||
|
|
80013ac: 0003 movs r3, r0
|
||
|
|
80013ae: 617b str r3, [r7, #20]
|
||
|
|
|
||
|
|
/* Wait till MSI is ready */
|
||
|
|
while(__HAL_RCC_GET_FLAG(RCC_FLAG_MSIRDY) != 0U)
|
||
|
|
80013b0: e008 b.n 80013c4 <HAL_RCC_OscConfig+0x3b8>
|
||
|
|
{
|
||
|
|
if((HAL_GetTick() - tickstart) > MSI_TIMEOUT_VALUE)
|
||
|
|
80013b2: f7ff faf7 bl 80009a4 <HAL_GetTick>
|
||
|
|
80013b6: 0002 movs r2, r0
|
||
|
|
80013b8: 697b ldr r3, [r7, #20]
|
||
|
|
80013ba: 1ad3 subs r3, r2, r3
|
||
|
|
80013bc: 2b02 cmp r3, #2
|
||
|
|
80013be: d901 bls.n 80013c4 <HAL_RCC_OscConfig+0x3b8>
|
||
|
|
{
|
||
|
|
return HAL_TIMEOUT;
|
||
|
|
80013c0: 2303 movs r3, #3
|
||
|
|
80013c2: e1eb b.n 800179c <HAL_RCC_OscConfig+0x790>
|
||
|
|
while(__HAL_RCC_GET_FLAG(RCC_FLAG_MSIRDY) != 0U)
|
||
|
|
80013c4: 4bb3 ldr r3, [pc, #716] ; (8001694 <HAL_RCC_OscConfig+0x688>)
|
||
|
|
80013c6: 681a ldr r2, [r3, #0]
|
||
|
|
80013c8: 2380 movs r3, #128 ; 0x80
|
||
|
|
80013ca: 009b lsls r3, r3, #2
|
||
|
|
80013cc: 4013 ands r3, r2
|
||
|
|
80013ce: d1f0 bne.n 80013b2 <HAL_RCC_OscConfig+0x3a6>
|
||
|
|
}
|
||
|
|
}
|
||
|
|
}
|
||
|
|
}
|
||
|
|
/*------------------------------ LSI Configuration -------------------------*/
|
||
|
|
if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)
|
||
|
|
80013d0: 687b ldr r3, [r7, #4]
|
||
|
|
80013d2: 681b ldr r3, [r3, #0]
|
||
|
|
80013d4: 2208 movs r2, #8
|
||
|
|
80013d6: 4013 ands r3, r2
|
||
|
|
80013d8: d036 beq.n 8001448 <HAL_RCC_OscConfig+0x43c>
|
||
|
|
{
|
||
|
|
/* Check the parameters */
|
||
|
|
assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState));
|
||
|
|
|
||
|
|
/* Check the LSI State */
|
||
|
|
if(RCC_OscInitStruct->LSIState != RCC_LSI_OFF)
|
||
|
|
80013da: 687b ldr r3, [r7, #4]
|
||
|
|
80013dc: 695b ldr r3, [r3, #20]
|
||
|
|
80013de: 2b00 cmp r3, #0
|
||
|
|
80013e0: d019 beq.n 8001416 <HAL_RCC_OscConfig+0x40a>
|
||
|
|
{
|
||
|
|
/* Enable the Internal Low Speed oscillator (LSI). */
|
||
|
|
__HAL_RCC_LSI_ENABLE();
|
||
|
|
80013e2: 4bac ldr r3, [pc, #688] ; (8001694 <HAL_RCC_OscConfig+0x688>)
|
||
|
|
80013e4: 4aab ldr r2, [pc, #684] ; (8001694 <HAL_RCC_OscConfig+0x688>)
|
||
|
|
80013e6: 6d12 ldr r2, [r2, #80] ; 0x50
|
||
|
|
80013e8: 2101 movs r1, #1
|
||
|
|
80013ea: 430a orrs r2, r1
|
||
|
|
80013ec: 651a str r2, [r3, #80] ; 0x50
|
||
|
|
|
||
|
|
/* Get Start Tick */
|
||
|
|
tickstart = HAL_GetTick();
|
||
|
|
80013ee: f7ff fad9 bl 80009a4 <HAL_GetTick>
|
||
|
|
80013f2: 0003 movs r3, r0
|
||
|
|
80013f4: 617b str r3, [r7, #20]
|
||
|
|
|
||
|
|
/* Wait till LSI is ready */
|
||
|
|
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == 0U)
|
||
|
|
80013f6: e008 b.n 800140a <HAL_RCC_OscConfig+0x3fe>
|
||
|
|
{
|
||
|
|
if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
|
||
|
|
80013f8: f7ff fad4 bl 80009a4 <HAL_GetTick>
|
||
|
|
80013fc: 0002 movs r2, r0
|
||
|
|
80013fe: 697b ldr r3, [r7, #20]
|
||
|
|
8001400: 1ad3 subs r3, r2, r3
|
||
|
|
8001402: 2b02 cmp r3, #2
|
||
|
|
8001404: d901 bls.n 800140a <HAL_RCC_OscConfig+0x3fe>
|
||
|
|
{
|
||
|
|
return HAL_TIMEOUT;
|
||
|
|
8001406: 2303 movs r3, #3
|
||
|
|
8001408: e1c8 b.n 800179c <HAL_RCC_OscConfig+0x790>
|
||
|
|
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == 0U)
|
||
|
|
800140a: 4ba2 ldr r3, [pc, #648] ; (8001694 <HAL_RCC_OscConfig+0x688>)
|
||
|
|
800140c: 6d1b ldr r3, [r3, #80] ; 0x50
|
||
|
|
800140e: 2202 movs r2, #2
|
||
|
|
8001410: 4013 ands r3, r2
|
||
|
|
8001412: d0f1 beq.n 80013f8 <HAL_RCC_OscConfig+0x3ec>
|
||
|
|
8001414: e018 b.n 8001448 <HAL_RCC_OscConfig+0x43c>
|
||
|
|
}
|
||
|
|
}
|
||
|
|
else
|
||
|
|
{
|
||
|
|
/* Disable the Internal Low Speed oscillator (LSI). */
|
||
|
|
__HAL_RCC_LSI_DISABLE();
|
||
|
|
8001416: 4b9f ldr r3, [pc, #636] ; (8001694 <HAL_RCC_OscConfig+0x688>)
|
||
|
|
8001418: 4a9e ldr r2, [pc, #632] ; (8001694 <HAL_RCC_OscConfig+0x688>)
|
||
|
|
800141a: 6d12 ldr r2, [r2, #80] ; 0x50
|
||
|
|
800141c: 2101 movs r1, #1
|
||
|
|
800141e: 438a bics r2, r1
|
||
|
|
8001420: 651a str r2, [r3, #80] ; 0x50
|
||
|
|
|
||
|
|
/* Get Start Tick */
|
||
|
|
tickstart = HAL_GetTick();
|
||
|
|
8001422: f7ff fabf bl 80009a4 <HAL_GetTick>
|
||
|
|
8001426: 0003 movs r3, r0
|
||
|
|
8001428: 617b str r3, [r7, #20]
|
||
|
|
|
||
|
|
/* Wait till LSI is disabled */
|
||
|
|
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != 0U)
|
||
|
|
800142a: e008 b.n 800143e <HAL_RCC_OscConfig+0x432>
|
||
|
|
{
|
||
|
|
if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
|
||
|
|
800142c: f7ff faba bl 80009a4 <HAL_GetTick>
|
||
|
|
8001430: 0002 movs r2, r0
|
||
|
|
8001432: 697b ldr r3, [r7, #20]
|
||
|
|
8001434: 1ad3 subs r3, r2, r3
|
||
|
|
8001436: 2b02 cmp r3, #2
|
||
|
|
8001438: d901 bls.n 800143e <HAL_RCC_OscConfig+0x432>
|
||
|
|
{
|
||
|
|
return HAL_TIMEOUT;
|
||
|
|
800143a: 2303 movs r3, #3
|
||
|
|
800143c: e1ae b.n 800179c <HAL_RCC_OscConfig+0x790>
|
||
|
|
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != 0U)
|
||
|
|
800143e: 4b95 ldr r3, [pc, #596] ; (8001694 <HAL_RCC_OscConfig+0x688>)
|
||
|
|
8001440: 6d1b ldr r3, [r3, #80] ; 0x50
|
||
|
|
8001442: 2202 movs r2, #2
|
||
|
|
8001444: 4013 ands r3, r2
|
||
|
|
8001446: d1f1 bne.n 800142c <HAL_RCC_OscConfig+0x420>
|
||
|
|
}
|
||
|
|
}
|
||
|
|
}
|
||
|
|
}
|
||
|
|
/*------------------------------ LSE Configuration -------------------------*/
|
||
|
|
if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)
|
||
|
|
8001448: 687b ldr r3, [r7, #4]
|
||
|
|
800144a: 681b ldr r3, [r3, #0]
|
||
|
|
800144c: 2204 movs r2, #4
|
||
|
|
800144e: 4013 ands r3, r2
|
||
|
|
8001450: d100 bne.n 8001454 <HAL_RCC_OscConfig+0x448>
|
||
|
|
8001452: e0af b.n 80015b4 <HAL_RCC_OscConfig+0x5a8>
|
||
|
|
{
|
||
|
|
FlagStatus pwrclkchanged = RESET;
|
||
|
|
8001454: 2323 movs r3, #35 ; 0x23
|
||
|
|
8001456: 18fb adds r3, r7, r3
|
||
|
|
8001458: 2200 movs r2, #0
|
||
|
|
800145a: 701a strb r2, [r3, #0]
|
||
|
|
/* Check the parameters */
|
||
|
|
assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState));
|
||
|
|
|
||
|
|
/* Update LSE configuration in Backup Domain control register */
|
||
|
|
/* Requires to enable write access to Backup Domain of necessary */
|
||
|
|
if(__HAL_RCC_PWR_IS_CLK_DISABLED())
|
||
|
|
800145c: 4b8d ldr r3, [pc, #564] ; (8001694 <HAL_RCC_OscConfig+0x688>)
|
||
|
|
800145e: 6b9a ldr r2, [r3, #56] ; 0x38
|
||
|
|
8001460: 2380 movs r3, #128 ; 0x80
|
||
|
|
8001462: 055b lsls r3, r3, #21
|
||
|
|
8001464: 4013 ands r3, r2
|
||
|
|
8001466: d10a bne.n 800147e <HAL_RCC_OscConfig+0x472>
|
||
|
|
{
|
||
|
|
__HAL_RCC_PWR_CLK_ENABLE();
|
||
|
|
8001468: 4b8a ldr r3, [pc, #552] ; (8001694 <HAL_RCC_OscConfig+0x688>)
|
||
|
|
800146a: 4a8a ldr r2, [pc, #552] ; (8001694 <HAL_RCC_OscConfig+0x688>)
|
||
|
|
800146c: 6b92 ldr r2, [r2, #56] ; 0x38
|
||
|
|
800146e: 2180 movs r1, #128 ; 0x80
|
||
|
|
8001470: 0549 lsls r1, r1, #21
|
||
|
|
8001472: 430a orrs r2, r1
|
||
|
|
8001474: 639a str r2, [r3, #56] ; 0x38
|
||
|
|
pwrclkchanged = SET;
|
||
|
|
8001476: 2323 movs r3, #35 ; 0x23
|
||
|
|
8001478: 18fb adds r3, r7, r3
|
||
|
|
800147a: 2201 movs r2, #1
|
||
|
|
800147c: 701a strb r2, [r3, #0]
|
||
|
|
}
|
||
|
|
|
||
|
|
if(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
|
||
|
|
800147e: 4b88 ldr r3, [pc, #544] ; (80016a0 <HAL_RCC_OscConfig+0x694>)
|
||
|
|
8001480: 681a ldr r2, [r3, #0]
|
||
|
|
8001482: 2380 movs r3, #128 ; 0x80
|
||
|
|
8001484: 005b lsls r3, r3, #1
|
||
|
|
8001486: 4013 ands r3, r2
|
||
|
|
8001488: d11a bne.n 80014c0 <HAL_RCC_OscConfig+0x4b4>
|
||
|
|
{
|
||
|
|
/* Enable write access to Backup domain */
|
||
|
|
SET_BIT(PWR->CR, PWR_CR_DBP);
|
||
|
|
800148a: 4b85 ldr r3, [pc, #532] ; (80016a0 <HAL_RCC_OscConfig+0x694>)
|
||
|
|
800148c: 4a84 ldr r2, [pc, #528] ; (80016a0 <HAL_RCC_OscConfig+0x694>)
|
||
|
|
800148e: 6812 ldr r2, [r2, #0]
|
||
|
|
8001490: 2180 movs r1, #128 ; 0x80
|
||
|
|
8001492: 0049 lsls r1, r1, #1
|
||
|
|
8001494: 430a orrs r2, r1
|
||
|
|
8001496: 601a str r2, [r3, #0]
|
||
|
|
|
||
|
|
/* Wait for Backup domain Write protection disable */
|
||
|
|
tickstart = HAL_GetTick();
|
||
|
|
8001498: f7ff fa84 bl 80009a4 <HAL_GetTick>
|
||
|
|
800149c: 0003 movs r3, r0
|
||
|
|
800149e: 617b str r3, [r7, #20]
|
||
|
|
|
||
|
|
while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
|
||
|
|
80014a0: e008 b.n 80014b4 <HAL_RCC_OscConfig+0x4a8>
|
||
|
|
{
|
||
|
|
if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
|
||
|
|
80014a2: f7ff fa7f bl 80009a4 <HAL_GetTick>
|
||
|
|
80014a6: 0002 movs r2, r0
|
||
|
|
80014a8: 697b ldr r3, [r7, #20]
|
||
|
|
80014aa: 1ad3 subs r3, r2, r3
|
||
|
|
80014ac: 2b64 cmp r3, #100 ; 0x64
|
||
|
|
80014ae: d901 bls.n 80014b4 <HAL_RCC_OscConfig+0x4a8>
|
||
|
|
{
|
||
|
|
return HAL_TIMEOUT;
|
||
|
|
80014b0: 2303 movs r3, #3
|
||
|
|
80014b2: e173 b.n 800179c <HAL_RCC_OscConfig+0x790>
|
||
|
|
while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
|
||
|
|
80014b4: 4b7a ldr r3, [pc, #488] ; (80016a0 <HAL_RCC_OscConfig+0x694>)
|
||
|
|
80014b6: 681a ldr r2, [r3, #0]
|
||
|
|
80014b8: 2380 movs r3, #128 ; 0x80
|
||
|
|
80014ba: 005b lsls r3, r3, #1
|
||
|
|
80014bc: 4013 ands r3, r2
|
||
|
|
80014be: d0f0 beq.n 80014a2 <HAL_RCC_OscConfig+0x496>
|
||
|
|
}
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
/* Set the new LSE configuration -----------------------------------------*/
|
||
|
|
__HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
|
||
|
|
80014c0: 687b ldr r3, [r7, #4]
|
||
|
|
80014c2: 689a ldr r2, [r3, #8]
|
||
|
|
80014c4: 2380 movs r3, #128 ; 0x80
|
||
|
|
80014c6: 005b lsls r3, r3, #1
|
||
|
|
80014c8: 429a cmp r2, r3
|
||
|
|
80014ca: d107 bne.n 80014dc <HAL_RCC_OscConfig+0x4d0>
|
||
|
|
80014cc: 4b71 ldr r3, [pc, #452] ; (8001694 <HAL_RCC_OscConfig+0x688>)
|
||
|
|
80014ce: 4a71 ldr r2, [pc, #452] ; (8001694 <HAL_RCC_OscConfig+0x688>)
|
||
|
|
80014d0: 6d12 ldr r2, [r2, #80] ; 0x50
|
||
|
|
80014d2: 2180 movs r1, #128 ; 0x80
|
||
|
|
80014d4: 0049 lsls r1, r1, #1
|
||
|
|
80014d6: 430a orrs r2, r1
|
||
|
|
80014d8: 651a str r2, [r3, #80] ; 0x50
|
||
|
|
80014da: e031 b.n 8001540 <HAL_RCC_OscConfig+0x534>
|
||
|
|
80014dc: 687b ldr r3, [r7, #4]
|
||
|
|
80014de: 689b ldr r3, [r3, #8]
|
||
|
|
80014e0: 2b00 cmp r3, #0
|
||
|
|
80014e2: d10c bne.n 80014fe <HAL_RCC_OscConfig+0x4f2>
|
||
|
|
80014e4: 4b6b ldr r3, [pc, #428] ; (8001694 <HAL_RCC_OscConfig+0x688>)
|
||
|
|
80014e6: 4a6b ldr r2, [pc, #428] ; (8001694 <HAL_RCC_OscConfig+0x688>)
|
||
|
|
80014e8: 6d12 ldr r2, [r2, #80] ; 0x50
|
||
|
|
80014ea: 496c ldr r1, [pc, #432] ; (800169c <HAL_RCC_OscConfig+0x690>)
|
||
|
|
80014ec: 400a ands r2, r1
|
||
|
|
80014ee: 651a str r2, [r3, #80] ; 0x50
|
||
|
|
80014f0: 4b68 ldr r3, [pc, #416] ; (8001694 <HAL_RCC_OscConfig+0x688>)
|
||
|
|
80014f2: 4a68 ldr r2, [pc, #416] ; (8001694 <HAL_RCC_OscConfig+0x688>)
|
||
|
|
80014f4: 6d12 ldr r2, [r2, #80] ; 0x50
|
||
|
|
80014f6: 496b ldr r1, [pc, #428] ; (80016a4 <HAL_RCC_OscConfig+0x698>)
|
||
|
|
80014f8: 400a ands r2, r1
|
||
|
|
80014fa: 651a str r2, [r3, #80] ; 0x50
|
||
|
|
80014fc: e020 b.n 8001540 <HAL_RCC_OscConfig+0x534>
|
||
|
|
80014fe: 687b ldr r3, [r7, #4]
|
||
|
|
8001500: 689a ldr r2, [r3, #8]
|
||
|
|
8001502: 23a0 movs r3, #160 ; 0xa0
|
||
|
|
8001504: 00db lsls r3, r3, #3
|
||
|
|
8001506: 429a cmp r2, r3
|
||
|
|
8001508: d10e bne.n 8001528 <HAL_RCC_OscConfig+0x51c>
|
||
|
|
800150a: 4b62 ldr r3, [pc, #392] ; (8001694 <HAL_RCC_OscConfig+0x688>)
|
||
|
|
800150c: 4a61 ldr r2, [pc, #388] ; (8001694 <HAL_RCC_OscConfig+0x688>)
|
||
|
|
800150e: 6d12 ldr r2, [r2, #80] ; 0x50
|
||
|
|
8001510: 2180 movs r1, #128 ; 0x80
|
||
|
|
8001512: 00c9 lsls r1, r1, #3
|
||
|
|
8001514: 430a orrs r2, r1
|
||
|
|
8001516: 651a str r2, [r3, #80] ; 0x50
|
||
|
|
8001518: 4b5e ldr r3, [pc, #376] ; (8001694 <HAL_RCC_OscConfig+0x688>)
|
||
|
|
800151a: 4a5e ldr r2, [pc, #376] ; (8001694 <HAL_RCC_OscConfig+0x688>)
|
||
|
|
800151c: 6d12 ldr r2, [r2, #80] ; 0x50
|
||
|
|
800151e: 2180 movs r1, #128 ; 0x80
|
||
|
|
8001520: 0049 lsls r1, r1, #1
|
||
|
|
8001522: 430a orrs r2, r1
|
||
|
|
8001524: 651a str r2, [r3, #80] ; 0x50
|
||
|
|
8001526: e00b b.n 8001540 <HAL_RCC_OscConfig+0x534>
|
||
|
|
8001528: 4b5a ldr r3, [pc, #360] ; (8001694 <HAL_RCC_OscConfig+0x688>)
|
||
|
|
800152a: 4a5a ldr r2, [pc, #360] ; (8001694 <HAL_RCC_OscConfig+0x688>)
|
||
|
|
800152c: 6d12 ldr r2, [r2, #80] ; 0x50
|
||
|
|
800152e: 495b ldr r1, [pc, #364] ; (800169c <HAL_RCC_OscConfig+0x690>)
|
||
|
|
8001530: 400a ands r2, r1
|
||
|
|
8001532: 651a str r2, [r3, #80] ; 0x50
|
||
|
|
8001534: 4b57 ldr r3, [pc, #348] ; (8001694 <HAL_RCC_OscConfig+0x688>)
|
||
|
|
8001536: 4a57 ldr r2, [pc, #348] ; (8001694 <HAL_RCC_OscConfig+0x688>)
|
||
|
|
8001538: 6d12 ldr r2, [r2, #80] ; 0x50
|
||
|
|
800153a: 495a ldr r1, [pc, #360] ; (80016a4 <HAL_RCC_OscConfig+0x698>)
|
||
|
|
800153c: 400a ands r2, r1
|
||
|
|
800153e: 651a str r2, [r3, #80] ; 0x50
|
||
|
|
|
||
|
|
/* Check the LSE State */
|
||
|
|
if(RCC_OscInitStruct->LSEState != RCC_LSE_OFF)
|
||
|
|
8001540: 687b ldr r3, [r7, #4]
|
||
|
|
8001542: 689b ldr r3, [r3, #8]
|
||
|
|
8001544: 2b00 cmp r3, #0
|
||
|
|
8001546: d015 beq.n 8001574 <HAL_RCC_OscConfig+0x568>
|
||
|
|
{
|
||
|
|
/* Get Start Tick */
|
||
|
|
tickstart = HAL_GetTick();
|
||
|
|
8001548: f7ff fa2c bl 80009a4 <HAL_GetTick>
|
||
|
|
800154c: 0003 movs r3, r0
|
||
|
|
800154e: 617b str r3, [r7, #20]
|
||
|
|
|
||
|
|
/* Wait till LSE is ready */
|
||
|
|
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == 0U)
|
||
|
|
8001550: e009 b.n 8001566 <HAL_RCC_OscConfig+0x55a>
|
||
|
|
{
|
||
|
|
if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
|
||
|
|
8001552: f7ff fa27 bl 80009a4 <HAL_GetTick>
|
||
|
|
8001556: 0002 movs r2, r0
|
||
|
|
8001558: 697b ldr r3, [r7, #20]
|
||
|
|
800155a: 1ad3 subs r3, r2, r3
|
||
|
|
800155c: 4a52 ldr r2, [pc, #328] ; (80016a8 <HAL_RCC_OscConfig+0x69c>)
|
||
|
|
800155e: 4293 cmp r3, r2
|
||
|
|
8001560: d901 bls.n 8001566 <HAL_RCC_OscConfig+0x55a>
|
||
|
|
{
|
||
|
|
return HAL_TIMEOUT;
|
||
|
|
8001562: 2303 movs r3, #3
|
||
|
|
8001564: e11a b.n 800179c <HAL_RCC_OscConfig+0x790>
|
||
|
|
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == 0U)
|
||
|
|
8001566: 4b4b ldr r3, [pc, #300] ; (8001694 <HAL_RCC_OscConfig+0x688>)
|
||
|
|
8001568: 6d1a ldr r2, [r3, #80] ; 0x50
|
||
|
|
800156a: 2380 movs r3, #128 ; 0x80
|
||
|
|
800156c: 009b lsls r3, r3, #2
|
||
|
|
800156e: 4013 ands r3, r2
|
||
|
|
8001570: d0ef beq.n 8001552 <HAL_RCC_OscConfig+0x546>
|
||
|
|
8001572: e014 b.n 800159e <HAL_RCC_OscConfig+0x592>
|
||
|
|
}
|
||
|
|
}
|
||
|
|
else
|
||
|
|
{
|
||
|
|
/* Get Start Tick */
|
||
|
|
tickstart = HAL_GetTick();
|
||
|
|
8001574: f7ff fa16 bl 80009a4 <HAL_GetTick>
|
||
|
|
8001578: 0003 movs r3, r0
|
||
|
|
800157a: 617b str r3, [r7, #20]
|
||
|
|
|
||
|
|
/* Wait till LSE is disabled */
|
||
|
|
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != 0U)
|
||
|
|
800157c: e009 b.n 8001592 <HAL_RCC_OscConfig+0x586>
|
||
|
|
{
|
||
|
|
if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
|
||
|
|
800157e: f7ff fa11 bl 80009a4 <HAL_GetTick>
|
||
|
|
8001582: 0002 movs r2, r0
|
||
|
|
8001584: 697b ldr r3, [r7, #20]
|
||
|
|
8001586: 1ad3 subs r3, r2, r3
|
||
|
|
8001588: 4a47 ldr r2, [pc, #284] ; (80016a8 <HAL_RCC_OscConfig+0x69c>)
|
||
|
|
800158a: 4293 cmp r3, r2
|
||
|
|
800158c: d901 bls.n 8001592 <HAL_RCC_OscConfig+0x586>
|
||
|
|
{
|
||
|
|
return HAL_TIMEOUT;
|
||
|
|
800158e: 2303 movs r3, #3
|
||
|
|
8001590: e104 b.n 800179c <HAL_RCC_OscConfig+0x790>
|
||
|
|
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != 0U)
|
||
|
|
8001592: 4b40 ldr r3, [pc, #256] ; (8001694 <HAL_RCC_OscConfig+0x688>)
|
||
|
|
8001594: 6d1a ldr r2, [r3, #80] ; 0x50
|
||
|
|
8001596: 2380 movs r3, #128 ; 0x80
|
||
|
|
8001598: 009b lsls r3, r3, #2
|
||
|
|
800159a: 4013 ands r3, r2
|
||
|
|
800159c: d1ef bne.n 800157e <HAL_RCC_OscConfig+0x572>
|
||
|
|
}
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
/* Require to disable power clock if necessary */
|
||
|
|
if(pwrclkchanged == SET)
|
||
|
|
800159e: 2323 movs r3, #35 ; 0x23
|
||
|
|
80015a0: 18fb adds r3, r7, r3
|
||
|
|
80015a2: 781b ldrb r3, [r3, #0]
|
||
|
|
80015a4: 2b01 cmp r3, #1
|
||
|
|
80015a6: d105 bne.n 80015b4 <HAL_RCC_OscConfig+0x5a8>
|
||
|
|
{
|
||
|
|
__HAL_RCC_PWR_CLK_DISABLE();
|
||
|
|
80015a8: 4b3a ldr r3, [pc, #232] ; (8001694 <HAL_RCC_OscConfig+0x688>)
|
||
|
|
80015aa: 4a3a ldr r2, [pc, #232] ; (8001694 <HAL_RCC_OscConfig+0x688>)
|
||
|
|
80015ac: 6b92 ldr r2, [r2, #56] ; 0x38
|
||
|
|
80015ae: 493f ldr r1, [pc, #252] ; (80016ac <HAL_RCC_OscConfig+0x6a0>)
|
||
|
|
80015b0: 400a ands r2, r1
|
||
|
|
80015b2: 639a str r2, [r3, #56] ; 0x38
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
#if defined(RCC_HSI48_SUPPORT)
|
||
|
|
/*----------------------------- HSI48 Configuration --------------------------*/
|
||
|
|
if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI48) == RCC_OSCILLATORTYPE_HSI48)
|
||
|
|
80015b4: 687b ldr r3, [r7, #4]
|
||
|
|
80015b6: 681b ldr r3, [r3, #0]
|
||
|
|
80015b8: 2220 movs r2, #32
|
||
|
|
80015ba: 4013 ands r3, r2
|
||
|
|
80015bc: d049 beq.n 8001652 <HAL_RCC_OscConfig+0x646>
|
||
|
|
{
|
||
|
|
/* Check the parameters */
|
||
|
|
assert_param(IS_RCC_HSI48(RCC_OscInitStruct->HSI48State));
|
||
|
|
|
||
|
|
/* Check the HSI48 State */
|
||
|
|
if(RCC_OscInitStruct->HSI48State != RCC_HSI48_OFF)
|
||
|
|
80015be: 687b ldr r3, [r7, #4]
|
||
|
|
80015c0: 699b ldr r3, [r3, #24]
|
||
|
|
80015c2: 2b00 cmp r3, #0
|
||
|
|
80015c4: d026 beq.n 8001614 <HAL_RCC_OscConfig+0x608>
|
||
|
|
{
|
||
|
|
/* Enable the Internal High Speed oscillator (HSI48). */
|
||
|
|
__HAL_RCC_HSI48_ENABLE();
|
||
|
|
80015c6: 4b33 ldr r3, [pc, #204] ; (8001694 <HAL_RCC_OscConfig+0x688>)
|
||
|
|
80015c8: 4a32 ldr r2, [pc, #200] ; (8001694 <HAL_RCC_OscConfig+0x688>)
|
||
|
|
80015ca: 6892 ldr r2, [r2, #8]
|
||
|
|
80015cc: 2101 movs r1, #1
|
||
|
|
80015ce: 430a orrs r2, r1
|
||
|
|
80015d0: 609a str r2, [r3, #8]
|
||
|
|
80015d2: 4b30 ldr r3, [pc, #192] ; (8001694 <HAL_RCC_OscConfig+0x688>)
|
||
|
|
80015d4: 4a2f ldr r2, [pc, #188] ; (8001694 <HAL_RCC_OscConfig+0x688>)
|
||
|
|
80015d6: 6b52 ldr r2, [r2, #52] ; 0x34
|
||
|
|
80015d8: 2101 movs r1, #1
|
||
|
|
80015da: 430a orrs r2, r1
|
||
|
|
80015dc: 635a str r2, [r3, #52] ; 0x34
|
||
|
|
80015de: 4b34 ldr r3, [pc, #208] ; (80016b0 <HAL_RCC_OscConfig+0x6a4>)
|
||
|
|
80015e0: 4a33 ldr r2, [pc, #204] ; (80016b0 <HAL_RCC_OscConfig+0x6a4>)
|
||
|
|
80015e2: 6a12 ldr r2, [r2, #32]
|
||
|
|
80015e4: 2180 movs r1, #128 ; 0x80
|
||
|
|
80015e6: 0189 lsls r1, r1, #6
|
||
|
|
80015e8: 430a orrs r2, r1
|
||
|
|
80015ea: 621a str r2, [r3, #32]
|
||
|
|
|
||
|
|
/* Get Start Tick */
|
||
|
|
tickstart = HAL_GetTick();
|
||
|
|
80015ec: f7ff f9da bl 80009a4 <HAL_GetTick>
|
||
|
|
80015f0: 0003 movs r3, r0
|
||
|
|
80015f2: 617b str r3, [r7, #20]
|
||
|
|
|
||
|
|
/* Wait till HSI48 is ready */
|
||
|
|
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSI48RDY) == 0U)
|
||
|
|
80015f4: e008 b.n 8001608 <HAL_RCC_OscConfig+0x5fc>
|
||
|
|
{
|
||
|
|
if((HAL_GetTick() - tickstart) > HSI48_TIMEOUT_VALUE)
|
||
|
|
80015f6: f7ff f9d5 bl 80009a4 <HAL_GetTick>
|
||
|
|
80015fa: 0002 movs r2, r0
|
||
|
|
80015fc: 697b ldr r3, [r7, #20]
|
||
|
|
80015fe: 1ad3 subs r3, r2, r3
|
||
|
|
8001600: 2b02 cmp r3, #2
|
||
|
|
8001602: d901 bls.n 8001608 <HAL_RCC_OscConfig+0x5fc>
|
||
|
|
{
|
||
|
|
return HAL_TIMEOUT;
|
||
|
|
8001604: 2303 movs r3, #3
|
||
|
|
8001606: e0c9 b.n 800179c <HAL_RCC_OscConfig+0x790>
|
||
|
|
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSI48RDY) == 0U)
|
||
|
|
8001608: 4b22 ldr r3, [pc, #136] ; (8001694 <HAL_RCC_OscConfig+0x688>)
|
||
|
|
800160a: 689b ldr r3, [r3, #8]
|
||
|
|
800160c: 2202 movs r2, #2
|
||
|
|
800160e: 4013 ands r3, r2
|
||
|
|
8001610: d0f1 beq.n 80015f6 <HAL_RCC_OscConfig+0x5ea>
|
||
|
|
8001612: e01e b.n 8001652 <HAL_RCC_OscConfig+0x646>
|
||
|
|
}
|
||
|
|
}
|
||
|
|
else
|
||
|
|
{
|
||
|
|
/* Disable the Internal High Speed oscillator (HSI48). */
|
||
|
|
__HAL_RCC_HSI48_DISABLE();
|
||
|
|
8001614: 4b1f ldr r3, [pc, #124] ; (8001694 <HAL_RCC_OscConfig+0x688>)
|
||
|
|
8001616: 4a1f ldr r2, [pc, #124] ; (8001694 <HAL_RCC_OscConfig+0x688>)
|
||
|
|
8001618: 6892 ldr r2, [r2, #8]
|
||
|
|
800161a: 2101 movs r1, #1
|
||
|
|
800161c: 438a bics r2, r1
|
||
|
|
800161e: 609a str r2, [r3, #8]
|
||
|
|
8001620: 4b23 ldr r3, [pc, #140] ; (80016b0 <HAL_RCC_OscConfig+0x6a4>)
|
||
|
|
8001622: 4a23 ldr r2, [pc, #140] ; (80016b0 <HAL_RCC_OscConfig+0x6a4>)
|
||
|
|
8001624: 6a12 ldr r2, [r2, #32]
|
||
|
|
8001626: 4923 ldr r1, [pc, #140] ; (80016b4 <HAL_RCC_OscConfig+0x6a8>)
|
||
|
|
8001628: 400a ands r2, r1
|
||
|
|
800162a: 621a str r2, [r3, #32]
|
||
|
|
|
||
|
|
/* Get Start Tick */
|
||
|
|
tickstart = HAL_GetTick();
|
||
|
|
800162c: f7ff f9ba bl 80009a4 <HAL_GetTick>
|
||
|
|
8001630: 0003 movs r3, r0
|
||
|
|
8001632: 617b str r3, [r7, #20]
|
||
|
|
|
||
|
|
/* Wait till HSI48 is ready */
|
||
|
|
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSI48RDY) != 0U)
|
||
|
|
8001634: e008 b.n 8001648 <HAL_RCC_OscConfig+0x63c>
|
||
|
|
{
|
||
|
|
if((HAL_GetTick() - tickstart) > HSI48_TIMEOUT_VALUE)
|
||
|
|
8001636: f7ff f9b5 bl 80009a4 <HAL_GetTick>
|
||
|
|
800163a: 0002 movs r2, r0
|
||
|
|
800163c: 697b ldr r3, [r7, #20]
|
||
|
|
800163e: 1ad3 subs r3, r2, r3
|
||
|
|
8001640: 2b02 cmp r3, #2
|
||
|
|
8001642: d901 bls.n 8001648 <HAL_RCC_OscConfig+0x63c>
|
||
|
|
{
|
||
|
|
return HAL_TIMEOUT;
|
||
|
|
8001644: 2303 movs r3, #3
|
||
|
|
8001646: e0a9 b.n 800179c <HAL_RCC_OscConfig+0x790>
|
||
|
|
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSI48RDY) != 0U)
|
||
|
|
8001648: 4b12 ldr r3, [pc, #72] ; (8001694 <HAL_RCC_OscConfig+0x688>)
|
||
|
|
800164a: 689b ldr r3, [r3, #8]
|
||
|
|
800164c: 2202 movs r2, #2
|
||
|
|
800164e: 4013 ands r3, r2
|
||
|
|
8001650: d1f1 bne.n 8001636 <HAL_RCC_OscConfig+0x62a>
|
||
|
|
#endif /* RCC_HSI48_SUPPORT */
|
||
|
|
|
||
|
|
/*-------------------------------- PLL Configuration -----------------------*/
|
||
|
|
/* Check the parameters */
|
||
|
|
assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState));
|
||
|
|
if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE)
|
||
|
|
8001652: 687b ldr r3, [r7, #4]
|
||
|
|
8001654: 6a9b ldr r3, [r3, #40] ; 0x28
|
||
|
|
8001656: 2b00 cmp r3, #0
|
||
|
|
8001658: d100 bne.n 800165c <HAL_RCC_OscConfig+0x650>
|
||
|
|
800165a: e09e b.n 800179a <HAL_RCC_OscConfig+0x78e>
|
||
|
|
{
|
||
|
|
/* Check if the PLL is used as system clock or not */
|
||
|
|
if(sysclk_source != RCC_SYSCLKSOURCE_STATUS_PLLCLK)
|
||
|
|
800165c: 69fb ldr r3, [r7, #28]
|
||
|
|
800165e: 2b0c cmp r3, #12
|
||
|
|
8001660: d100 bne.n 8001664 <HAL_RCC_OscConfig+0x658>
|
||
|
|
8001662: e077 b.n 8001754 <HAL_RCC_OscConfig+0x748>
|
||
|
|
{
|
||
|
|
if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON)
|
||
|
|
8001664: 687b ldr r3, [r7, #4]
|
||
|
|
8001666: 6a9b ldr r3, [r3, #40] ; 0x28
|
||
|
|
8001668: 2b02 cmp r3, #2
|
||
|
|
800166a: d158 bne.n 800171e <HAL_RCC_OscConfig+0x712>
|
||
|
|
assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct->PLL.PLLSource));
|
||
|
|
assert_param(IS_RCC_PLL_MUL(RCC_OscInitStruct->PLL.PLLMUL));
|
||
|
|
assert_param(IS_RCC_PLL_DIV(RCC_OscInitStruct->PLL.PLLDIV));
|
||
|
|
|
||
|
|
/* Disable the main PLL. */
|
||
|
|
__HAL_RCC_PLL_DISABLE();
|
||
|
|
800166c: 4b09 ldr r3, [pc, #36] ; (8001694 <HAL_RCC_OscConfig+0x688>)
|
||
|
|
800166e: 4a09 ldr r2, [pc, #36] ; (8001694 <HAL_RCC_OscConfig+0x688>)
|
||
|
|
8001670: 6812 ldr r2, [r2, #0]
|
||
|
|
8001672: 4911 ldr r1, [pc, #68] ; (80016b8 <HAL_RCC_OscConfig+0x6ac>)
|
||
|
|
8001674: 400a ands r2, r1
|
||
|
|
8001676: 601a str r2, [r3, #0]
|
||
|
|
|
||
|
|
/* Get Start Tick */
|
||
|
|
tickstart = HAL_GetTick();
|
||
|
|
8001678: f7ff f994 bl 80009a4 <HAL_GetTick>
|
||
|
|
800167c: 0003 movs r3, r0
|
||
|
|
800167e: 617b str r3, [r7, #20]
|
||
|
|
|
||
|
|
/* Wait till PLL is ready */
|
||
|
|
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != 0U)
|
||
|
|
8001680: e01c b.n 80016bc <HAL_RCC_OscConfig+0x6b0>
|
||
|
|
{
|
||
|
|
if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
|
||
|
|
8001682: f7ff f98f bl 80009a4 <HAL_GetTick>
|
||
|
|
8001686: 0002 movs r2, r0
|
||
|
|
8001688: 697b ldr r3, [r7, #20]
|
||
|
|
800168a: 1ad3 subs r3, r2, r3
|
||
|
|
800168c: 2b02 cmp r3, #2
|
||
|
|
800168e: d915 bls.n 80016bc <HAL_RCC_OscConfig+0x6b0>
|
||
|
|
{
|
||
|
|
return HAL_TIMEOUT;
|
||
|
|
8001690: 2303 movs r3, #3
|
||
|
|
8001692: e083 b.n 800179c <HAL_RCC_OscConfig+0x790>
|
||
|
|
8001694: 40021000 .word 0x40021000
|
||
|
|
8001698: ffff1fff .word 0xffff1fff
|
||
|
|
800169c: fffffeff .word 0xfffffeff
|
||
|
|
80016a0: 40007000 .word 0x40007000
|
||
|
|
80016a4: fffffbff .word 0xfffffbff
|
||
|
|
80016a8: 00001388 .word 0x00001388
|
||
|
|
80016ac: efffffff .word 0xefffffff
|
||
|
|
80016b0: 40010000 .word 0x40010000
|
||
|
|
80016b4: ffffdfff .word 0xffffdfff
|
||
|
|
80016b8: feffffff .word 0xfeffffff
|
||
|
|
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != 0U)
|
||
|
|
80016bc: 4b39 ldr r3, [pc, #228] ; (80017a4 <HAL_RCC_OscConfig+0x798>)
|
||
|
|
80016be: 681a ldr r2, [r3, #0]
|
||
|
|
80016c0: 2380 movs r3, #128 ; 0x80
|
||
|
|
80016c2: 049b lsls r3, r3, #18
|
||
|
|
80016c4: 4013 ands r3, r2
|
||
|
|
80016c6: d1dc bne.n 8001682 <HAL_RCC_OscConfig+0x676>
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
/* Configure the main PLL clock source, multiplication and division factors. */
|
||
|
|
__HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource,
|
||
|
|
80016c8: 4a36 ldr r2, [pc, #216] ; (80017a4 <HAL_RCC_OscConfig+0x798>)
|
||
|
|
80016ca: 4b36 ldr r3, [pc, #216] ; (80017a4 <HAL_RCC_OscConfig+0x798>)
|
||
|
|
80016cc: 68db ldr r3, [r3, #12]
|
||
|
|
80016ce: 4936 ldr r1, [pc, #216] ; (80017a8 <HAL_RCC_OscConfig+0x79c>)
|
||
|
|
80016d0: 4019 ands r1, r3
|
||
|
|
80016d2: 687b ldr r3, [r7, #4]
|
||
|
|
80016d4: 6ad8 ldr r0, [r3, #44] ; 0x2c
|
||
|
|
80016d6: 687b ldr r3, [r7, #4]
|
||
|
|
80016d8: 6b1b ldr r3, [r3, #48] ; 0x30
|
||
|
|
80016da: 4318 orrs r0, r3
|
||
|
|
80016dc: 687b ldr r3, [r7, #4]
|
||
|
|
80016de: 6b5b ldr r3, [r3, #52] ; 0x34
|
||
|
|
80016e0: 4303 orrs r3, r0
|
||
|
|
80016e2: 430b orrs r3, r1
|
||
|
|
80016e4: 60d3 str r3, [r2, #12]
|
||
|
|
RCC_OscInitStruct->PLL.PLLMUL,
|
||
|
|
RCC_OscInitStruct->PLL.PLLDIV);
|
||
|
|
/* Enable the main PLL. */
|
||
|
|
__HAL_RCC_PLL_ENABLE();
|
||
|
|
80016e6: 4b2f ldr r3, [pc, #188] ; (80017a4 <HAL_RCC_OscConfig+0x798>)
|
||
|
|
80016e8: 4a2e ldr r2, [pc, #184] ; (80017a4 <HAL_RCC_OscConfig+0x798>)
|
||
|
|
80016ea: 6812 ldr r2, [r2, #0]
|
||
|
|
80016ec: 2180 movs r1, #128 ; 0x80
|
||
|
|
80016ee: 0449 lsls r1, r1, #17
|
||
|
|
80016f0: 430a orrs r2, r1
|
||
|
|
80016f2: 601a str r2, [r3, #0]
|
||
|
|
|
||
|
|
/* Get Start Tick */
|
||
|
|
tickstart = HAL_GetTick();
|
||
|
|
80016f4: f7ff f956 bl 80009a4 <HAL_GetTick>
|
||
|
|
80016f8: 0003 movs r3, r0
|
||
|
|
80016fa: 617b str r3, [r7, #20]
|
||
|
|
|
||
|
|
/* Wait till PLL is ready */
|
||
|
|
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == 0U)
|
||
|
|
80016fc: e008 b.n 8001710 <HAL_RCC_OscConfig+0x704>
|
||
|
|
{
|
||
|
|
if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
|
||
|
|
80016fe: f7ff f951 bl 80009a4 <HAL_GetTick>
|
||
|
|
8001702: 0002 movs r2, r0
|
||
|
|
8001704: 697b ldr r3, [r7, #20]
|
||
|
|
8001706: 1ad3 subs r3, r2, r3
|
||
|
|
8001708: 2b02 cmp r3, #2
|
||
|
|
800170a: d901 bls.n 8001710 <HAL_RCC_OscConfig+0x704>
|
||
|
|
{
|
||
|
|
return HAL_TIMEOUT;
|
||
|
|
800170c: 2303 movs r3, #3
|
||
|
|
800170e: e045 b.n 800179c <HAL_RCC_OscConfig+0x790>
|
||
|
|
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == 0U)
|
||
|
|
8001710: 4b24 ldr r3, [pc, #144] ; (80017a4 <HAL_RCC_OscConfig+0x798>)
|
||
|
|
8001712: 681a ldr r2, [r3, #0]
|
||
|
|
8001714: 2380 movs r3, #128 ; 0x80
|
||
|
|
8001716: 049b lsls r3, r3, #18
|
||
|
|
8001718: 4013 ands r3, r2
|
||
|
|
800171a: d0f0 beq.n 80016fe <HAL_RCC_OscConfig+0x6f2>
|
||
|
|
800171c: e03d b.n 800179a <HAL_RCC_OscConfig+0x78e>
|
||
|
|
}
|
||
|
|
}
|
||
|
|
else
|
||
|
|
{
|
||
|
|
/* Disable the main PLL. */
|
||
|
|
__HAL_RCC_PLL_DISABLE();
|
||
|
|
800171e: 4b21 ldr r3, [pc, #132] ; (80017a4 <HAL_RCC_OscConfig+0x798>)
|
||
|
|
8001720: 4a20 ldr r2, [pc, #128] ; (80017a4 <HAL_RCC_OscConfig+0x798>)
|
||
|
|
8001722: 6812 ldr r2, [r2, #0]
|
||
|
|
8001724: 4921 ldr r1, [pc, #132] ; (80017ac <HAL_RCC_OscConfig+0x7a0>)
|
||
|
|
8001726: 400a ands r2, r1
|
||
|
|
8001728: 601a str r2, [r3, #0]
|
||
|
|
|
||
|
|
/* Get Start Tick */
|
||
|
|
tickstart = HAL_GetTick();
|
||
|
|
800172a: f7ff f93b bl 80009a4 <HAL_GetTick>
|
||
|
|
800172e: 0003 movs r3, r0
|
||
|
|
8001730: 617b str r3, [r7, #20]
|
||
|
|
|
||
|
|
/* Wait till PLL is disabled */
|
||
|
|
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != 0U)
|
||
|
|
8001732: e008 b.n 8001746 <HAL_RCC_OscConfig+0x73a>
|
||
|
|
{
|
||
|
|
if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
|
||
|
|
8001734: f7ff f936 bl 80009a4 <HAL_GetTick>
|
||
|
|
8001738: 0002 movs r2, r0
|
||
|
|
800173a: 697b ldr r3, [r7, #20]
|
||
|
|
800173c: 1ad3 subs r3, r2, r3
|
||
|
|
800173e: 2b02 cmp r3, #2
|
||
|
|
8001740: d901 bls.n 8001746 <HAL_RCC_OscConfig+0x73a>
|
||
|
|
{
|
||
|
|
return HAL_TIMEOUT;
|
||
|
|
8001742: 2303 movs r3, #3
|
||
|
|
8001744: e02a b.n 800179c <HAL_RCC_OscConfig+0x790>
|
||
|
|
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != 0U)
|
||
|
|
8001746: 4b17 ldr r3, [pc, #92] ; (80017a4 <HAL_RCC_OscConfig+0x798>)
|
||
|
|
8001748: 681a ldr r2, [r3, #0]
|
||
|
|
800174a: 2380 movs r3, #128 ; 0x80
|
||
|
|
800174c: 049b lsls r3, r3, #18
|
||
|
|
800174e: 4013 ands r3, r2
|
||
|
|
8001750: d1f0 bne.n 8001734 <HAL_RCC_OscConfig+0x728>
|
||
|
|
8001752: e022 b.n 800179a <HAL_RCC_OscConfig+0x78e>
|
||
|
|
}
|
||
|
|
}
|
||
|
|
else
|
||
|
|
{
|
||
|
|
/* Check if there is a request to disable the PLL used as System clock source */
|
||
|
|
if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF)
|
||
|
|
8001754: 687b ldr r3, [r7, #4]
|
||
|
|
8001756: 6a9b ldr r3, [r3, #40] ; 0x28
|
||
|
|
8001758: 2b01 cmp r3, #1
|
||
|
|
800175a: d101 bne.n 8001760 <HAL_RCC_OscConfig+0x754>
|
||
|
|
{
|
||
|
|
return HAL_ERROR;
|
||
|
|
800175c: 2301 movs r3, #1
|
||
|
|
800175e: e01d b.n 800179c <HAL_RCC_OscConfig+0x790>
|
||
|
|
}
|
||
|
|
else
|
||
|
|
{
|
||
|
|
/* Do not return HAL_ERROR if request repeats the current configuration */
|
||
|
|
pll_config = RCC->CFGR;
|
||
|
|
8001760: 4b10 ldr r3, [pc, #64] ; (80017a4 <HAL_RCC_OscConfig+0x798>)
|
||
|
|
8001762: 68db ldr r3, [r3, #12]
|
||
|
|
8001764: 61bb str r3, [r7, #24]
|
||
|
|
if((READ_BIT(pll_config, RCC_CFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
|
||
|
|
8001766: 69ba ldr r2, [r7, #24]
|
||
|
|
8001768: 2380 movs r3, #128 ; 0x80
|
||
|
|
800176a: 025b lsls r3, r3, #9
|
||
|
|
800176c: 401a ands r2, r3
|
||
|
|
800176e: 687b ldr r3, [r7, #4]
|
||
|
|
8001770: 6adb ldr r3, [r3, #44] ; 0x2c
|
||
|
|
8001772: 429a cmp r2, r3
|
||
|
|
8001774: d10f bne.n 8001796 <HAL_RCC_OscConfig+0x78a>
|
||
|
|
(READ_BIT(pll_config, RCC_CFGR_PLLMUL) != RCC_OscInitStruct->PLL.PLLMUL) ||
|
||
|
|
8001776: 69ba ldr r2, [r7, #24]
|
||
|
|
8001778: 23f0 movs r3, #240 ; 0xf0
|
||
|
|
800177a: 039b lsls r3, r3, #14
|
||
|
|
800177c: 401a ands r2, r3
|
||
|
|
800177e: 687b ldr r3, [r7, #4]
|
||
|
|
8001780: 6b1b ldr r3, [r3, #48] ; 0x30
|
||
|
|
if((READ_BIT(pll_config, RCC_CFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
|
||
|
|
8001782: 429a cmp r2, r3
|
||
|
|
8001784: d107 bne.n 8001796 <HAL_RCC_OscConfig+0x78a>
|
||
|
|
(READ_BIT(pll_config, RCC_CFGR_PLLDIV) != RCC_OscInitStruct->PLL.PLLDIV))
|
||
|
|
8001786: 69ba ldr r2, [r7, #24]
|
||
|
|
8001788: 23c0 movs r3, #192 ; 0xc0
|
||
|
|
800178a: 041b lsls r3, r3, #16
|
||
|
|
800178c: 401a ands r2, r3
|
||
|
|
800178e: 687b ldr r3, [r7, #4]
|
||
|
|
8001790: 6b5b ldr r3, [r3, #52] ; 0x34
|
||
|
|
(READ_BIT(pll_config, RCC_CFGR_PLLMUL) != RCC_OscInitStruct->PLL.PLLMUL) ||
|
||
|
|
8001792: 429a cmp r2, r3
|
||
|
|
8001794: d001 beq.n 800179a <HAL_RCC_OscConfig+0x78e>
|
||
|
|
{
|
||
|
|
return HAL_ERROR;
|
||
|
|
8001796: 2301 movs r3, #1
|
||
|
|
8001798: e000 b.n 800179c <HAL_RCC_OscConfig+0x790>
|
||
|
|
}
|
||
|
|
}
|
||
|
|
}
|
||
|
|
}
|
||
|
|
return HAL_OK;
|
||
|
|
800179a: 2300 movs r3, #0
|
||
|
|
}
|
||
|
|
800179c: 0018 movs r0, r3
|
||
|
|
800179e: 46bd mov sp, r7
|
||
|
|
80017a0: b00b add sp, #44 ; 0x2c
|
||
|
|
80017a2: bd90 pop {r4, r7, pc}
|
||
|
|
80017a4: 40021000 .word 0x40021000
|
||
|
|
80017a8: ff02ffff .word 0xff02ffff
|
||
|
|
80017ac: feffffff .word 0xfeffffff
|
||
|
|
|
||
|
|
080017b0 <HAL_RCC_ClockConfig>:
|
||
|
|
* HPRE[3:0] bits to ensure that HCLK not exceed the maximum allowed frequency
|
||
|
|
* (for more details refer to section above "Initialization/de-initialization functions")
|
||
|
|
* @retval HAL status
|
||
|
|
*/
|
||
|
|
HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency)
|
||
|
|
{
|
||
|
|
80017b0: b590 push {r4, r7, lr}
|
||
|
|
80017b2: b085 sub sp, #20
|
||
|
|
80017b4: af00 add r7, sp, #0
|
||
|
|
80017b6: 6078 str r0, [r7, #4]
|
||
|
|
80017b8: 6039 str r1, [r7, #0]
|
||
|
|
uint32_t tickstart;
|
||
|
|
HAL_StatusTypeDef status;
|
||
|
|
|
||
|
|
/* Check Null pointer */
|
||
|
|
if(RCC_ClkInitStruct == NULL)
|
||
|
|
80017ba: 687b ldr r3, [r7, #4]
|
||
|
|
80017bc: 2b00 cmp r3, #0
|
||
|
|
80017be: d101 bne.n 80017c4 <HAL_RCC_ClockConfig+0x14>
|
||
|
|
{
|
||
|
|
return HAL_ERROR;
|
||
|
|
80017c0: 2301 movs r3, #1
|
||
|
|
80017c2: e128 b.n 8001a16 <HAL_RCC_ClockConfig+0x266>
|
||
|
|
/* To correctly read data from FLASH memory, the number of wait states (LATENCY)
|
||
|
|
must be correctly programmed according to the frequency of the CPU clock
|
||
|
|
(HCLK) and the supply voltage of the device. */
|
||
|
|
|
||
|
|
/* Increasing the number of wait states because of higher CPU frequency */
|
||
|
|
if(FLatency > __HAL_FLASH_GET_LATENCY())
|
||
|
|
80017c4: 4b96 ldr r3, [pc, #600] ; (8001a20 <HAL_RCC_ClockConfig+0x270>)
|
||
|
|
80017c6: 681b ldr r3, [r3, #0]
|
||
|
|
80017c8: 2201 movs r2, #1
|
||
|
|
80017ca: 401a ands r2, r3
|
||
|
|
80017cc: 683b ldr r3, [r7, #0]
|
||
|
|
80017ce: 429a cmp r2, r3
|
||
|
|
80017d0: d21e bcs.n 8001810 <HAL_RCC_ClockConfig+0x60>
|
||
|
|
{
|
||
|
|
/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
|
||
|
|
__HAL_FLASH_SET_LATENCY(FLatency);
|
||
|
|
80017d2: 4b93 ldr r3, [pc, #588] ; (8001a20 <HAL_RCC_ClockConfig+0x270>)
|
||
|
|
80017d4: 4a92 ldr r2, [pc, #584] ; (8001a20 <HAL_RCC_ClockConfig+0x270>)
|
||
|
|
80017d6: 6812 ldr r2, [r2, #0]
|
||
|
|
80017d8: 2101 movs r1, #1
|
||
|
|
80017da: 438a bics r2, r1
|
||
|
|
80017dc: 0011 movs r1, r2
|
||
|
|
80017de: 683a ldr r2, [r7, #0]
|
||
|
|
80017e0: 430a orrs r2, r1
|
||
|
|
80017e2: 601a str r2, [r3, #0]
|
||
|
|
|
||
|
|
/* Check that the new number of wait states is taken into account to access the Flash
|
||
|
|
memory by polling the FLASH_ACR register */
|
||
|
|
tickstart = HAL_GetTick();
|
||
|
|
80017e4: f7ff f8de bl 80009a4 <HAL_GetTick>
|
||
|
|
80017e8: 0003 movs r3, r0
|
||
|
|
80017ea: 60fb str r3, [r7, #12]
|
||
|
|
|
||
|
|
while (__HAL_FLASH_GET_LATENCY() != FLatency)
|
||
|
|
80017ec: e009 b.n 8001802 <HAL_RCC_ClockConfig+0x52>
|
||
|
|
{
|
||
|
|
if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
|
||
|
|
80017ee: f7ff f8d9 bl 80009a4 <HAL_GetTick>
|
||
|
|
80017f2: 0002 movs r2, r0
|
||
|
|
80017f4: 68fb ldr r3, [r7, #12]
|
||
|
|
80017f6: 1ad3 subs r3, r2, r3
|
||
|
|
80017f8: 4a8a ldr r2, [pc, #552] ; (8001a24 <HAL_RCC_ClockConfig+0x274>)
|
||
|
|
80017fa: 4293 cmp r3, r2
|
||
|
|
80017fc: d901 bls.n 8001802 <HAL_RCC_ClockConfig+0x52>
|
||
|
|
{
|
||
|
|
return HAL_TIMEOUT;
|
||
|
|
80017fe: 2303 movs r3, #3
|
||
|
|
8001800: e109 b.n 8001a16 <HAL_RCC_ClockConfig+0x266>
|
||
|
|
while (__HAL_FLASH_GET_LATENCY() != FLatency)
|
||
|
|
8001802: 4b87 ldr r3, [pc, #540] ; (8001a20 <HAL_RCC_ClockConfig+0x270>)
|
||
|
|
8001804: 681b ldr r3, [r3, #0]
|
||
|
|
8001806: 2201 movs r2, #1
|
||
|
|
8001808: 401a ands r2, r3
|
||
|
|
800180a: 683b ldr r3, [r7, #0]
|
||
|
|
800180c: 429a cmp r2, r3
|
||
|
|
800180e: d1ee bne.n 80017ee <HAL_RCC_ClockConfig+0x3e>
|
||
|
|
}
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
/*-------------------------- HCLK Configuration --------------------------*/
|
||
|
|
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
|
||
|
|
8001810: 687b ldr r3, [r7, #4]
|
||
|
|
8001812: 681b ldr r3, [r3, #0]
|
||
|
|
8001814: 2202 movs r2, #2
|
||
|
|
8001816: 4013 ands r3, r2
|
||
|
|
8001818: d009 beq.n 800182e <HAL_RCC_ClockConfig+0x7e>
|
||
|
|
{
|
||
|
|
assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));
|
||
|
|
MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
|
||
|
|
800181a: 4a83 ldr r2, [pc, #524] ; (8001a28 <HAL_RCC_ClockConfig+0x278>)
|
||
|
|
800181c: 4b82 ldr r3, [pc, #520] ; (8001a28 <HAL_RCC_ClockConfig+0x278>)
|
||
|
|
800181e: 68db ldr r3, [r3, #12]
|
||
|
|
8001820: 21f0 movs r1, #240 ; 0xf0
|
||
|
|
8001822: 438b bics r3, r1
|
||
|
|
8001824: 0019 movs r1, r3
|
||
|
|
8001826: 687b ldr r3, [r7, #4]
|
||
|
|
8001828: 689b ldr r3, [r3, #8]
|
||
|
|
800182a: 430b orrs r3, r1
|
||
|
|
800182c: 60d3 str r3, [r2, #12]
|
||
|
|
}
|
||
|
|
|
||
|
|
/*------------------------- SYSCLK Configuration ---------------------------*/
|
||
|
|
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
|
||
|
|
800182e: 687b ldr r3, [r7, #4]
|
||
|
|
8001830: 681b ldr r3, [r3, #0]
|
||
|
|
8001832: 2201 movs r2, #1
|
||
|
|
8001834: 4013 ands r3, r2
|
||
|
|
8001836: d100 bne.n 800183a <HAL_RCC_ClockConfig+0x8a>
|
||
|
|
8001838: e089 b.n 800194e <HAL_RCC_ClockConfig+0x19e>
|
||
|
|
{
|
||
|
|
assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource));
|
||
|
|
|
||
|
|
/* HSE is selected as System Clock Source */
|
||
|
|
if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
|
||
|
|
800183a: 687b ldr r3, [r7, #4]
|
||
|
|
800183c: 685b ldr r3, [r3, #4]
|
||
|
|
800183e: 2b02 cmp r3, #2
|
||
|
|
8001840: d107 bne.n 8001852 <HAL_RCC_ClockConfig+0xa2>
|
||
|
|
{
|
||
|
|
/* Check the HSE ready flag */
|
||
|
|
if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == 0U)
|
||
|
|
8001842: 4b79 ldr r3, [pc, #484] ; (8001a28 <HAL_RCC_ClockConfig+0x278>)
|
||
|
|
8001844: 681a ldr r2, [r3, #0]
|
||
|
|
8001846: 2380 movs r3, #128 ; 0x80
|
||
|
|
8001848: 029b lsls r3, r3, #10
|
||
|
|
800184a: 4013 ands r3, r2
|
||
|
|
800184c: d120 bne.n 8001890 <HAL_RCC_ClockConfig+0xe0>
|
||
|
|
{
|
||
|
|
return HAL_ERROR;
|
||
|
|
800184e: 2301 movs r3, #1
|
||
|
|
8001850: e0e1 b.n 8001a16 <HAL_RCC_ClockConfig+0x266>
|
||
|
|
}
|
||
|
|
}
|
||
|
|
/* PLL is selected as System Clock Source */
|
||
|
|
else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
|
||
|
|
8001852: 687b ldr r3, [r7, #4]
|
||
|
|
8001854: 685b ldr r3, [r3, #4]
|
||
|
|
8001856: 2b03 cmp r3, #3
|
||
|
|
8001858: d107 bne.n 800186a <HAL_RCC_ClockConfig+0xba>
|
||
|
|
{
|
||
|
|
/* Check the PLL ready flag */
|
||
|
|
if(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == 0U)
|
||
|
|
800185a: 4b73 ldr r3, [pc, #460] ; (8001a28 <HAL_RCC_ClockConfig+0x278>)
|
||
|
|
800185c: 681a ldr r2, [r3, #0]
|
||
|
|
800185e: 2380 movs r3, #128 ; 0x80
|
||
|
|
8001860: 049b lsls r3, r3, #18
|
||
|
|
8001862: 4013 ands r3, r2
|
||
|
|
8001864: d114 bne.n 8001890 <HAL_RCC_ClockConfig+0xe0>
|
||
|
|
{
|
||
|
|
return HAL_ERROR;
|
||
|
|
8001866: 2301 movs r3, #1
|
||
|
|
8001868: e0d5 b.n 8001a16 <HAL_RCC_ClockConfig+0x266>
|
||
|
|
}
|
||
|
|
}
|
||
|
|
/* HSI is selected as System Clock Source */
|
||
|
|
else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSI)
|
||
|
|
800186a: 687b ldr r3, [r7, #4]
|
||
|
|
800186c: 685b ldr r3, [r3, #4]
|
||
|
|
800186e: 2b01 cmp r3, #1
|
||
|
|
8001870: d106 bne.n 8001880 <HAL_RCC_ClockConfig+0xd0>
|
||
|
|
{
|
||
|
|
/* Check the HSI ready flag */
|
||
|
|
if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == 0U)
|
||
|
|
8001872: 4b6d ldr r3, [pc, #436] ; (8001a28 <HAL_RCC_ClockConfig+0x278>)
|
||
|
|
8001874: 681b ldr r3, [r3, #0]
|
||
|
|
8001876: 2204 movs r2, #4
|
||
|
|
8001878: 4013 ands r3, r2
|
||
|
|
800187a: d109 bne.n 8001890 <HAL_RCC_ClockConfig+0xe0>
|
||
|
|
{
|
||
|
|
return HAL_ERROR;
|
||
|
|
800187c: 2301 movs r3, #1
|
||
|
|
800187e: e0ca b.n 8001a16 <HAL_RCC_ClockConfig+0x266>
|
||
|
|
}
|
||
|
|
/* MSI is selected as System Clock Source */
|
||
|
|
else
|
||
|
|
{
|
||
|
|
/* Check the MSI ready flag */
|
||
|
|
if(__HAL_RCC_GET_FLAG(RCC_FLAG_MSIRDY) == 0U)
|
||
|
|
8001880: 4b69 ldr r3, [pc, #420] ; (8001a28 <HAL_RCC_ClockConfig+0x278>)
|
||
|
|
8001882: 681a ldr r2, [r3, #0]
|
||
|
|
8001884: 2380 movs r3, #128 ; 0x80
|
||
|
|
8001886: 009b lsls r3, r3, #2
|
||
|
|
8001888: 4013 ands r3, r2
|
||
|
|
800188a: d101 bne.n 8001890 <HAL_RCC_ClockConfig+0xe0>
|
||
|
|
{
|
||
|
|
return HAL_ERROR;
|
||
|
|
800188c: 2301 movs r3, #1
|
||
|
|
800188e: e0c2 b.n 8001a16 <HAL_RCC_ClockConfig+0x266>
|
||
|
|
}
|
||
|
|
}
|
||
|
|
__HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource);
|
||
|
|
8001890: 4a65 ldr r2, [pc, #404] ; (8001a28 <HAL_RCC_ClockConfig+0x278>)
|
||
|
|
8001892: 4b65 ldr r3, [pc, #404] ; (8001a28 <HAL_RCC_ClockConfig+0x278>)
|
||
|
|
8001894: 68db ldr r3, [r3, #12]
|
||
|
|
8001896: 2103 movs r1, #3
|
||
|
|
8001898: 438b bics r3, r1
|
||
|
|
800189a: 0019 movs r1, r3
|
||
|
|
800189c: 687b ldr r3, [r7, #4]
|
||
|
|
800189e: 685b ldr r3, [r3, #4]
|
||
|
|
80018a0: 430b orrs r3, r1
|
||
|
|
80018a2: 60d3 str r3, [r2, #12]
|
||
|
|
|
||
|
|
/* Get Start Tick */
|
||
|
|
tickstart = HAL_GetTick();
|
||
|
|
80018a4: f7ff f87e bl 80009a4 <HAL_GetTick>
|
||
|
|
80018a8: 0003 movs r3, r0
|
||
|
|
80018aa: 60fb str r3, [r7, #12]
|
||
|
|
|
||
|
|
if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
|
||
|
|
80018ac: 687b ldr r3, [r7, #4]
|
||
|
|
80018ae: 685b ldr r3, [r3, #4]
|
||
|
|
80018b0: 2b02 cmp r3, #2
|
||
|
|
80018b2: d111 bne.n 80018d8 <HAL_RCC_ClockConfig+0x128>
|
||
|
|
{
|
||
|
|
while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSE)
|
||
|
|
80018b4: e009 b.n 80018ca <HAL_RCC_ClockConfig+0x11a>
|
||
|
|
{
|
||
|
|
if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
|
||
|
|
80018b6: f7ff f875 bl 80009a4 <HAL_GetTick>
|
||
|
|
80018ba: 0002 movs r2, r0
|
||
|
|
80018bc: 68fb ldr r3, [r7, #12]
|
||
|
|
80018be: 1ad3 subs r3, r2, r3
|
||
|
|
80018c0: 4a58 ldr r2, [pc, #352] ; (8001a24 <HAL_RCC_ClockConfig+0x274>)
|
||
|
|
80018c2: 4293 cmp r3, r2
|
||
|
|
80018c4: d901 bls.n 80018ca <HAL_RCC_ClockConfig+0x11a>
|
||
|
|
{
|
||
|
|
return HAL_TIMEOUT;
|
||
|
|
80018c6: 2303 movs r3, #3
|
||
|
|
80018c8: e0a5 b.n 8001a16 <HAL_RCC_ClockConfig+0x266>
|
||
|
|
while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSE)
|
||
|
|
80018ca: 4b57 ldr r3, [pc, #348] ; (8001a28 <HAL_RCC_ClockConfig+0x278>)
|
||
|
|
80018cc: 68db ldr r3, [r3, #12]
|
||
|
|
80018ce: 220c movs r2, #12
|
||
|
|
80018d0: 4013 ands r3, r2
|
||
|
|
80018d2: 2b08 cmp r3, #8
|
||
|
|
80018d4: d1ef bne.n 80018b6 <HAL_RCC_ClockConfig+0x106>
|
||
|
|
80018d6: e03a b.n 800194e <HAL_RCC_ClockConfig+0x19e>
|
||
|
|
}
|
||
|
|
}
|
||
|
|
}
|
||
|
|
else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
|
||
|
|
80018d8: 687b ldr r3, [r7, #4]
|
||
|
|
80018da: 685b ldr r3, [r3, #4]
|
||
|
|
80018dc: 2b03 cmp r3, #3
|
||
|
|
80018de: d111 bne.n 8001904 <HAL_RCC_ClockConfig+0x154>
|
||
|
|
{
|
||
|
|
while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK)
|
||
|
|
80018e0: e009 b.n 80018f6 <HAL_RCC_ClockConfig+0x146>
|
||
|
|
{
|
||
|
|
if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
|
||
|
|
80018e2: f7ff f85f bl 80009a4 <HAL_GetTick>
|
||
|
|
80018e6: 0002 movs r2, r0
|
||
|
|
80018e8: 68fb ldr r3, [r7, #12]
|
||
|
|
80018ea: 1ad3 subs r3, r2, r3
|
||
|
|
80018ec: 4a4d ldr r2, [pc, #308] ; (8001a24 <HAL_RCC_ClockConfig+0x274>)
|
||
|
|
80018ee: 4293 cmp r3, r2
|
||
|
|
80018f0: d901 bls.n 80018f6 <HAL_RCC_ClockConfig+0x146>
|
||
|
|
{
|
||
|
|
return HAL_TIMEOUT;
|
||
|
|
80018f2: 2303 movs r3, #3
|
||
|
|
80018f4: e08f b.n 8001a16 <HAL_RCC_ClockConfig+0x266>
|
||
|
|
while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK)
|
||
|
|
80018f6: 4b4c ldr r3, [pc, #304] ; (8001a28 <HAL_RCC_ClockConfig+0x278>)
|
||
|
|
80018f8: 68db ldr r3, [r3, #12]
|
||
|
|
80018fa: 220c movs r2, #12
|
||
|
|
80018fc: 4013 ands r3, r2
|
||
|
|
80018fe: 2b0c cmp r3, #12
|
||
|
|
8001900: d1ef bne.n 80018e2 <HAL_RCC_ClockConfig+0x132>
|
||
|
|
8001902: e024 b.n 800194e <HAL_RCC_ClockConfig+0x19e>
|
||
|
|
}
|
||
|
|
}
|
||
|
|
}
|
||
|
|
else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSI)
|
||
|
|
8001904: 687b ldr r3, [r7, #4]
|
||
|
|
8001906: 685b ldr r3, [r3, #4]
|
||
|
|
8001908: 2b01 cmp r3, #1
|
||
|
|
800190a: d11b bne.n 8001944 <HAL_RCC_ClockConfig+0x194>
|
||
|
|
{
|
||
|
|
while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSI)
|
||
|
|
800190c: e009 b.n 8001922 <HAL_RCC_ClockConfig+0x172>
|
||
|
|
{
|
||
|
|
if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
|
||
|
|
800190e: f7ff f849 bl 80009a4 <HAL_GetTick>
|
||
|
|
8001912: 0002 movs r2, r0
|
||
|
|
8001914: 68fb ldr r3, [r7, #12]
|
||
|
|
8001916: 1ad3 subs r3, r2, r3
|
||
|
|
8001918: 4a42 ldr r2, [pc, #264] ; (8001a24 <HAL_RCC_ClockConfig+0x274>)
|
||
|
|
800191a: 4293 cmp r3, r2
|
||
|
|
800191c: d901 bls.n 8001922 <HAL_RCC_ClockConfig+0x172>
|
||
|
|
{
|
||
|
|
return HAL_TIMEOUT;
|
||
|
|
800191e: 2303 movs r3, #3
|
||
|
|
8001920: e079 b.n 8001a16 <HAL_RCC_ClockConfig+0x266>
|
||
|
|
while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSI)
|
||
|
|
8001922: 4b41 ldr r3, [pc, #260] ; (8001a28 <HAL_RCC_ClockConfig+0x278>)
|
||
|
|
8001924: 68db ldr r3, [r3, #12]
|
||
|
|
8001926: 220c movs r2, #12
|
||
|
|
8001928: 4013 ands r3, r2
|
||
|
|
800192a: 2b04 cmp r3, #4
|
||
|
|
800192c: d1ef bne.n 800190e <HAL_RCC_ClockConfig+0x15e>
|
||
|
|
800192e: e00e b.n 800194e <HAL_RCC_ClockConfig+0x19e>
|
||
|
|
}
|
||
|
|
else
|
||
|
|
{
|
||
|
|
while(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_MSI)
|
||
|
|
{
|
||
|
|
if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
|
||
|
|
8001930: f7ff f838 bl 80009a4 <HAL_GetTick>
|
||
|
|
8001934: 0002 movs r2, r0
|
||
|
|
8001936: 68fb ldr r3, [r7, #12]
|
||
|
|
8001938: 1ad3 subs r3, r2, r3
|
||
|
|
800193a: 4a3a ldr r2, [pc, #232] ; (8001a24 <HAL_RCC_ClockConfig+0x274>)
|
||
|
|
800193c: 4293 cmp r3, r2
|
||
|
|
800193e: d901 bls.n 8001944 <HAL_RCC_ClockConfig+0x194>
|
||
|
|
{
|
||
|
|
return HAL_TIMEOUT;
|
||
|
|
8001940: 2303 movs r3, #3
|
||
|
|
8001942: e068 b.n 8001a16 <HAL_RCC_ClockConfig+0x266>
|
||
|
|
while(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_MSI)
|
||
|
|
8001944: 4b38 ldr r3, [pc, #224] ; (8001a28 <HAL_RCC_ClockConfig+0x278>)
|
||
|
|
8001946: 68db ldr r3, [r3, #12]
|
||
|
|
8001948: 220c movs r2, #12
|
||
|
|
800194a: 4013 ands r3, r2
|
||
|
|
800194c: d1f0 bne.n 8001930 <HAL_RCC_ClockConfig+0x180>
|
||
|
|
}
|
||
|
|
}
|
||
|
|
}
|
||
|
|
}
|
||
|
|
/* Decreasing the number of wait states because of lower CPU frequency */
|
||
|
|
if(FLatency < __HAL_FLASH_GET_LATENCY())
|
||
|
|
800194e: 4b34 ldr r3, [pc, #208] ; (8001a20 <HAL_RCC_ClockConfig+0x270>)
|
||
|
|
8001950: 681b ldr r3, [r3, #0]
|
||
|
|
8001952: 2201 movs r2, #1
|
||
|
|
8001954: 401a ands r2, r3
|
||
|
|
8001956: 683b ldr r3, [r7, #0]
|
||
|
|
8001958: 429a cmp r2, r3
|
||
|
|
800195a: d91e bls.n 800199a <HAL_RCC_ClockConfig+0x1ea>
|
||
|
|
{
|
||
|
|
/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
|
||
|
|
__HAL_FLASH_SET_LATENCY(FLatency);
|
||
|
|
800195c: 4b30 ldr r3, [pc, #192] ; (8001a20 <HAL_RCC_ClockConfig+0x270>)
|
||
|
|
800195e: 4a30 ldr r2, [pc, #192] ; (8001a20 <HAL_RCC_ClockConfig+0x270>)
|
||
|
|
8001960: 6812 ldr r2, [r2, #0]
|
||
|
|
8001962: 2101 movs r1, #1
|
||
|
|
8001964: 438a bics r2, r1
|
||
|
|
8001966: 0011 movs r1, r2
|
||
|
|
8001968: 683a ldr r2, [r7, #0]
|
||
|
|
800196a: 430a orrs r2, r1
|
||
|
|
800196c: 601a str r2, [r3, #0]
|
||
|
|
|
||
|
|
/* Check that the new number of wait states is taken into account to access the Flash
|
||
|
|
memory by polling the FLASH_ACR register */
|
||
|
|
tickstart = HAL_GetTick();
|
||
|
|
800196e: f7ff f819 bl 80009a4 <HAL_GetTick>
|
||
|
|
8001972: 0003 movs r3, r0
|
||
|
|
8001974: 60fb str r3, [r7, #12]
|
||
|
|
|
||
|
|
while (__HAL_FLASH_GET_LATENCY() != FLatency)
|
||
|
|
8001976: e009 b.n 800198c <HAL_RCC_ClockConfig+0x1dc>
|
||
|
|
{
|
||
|
|
if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
|
||
|
|
8001978: f7ff f814 bl 80009a4 <HAL_GetTick>
|
||
|
|
800197c: 0002 movs r2, r0
|
||
|
|
800197e: 68fb ldr r3, [r7, #12]
|
||
|
|
8001980: 1ad3 subs r3, r2, r3
|
||
|
|
8001982: 4a28 ldr r2, [pc, #160] ; (8001a24 <HAL_RCC_ClockConfig+0x274>)
|
||
|
|
8001984: 4293 cmp r3, r2
|
||
|
|
8001986: d901 bls.n 800198c <HAL_RCC_ClockConfig+0x1dc>
|
||
|
|
{
|
||
|
|
return HAL_TIMEOUT;
|
||
|
|
8001988: 2303 movs r3, #3
|
||
|
|
800198a: e044 b.n 8001a16 <HAL_RCC_ClockConfig+0x266>
|
||
|
|
while (__HAL_FLASH_GET_LATENCY() != FLatency)
|
||
|
|
800198c: 4b24 ldr r3, [pc, #144] ; (8001a20 <HAL_RCC_ClockConfig+0x270>)
|
||
|
|
800198e: 681b ldr r3, [r3, #0]
|
||
|
|
8001990: 2201 movs r2, #1
|
||
|
|
8001992: 401a ands r2, r3
|
||
|
|
8001994: 683b ldr r3, [r7, #0]
|
||
|
|
8001996: 429a cmp r2, r3
|
||
|
|
8001998: d1ee bne.n 8001978 <HAL_RCC_ClockConfig+0x1c8>
|
||
|
|
}
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
/*-------------------------- PCLK1 Configuration ---------------------------*/
|
||
|
|
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
|
||
|
|
800199a: 687b ldr r3, [r7, #4]
|
||
|
|
800199c: 681b ldr r3, [r3, #0]
|
||
|
|
800199e: 2204 movs r2, #4
|
||
|
|
80019a0: 4013 ands r3, r2
|
||
|
|
80019a2: d008 beq.n 80019b6 <HAL_RCC_ClockConfig+0x206>
|
||
|
|
{
|
||
|
|
assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider));
|
||
|
|
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider);
|
||
|
|
80019a4: 4a20 ldr r2, [pc, #128] ; (8001a28 <HAL_RCC_ClockConfig+0x278>)
|
||
|
|
80019a6: 4b20 ldr r3, [pc, #128] ; (8001a28 <HAL_RCC_ClockConfig+0x278>)
|
||
|
|
80019a8: 68db ldr r3, [r3, #12]
|
||
|
|
80019aa: 4920 ldr r1, [pc, #128] ; (8001a2c <HAL_RCC_ClockConfig+0x27c>)
|
||
|
|
80019ac: 4019 ands r1, r3
|
||
|
|
80019ae: 687b ldr r3, [r7, #4]
|
||
|
|
80019b0: 68db ldr r3, [r3, #12]
|
||
|
|
80019b2: 430b orrs r3, r1
|
||
|
|
80019b4: 60d3 str r3, [r2, #12]
|
||
|
|
}
|
||
|
|
|
||
|
|
/*-------------------------- PCLK2 Configuration ---------------------------*/
|
||
|
|
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
|
||
|
|
80019b6: 687b ldr r3, [r7, #4]
|
||
|
|
80019b8: 681b ldr r3, [r3, #0]
|
||
|
|
80019ba: 2208 movs r2, #8
|
||
|
|
80019bc: 4013 ands r3, r2
|
||
|
|
80019be: d009 beq.n 80019d4 <HAL_RCC_ClockConfig+0x224>
|
||
|
|
{
|
||
|
|
assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider));
|
||
|
|
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3));
|
||
|
|
80019c0: 4a19 ldr r2, [pc, #100] ; (8001a28 <HAL_RCC_ClockConfig+0x278>)
|
||
|
|
80019c2: 4b19 ldr r3, [pc, #100] ; (8001a28 <HAL_RCC_ClockConfig+0x278>)
|
||
|
|
80019c4: 68db ldr r3, [r3, #12]
|
||
|
|
80019c6: 491a ldr r1, [pc, #104] ; (8001a30 <HAL_RCC_ClockConfig+0x280>)
|
||
|
|
80019c8: 4019 ands r1, r3
|
||
|
|
80019ca: 687b ldr r3, [r7, #4]
|
||
|
|
80019cc: 691b ldr r3, [r3, #16]
|
||
|
|
80019ce: 00db lsls r3, r3, #3
|
||
|
|
80019d0: 430b orrs r3, r1
|
||
|
|
80019d2: 60d3 str r3, [r2, #12]
|
||
|
|
}
|
||
|
|
|
||
|
|
/* Update the SystemCoreClock global variable */
|
||
|
|
SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE)>> RCC_CFGR_HPRE_Pos];
|
||
|
|
80019d4: f000 f834 bl 8001a40 <HAL_RCC_GetSysClockFreq>
|
||
|
|
80019d8: 0001 movs r1, r0
|
||
|
|
80019da: 4b13 ldr r3, [pc, #76] ; (8001a28 <HAL_RCC_ClockConfig+0x278>)
|
||
|
|
80019dc: 68db ldr r3, [r3, #12]
|
||
|
|
80019de: 091b lsrs r3, r3, #4
|
||
|
|
80019e0: 220f movs r2, #15
|
||
|
|
80019e2: 4013 ands r3, r2
|
||
|
|
80019e4: 4a13 ldr r2, [pc, #76] ; (8001a34 <HAL_RCC_ClockConfig+0x284>)
|
||
|
|
80019e6: 5cd3 ldrb r3, [r2, r3]
|
||
|
|
80019e8: 000a movs r2, r1
|
||
|
|
80019ea: 40da lsrs r2, r3
|
||
|
|
80019ec: 4b12 ldr r3, [pc, #72] ; (8001a38 <HAL_RCC_ClockConfig+0x288>)
|
||
|
|
80019ee: 601a str r2, [r3, #0]
|
||
|
|
|
||
|
|
/* Configure the source of time base considering new system clocks settings*/
|
||
|
|
status = HAL_InitTick(uwTickPrio);
|
||
|
|
80019f0: 4b12 ldr r3, [pc, #72] ; (8001a3c <HAL_RCC_ClockConfig+0x28c>)
|
||
|
|
80019f2: 681b ldr r3, [r3, #0]
|
||
|
|
80019f4: 220b movs r2, #11
|
||
|
|
80019f6: 18bc adds r4, r7, r2
|
||
|
|
80019f8: 0018 movs r0, r3
|
||
|
|
80019fa: f7fe ff8d bl 8000918 <HAL_InitTick>
|
||
|
|
80019fe: 0003 movs r3, r0
|
||
|
|
8001a00: 7023 strb r3, [r4, #0]
|
||
|
|
if(status != HAL_OK)
|
||
|
|
8001a02: 230b movs r3, #11
|
||
|
|
8001a04: 18fb adds r3, r7, r3
|
||
|
|
8001a06: 781b ldrb r3, [r3, #0]
|
||
|
|
8001a08: 2b00 cmp r3, #0
|
||
|
|
8001a0a: d003 beq.n 8001a14 <HAL_RCC_ClockConfig+0x264>
|
||
|
|
{
|
||
|
|
return status;
|
||
|
|
8001a0c: 230b movs r3, #11
|
||
|
|
8001a0e: 18fb adds r3, r7, r3
|
||
|
|
8001a10: 781b ldrb r3, [r3, #0]
|
||
|
|
8001a12: e000 b.n 8001a16 <HAL_RCC_ClockConfig+0x266>
|
||
|
|
}
|
||
|
|
|
||
|
|
return HAL_OK;
|
||
|
|
8001a14: 2300 movs r3, #0
|
||
|
|
}
|
||
|
|
8001a16: 0018 movs r0, r3
|
||
|
|
8001a18: 46bd mov sp, r7
|
||
|
|
8001a1a: b005 add sp, #20
|
||
|
|
8001a1c: bd90 pop {r4, r7, pc}
|
||
|
|
8001a1e: 46c0 nop ; (mov r8, r8)
|
||
|
|
8001a20: 40022000 .word 0x40022000
|
||
|
|
8001a24: 00001388 .word 0x00001388
|
||
|
|
8001a28: 40021000 .word 0x40021000
|
||
|
|
8001a2c: fffff8ff .word 0xfffff8ff
|
||
|
|
8001a30: ffffc7ff .word 0xffffc7ff
|
||
|
|
8001a34: 08002d90 .word 0x08002d90
|
||
|
|
8001a38: 20000000 .word 0x20000000
|
||
|
|
8001a3c: 20000004 .word 0x20000004
|
||
|
|
|
||
|
|
08001a40 <HAL_RCC_GetSysClockFreq>:
|
||
|
|
* right SYSCLK value. Otherwise, any configuration based on this function will be incorrect.
|
||
|
|
*
|
||
|
|
* @retval SYSCLK frequency
|
||
|
|
*/
|
||
|
|
uint32_t HAL_RCC_GetSysClockFreq(void)
|
||
|
|
{
|
||
|
|
8001a40: b5f0 push {r4, r5, r6, r7, lr}
|
||
|
|
8001a42: b08f sub sp, #60 ; 0x3c
|
||
|
|
8001a44: af00 add r7, sp, #0
|
||
|
|
uint32_t tmpreg, pllm, plld, pllvco, msiclkrange; /* no init needed */
|
||
|
|
uint32_t sysclockfreq;
|
||
|
|
|
||
|
|
tmpreg = RCC->CFGR;
|
||
|
|
8001a46: 4b4a ldr r3, [pc, #296] ; (8001b70 <HAL_RCC_GetSysClockFreq+0x130>)
|
||
|
|
8001a48: 68db ldr r3, [r3, #12]
|
||
|
|
8001a4a: 62fb str r3, [r7, #44] ; 0x2c
|
||
|
|
|
||
|
|
/* Get SYSCLK source -------------------------------------------------------*/
|
||
|
|
switch (tmpreg & RCC_CFGR_SWS)
|
||
|
|
8001a4c: 6afa ldr r2, [r7, #44] ; 0x2c
|
||
|
|
8001a4e: 230c movs r3, #12
|
||
|
|
8001a50: 4013 ands r3, r2
|
||
|
|
8001a52: 2b08 cmp r3, #8
|
||
|
|
8001a54: d00f beq.n 8001a76 <HAL_RCC_GetSysClockFreq+0x36>
|
||
|
|
8001a56: 2b0c cmp r3, #12
|
||
|
|
8001a58: d010 beq.n 8001a7c <HAL_RCC_GetSysClockFreq+0x3c>
|
||
|
|
8001a5a: 2b04 cmp r3, #4
|
||
|
|
8001a5c: d000 beq.n 8001a60 <HAL_RCC_GetSysClockFreq+0x20>
|
||
|
|
8001a5e: e073 b.n 8001b48 <HAL_RCC_GetSysClockFreq+0x108>
|
||
|
|
{
|
||
|
|
case RCC_SYSCLKSOURCE_STATUS_HSI: /* HSI used as system clock source */
|
||
|
|
{
|
||
|
|
if ((RCC->CR & RCC_CR_HSIDIVF) != 0U)
|
||
|
|
8001a60: 4b43 ldr r3, [pc, #268] ; (8001b70 <HAL_RCC_GetSysClockFreq+0x130>)
|
||
|
|
8001a62: 681b ldr r3, [r3, #0]
|
||
|
|
8001a64: 2210 movs r2, #16
|
||
|
|
8001a66: 4013 ands r3, r2
|
||
|
|
8001a68: d002 beq.n 8001a70 <HAL_RCC_GetSysClockFreq+0x30>
|
||
|
|
{
|
||
|
|
sysclockfreq = (HSI_VALUE >> 2);
|
||
|
|
8001a6a: 4b42 ldr r3, [pc, #264] ; (8001b74 <HAL_RCC_GetSysClockFreq+0x134>)
|
||
|
|
8001a6c: 633b str r3, [r7, #48] ; 0x30
|
||
|
|
}
|
||
|
|
else
|
||
|
|
{
|
||
|
|
sysclockfreq = HSI_VALUE;
|
||
|
|
}
|
||
|
|
break;
|
||
|
|
8001a6e: e079 b.n 8001b64 <HAL_RCC_GetSysClockFreq+0x124>
|
||
|
|
sysclockfreq = HSI_VALUE;
|
||
|
|
8001a70: 4b41 ldr r3, [pc, #260] ; (8001b78 <HAL_RCC_GetSysClockFreq+0x138>)
|
||
|
|
8001a72: 633b str r3, [r7, #48] ; 0x30
|
||
|
|
break;
|
||
|
|
8001a74: e076 b.n 8001b64 <HAL_RCC_GetSysClockFreq+0x124>
|
||
|
|
}
|
||
|
|
case RCC_SYSCLKSOURCE_STATUS_HSE: /* HSE used as system clock */
|
||
|
|
{
|
||
|
|
sysclockfreq = HSE_VALUE;
|
||
|
|
8001a76: 4b41 ldr r3, [pc, #260] ; (8001b7c <HAL_RCC_GetSysClockFreq+0x13c>)
|
||
|
|
8001a78: 633b str r3, [r7, #48] ; 0x30
|
||
|
|
break;
|
||
|
|
8001a7a: e073 b.n 8001b64 <HAL_RCC_GetSysClockFreq+0x124>
|
||
|
|
}
|
||
|
|
case RCC_SYSCLKSOURCE_STATUS_PLLCLK: /* PLL used as system clock */
|
||
|
|
{
|
||
|
|
pllm = PLLMulTable[(uint32_t)(tmpreg & RCC_CFGR_PLLMUL) >> RCC_CFGR_PLLMUL_Pos];
|
||
|
|
8001a7c: 6afb ldr r3, [r7, #44] ; 0x2c
|
||
|
|
8001a7e: 0c9a lsrs r2, r3, #18
|
||
|
|
8001a80: 230f movs r3, #15
|
||
|
|
8001a82: 401a ands r2, r3
|
||
|
|
8001a84: 4b3e ldr r3, [pc, #248] ; (8001b80 <HAL_RCC_GetSysClockFreq+0x140>)
|
||
|
|
8001a86: 5c9b ldrb r3, [r3, r2]
|
||
|
|
8001a88: 62bb str r3, [r7, #40] ; 0x28
|
||
|
|
plld = ((uint32_t)(tmpreg & RCC_CFGR_PLLDIV) >> RCC_CFGR_PLLDIV_Pos) + 1U;
|
||
|
|
8001a8a: 6afb ldr r3, [r7, #44] ; 0x2c
|
||
|
|
8001a8c: 0d9a lsrs r2, r3, #22
|
||
|
|
8001a8e: 2303 movs r3, #3
|
||
|
|
8001a90: 4013 ands r3, r2
|
||
|
|
8001a92: 3301 adds r3, #1
|
||
|
|
8001a94: 627b str r3, [r7, #36] ; 0x24
|
||
|
|
if (__HAL_RCC_GET_PLL_OSCSOURCE() != RCC_PLLSOURCE_HSI)
|
||
|
|
8001a96: 4b36 ldr r3, [pc, #216] ; (8001b70 <HAL_RCC_GetSysClockFreq+0x130>)
|
||
|
|
8001a98: 68da ldr r2, [r3, #12]
|
||
|
|
8001a9a: 2380 movs r3, #128 ; 0x80
|
||
|
|
8001a9c: 025b lsls r3, r3, #9
|
||
|
|
8001a9e: 4013 ands r3, r2
|
||
|
|
8001aa0: d019 beq.n 8001ad6 <HAL_RCC_GetSysClockFreq+0x96>
|
||
|
|
{
|
||
|
|
/* HSE used as PLL clock source */
|
||
|
|
pllvco = (uint32_t)(((uint64_t)HSE_VALUE * (uint64_t)pllm) / (uint64_t)plld);
|
||
|
|
8001aa2: 6abb ldr r3, [r7, #40] ; 0x28
|
||
|
|
8001aa4: 61bb str r3, [r7, #24]
|
||
|
|
8001aa6: 2300 movs r3, #0
|
||
|
|
8001aa8: 61fb str r3, [r7, #28]
|
||
|
|
8001aaa: 4a34 ldr r2, [pc, #208] ; (8001b7c <HAL_RCC_GetSysClockFreq+0x13c>)
|
||
|
|
8001aac: 2300 movs r3, #0
|
||
|
|
8001aae: 69b8 ldr r0, [r7, #24]
|
||
|
|
8001ab0: 69f9 ldr r1, [r7, #28]
|
||
|
|
8001ab2: f7fe fbd5 bl 8000260 <__aeabi_lmul>
|
||
|
|
8001ab6: 0003 movs r3, r0
|
||
|
|
8001ab8: 000c movs r4, r1
|
||
|
|
8001aba: 0018 movs r0, r3
|
||
|
|
8001abc: 0021 movs r1, r4
|
||
|
|
8001abe: 6a7b ldr r3, [r7, #36] ; 0x24
|
||
|
|
8001ac0: 613b str r3, [r7, #16]
|
||
|
|
8001ac2: 2300 movs r3, #0
|
||
|
|
8001ac4: 617b str r3, [r7, #20]
|
||
|
|
8001ac6: 693a ldr r2, [r7, #16]
|
||
|
|
8001ac8: 697b ldr r3, [r7, #20]
|
||
|
|
8001aca: f7fe fba9 bl 8000220 <__aeabi_uldivmod>
|
||
|
|
8001ace: 0003 movs r3, r0
|
||
|
|
8001ad0: 000c movs r4, r1
|
||
|
|
8001ad2: 637b str r3, [r7, #52] ; 0x34
|
||
|
|
8001ad4: e035 b.n 8001b42 <HAL_RCC_GetSysClockFreq+0x102>
|
||
|
|
}
|
||
|
|
else
|
||
|
|
{
|
||
|
|
if ((RCC->CR & RCC_CR_HSIDIVF) != 0U)
|
||
|
|
8001ad6: 4b26 ldr r3, [pc, #152] ; (8001b70 <HAL_RCC_GetSysClockFreq+0x130>)
|
||
|
|
8001ad8: 681b ldr r3, [r3, #0]
|
||
|
|
8001ada: 2210 movs r2, #16
|
||
|
|
8001adc: 4013 ands r3, r2
|
||
|
|
8001ade: d019 beq.n 8001b14 <HAL_RCC_GetSysClockFreq+0xd4>
|
||
|
|
{
|
||
|
|
pllvco = (uint32_t)((((uint64_t)(HSI_VALUE >> 2)) * (uint64_t)pllm) / (uint64_t)plld);
|
||
|
|
8001ae0: 6abb ldr r3, [r7, #40] ; 0x28
|
||
|
|
8001ae2: 60bb str r3, [r7, #8]
|
||
|
|
8001ae4: 2300 movs r3, #0
|
||
|
|
8001ae6: 60fb str r3, [r7, #12]
|
||
|
|
8001ae8: 4a22 ldr r2, [pc, #136] ; (8001b74 <HAL_RCC_GetSysClockFreq+0x134>)
|
||
|
|
8001aea: 2300 movs r3, #0
|
||
|
|
8001aec: 68b8 ldr r0, [r7, #8]
|
||
|
|
8001aee: 68f9 ldr r1, [r7, #12]
|
||
|
|
8001af0: f7fe fbb6 bl 8000260 <__aeabi_lmul>
|
||
|
|
8001af4: 0003 movs r3, r0
|
||
|
|
8001af6: 000c movs r4, r1
|
||
|
|
8001af8: 0018 movs r0, r3
|
||
|
|
8001afa: 0021 movs r1, r4
|
||
|
|
8001afc: 6a7b ldr r3, [r7, #36] ; 0x24
|
||
|
|
8001afe: 603b str r3, [r7, #0]
|
||
|
|
8001b00: 2300 movs r3, #0
|
||
|
|
8001b02: 607b str r3, [r7, #4]
|
||
|
|
8001b04: 683a ldr r2, [r7, #0]
|
||
|
|
8001b06: 687b ldr r3, [r7, #4]
|
||
|
|
8001b08: f7fe fb8a bl 8000220 <__aeabi_uldivmod>
|
||
|
|
8001b0c: 0003 movs r3, r0
|
||
|
|
8001b0e: 000c movs r4, r1
|
||
|
|
8001b10: 637b str r3, [r7, #52] ; 0x34
|
||
|
|
8001b12: e016 b.n 8001b42 <HAL_RCC_GetSysClockFreq+0x102>
|
||
|
|
}
|
||
|
|
else
|
||
|
|
{
|
||
|
|
pllvco = (uint32_t)(((uint64_t)HSI_VALUE * (uint64_t)pllm) / (uint64_t)plld);
|
||
|
|
8001b14: 6abb ldr r3, [r7, #40] ; 0x28
|
||
|
|
8001b16: 0018 movs r0, r3
|
||
|
|
8001b18: 2300 movs r3, #0
|
||
|
|
8001b1a: 0019 movs r1, r3
|
||
|
|
8001b1c: 4a16 ldr r2, [pc, #88] ; (8001b78 <HAL_RCC_GetSysClockFreq+0x138>)
|
||
|
|
8001b1e: 2300 movs r3, #0
|
||
|
|
8001b20: f7fe fb9e bl 8000260 <__aeabi_lmul>
|
||
|
|
8001b24: 0003 movs r3, r0
|
||
|
|
8001b26: 000c movs r4, r1
|
||
|
|
8001b28: 0018 movs r0, r3
|
||
|
|
8001b2a: 0021 movs r1, r4
|
||
|
|
8001b2c: 6a7b ldr r3, [r7, #36] ; 0x24
|
||
|
|
8001b2e: 001d movs r5, r3
|
||
|
|
8001b30: 2300 movs r3, #0
|
||
|
|
8001b32: 001e movs r6, r3
|
||
|
|
8001b34: 002a movs r2, r5
|
||
|
|
8001b36: 0033 movs r3, r6
|
||
|
|
8001b38: f7fe fb72 bl 8000220 <__aeabi_uldivmod>
|
||
|
|
8001b3c: 0003 movs r3, r0
|
||
|
|
8001b3e: 000c movs r4, r1
|
||
|
|
8001b40: 637b str r3, [r7, #52] ; 0x34
|
||
|
|
}
|
||
|
|
}
|
||
|
|
sysclockfreq = pllvco;
|
||
|
|
8001b42: 6b7b ldr r3, [r7, #52] ; 0x34
|
||
|
|
8001b44: 633b str r3, [r7, #48] ; 0x30
|
||
|
|
break;
|
||
|
|
8001b46: e00d b.n 8001b64 <HAL_RCC_GetSysClockFreq+0x124>
|
||
|
|
}
|
||
|
|
case RCC_SYSCLKSOURCE_STATUS_MSI: /* MSI used as system clock source */
|
||
|
|
default: /* MSI used as system clock */
|
||
|
|
{
|
||
|
|
msiclkrange = (RCC->ICSCR & RCC_ICSCR_MSIRANGE ) >> RCC_ICSCR_MSIRANGE_Pos;
|
||
|
|
8001b48: 4b09 ldr r3, [pc, #36] ; (8001b70 <HAL_RCC_GetSysClockFreq+0x130>)
|
||
|
|
8001b4a: 685b ldr r3, [r3, #4]
|
||
|
|
8001b4c: 0b5b lsrs r3, r3, #13
|
||
|
|
8001b4e: 2207 movs r2, #7
|
||
|
|
8001b50: 4013 ands r3, r2
|
||
|
|
8001b52: 623b str r3, [r7, #32]
|
||
|
|
sysclockfreq = (32768U * (1UL << (msiclkrange + 1U)));
|
||
|
|
8001b54: 6a3b ldr r3, [r7, #32]
|
||
|
|
8001b56: 3301 adds r3, #1
|
||
|
|
8001b58: 2280 movs r2, #128 ; 0x80
|
||
|
|
8001b5a: 0212 lsls r2, r2, #8
|
||
|
|
8001b5c: 409a lsls r2, r3
|
||
|
|
8001b5e: 0013 movs r3, r2
|
||
|
|
8001b60: 633b str r3, [r7, #48] ; 0x30
|
||
|
|
break;
|
||
|
|
8001b62: 46c0 nop ; (mov r8, r8)
|
||
|
|
}
|
||
|
|
}
|
||
|
|
return sysclockfreq;
|
||
|
|
8001b64: 6b3b ldr r3, [r7, #48] ; 0x30
|
||
|
|
}
|
||
|
|
8001b66: 0018 movs r0, r3
|
||
|
|
8001b68: 46bd mov sp, r7
|
||
|
|
8001b6a: b00f add sp, #60 ; 0x3c
|
||
|
|
8001b6c: bdf0 pop {r4, r5, r6, r7, pc}
|
||
|
|
8001b6e: 46c0 nop ; (mov r8, r8)
|
||
|
|
8001b70: 40021000 .word 0x40021000
|
||
|
|
8001b74: 003d0900 .word 0x003d0900
|
||
|
|
8001b78: 00f42400 .word 0x00f42400
|
||
|
|
8001b7c: 007a1200 .word 0x007a1200
|
||
|
|
8001b80: 08002da8 .word 0x08002da8
|
||
|
|
|
||
|
|
08001b84 <HAL_RCC_GetHCLKFreq>:
|
||
|
|
* @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency
|
||
|
|
* and updated within this function
|
||
|
|
* @retval HCLK frequency
|
||
|
|
*/
|
||
|
|
uint32_t HAL_RCC_GetHCLKFreq(void)
|
||
|
|
{
|
||
|
|
8001b84: b580 push {r7, lr}
|
||
|
|
8001b86: af00 add r7, sp, #0
|
||
|
|
return SystemCoreClock;
|
||
|
|
8001b88: 4b02 ldr r3, [pc, #8] ; (8001b94 <HAL_RCC_GetHCLKFreq+0x10>)
|
||
|
|
8001b8a: 681b ldr r3, [r3, #0]
|
||
|
|
}
|
||
|
|
8001b8c: 0018 movs r0, r3
|
||
|
|
8001b8e: 46bd mov sp, r7
|
||
|
|
8001b90: bd80 pop {r7, pc}
|
||
|
|
8001b92: 46c0 nop ; (mov r8, r8)
|
||
|
|
8001b94: 20000000 .word 0x20000000
|
||
|
|
|
||
|
|
08001b98 <HAL_RCC_GetPCLK1Freq>:
|
||
|
|
* @note Each time PCLK1 changes, this function must be called to update the
|
||
|
|
* right PCLK1 value. Otherwise, any configuration based on this function will be incorrect.
|
||
|
|
* @retval PCLK1 frequency
|
||
|
|
*/
|
||
|
|
uint32_t HAL_RCC_GetPCLK1Freq(void)
|
||
|
|
{
|
||
|
|
8001b98: b580 push {r7, lr}
|
||
|
|
8001b9a: af00 add r7, sp, #0
|
||
|
|
/* Get HCLK source and Compute PCLK1 frequency ---------------------------*/
|
||
|
|
return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE1) >> RCC_CFGR_PPRE1_Pos]);
|
||
|
|
8001b9c: f7ff fff2 bl 8001b84 <HAL_RCC_GetHCLKFreq>
|
||
|
|
8001ba0: 0001 movs r1, r0
|
||
|
|
8001ba2: 4b06 ldr r3, [pc, #24] ; (8001bbc <HAL_RCC_GetPCLK1Freq+0x24>)
|
||
|
|
8001ba4: 68db ldr r3, [r3, #12]
|
||
|
|
8001ba6: 0a1b lsrs r3, r3, #8
|
||
|
|
8001ba8: 2207 movs r2, #7
|
||
|
|
8001baa: 4013 ands r3, r2
|
||
|
|
8001bac: 4a04 ldr r2, [pc, #16] ; (8001bc0 <HAL_RCC_GetPCLK1Freq+0x28>)
|
||
|
|
8001bae: 5cd3 ldrb r3, [r2, r3]
|
||
|
|
8001bb0: 40d9 lsrs r1, r3
|
||
|
|
8001bb2: 000b movs r3, r1
|
||
|
|
}
|
||
|
|
8001bb4: 0018 movs r0, r3
|
||
|
|
8001bb6: 46bd mov sp, r7
|
||
|
|
8001bb8: bd80 pop {r7, pc}
|
||
|
|
8001bba: 46c0 nop ; (mov r8, r8)
|
||
|
|
8001bbc: 40021000 .word 0x40021000
|
||
|
|
8001bc0: 08002da0 .word 0x08002da0
|
||
|
|
|
||
|
|
08001bc4 <HAL_RCC_GetPCLK2Freq>:
|
||
|
|
* @note Each time PCLK2 changes, this function must be called to update the
|
||
|
|
* right PCLK2 value. Otherwise, any configuration based on this function will be incorrect.
|
||
|
|
* @retval PCLK2 frequency
|
||
|
|
*/
|
||
|
|
uint32_t HAL_RCC_GetPCLK2Freq(void)
|
||
|
|
{
|
||
|
|
8001bc4: b580 push {r7, lr}
|
||
|
|
8001bc6: af00 add r7, sp, #0
|
||
|
|
/* Get HCLK source and Compute PCLK2 frequency ---------------------------*/
|
||
|
|
return (HAL_RCC_GetHCLKFreq()>> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE2) >> RCC_CFGR_PPRE2_Pos]);
|
||
|
|
8001bc8: f7ff ffdc bl 8001b84 <HAL_RCC_GetHCLKFreq>
|
||
|
|
8001bcc: 0001 movs r1, r0
|
||
|
|
8001bce: 4b06 ldr r3, [pc, #24] ; (8001be8 <HAL_RCC_GetPCLK2Freq+0x24>)
|
||
|
|
8001bd0: 68db ldr r3, [r3, #12]
|
||
|
|
8001bd2: 0adb lsrs r3, r3, #11
|
||
|
|
8001bd4: 2207 movs r2, #7
|
||
|
|
8001bd6: 4013 ands r3, r2
|
||
|
|
8001bd8: 4a04 ldr r2, [pc, #16] ; (8001bec <HAL_RCC_GetPCLK2Freq+0x28>)
|
||
|
|
8001bda: 5cd3 ldrb r3, [r2, r3]
|
||
|
|
8001bdc: 40d9 lsrs r1, r3
|
||
|
|
8001bde: 000b movs r3, r1
|
||
|
|
}
|
||
|
|
8001be0: 0018 movs r0, r3
|
||
|
|
8001be2: 46bd mov sp, r7
|
||
|
|
8001be4: bd80 pop {r7, pc}
|
||
|
|
8001be6: 46c0 nop ; (mov r8, r8)
|
||
|
|
8001be8: 40021000 .word 0x40021000
|
||
|
|
8001bec: 08002da0 .word 0x08002da0
|
||
|
|
|
||
|
|
08001bf0 <HAL_RCCEx_PeriphCLKConfig>:
|
||
|
|
* @retval HAL status
|
||
|
|
* @note If HAL_ERROR returned, first switch-OFF HSE clock oscillator with @ref HAL_RCC_OscConfig()
|
||
|
|
* to possibly update HSE divider.
|
||
|
|
*/
|
||
|
|
HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
|
||
|
|
{
|
||
|
|
8001bf0: b580 push {r7, lr}
|
||
|
|
8001bf2: b086 sub sp, #24
|
||
|
|
8001bf4: af00 add r7, sp, #0
|
||
|
|
8001bf6: 6078 str r0, [r7, #4]
|
||
|
|
uint32_t tickstart;
|
||
|
|
uint32_t temp_reg;
|
||
|
|
FlagStatus pwrclkchanged = RESET;
|
||
|
|
8001bf8: 2317 movs r3, #23
|
||
|
|
8001bfa: 18fb adds r3, r7, r3
|
||
|
|
8001bfc: 2200 movs r2, #0
|
||
|
|
8001bfe: 701a strb r2, [r3, #0]
|
||
|
|
|
||
|
|
/* Check the parameters */
|
||
|
|
assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection));
|
||
|
|
|
||
|
|
/*------------------------------- RTC/LCD Configuration ------------------------*/
|
||
|
|
if ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC)
|
||
|
|
8001c00: 687b ldr r3, [r7, #4]
|
||
|
|
8001c02: 681b ldr r3, [r3, #0]
|
||
|
|
8001c04: 2220 movs r2, #32
|
||
|
|
8001c06: 4013 ands r3, r2
|
||
|
|
8001c08: d100 bne.n 8001c0c <HAL_RCCEx_PeriphCLKConfig+0x1c>
|
||
|
|
8001c0a: e0c2 b.n 8001d92 <HAL_RCCEx_PeriphCLKConfig+0x1a2>
|
||
|
|
#endif /* LCD */
|
||
|
|
|
||
|
|
/* As soon as function is called to change RTC clock source, activation of the
|
||
|
|
power domain is done. */
|
||
|
|
/* Requires to enable write access to Backup Domain of necessary */
|
||
|
|
if(__HAL_RCC_PWR_IS_CLK_DISABLED())
|
||
|
|
8001c0c: 4b96 ldr r3, [pc, #600] ; (8001e68 <HAL_RCCEx_PeriphCLKConfig+0x278>)
|
||
|
|
8001c0e: 6b9a ldr r2, [r3, #56] ; 0x38
|
||
|
|
8001c10: 2380 movs r3, #128 ; 0x80
|
||
|
|
8001c12: 055b lsls r3, r3, #21
|
||
|
|
8001c14: 4013 ands r3, r2
|
||
|
|
8001c16: d10a bne.n 8001c2e <HAL_RCCEx_PeriphCLKConfig+0x3e>
|
||
|
|
{
|
||
|
|
__HAL_RCC_PWR_CLK_ENABLE();
|
||
|
|
8001c18: 4b93 ldr r3, [pc, #588] ; (8001e68 <HAL_RCCEx_PeriphCLKConfig+0x278>)
|
||
|
|
8001c1a: 4a93 ldr r2, [pc, #588] ; (8001e68 <HAL_RCCEx_PeriphCLKConfig+0x278>)
|
||
|
|
8001c1c: 6b92 ldr r2, [r2, #56] ; 0x38
|
||
|
|
8001c1e: 2180 movs r1, #128 ; 0x80
|
||
|
|
8001c20: 0549 lsls r1, r1, #21
|
||
|
|
8001c22: 430a orrs r2, r1
|
||
|
|
8001c24: 639a str r2, [r3, #56] ; 0x38
|
||
|
|
pwrclkchanged = SET;
|
||
|
|
8001c26: 2317 movs r3, #23
|
||
|
|
8001c28: 18fb adds r3, r7, r3
|
||
|
|
8001c2a: 2201 movs r2, #1
|
||
|
|
8001c2c: 701a strb r2, [r3, #0]
|
||
|
|
}
|
||
|
|
|
||
|
|
if(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
|
||
|
|
8001c2e: 4b8f ldr r3, [pc, #572] ; (8001e6c <HAL_RCCEx_PeriphCLKConfig+0x27c>)
|
||
|
|
8001c30: 681a ldr r2, [r3, #0]
|
||
|
|
8001c32: 2380 movs r3, #128 ; 0x80
|
||
|
|
8001c34: 005b lsls r3, r3, #1
|
||
|
|
8001c36: 4013 ands r3, r2
|
||
|
|
8001c38: d11a bne.n 8001c70 <HAL_RCCEx_PeriphCLKConfig+0x80>
|
||
|
|
{
|
||
|
|
/* Enable write access to Backup domain */
|
||
|
|
SET_BIT(PWR->CR, PWR_CR_DBP);
|
||
|
|
8001c3a: 4b8c ldr r3, [pc, #560] ; (8001e6c <HAL_RCCEx_PeriphCLKConfig+0x27c>)
|
||
|
|
8001c3c: 4a8b ldr r2, [pc, #556] ; (8001e6c <HAL_RCCEx_PeriphCLKConfig+0x27c>)
|
||
|
|
8001c3e: 6812 ldr r2, [r2, #0]
|
||
|
|
8001c40: 2180 movs r1, #128 ; 0x80
|
||
|
|
8001c42: 0049 lsls r1, r1, #1
|
||
|
|
8001c44: 430a orrs r2, r1
|
||
|
|
8001c46: 601a str r2, [r3, #0]
|
||
|
|
|
||
|
|
/* Wait for Backup domain Write protection disable */
|
||
|
|
tickstart = HAL_GetTick();
|
||
|
|
8001c48: f7fe feac bl 80009a4 <HAL_GetTick>
|
||
|
|
8001c4c: 0003 movs r3, r0
|
||
|
|
8001c4e: 613b str r3, [r7, #16]
|
||
|
|
|
||
|
|
while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
|
||
|
|
8001c50: e008 b.n 8001c64 <HAL_RCCEx_PeriphCLKConfig+0x74>
|
||
|
|
{
|
||
|
|
if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
|
||
|
|
8001c52: f7fe fea7 bl 80009a4 <HAL_GetTick>
|
||
|
|
8001c56: 0002 movs r2, r0
|
||
|
|
8001c58: 693b ldr r3, [r7, #16]
|
||
|
|
8001c5a: 1ad3 subs r3, r2, r3
|
||
|
|
8001c5c: 2b64 cmp r3, #100 ; 0x64
|
||
|
|
8001c5e: d901 bls.n 8001c64 <HAL_RCCEx_PeriphCLKConfig+0x74>
|
||
|
|
{
|
||
|
|
return HAL_TIMEOUT;
|
||
|
|
8001c60: 2303 movs r3, #3
|
||
|
|
8001c62: e0fc b.n 8001e5e <HAL_RCCEx_PeriphCLKConfig+0x26e>
|
||
|
|
while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
|
||
|
|
8001c64: 4b81 ldr r3, [pc, #516] ; (8001e6c <HAL_RCCEx_PeriphCLKConfig+0x27c>)
|
||
|
|
8001c66: 681a ldr r2, [r3, #0]
|
||
|
|
8001c68: 2380 movs r3, #128 ; 0x80
|
||
|
|
8001c6a: 005b lsls r3, r3, #1
|
||
|
|
8001c6c: 4013 ands r3, r2
|
||
|
|
8001c6e: d0f0 beq.n 8001c52 <HAL_RCCEx_PeriphCLKConfig+0x62>
|
||
|
|
}
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
/* Check if user wants to change HSE RTC prescaler whereas HSE is enabled */
|
||
|
|
temp_reg = (RCC->CR & RCC_CR_RTCPRE);
|
||
|
|
8001c70: 4b7d ldr r3, [pc, #500] ; (8001e68 <HAL_RCCEx_PeriphCLKConfig+0x278>)
|
||
|
|
8001c72: 681a ldr r2, [r3, #0]
|
||
|
|
8001c74: 23c0 movs r3, #192 ; 0xc0
|
||
|
|
8001c76: 039b lsls r3, r3, #14
|
||
|
|
8001c78: 4013 ands r3, r2
|
||
|
|
8001c7a: 60fb str r3, [r7, #12]
|
||
|
|
if ((temp_reg != (PeriphClkInit->RTCClockSelection & RCC_CR_RTCPRE))
|
||
|
|
8001c7c: 687b ldr r3, [r7, #4]
|
||
|
|
8001c7e: 685a ldr r2, [r3, #4]
|
||
|
|
8001c80: 23c0 movs r3, #192 ; 0xc0
|
||
|
|
8001c82: 039b lsls r3, r3, #14
|
||
|
|
8001c84: 401a ands r2, r3
|
||
|
|
8001c86: 68fb ldr r3, [r7, #12]
|
||
|
|
8001c88: 429a cmp r2, r3
|
||
|
|
8001c8a: d013 beq.n 8001cb4 <HAL_RCCEx_PeriphCLKConfig+0xc4>
|
||
|
|
#if defined (LCD)
|
||
|
|
|| (temp_reg != (PeriphClkInit->LCDClockSelection & RCC_CR_RTCPRE))
|
||
|
|
#endif /* LCD */
|
||
|
|
)
|
||
|
|
{ /* Check HSE State */
|
||
|
|
if ((PeriphClkInit->RTCClockSelection & RCC_CSR_RTCSEL) == RCC_CSR_RTCSEL_HSE)
|
||
|
|
8001c8c: 687b ldr r3, [r7, #4]
|
||
|
|
8001c8e: 685a ldr r2, [r3, #4]
|
||
|
|
8001c90: 23c0 movs r3, #192 ; 0xc0
|
||
|
|
8001c92: 029b lsls r3, r3, #10
|
||
|
|
8001c94: 401a ands r2, r3
|
||
|
|
8001c96: 23c0 movs r3, #192 ; 0xc0
|
||
|
|
8001c98: 029b lsls r3, r3, #10
|
||
|
|
8001c9a: 429a cmp r2, r3
|
||
|
|
8001c9c: d10a bne.n 8001cb4 <HAL_RCCEx_PeriphCLKConfig+0xc4>
|
||
|
|
{
|
||
|
|
if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY))
|
||
|
|
8001c9e: 4b72 ldr r3, [pc, #456] ; (8001e68 <HAL_RCCEx_PeriphCLKConfig+0x278>)
|
||
|
|
8001ca0: 681a ldr r2, [r3, #0]
|
||
|
|
8001ca2: 2380 movs r3, #128 ; 0x80
|
||
|
|
8001ca4: 029b lsls r3, r3, #10
|
||
|
|
8001ca6: 401a ands r2, r3
|
||
|
|
8001ca8: 2380 movs r3, #128 ; 0x80
|
||
|
|
8001caa: 029b lsls r3, r3, #10
|
||
|
|
8001cac: 429a cmp r2, r3
|
||
|
|
8001cae: d101 bne.n 8001cb4 <HAL_RCCEx_PeriphCLKConfig+0xc4>
|
||
|
|
{
|
||
|
|
/* To update HSE divider, first switch-OFF HSE clock oscillator*/
|
||
|
|
return HAL_ERROR;
|
||
|
|
8001cb0: 2301 movs r3, #1
|
||
|
|
8001cb2: e0d4 b.n 8001e5e <HAL_RCCEx_PeriphCLKConfig+0x26e>
|
||
|
|
}
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
/* Reset the Backup domain only if the RTC Clock source selection is modified from reset value */
|
||
|
|
temp_reg = (RCC->CSR & RCC_CSR_RTCSEL);
|
||
|
|
8001cb4: 4b6c ldr r3, [pc, #432] ; (8001e68 <HAL_RCCEx_PeriphCLKConfig+0x278>)
|
||
|
|
8001cb6: 6d1a ldr r2, [r3, #80] ; 0x50
|
||
|
|
8001cb8: 23c0 movs r3, #192 ; 0xc0
|
||
|
|
8001cba: 029b lsls r3, r3, #10
|
||
|
|
8001cbc: 4013 ands r3, r2
|
||
|
|
8001cbe: 60fb str r3, [r7, #12]
|
||
|
|
|
||
|
|
if((temp_reg != 0x00000000U) && (((temp_reg != (PeriphClkInit->RTCClockSelection & RCC_CSR_RTCSEL)) \
|
||
|
|
8001cc0: 68fb ldr r3, [r7, #12]
|
||
|
|
8001cc2: 2b00 cmp r3, #0
|
||
|
|
8001cc4: d03b beq.n 8001d3e <HAL_RCCEx_PeriphCLKConfig+0x14e>
|
||
|
|
8001cc6: 687b ldr r3, [r7, #4]
|
||
|
|
8001cc8: 685a ldr r2, [r3, #4]
|
||
|
|
8001cca: 23c0 movs r3, #192 ; 0xc0
|
||
|
|
8001ccc: 029b lsls r3, r3, #10
|
||
|
|
8001cce: 401a ands r2, r3
|
||
|
|
8001cd0: 68fb ldr r3, [r7, #12]
|
||
|
|
8001cd2: 429a cmp r2, r3
|
||
|
|
8001cd4: d033 beq.n 8001d3e <HAL_RCCEx_PeriphCLKConfig+0x14e>
|
||
|
|
&& (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC))
|
||
|
|
8001cd6: 687b ldr r3, [r7, #4]
|
||
|
|
8001cd8: 681b ldr r3, [r3, #0]
|
||
|
|
8001cda: 2220 movs r2, #32
|
||
|
|
8001cdc: 4013 ands r3, r2
|
||
|
|
8001cde: d02e beq.n 8001d3e <HAL_RCCEx_PeriphCLKConfig+0x14e>
|
||
|
|
&& (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LCD) == RCC_PERIPHCLK_LCD))
|
||
|
|
#endif /* LCD */
|
||
|
|
))
|
||
|
|
{
|
||
|
|
/* Store the content of CSR register before the reset of Backup Domain */
|
||
|
|
temp_reg = (RCC->CSR & ~(RCC_CSR_RTCSEL));
|
||
|
|
8001ce0: 4b61 ldr r3, [pc, #388] ; (8001e68 <HAL_RCCEx_PeriphCLKConfig+0x278>)
|
||
|
|
8001ce2: 6d1b ldr r3, [r3, #80] ; 0x50
|
||
|
|
8001ce4: 4a62 ldr r2, [pc, #392] ; (8001e70 <HAL_RCCEx_PeriphCLKConfig+0x280>)
|
||
|
|
8001ce6: 4013 ands r3, r2
|
||
|
|
8001ce8: 60fb str r3, [r7, #12]
|
||
|
|
|
||
|
|
/* RTC Clock selection can be changed only if the Backup Domain is reset */
|
||
|
|
__HAL_RCC_BACKUPRESET_FORCE();
|
||
|
|
8001cea: 4b5f ldr r3, [pc, #380] ; (8001e68 <HAL_RCCEx_PeriphCLKConfig+0x278>)
|
||
|
|
8001cec: 4a5e ldr r2, [pc, #376] ; (8001e68 <HAL_RCCEx_PeriphCLKConfig+0x278>)
|
||
|
|
8001cee: 6d12 ldr r2, [r2, #80] ; 0x50
|
||
|
|
8001cf0: 2180 movs r1, #128 ; 0x80
|
||
|
|
8001cf2: 0309 lsls r1, r1, #12
|
||
|
|
8001cf4: 430a orrs r2, r1
|
||
|
|
8001cf6: 651a str r2, [r3, #80] ; 0x50
|
||
|
|
__HAL_RCC_BACKUPRESET_RELEASE();
|
||
|
|
8001cf8: 4b5b ldr r3, [pc, #364] ; (8001e68 <HAL_RCCEx_PeriphCLKConfig+0x278>)
|
||
|
|
8001cfa: 4a5b ldr r2, [pc, #364] ; (8001e68 <HAL_RCCEx_PeriphCLKConfig+0x278>)
|
||
|
|
8001cfc: 6d12 ldr r2, [r2, #80] ; 0x50
|
||
|
|
8001cfe: 495d ldr r1, [pc, #372] ; (8001e74 <HAL_RCCEx_PeriphCLKConfig+0x284>)
|
||
|
|
8001d00: 400a ands r2, r1
|
||
|
|
8001d02: 651a str r2, [r3, #80] ; 0x50
|
||
|
|
|
||
|
|
/* Restore the Content of CSR register */
|
||
|
|
RCC->CSR = temp_reg;
|
||
|
|
8001d04: 4b58 ldr r3, [pc, #352] ; (8001e68 <HAL_RCCEx_PeriphCLKConfig+0x278>)
|
||
|
|
8001d06: 68fa ldr r2, [r7, #12]
|
||
|
|
8001d08: 651a str r2, [r3, #80] ; 0x50
|
||
|
|
|
||
|
|
/* Wait for LSERDY if LSE was enabled */
|
||
|
|
if (HAL_IS_BIT_SET(temp_reg, RCC_CSR_LSEON))
|
||
|
|
8001d0a: 68fa ldr r2, [r7, #12]
|
||
|
|
8001d0c: 2380 movs r3, #128 ; 0x80
|
||
|
|
8001d0e: 005b lsls r3, r3, #1
|
||
|
|
8001d10: 4013 ands r3, r2
|
||
|
|
8001d12: d014 beq.n 8001d3e <HAL_RCCEx_PeriphCLKConfig+0x14e>
|
||
|
|
{
|
||
|
|
/* Get Start Tick */
|
||
|
|
tickstart = HAL_GetTick();
|
||
|
|
8001d14: f7fe fe46 bl 80009a4 <HAL_GetTick>
|
||
|
|
8001d18: 0003 movs r3, r0
|
||
|
|
8001d1a: 613b str r3, [r7, #16]
|
||
|
|
|
||
|
|
/* Wait till LSE is ready */
|
||
|
|
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == 0U)
|
||
|
|
8001d1c: e009 b.n 8001d32 <HAL_RCCEx_PeriphCLKConfig+0x142>
|
||
|
|
{
|
||
|
|
if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
|
||
|
|
8001d1e: f7fe fe41 bl 80009a4 <HAL_GetTick>
|
||
|
|
8001d22: 0002 movs r2, r0
|
||
|
|
8001d24: 693b ldr r3, [r7, #16]
|
||
|
|
8001d26: 1ad3 subs r3, r2, r3
|
||
|
|
8001d28: 4a53 ldr r2, [pc, #332] ; (8001e78 <HAL_RCCEx_PeriphCLKConfig+0x288>)
|
||
|
|
8001d2a: 4293 cmp r3, r2
|
||
|
|
8001d2c: d901 bls.n 8001d32 <HAL_RCCEx_PeriphCLKConfig+0x142>
|
||
|
|
{
|
||
|
|
return HAL_TIMEOUT;
|
||
|
|
8001d2e: 2303 movs r3, #3
|
||
|
|
8001d30: e095 b.n 8001e5e <HAL_RCCEx_PeriphCLKConfig+0x26e>
|
||
|
|
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == 0U)
|
||
|
|
8001d32: 4b4d ldr r3, [pc, #308] ; (8001e68 <HAL_RCCEx_PeriphCLKConfig+0x278>)
|
||
|
|
8001d34: 6d1a ldr r2, [r3, #80] ; 0x50
|
||
|
|
8001d36: 2380 movs r3, #128 ; 0x80
|
||
|
|
8001d38: 009b lsls r3, r3, #2
|
||
|
|
8001d3a: 4013 ands r3, r2
|
||
|
|
8001d3c: d0ef beq.n 8001d1e <HAL_RCCEx_PeriphCLKConfig+0x12e>
|
||
|
|
}
|
||
|
|
}
|
||
|
|
}
|
||
|
|
}
|
||
|
|
__HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);
|
||
|
|
8001d3e: 687b ldr r3, [r7, #4]
|
||
|
|
8001d40: 685a ldr r2, [r3, #4]
|
||
|
|
8001d42: 23c0 movs r3, #192 ; 0xc0
|
||
|
|
8001d44: 029b lsls r3, r3, #10
|
||
|
|
8001d46: 401a ands r2, r3
|
||
|
|
8001d48: 23c0 movs r3, #192 ; 0xc0
|
||
|
|
8001d4a: 029b lsls r3, r3, #10
|
||
|
|
8001d4c: 429a cmp r2, r3
|
||
|
|
8001d4e: d10b bne.n 8001d68 <HAL_RCCEx_PeriphCLKConfig+0x178>
|
||
|
|
8001d50: 4a45 ldr r2, [pc, #276] ; (8001e68 <HAL_RCCEx_PeriphCLKConfig+0x278>)
|
||
|
|
8001d52: 4b45 ldr r3, [pc, #276] ; (8001e68 <HAL_RCCEx_PeriphCLKConfig+0x278>)
|
||
|
|
8001d54: 681b ldr r3, [r3, #0]
|
||
|
|
8001d56: 4949 ldr r1, [pc, #292] ; (8001e7c <HAL_RCCEx_PeriphCLKConfig+0x28c>)
|
||
|
|
8001d58: 4019 ands r1, r3
|
||
|
|
8001d5a: 687b ldr r3, [r7, #4]
|
||
|
|
8001d5c: 6858 ldr r0, [r3, #4]
|
||
|
|
8001d5e: 23c0 movs r3, #192 ; 0xc0
|
||
|
|
8001d60: 039b lsls r3, r3, #14
|
||
|
|
8001d62: 4003 ands r3, r0
|
||
|
|
8001d64: 430b orrs r3, r1
|
||
|
|
8001d66: 6013 str r3, [r2, #0]
|
||
|
|
8001d68: 4a3f ldr r2, [pc, #252] ; (8001e68 <HAL_RCCEx_PeriphCLKConfig+0x278>)
|
||
|
|
8001d6a: 4b3f ldr r3, [pc, #252] ; (8001e68 <HAL_RCCEx_PeriphCLKConfig+0x278>)
|
||
|
|
8001d6c: 6d19 ldr r1, [r3, #80] ; 0x50
|
||
|
|
8001d6e: 687b ldr r3, [r7, #4]
|
||
|
|
8001d70: 6858 ldr r0, [r3, #4]
|
||
|
|
8001d72: 23c0 movs r3, #192 ; 0xc0
|
||
|
|
8001d74: 029b lsls r3, r3, #10
|
||
|
|
8001d76: 4003 ands r3, r0
|
||
|
|
8001d78: 430b orrs r3, r1
|
||
|
|
8001d7a: 6513 str r3, [r2, #80] ; 0x50
|
||
|
|
|
||
|
|
/* Require to disable power clock if necessary */
|
||
|
|
if(pwrclkchanged == SET)
|
||
|
|
8001d7c: 2317 movs r3, #23
|
||
|
|
8001d7e: 18fb adds r3, r7, r3
|
||
|
|
8001d80: 781b ldrb r3, [r3, #0]
|
||
|
|
8001d82: 2b01 cmp r3, #1
|
||
|
|
8001d84: d105 bne.n 8001d92 <HAL_RCCEx_PeriphCLKConfig+0x1a2>
|
||
|
|
{
|
||
|
|
__HAL_RCC_PWR_CLK_DISABLE();
|
||
|
|
8001d86: 4b38 ldr r3, [pc, #224] ; (8001e68 <HAL_RCCEx_PeriphCLKConfig+0x278>)
|
||
|
|
8001d88: 4a37 ldr r2, [pc, #220] ; (8001e68 <HAL_RCCEx_PeriphCLKConfig+0x278>)
|
||
|
|
8001d8a: 6b92 ldr r2, [r2, #56] ; 0x38
|
||
|
|
8001d8c: 493c ldr r1, [pc, #240] ; (8001e80 <HAL_RCCEx_PeriphCLKConfig+0x290>)
|
||
|
|
8001d8e: 400a ands r2, r1
|
||
|
|
8001d90: 639a str r2, [r3, #56] ; 0x38
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
#if defined (RCC_CCIPR_USART1SEL)
|
||
|
|
/*------------------------------- USART1 Configuration ------------------------*/
|
||
|
|
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1)
|
||
|
|
8001d92: 687b ldr r3, [r7, #4]
|
||
|
|
8001d94: 681b ldr r3, [r3, #0]
|
||
|
|
8001d96: 2201 movs r2, #1
|
||
|
|
8001d98: 4013 ands r3, r2
|
||
|
|
8001d9a: d009 beq.n 8001db0 <HAL_RCCEx_PeriphCLKConfig+0x1c0>
|
||
|
|
{
|
||
|
|
/* Check the parameters */
|
||
|
|
assert_param(IS_RCC_USART1CLKSOURCE(PeriphClkInit->Usart1ClockSelection));
|
||
|
|
|
||
|
|
/* Configure the USART1 clock source */
|
||
|
|
__HAL_RCC_USART1_CONFIG(PeriphClkInit->Usart1ClockSelection);
|
||
|
|
8001d9c: 4a32 ldr r2, [pc, #200] ; (8001e68 <HAL_RCCEx_PeriphCLKConfig+0x278>)
|
||
|
|
8001d9e: 4b32 ldr r3, [pc, #200] ; (8001e68 <HAL_RCCEx_PeriphCLKConfig+0x278>)
|
||
|
|
8001da0: 6cdb ldr r3, [r3, #76] ; 0x4c
|
||
|
|
8001da2: 2103 movs r1, #3
|
||
|
|
8001da4: 438b bics r3, r1
|
||
|
|
8001da6: 0019 movs r1, r3
|
||
|
|
8001da8: 687b ldr r3, [r7, #4]
|
||
|
|
8001daa: 689b ldr r3, [r3, #8]
|
||
|
|
8001dac: 430b orrs r3, r1
|
||
|
|
8001dae: 64d3 str r3, [r2, #76] ; 0x4c
|
||
|
|
}
|
||
|
|
#endif /* RCC_CCIPR_USART1SEL */
|
||
|
|
|
||
|
|
/*----------------------------- USART2 Configuration --------------------------*/
|
||
|
|
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2)
|
||
|
|
8001db0: 687b ldr r3, [r7, #4]
|
||
|
|
8001db2: 681b ldr r3, [r3, #0]
|
||
|
|
8001db4: 2202 movs r2, #2
|
||
|
|
8001db6: 4013 ands r3, r2
|
||
|
|
8001db8: d009 beq.n 8001dce <HAL_RCCEx_PeriphCLKConfig+0x1de>
|
||
|
|
{
|
||
|
|
/* Check the parameters */
|
||
|
|
assert_param(IS_RCC_USART2CLKSOURCE(PeriphClkInit->Usart2ClockSelection));
|
||
|
|
|
||
|
|
/* Configure the USART2 clock source */
|
||
|
|
__HAL_RCC_USART2_CONFIG(PeriphClkInit->Usart2ClockSelection);
|
||
|
|
8001dba: 4a2b ldr r2, [pc, #172] ; (8001e68 <HAL_RCCEx_PeriphCLKConfig+0x278>)
|
||
|
|
8001dbc: 4b2a ldr r3, [pc, #168] ; (8001e68 <HAL_RCCEx_PeriphCLKConfig+0x278>)
|
||
|
|
8001dbe: 6cdb ldr r3, [r3, #76] ; 0x4c
|
||
|
|
8001dc0: 210c movs r1, #12
|
||
|
|
8001dc2: 438b bics r3, r1
|
||
|
|
8001dc4: 0019 movs r1, r3
|
||
|
|
8001dc6: 687b ldr r3, [r7, #4]
|
||
|
|
8001dc8: 68db ldr r3, [r3, #12]
|
||
|
|
8001dca: 430b orrs r3, r1
|
||
|
|
8001dcc: 64d3 str r3, [r2, #76] ; 0x4c
|
||
|
|
}
|
||
|
|
|
||
|
|
/*------------------------------ LPUART1 Configuration ------------------------*/
|
||
|
|
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1)
|
||
|
|
8001dce: 687b ldr r3, [r7, #4]
|
||
|
|
8001dd0: 681b ldr r3, [r3, #0]
|
||
|
|
8001dd2: 2204 movs r2, #4
|
||
|
|
8001dd4: 4013 ands r3, r2
|
||
|
|
8001dd6: d008 beq.n 8001dea <HAL_RCCEx_PeriphCLKConfig+0x1fa>
|
||
|
|
{
|
||
|
|
/* Check the parameters */
|
||
|
|
assert_param(IS_RCC_LPUART1CLKSOURCE(PeriphClkInit->Lpuart1ClockSelection));
|
||
|
|
|
||
|
|
/* Configure the LPUAR1 clock source */
|
||
|
|
__HAL_RCC_LPUART1_CONFIG(PeriphClkInit->Lpuart1ClockSelection);
|
||
|
|
8001dd8: 4a23 ldr r2, [pc, #140] ; (8001e68 <HAL_RCCEx_PeriphCLKConfig+0x278>)
|
||
|
|
8001dda: 4b23 ldr r3, [pc, #140] ; (8001e68 <HAL_RCCEx_PeriphCLKConfig+0x278>)
|
||
|
|
8001ddc: 6cdb ldr r3, [r3, #76] ; 0x4c
|
||
|
|
8001dde: 4929 ldr r1, [pc, #164] ; (8001e84 <HAL_RCCEx_PeriphCLKConfig+0x294>)
|
||
|
|
8001de0: 4019 ands r1, r3
|
||
|
|
8001de2: 687b ldr r3, [r7, #4]
|
||
|
|
8001de4: 691b ldr r3, [r3, #16]
|
||
|
|
8001de6: 430b orrs r3, r1
|
||
|
|
8001de8: 64d3 str r3, [r2, #76] ; 0x4c
|
||
|
|
}
|
||
|
|
|
||
|
|
/*------------------------------ I2C1 Configuration ------------------------*/
|
||
|
|
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1)
|
||
|
|
8001dea: 687b ldr r3, [r7, #4]
|
||
|
|
8001dec: 681b ldr r3, [r3, #0]
|
||
|
|
8001dee: 2208 movs r2, #8
|
||
|
|
8001df0: 4013 ands r3, r2
|
||
|
|
8001df2: d008 beq.n 8001e06 <HAL_RCCEx_PeriphCLKConfig+0x216>
|
||
|
|
{
|
||
|
|
/* Check the parameters */
|
||
|
|
assert_param(IS_RCC_I2C1CLKSOURCE(PeriphClkInit->I2c1ClockSelection));
|
||
|
|
|
||
|
|
/* Configure the I2C1 clock source */
|
||
|
|
__HAL_RCC_I2C1_CONFIG(PeriphClkInit->I2c1ClockSelection);
|
||
|
|
8001df4: 4a1c ldr r2, [pc, #112] ; (8001e68 <HAL_RCCEx_PeriphCLKConfig+0x278>)
|
||
|
|
8001df6: 4b1c ldr r3, [pc, #112] ; (8001e68 <HAL_RCCEx_PeriphCLKConfig+0x278>)
|
||
|
|
8001df8: 6cdb ldr r3, [r3, #76] ; 0x4c
|
||
|
|
8001dfa: 4923 ldr r1, [pc, #140] ; (8001e88 <HAL_RCCEx_PeriphCLKConfig+0x298>)
|
||
|
|
8001dfc: 4019 ands r1, r3
|
||
|
|
8001dfe: 687b ldr r3, [r7, #4]
|
||
|
|
8001e00: 695b ldr r3, [r3, #20]
|
||
|
|
8001e02: 430b orrs r3, r1
|
||
|
|
8001e04: 64d3 str r3, [r2, #76] ; 0x4c
|
||
|
|
}
|
||
|
|
|
||
|
|
#if defined (RCC_CCIPR_I2C3SEL)
|
||
|
|
/*------------------------------ I2C3 Configuration ------------------------*/
|
||
|
|
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3)
|
||
|
|
8001e06: 687b ldr r3, [r7, #4]
|
||
|
|
8001e08: 681a ldr r2, [r3, #0]
|
||
|
|
8001e0a: 2380 movs r3, #128 ; 0x80
|
||
|
|
8001e0c: 005b lsls r3, r3, #1
|
||
|
|
8001e0e: 4013 ands r3, r2
|
||
|
|
8001e10: d008 beq.n 8001e24 <HAL_RCCEx_PeriphCLKConfig+0x234>
|
||
|
|
{
|
||
|
|
/* Check the parameters */
|
||
|
|
assert_param(IS_RCC_I2C3CLKSOURCE(PeriphClkInit->I2c3ClockSelection));
|
||
|
|
|
||
|
|
/* Configure the I2C3 clock source */
|
||
|
|
__HAL_RCC_I2C3_CONFIG(PeriphClkInit->I2c3ClockSelection);
|
||
|
|
8001e12: 4a15 ldr r2, [pc, #84] ; (8001e68 <HAL_RCCEx_PeriphCLKConfig+0x278>)
|
||
|
|
8001e14: 4b14 ldr r3, [pc, #80] ; (8001e68 <HAL_RCCEx_PeriphCLKConfig+0x278>)
|
||
|
|
8001e16: 6cdb ldr r3, [r3, #76] ; 0x4c
|
||
|
|
8001e18: 4915 ldr r1, [pc, #84] ; (8001e70 <HAL_RCCEx_PeriphCLKConfig+0x280>)
|
||
|
|
8001e1a: 4019 ands r1, r3
|
||
|
|
8001e1c: 687b ldr r3, [r7, #4]
|
||
|
|
8001e1e: 699b ldr r3, [r3, #24]
|
||
|
|
8001e20: 430b orrs r3, r1
|
||
|
|
8001e22: 64d3 str r3, [r2, #76] ; 0x4c
|
||
|
|
}
|
||
|
|
#endif /* RCC_CCIPR_I2C3SEL */
|
||
|
|
|
||
|
|
#if defined(USB)
|
||
|
|
/*---------------------------- USB and RNG configuration --------------------*/
|
||
|
|
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USB) == (RCC_PERIPHCLK_USB))
|
||
|
|
8001e24: 687b ldr r3, [r7, #4]
|
||
|
|
8001e26: 681b ldr r3, [r3, #0]
|
||
|
|
8001e28: 2240 movs r2, #64 ; 0x40
|
||
|
|
8001e2a: 4013 ands r3, r2
|
||
|
|
8001e2c: d008 beq.n 8001e40 <HAL_RCCEx_PeriphCLKConfig+0x250>
|
||
|
|
{
|
||
|
|
assert_param(IS_RCC_USBCLKSOURCE(PeriphClkInit->UsbClockSelection));
|
||
|
|
__HAL_RCC_USB_CONFIG(PeriphClkInit->UsbClockSelection);
|
||
|
|
8001e2e: 4a0e ldr r2, [pc, #56] ; (8001e68 <HAL_RCCEx_PeriphCLKConfig+0x278>)
|
||
|
|
8001e30: 4b0d ldr r3, [pc, #52] ; (8001e68 <HAL_RCCEx_PeriphCLKConfig+0x278>)
|
||
|
|
8001e32: 6cdb ldr r3, [r3, #76] ; 0x4c
|
||
|
|
8001e34: 4915 ldr r1, [pc, #84] ; (8001e8c <HAL_RCCEx_PeriphCLKConfig+0x29c>)
|
||
|
|
8001e36: 4019 ands r1, r3
|
||
|
|
8001e38: 687b ldr r3, [r7, #4]
|
||
|
|
8001e3a: 6a1b ldr r3, [r3, #32]
|
||
|
|
8001e3c: 430b orrs r3, r1
|
||
|
|
8001e3e: 64d3 str r3, [r2, #76] ; 0x4c
|
||
|
|
}
|
||
|
|
#endif /* USB */
|
||
|
|
|
||
|
|
/*---------------------------- LPTIM1 configuration ------------------------*/
|
||
|
|
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM1) == (RCC_PERIPHCLK_LPTIM1))
|
||
|
|
8001e40: 687b ldr r3, [r7, #4]
|
||
|
|
8001e42: 681b ldr r3, [r3, #0]
|
||
|
|
8001e44: 2280 movs r2, #128 ; 0x80
|
||
|
|
8001e46: 4013 ands r3, r2
|
||
|
|
8001e48: d008 beq.n 8001e5c <HAL_RCCEx_PeriphCLKConfig+0x26c>
|
||
|
|
{
|
||
|
|
assert_param(IS_RCC_LPTIMCLK(PeriphClkInit->LptimClockSelection));
|
||
|
|
__HAL_RCC_LPTIM1_CONFIG(PeriphClkInit->LptimClockSelection);
|
||
|
|
8001e4a: 4a07 ldr r2, [pc, #28] ; (8001e68 <HAL_RCCEx_PeriphCLKConfig+0x278>)
|
||
|
|
8001e4c: 4b06 ldr r3, [pc, #24] ; (8001e68 <HAL_RCCEx_PeriphCLKConfig+0x278>)
|
||
|
|
8001e4e: 6cdb ldr r3, [r3, #76] ; 0x4c
|
||
|
|
8001e50: 490f ldr r1, [pc, #60] ; (8001e90 <HAL_RCCEx_PeriphCLKConfig+0x2a0>)
|
||
|
|
8001e52: 4019 ands r1, r3
|
||
|
|
8001e54: 687b ldr r3, [r7, #4]
|
||
|
|
8001e56: 69db ldr r3, [r3, #28]
|
||
|
|
8001e58: 430b orrs r3, r1
|
||
|
|
8001e5a: 64d3 str r3, [r2, #76] ; 0x4c
|
||
|
|
}
|
||
|
|
|
||
|
|
return HAL_OK;
|
||
|
|
8001e5c: 2300 movs r3, #0
|
||
|
|
}
|
||
|
|
8001e5e: 0018 movs r0, r3
|
||
|
|
8001e60: 46bd mov sp, r7
|
||
|
|
8001e62: b006 add sp, #24
|
||
|
|
8001e64: bd80 pop {r7, pc}
|
||
|
|
8001e66: 46c0 nop ; (mov r8, r8)
|
||
|
|
8001e68: 40021000 .word 0x40021000
|
||
|
|
8001e6c: 40007000 .word 0x40007000
|
||
|
|
8001e70: fffcffff .word 0xfffcffff
|
||
|
|
8001e74: fff7ffff .word 0xfff7ffff
|
||
|
|
8001e78: 00001388 .word 0x00001388
|
||
|
|
8001e7c: ffcfffff .word 0xffcfffff
|
||
|
|
8001e80: efffffff .word 0xefffffff
|
||
|
|
8001e84: fffff3ff .word 0xfffff3ff
|
||
|
|
8001e88: ffffcfff .word 0xffffcfff
|
||
|
|
8001e8c: fbffffff .word 0xfbffffff
|
||
|
|
8001e90: fff3ffff .word 0xfff3ffff
|
||
|
|
|
||
|
|
08001e94 <HAL_UART_Init>:
|
||
|
|
* parameters in the UART_InitTypeDef and initialize the associated handle.
|
||
|
|
* @param huart UART handle.
|
||
|
|
* @retval HAL status
|
||
|
|
*/
|
||
|
|
HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart)
|
||
|
|
{
|
||
|
|
8001e94: b580 push {r7, lr}
|
||
|
|
8001e96: b082 sub sp, #8
|
||
|
|
8001e98: af00 add r7, sp, #0
|
||
|
|
8001e9a: 6078 str r0, [r7, #4]
|
||
|
|
/* Check the UART handle allocation */
|
||
|
|
if (huart == NULL)
|
||
|
|
8001e9c: 687b ldr r3, [r7, #4]
|
||
|
|
8001e9e: 2b00 cmp r3, #0
|
||
|
|
8001ea0: d101 bne.n 8001ea6 <HAL_UART_Init+0x12>
|
||
|
|
{
|
||
|
|
return HAL_ERROR;
|
||
|
|
8001ea2: 2301 movs r3, #1
|
||
|
|
8001ea4: e044 b.n 8001f30 <HAL_UART_Init+0x9c>
|
||
|
|
{
|
||
|
|
/* Check the parameters */
|
||
|
|
assert_param((IS_UART_INSTANCE(huart->Instance)) || (IS_LPUART_INSTANCE(huart->Instance)));
|
||
|
|
}
|
||
|
|
|
||
|
|
if (huart->gState == HAL_UART_STATE_RESET)
|
||
|
|
8001ea6: 687b ldr r3, [r7, #4]
|
||
|
|
8001ea8: 6f9b ldr r3, [r3, #120] ; 0x78
|
||
|
|
8001eaa: 2b00 cmp r3, #0
|
||
|
|
8001eac: d107 bne.n 8001ebe <HAL_UART_Init+0x2a>
|
||
|
|
{
|
||
|
|
/* Allocate lock resource and initialize it */
|
||
|
|
huart->Lock = HAL_UNLOCKED;
|
||
|
|
8001eae: 687b ldr r3, [r7, #4]
|
||
|
|
8001eb0: 2274 movs r2, #116 ; 0x74
|
||
|
|
8001eb2: 2100 movs r1, #0
|
||
|
|
8001eb4: 5499 strb r1, [r3, r2]
|
||
|
|
|
||
|
|
/* Init the low level hardware */
|
||
|
|
huart->MspInitCallback(huart);
|
||
|
|
#else
|
||
|
|
/* Init the low level hardware : GPIO, CLOCK */
|
||
|
|
HAL_UART_MspInit(huart);
|
||
|
|
8001eb6: 687b ldr r3, [r7, #4]
|
||
|
|
8001eb8: 0018 movs r0, r3
|
||
|
|
8001eba: f7fe fcbb bl 8000834 <HAL_UART_MspInit>
|
||
|
|
#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
|
||
|
|
}
|
||
|
|
|
||
|
|
huart->gState = HAL_UART_STATE_BUSY;
|
||
|
|
8001ebe: 687b ldr r3, [r7, #4]
|
||
|
|
8001ec0: 2224 movs r2, #36 ; 0x24
|
||
|
|
8001ec2: 679a str r2, [r3, #120] ; 0x78
|
||
|
|
|
||
|
|
__HAL_UART_DISABLE(huart);
|
||
|
|
8001ec4: 687b ldr r3, [r7, #4]
|
||
|
|
8001ec6: 681b ldr r3, [r3, #0]
|
||
|
|
8001ec8: 687a ldr r2, [r7, #4]
|
||
|
|
8001eca: 6812 ldr r2, [r2, #0]
|
||
|
|
8001ecc: 6812 ldr r2, [r2, #0]
|
||
|
|
8001ece: 2101 movs r1, #1
|
||
|
|
8001ed0: 438a bics r2, r1
|
||
|
|
8001ed2: 601a str r2, [r3, #0]
|
||
|
|
|
||
|
|
/* Set the UART Communication parameters */
|
||
|
|
if (UART_SetConfig(huart) == HAL_ERROR)
|
||
|
|
8001ed4: 687b ldr r3, [r7, #4]
|
||
|
|
8001ed6: 0018 movs r0, r3
|
||
|
|
8001ed8: f000 fa58 bl 800238c <UART_SetConfig>
|
||
|
|
8001edc: 0003 movs r3, r0
|
||
|
|
8001ede: 2b01 cmp r3, #1
|
||
|
|
8001ee0: d101 bne.n 8001ee6 <HAL_UART_Init+0x52>
|
||
|
|
{
|
||
|
|
return HAL_ERROR;
|
||
|
|
8001ee2: 2301 movs r3, #1
|
||
|
|
8001ee4: e024 b.n 8001f30 <HAL_UART_Init+0x9c>
|
||
|
|
}
|
||
|
|
|
||
|
|
if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)
|
||
|
|
8001ee6: 687b ldr r3, [r7, #4]
|
||
|
|
8001ee8: 6a5b ldr r3, [r3, #36] ; 0x24
|
||
|
|
8001eea: 2b00 cmp r3, #0
|
||
|
|
8001eec: d003 beq.n 8001ef6 <HAL_UART_Init+0x62>
|
||
|
|
{
|
||
|
|
UART_AdvFeatureConfig(huart);
|
||
|
|
8001eee: 687b ldr r3, [r7, #4]
|
||
|
|
8001ef0: 0018 movs r0, r3
|
||
|
|
8001ef2: f000 fd0d bl 8002910 <UART_AdvFeatureConfig>
|
||
|
|
}
|
||
|
|
|
||
|
|
/* In asynchronous mode, the following bits must be kept cleared:
|
||
|
|
- LINEN and CLKEN bits in the USART_CR2 register,
|
||
|
|
- SCEN, HDSEL and IREN bits in the USART_CR3 register.*/
|
||
|
|
CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
|
||
|
|
8001ef6: 687b ldr r3, [r7, #4]
|
||
|
|
8001ef8: 681b ldr r3, [r3, #0]
|
||
|
|
8001efa: 687a ldr r2, [r7, #4]
|
||
|
|
8001efc: 6812 ldr r2, [r2, #0]
|
||
|
|
8001efe: 6852 ldr r2, [r2, #4]
|
||
|
|
8001f00: 490d ldr r1, [pc, #52] ; (8001f38 <HAL_UART_Init+0xa4>)
|
||
|
|
8001f02: 400a ands r2, r1
|
||
|
|
8001f04: 605a str r2, [r3, #4]
|
||
|
|
CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN));
|
||
|
|
8001f06: 687b ldr r3, [r7, #4]
|
||
|
|
8001f08: 681b ldr r3, [r3, #0]
|
||
|
|
8001f0a: 687a ldr r2, [r7, #4]
|
||
|
|
8001f0c: 6812 ldr r2, [r2, #0]
|
||
|
|
8001f0e: 6892 ldr r2, [r2, #8]
|
||
|
|
8001f10: 212a movs r1, #42 ; 0x2a
|
||
|
|
8001f12: 438a bics r2, r1
|
||
|
|
8001f14: 609a str r2, [r3, #8]
|
||
|
|
|
||
|
|
__HAL_UART_ENABLE(huart);
|
||
|
|
8001f16: 687b ldr r3, [r7, #4]
|
||
|
|
8001f18: 681b ldr r3, [r3, #0]
|
||
|
|
8001f1a: 687a ldr r2, [r7, #4]
|
||
|
|
8001f1c: 6812 ldr r2, [r2, #0]
|
||
|
|
8001f1e: 6812 ldr r2, [r2, #0]
|
||
|
|
8001f20: 2101 movs r1, #1
|
||
|
|
8001f22: 430a orrs r2, r1
|
||
|
|
8001f24: 601a str r2, [r3, #0]
|
||
|
|
|
||
|
|
/* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */
|
||
|
|
return (UART_CheckIdleState(huart));
|
||
|
|
8001f26: 687b ldr r3, [r7, #4]
|
||
|
|
8001f28: 0018 movs r0, r3
|
||
|
|
8001f2a: f000 fd9d bl 8002a68 <UART_CheckIdleState>
|
||
|
|
8001f2e: 0003 movs r3, r0
|
||
|
|
}
|
||
|
|
8001f30: 0018 movs r0, r3
|
||
|
|
8001f32: 46bd mov sp, r7
|
||
|
|
8001f34: b002 add sp, #8
|
||
|
|
8001f36: bd80 pop {r7, pc}
|
||
|
|
8001f38: ffffb7ff .word 0xffffb7ff
|
||
|
|
|
||
|
|
08001f3c <HAL_UART_IRQHandler>:
|
||
|
|
* @brief Handle UART interrupt request.
|
||
|
|
* @param huart UART handle.
|
||
|
|
* @retval None
|
||
|
|
*/
|
||
|
|
void HAL_UART_IRQHandler(UART_HandleTypeDef *huart)
|
||
|
|
{
|
||
|
|
8001f3c: b580 push {r7, lr}
|
||
|
|
8001f3e: b088 sub sp, #32
|
||
|
|
8001f40: af00 add r7, sp, #0
|
||
|
|
8001f42: 6078 str r0, [r7, #4]
|
||
|
|
uint32_t isrflags = READ_REG(huart->Instance->ISR);
|
||
|
|
8001f44: 687b ldr r3, [r7, #4]
|
||
|
|
8001f46: 681b ldr r3, [r3, #0]
|
||
|
|
8001f48: 69db ldr r3, [r3, #28]
|
||
|
|
8001f4a: 61fb str r3, [r7, #28]
|
||
|
|
uint32_t cr1its = READ_REG(huart->Instance->CR1);
|
||
|
|
8001f4c: 687b ldr r3, [r7, #4]
|
||
|
|
8001f4e: 681b ldr r3, [r3, #0]
|
||
|
|
8001f50: 681b ldr r3, [r3, #0]
|
||
|
|
8001f52: 61bb str r3, [r7, #24]
|
||
|
|
uint32_t cr3its = READ_REG(huart->Instance->CR3);
|
||
|
|
8001f54: 687b ldr r3, [r7, #4]
|
||
|
|
8001f56: 681b ldr r3, [r3, #0]
|
||
|
|
8001f58: 689b ldr r3, [r3, #8]
|
||
|
|
8001f5a: 617b str r3, [r7, #20]
|
||
|
|
|
||
|
|
uint32_t errorflags;
|
||
|
|
uint32_t errorcode;
|
||
|
|
|
||
|
|
/* If no error occurs */
|
||
|
|
errorflags = (isrflags & (uint32_t)(USART_ISR_PE | USART_ISR_FE | USART_ISR_ORE | USART_ISR_NE | USART_ISR_RTOF));
|
||
|
|
8001f5c: 69fb ldr r3, [r7, #28]
|
||
|
|
8001f5e: 4ab7 ldr r2, [pc, #732] ; (800223c <HAL_UART_IRQHandler+0x300>)
|
||
|
|
8001f60: 4013 ands r3, r2
|
||
|
|
8001f62: 613b str r3, [r7, #16]
|
||
|
|
if (errorflags == 0U)
|
||
|
|
8001f64: 693b ldr r3, [r7, #16]
|
||
|
|
8001f66: 2b00 cmp r3, #0
|
||
|
|
8001f68: d112 bne.n 8001f90 <HAL_UART_IRQHandler+0x54>
|
||
|
|
{
|
||
|
|
/* UART in mode Receiver ---------------------------------------------------*/
|
||
|
|
if (((isrflags & USART_ISR_RXNE) != 0U)
|
||
|
|
8001f6a: 69fb ldr r3, [r7, #28]
|
||
|
|
8001f6c: 2220 movs r2, #32
|
||
|
|
8001f6e: 4013 ands r3, r2
|
||
|
|
8001f70: d00e beq.n 8001f90 <HAL_UART_IRQHandler+0x54>
|
||
|
|
&& ((cr1its & USART_CR1_RXNEIE) != 0U))
|
||
|
|
8001f72: 69bb ldr r3, [r7, #24]
|
||
|
|
8001f74: 2220 movs r2, #32
|
||
|
|
8001f76: 4013 ands r3, r2
|
||
|
|
8001f78: d00a beq.n 8001f90 <HAL_UART_IRQHandler+0x54>
|
||
|
|
{
|
||
|
|
if (huart->RxISR != NULL)
|
||
|
|
8001f7a: 687b ldr r3, [r7, #4]
|
||
|
|
8001f7c: 6e5b ldr r3, [r3, #100] ; 0x64
|
||
|
|
8001f7e: 2b00 cmp r3, #0
|
||
|
|
8001f80: d100 bne.n 8001f84 <HAL_UART_IRQHandler+0x48>
|
||
|
|
8001f82: e1d8 b.n 8002336 <HAL_UART_IRQHandler+0x3fa>
|
||
|
|
{
|
||
|
|
huart->RxISR(huart);
|
||
|
|
8001f84: 687b ldr r3, [r7, #4]
|
||
|
|
8001f86: 6e5b ldr r3, [r3, #100] ; 0x64
|
||
|
|
8001f88: 687a ldr r2, [r7, #4]
|
||
|
|
8001f8a: 0010 movs r0, r2
|
||
|
|
8001f8c: 4798 blx r3
|
||
|
|
}
|
||
|
|
return;
|
||
|
|
8001f8e: e1d2 b.n 8002336 <HAL_UART_IRQHandler+0x3fa>
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
/* If some errors occur */
|
||
|
|
if ((errorflags != 0U)
|
||
|
|
8001f90: 693b ldr r3, [r7, #16]
|
||
|
|
8001f92: 2b00 cmp r3, #0
|
||
|
|
8001f94: d100 bne.n 8001f98 <HAL_UART_IRQHandler+0x5c>
|
||
|
|
8001f96: e0d9 b.n 800214c <HAL_UART_IRQHandler+0x210>
|
||
|
|
&& (((cr3its & USART_CR3_EIE) != 0U)
|
||
|
|
8001f98: 697b ldr r3, [r7, #20]
|
||
|
|
8001f9a: 2201 movs r2, #1
|
||
|
|
8001f9c: 4013 ands r3, r2
|
||
|
|
8001f9e: d104 bne.n 8001faa <HAL_UART_IRQHandler+0x6e>
|
||
|
|
|| ((cr1its & (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_RTOIE)) != 0U)))
|
||
|
|
8001fa0: 69bb ldr r3, [r7, #24]
|
||
|
|
8001fa2: 4aa7 ldr r2, [pc, #668] ; (8002240 <HAL_UART_IRQHandler+0x304>)
|
||
|
|
8001fa4: 4013 ands r3, r2
|
||
|
|
8001fa6: d100 bne.n 8001faa <HAL_UART_IRQHandler+0x6e>
|
||
|
|
8001fa8: e0d0 b.n 800214c <HAL_UART_IRQHandler+0x210>
|
||
|
|
{
|
||
|
|
/* UART parity error interrupt occurred -------------------------------------*/
|
||
|
|
if (((isrflags & USART_ISR_PE) != 0U) && ((cr1its & USART_CR1_PEIE) != 0U))
|
||
|
|
8001faa: 69fb ldr r3, [r7, #28]
|
||
|
|
8001fac: 2201 movs r2, #1
|
||
|
|
8001fae: 4013 ands r3, r2
|
||
|
|
8001fb0: d010 beq.n 8001fd4 <HAL_UART_IRQHandler+0x98>
|
||
|
|
8001fb2: 69ba ldr r2, [r7, #24]
|
||
|
|
8001fb4: 2380 movs r3, #128 ; 0x80
|
||
|
|
8001fb6: 005b lsls r3, r3, #1
|
||
|
|
8001fb8: 4013 ands r3, r2
|
||
|
|
8001fba: d00b beq.n 8001fd4 <HAL_UART_IRQHandler+0x98>
|
||
|
|
{
|
||
|
|
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_PEF);
|
||
|
|
8001fbc: 687b ldr r3, [r7, #4]
|
||
|
|
8001fbe: 681b ldr r3, [r3, #0]
|
||
|
|
8001fc0: 2201 movs r2, #1
|
||
|
|
8001fc2: 621a str r2, [r3, #32]
|
||
|
|
|
||
|
|
huart->ErrorCode |= HAL_UART_ERROR_PE;
|
||
|
|
8001fc4: 687b ldr r3, [r7, #4]
|
||
|
|
8001fc6: 2280 movs r2, #128 ; 0x80
|
||
|
|
8001fc8: 589b ldr r3, [r3, r2]
|
||
|
|
8001fca: 2201 movs r2, #1
|
||
|
|
8001fcc: 431a orrs r2, r3
|
||
|
|
8001fce: 687b ldr r3, [r7, #4]
|
||
|
|
8001fd0: 2180 movs r1, #128 ; 0x80
|
||
|
|
8001fd2: 505a str r2, [r3, r1]
|
||
|
|
}
|
||
|
|
|
||
|
|
/* UART frame error interrupt occurred --------------------------------------*/
|
||
|
|
if (((isrflags & USART_ISR_FE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U))
|
||
|
|
8001fd4: 69fb ldr r3, [r7, #28]
|
||
|
|
8001fd6: 2202 movs r2, #2
|
||
|
|
8001fd8: 4013 ands r3, r2
|
||
|
|
8001fda: d00f beq.n 8001ffc <HAL_UART_IRQHandler+0xc0>
|
||
|
|
8001fdc: 697b ldr r3, [r7, #20]
|
||
|
|
8001fde: 2201 movs r2, #1
|
||
|
|
8001fe0: 4013 ands r3, r2
|
||
|
|
8001fe2: d00b beq.n 8001ffc <HAL_UART_IRQHandler+0xc0>
|
||
|
|
{
|
||
|
|
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_FEF);
|
||
|
|
8001fe4: 687b ldr r3, [r7, #4]
|
||
|
|
8001fe6: 681b ldr r3, [r3, #0]
|
||
|
|
8001fe8: 2202 movs r2, #2
|
||
|
|
8001fea: 621a str r2, [r3, #32]
|
||
|
|
|
||
|
|
huart->ErrorCode |= HAL_UART_ERROR_FE;
|
||
|
|
8001fec: 687b ldr r3, [r7, #4]
|
||
|
|
8001fee: 2280 movs r2, #128 ; 0x80
|
||
|
|
8001ff0: 589b ldr r3, [r3, r2]
|
||
|
|
8001ff2: 2204 movs r2, #4
|
||
|
|
8001ff4: 431a orrs r2, r3
|
||
|
|
8001ff6: 687b ldr r3, [r7, #4]
|
||
|
|
8001ff8: 2180 movs r1, #128 ; 0x80
|
||
|
|
8001ffa: 505a str r2, [r3, r1]
|
||
|
|
}
|
||
|
|
|
||
|
|
/* UART noise error interrupt occurred --------------------------------------*/
|
||
|
|
if (((isrflags & USART_ISR_NE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U))
|
||
|
|
8001ffc: 69fb ldr r3, [r7, #28]
|
||
|
|
8001ffe: 2204 movs r2, #4
|
||
|
|
8002000: 4013 ands r3, r2
|
||
|
|
8002002: d00f beq.n 8002024 <HAL_UART_IRQHandler+0xe8>
|
||
|
|
8002004: 697b ldr r3, [r7, #20]
|
||
|
|
8002006: 2201 movs r2, #1
|
||
|
|
8002008: 4013 ands r3, r2
|
||
|
|
800200a: d00b beq.n 8002024 <HAL_UART_IRQHandler+0xe8>
|
||
|
|
{
|
||
|
|
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_NEF);
|
||
|
|
800200c: 687b ldr r3, [r7, #4]
|
||
|
|
800200e: 681b ldr r3, [r3, #0]
|
||
|
|
8002010: 2204 movs r2, #4
|
||
|
|
8002012: 621a str r2, [r3, #32]
|
||
|
|
|
||
|
|
huart->ErrorCode |= HAL_UART_ERROR_NE;
|
||
|
|
8002014: 687b ldr r3, [r7, #4]
|
||
|
|
8002016: 2280 movs r2, #128 ; 0x80
|
||
|
|
8002018: 589b ldr r3, [r3, r2]
|
||
|
|
800201a: 2202 movs r2, #2
|
||
|
|
800201c: 431a orrs r2, r3
|
||
|
|
800201e: 687b ldr r3, [r7, #4]
|
||
|
|
8002020: 2180 movs r1, #128 ; 0x80
|
||
|
|
8002022: 505a str r2, [r3, r1]
|
||
|
|
}
|
||
|
|
|
||
|
|
/* UART Over-Run interrupt occurred -----------------------------------------*/
|
||
|
|
if (((isrflags & USART_ISR_ORE) != 0U)
|
||
|
|
8002024: 69fb ldr r3, [r7, #28]
|
||
|
|
8002026: 2208 movs r2, #8
|
||
|
|
8002028: 4013 ands r3, r2
|
||
|
|
800202a: d013 beq.n 8002054 <HAL_UART_IRQHandler+0x118>
|
||
|
|
&& (((cr1its & USART_CR1_RXNEIE) != 0U) ||
|
||
|
|
800202c: 69bb ldr r3, [r7, #24]
|
||
|
|
800202e: 2220 movs r2, #32
|
||
|
|
8002030: 4013 ands r3, r2
|
||
|
|
8002032: d103 bne.n 800203c <HAL_UART_IRQHandler+0x100>
|
||
|
|
((cr3its & USART_CR3_EIE) != 0U)))
|
||
|
|
8002034: 697b ldr r3, [r7, #20]
|
||
|
|
8002036: 2201 movs r2, #1
|
||
|
|
8002038: 4013 ands r3, r2
|
||
|
|
&& (((cr1its & USART_CR1_RXNEIE) != 0U) ||
|
||
|
|
800203a: d00b beq.n 8002054 <HAL_UART_IRQHandler+0x118>
|
||
|
|
{
|
||
|
|
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF);
|
||
|
|
800203c: 687b ldr r3, [r7, #4]
|
||
|
|
800203e: 681b ldr r3, [r3, #0]
|
||
|
|
8002040: 2208 movs r2, #8
|
||
|
|
8002042: 621a str r2, [r3, #32]
|
||
|
|
|
||
|
|
huart->ErrorCode |= HAL_UART_ERROR_ORE;
|
||
|
|
8002044: 687b ldr r3, [r7, #4]
|
||
|
|
8002046: 2280 movs r2, #128 ; 0x80
|
||
|
|
8002048: 589b ldr r3, [r3, r2]
|
||
|
|
800204a: 2208 movs r2, #8
|
||
|
|
800204c: 431a orrs r2, r3
|
||
|
|
800204e: 687b ldr r3, [r7, #4]
|
||
|
|
8002050: 2180 movs r1, #128 ; 0x80
|
||
|
|
8002052: 505a str r2, [r3, r1]
|
||
|
|
}
|
||
|
|
|
||
|
|
/* UART Receiver Timeout interrupt occurred ---------------------------------*/
|
||
|
|
if (((isrflags & USART_ISR_RTOF) != 0U) && ((cr1its & USART_CR1_RTOIE) != 0U))
|
||
|
|
8002054: 69fa ldr r2, [r7, #28]
|
||
|
|
8002056: 2380 movs r3, #128 ; 0x80
|
||
|
|
8002058: 011b lsls r3, r3, #4
|
||
|
|
800205a: 4013 ands r3, r2
|
||
|
|
800205c: d011 beq.n 8002082 <HAL_UART_IRQHandler+0x146>
|
||
|
|
800205e: 69ba ldr r2, [r7, #24]
|
||
|
|
8002060: 2380 movs r3, #128 ; 0x80
|
||
|
|
8002062: 04db lsls r3, r3, #19
|
||
|
|
8002064: 4013 ands r3, r2
|
||
|
|
8002066: d00c beq.n 8002082 <HAL_UART_IRQHandler+0x146>
|
||
|
|
{
|
||
|
|
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_RTOF);
|
||
|
|
8002068: 687b ldr r3, [r7, #4]
|
||
|
|
800206a: 681b ldr r3, [r3, #0]
|
||
|
|
800206c: 2280 movs r2, #128 ; 0x80
|
||
|
|
800206e: 0112 lsls r2, r2, #4
|
||
|
|
8002070: 621a str r2, [r3, #32]
|
||
|
|
|
||
|
|
huart->ErrorCode |= HAL_UART_ERROR_RTO;
|
||
|
|
8002072: 687b ldr r3, [r7, #4]
|
||
|
|
8002074: 2280 movs r2, #128 ; 0x80
|
||
|
|
8002076: 589b ldr r3, [r3, r2]
|
||
|
|
8002078: 2220 movs r2, #32
|
||
|
|
800207a: 431a orrs r2, r3
|
||
|
|
800207c: 687b ldr r3, [r7, #4]
|
||
|
|
800207e: 2180 movs r1, #128 ; 0x80
|
||
|
|
8002080: 505a str r2, [r3, r1]
|
||
|
|
}
|
||
|
|
|
||
|
|
/* Call UART Error Call back function if need be ----------------------------*/
|
||
|
|
if (huart->ErrorCode != HAL_UART_ERROR_NONE)
|
||
|
|
8002082: 687b ldr r3, [r7, #4]
|
||
|
|
8002084: 2280 movs r2, #128 ; 0x80
|
||
|
|
8002086: 589b ldr r3, [r3, r2]
|
||
|
|
8002088: 2b00 cmp r3, #0
|
||
|
|
800208a: d100 bne.n 800208e <HAL_UART_IRQHandler+0x152>
|
||
|
|
800208c: e155 b.n 800233a <HAL_UART_IRQHandler+0x3fe>
|
||
|
|
{
|
||
|
|
/* UART in mode Receiver --------------------------------------------------*/
|
||
|
|
if (((isrflags & USART_ISR_RXNE) != 0U)
|
||
|
|
800208e: 69fb ldr r3, [r7, #28]
|
||
|
|
8002090: 2220 movs r2, #32
|
||
|
|
8002092: 4013 ands r3, r2
|
||
|
|
8002094: d00c beq.n 80020b0 <HAL_UART_IRQHandler+0x174>
|
||
|
|
&& ((cr1its & USART_CR1_RXNEIE) != 0U))
|
||
|
|
8002096: 69bb ldr r3, [r7, #24]
|
||
|
|
8002098: 2220 movs r2, #32
|
||
|
|
800209a: 4013 ands r3, r2
|
||
|
|
800209c: d008 beq.n 80020b0 <HAL_UART_IRQHandler+0x174>
|
||
|
|
{
|
||
|
|
if (huart->RxISR != NULL)
|
||
|
|
800209e: 687b ldr r3, [r7, #4]
|
||
|
|
80020a0: 6e5b ldr r3, [r3, #100] ; 0x64
|
||
|
|
80020a2: 2b00 cmp r3, #0
|
||
|
|
80020a4: d004 beq.n 80020b0 <HAL_UART_IRQHandler+0x174>
|
||
|
|
{
|
||
|
|
huart->RxISR(huart);
|
||
|
|
80020a6: 687b ldr r3, [r7, #4]
|
||
|
|
80020a8: 6e5b ldr r3, [r3, #100] ; 0x64
|
||
|
|
80020aa: 687a ldr r2, [r7, #4]
|
||
|
|
80020ac: 0010 movs r0, r2
|
||
|
|
80020ae: 4798 blx r3
|
||
|
|
/* If Error is to be considered as blocking :
|
||
|
|
- Receiver Timeout error in Reception
|
||
|
|
- Overrun error in Reception
|
||
|
|
- any error occurs in DMA mode reception
|
||
|
|
*/
|
||
|
|
errorcode = huart->ErrorCode;
|
||
|
|
80020b0: 687b ldr r3, [r7, #4]
|
||
|
|
80020b2: 2280 movs r2, #128 ; 0x80
|
||
|
|
80020b4: 589b ldr r3, [r3, r2]
|
||
|
|
80020b6: 60fb str r3, [r7, #12]
|
||
|
|
if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) ||
|
||
|
|
80020b8: 687b ldr r3, [r7, #4]
|
||
|
|
80020ba: 681b ldr r3, [r3, #0]
|
||
|
|
80020bc: 689b ldr r3, [r3, #8]
|
||
|
|
80020be: 2240 movs r2, #64 ; 0x40
|
||
|
|
80020c0: 4013 ands r3, r2
|
||
|
|
80020c2: 2b40 cmp r3, #64 ; 0x40
|
||
|
|
80020c4: d003 beq.n 80020ce <HAL_UART_IRQHandler+0x192>
|
||
|
|
((errorcode & (HAL_UART_ERROR_RTO | HAL_UART_ERROR_ORE)) != 0U))
|
||
|
|
80020c6: 68fb ldr r3, [r7, #12]
|
||
|
|
80020c8: 2228 movs r2, #40 ; 0x28
|
||
|
|
80020ca: 4013 ands r3, r2
|
||
|
|
if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) ||
|
||
|
|
80020cc: d033 beq.n 8002136 <HAL_UART_IRQHandler+0x1fa>
|
||
|
|
{
|
||
|
|
/* Blocking error : transfer is aborted
|
||
|
|
Set the UART state ready to be able to start again the process,
|
||
|
|
Disable Rx Interrupts, and disable Rx DMA request, if ongoing */
|
||
|
|
UART_EndRxTransfer(huart);
|
||
|
|
80020ce: 687b ldr r3, [r7, #4]
|
||
|
|
80020d0: 0018 movs r0, r3
|
||
|
|
80020d2: f000 fd91 bl 8002bf8 <UART_EndRxTransfer>
|
||
|
|
|
||
|
|
/* Disable the UART DMA Rx request if enabled */
|
||
|
|
if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
|
||
|
|
80020d6: 687b ldr r3, [r7, #4]
|
||
|
|
80020d8: 681b ldr r3, [r3, #0]
|
||
|
|
80020da: 689b ldr r3, [r3, #8]
|
||
|
|
80020dc: 2240 movs r2, #64 ; 0x40
|
||
|
|
80020de: 4013 ands r3, r2
|
||
|
|
80020e0: 2b40 cmp r3, #64 ; 0x40
|
||
|
|
80020e2: d123 bne.n 800212c <HAL_UART_IRQHandler+0x1f0>
|
||
|
|
{
|
||
|
|
CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
|
||
|
|
80020e4: 687b ldr r3, [r7, #4]
|
||
|
|
80020e6: 681b ldr r3, [r3, #0]
|
||
|
|
80020e8: 687a ldr r2, [r7, #4]
|
||
|
|
80020ea: 6812 ldr r2, [r2, #0]
|
||
|
|
80020ec: 6892 ldr r2, [r2, #8]
|
||
|
|
80020ee: 2140 movs r1, #64 ; 0x40
|
||
|
|
80020f0: 438a bics r2, r1
|
||
|
|
80020f2: 609a str r2, [r3, #8]
|
||
|
|
|
||
|
|
/* Abort the UART DMA Rx channel */
|
||
|
|
if (huart->hdmarx != NULL)
|
||
|
|
80020f4: 687b ldr r3, [r7, #4]
|
||
|
|
80020f6: 6f1b ldr r3, [r3, #112] ; 0x70
|
||
|
|
80020f8: 2b00 cmp r3, #0
|
||
|
|
80020fa: d012 beq.n 8002122 <HAL_UART_IRQHandler+0x1e6>
|
||
|
|
{
|
||
|
|
/* Set the UART DMA Abort callback :
|
||
|
|
will lead to call HAL_UART_ErrorCallback() at end of DMA abort procedure */
|
||
|
|
huart->hdmarx->XferAbortCallback = UART_DMAAbortOnError;
|
||
|
|
80020fc: 687b ldr r3, [r7, #4]
|
||
|
|
80020fe: 6f1b ldr r3, [r3, #112] ; 0x70
|
||
|
|
8002100: 4a50 ldr r2, [pc, #320] ; (8002244 <HAL_UART_IRQHandler+0x308>)
|
||
|
|
8002102: 639a str r2, [r3, #56] ; 0x38
|
||
|
|
|
||
|
|
/* Abort DMA RX */
|
||
|
|
if (HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK)
|
||
|
|
8002104: 687b ldr r3, [r7, #4]
|
||
|
|
8002106: 6f1b ldr r3, [r3, #112] ; 0x70
|
||
|
|
8002108: 0018 movs r0, r3
|
||
|
|
800210a: f7fe fd74 bl 8000bf6 <HAL_DMA_Abort_IT>
|
||
|
|
800210e: 1e03 subs r3, r0, #0
|
||
|
|
8002110: d01a beq.n 8002148 <HAL_UART_IRQHandler+0x20c>
|
||
|
|
{
|
||
|
|
/* Call Directly huart->hdmarx->XferAbortCallback function in case of error */
|
||
|
|
huart->hdmarx->XferAbortCallback(huart->hdmarx);
|
||
|
|
8002112: 687b ldr r3, [r7, #4]
|
||
|
|
8002114: 6f1b ldr r3, [r3, #112] ; 0x70
|
||
|
|
8002116: 6b9a ldr r2, [r3, #56] ; 0x38
|
||
|
|
8002118: 687b ldr r3, [r7, #4]
|
||
|
|
800211a: 6f1b ldr r3, [r3, #112] ; 0x70
|
||
|
|
800211c: 0018 movs r0, r3
|
||
|
|
800211e: 4790 blx r2
|
||
|
|
if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
|
||
|
|
8002120: e012 b.n 8002148 <HAL_UART_IRQHandler+0x20c>
|
||
|
|
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
|
||
|
|
/*Call registered error callback*/
|
||
|
|
huart->ErrorCallback(huart);
|
||
|
|
#else
|
||
|
|
/*Call legacy weak error callback*/
|
||
|
|
HAL_UART_ErrorCallback(huart);
|
||
|
|
8002122: 687b ldr r3, [r7, #4]
|
||
|
|
8002124: 0018 movs r0, r3
|
||
|
|
8002126: f000 f91d bl 8002364 <HAL_UART_ErrorCallback>
|
||
|
|
if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
|
||
|
|
800212a: e00d b.n 8002148 <HAL_UART_IRQHandler+0x20c>
|
||
|
|
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
|
||
|
|
/*Call registered error callback*/
|
||
|
|
huart->ErrorCallback(huart);
|
||
|
|
#else
|
||
|
|
/*Call legacy weak error callback*/
|
||
|
|
HAL_UART_ErrorCallback(huart);
|
||
|
|
800212c: 687b ldr r3, [r7, #4]
|
||
|
|
800212e: 0018 movs r0, r3
|
||
|
|
8002130: f000 f918 bl 8002364 <HAL_UART_ErrorCallback>
|
||
|
|
if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
|
||
|
|
8002134: e008 b.n 8002148 <HAL_UART_IRQHandler+0x20c>
|
||
|
|
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
|
||
|
|
/*Call registered error callback*/
|
||
|
|
huart->ErrorCallback(huart);
|
||
|
|
#else
|
||
|
|
/*Call legacy weak error callback*/
|
||
|
|
HAL_UART_ErrorCallback(huart);
|
||
|
|
8002136: 687b ldr r3, [r7, #4]
|
||
|
|
8002138: 0018 movs r0, r3
|
||
|
|
800213a: f000 f913 bl 8002364 <HAL_UART_ErrorCallback>
|
||
|
|
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
|
||
|
|
huart->ErrorCode = HAL_UART_ERROR_NONE;
|
||
|
|
800213e: 687b ldr r3, [r7, #4]
|
||
|
|
8002140: 2280 movs r2, #128 ; 0x80
|
||
|
|
8002142: 2100 movs r1, #0
|
||
|
|
8002144: 5099 str r1, [r3, r2]
|
||
|
|
}
|
||
|
|
}
|
||
|
|
return;
|
||
|
|
8002146: e0f8 b.n 800233a <HAL_UART_IRQHandler+0x3fe>
|
||
|
|
if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
|
||
|
|
8002148: 46c0 nop ; (mov r8, r8)
|
||
|
|
return;
|
||
|
|
800214a: e0f6 b.n 800233a <HAL_UART_IRQHandler+0x3fe>
|
||
|
|
|
||
|
|
} /* End if some error occurs */
|
||
|
|
|
||
|
|
/* Check current reception Mode :
|
||
|
|
If Reception till IDLE event has been selected : */
|
||
|
|
if ( (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
|
||
|
|
800214c: 687b ldr r3, [r7, #4]
|
||
|
|
800214e: 6e1b ldr r3, [r3, #96] ; 0x60
|
||
|
|
8002150: 2b01 cmp r3, #1
|
||
|
|
8002152: d000 beq.n 8002156 <HAL_UART_IRQHandler+0x21a>
|
||
|
|
8002154: e0bb b.n 80022ce <HAL_UART_IRQHandler+0x392>
|
||
|
|
&&((isrflags & USART_ISR_IDLE) != 0U)
|
||
|
|
8002156: 69fb ldr r3, [r7, #28]
|
||
|
|
8002158: 2210 movs r2, #16
|
||
|
|
800215a: 4013 ands r3, r2
|
||
|
|
800215c: d100 bne.n 8002160 <HAL_UART_IRQHandler+0x224>
|
||
|
|
800215e: e0b6 b.n 80022ce <HAL_UART_IRQHandler+0x392>
|
||
|
|
&&((cr1its & USART_ISR_IDLE) != 0U))
|
||
|
|
8002160: 69bb ldr r3, [r7, #24]
|
||
|
|
8002162: 2210 movs r2, #16
|
||
|
|
8002164: 4013 ands r3, r2
|
||
|
|
8002166: d100 bne.n 800216a <HAL_UART_IRQHandler+0x22e>
|
||
|
|
8002168: e0b1 b.n 80022ce <HAL_UART_IRQHandler+0x392>
|
||
|
|
{
|
||
|
|
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF);
|
||
|
|
800216a: 687b ldr r3, [r7, #4]
|
||
|
|
800216c: 681b ldr r3, [r3, #0]
|
||
|
|
800216e: 2210 movs r2, #16
|
||
|
|
8002170: 621a str r2, [r3, #32]
|
||
|
|
|
||
|
|
/* Check if DMA mode is enabled in UART */
|
||
|
|
if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
|
||
|
|
8002172: 687b ldr r3, [r7, #4]
|
||
|
|
8002174: 681b ldr r3, [r3, #0]
|
||
|
|
8002176: 689b ldr r3, [r3, #8]
|
||
|
|
8002178: 2240 movs r2, #64 ; 0x40
|
||
|
|
800217a: 4013 ands r3, r2
|
||
|
|
800217c: 2b40 cmp r3, #64 ; 0x40
|
||
|
|
800217e: d165 bne.n 800224c <HAL_UART_IRQHandler+0x310>
|
||
|
|
{
|
||
|
|
/* DMA mode enabled */
|
||
|
|
/* Check received length : If all expected data are received, do nothing,
|
||
|
|
(DMA cplt callback will be called).
|
||
|
|
Otherwise, if at least one data has already been received, IDLE event is to be notified to user */
|
||
|
|
uint16_t nb_remaining_rx_data = (uint16_t) __HAL_DMA_GET_COUNTER(huart->hdmarx);
|
||
|
|
8002180: 687b ldr r3, [r7, #4]
|
||
|
|
8002182: 6f1b ldr r3, [r3, #112] ; 0x70
|
||
|
|
8002184: 681b ldr r3, [r3, #0]
|
||
|
|
8002186: 685a ldr r2, [r3, #4]
|
||
|
|
8002188: 230a movs r3, #10
|
||
|
|
800218a: 18fb adds r3, r7, r3
|
||
|
|
800218c: 801a strh r2, [r3, #0]
|
||
|
|
if ( (nb_remaining_rx_data > 0U)
|
||
|
|
800218e: 230a movs r3, #10
|
||
|
|
8002190: 18fb adds r3, r7, r3
|
||
|
|
8002192: 881b ldrh r3, [r3, #0]
|
||
|
|
8002194: 2b00 cmp r3, #0
|
||
|
|
8002196: d100 bne.n 800219a <HAL_UART_IRQHandler+0x25e>
|
||
|
|
8002198: e0d1 b.n 800233e <HAL_UART_IRQHandler+0x402>
|
||
|
|
&&(nb_remaining_rx_data < huart->RxXferSize))
|
||
|
|
800219a: 687b ldr r3, [r7, #4]
|
||
|
|
800219c: 2258 movs r2, #88 ; 0x58
|
||
|
|
800219e: 5a9b ldrh r3, [r3, r2]
|
||
|
|
80021a0: 220a movs r2, #10
|
||
|
|
80021a2: 18ba adds r2, r7, r2
|
||
|
|
80021a4: 8812 ldrh r2, [r2, #0]
|
||
|
|
80021a6: 429a cmp r2, r3
|
||
|
|
80021a8: d300 bcc.n 80021ac <HAL_UART_IRQHandler+0x270>
|
||
|
|
80021aa: e0c8 b.n 800233e <HAL_UART_IRQHandler+0x402>
|
||
|
|
{
|
||
|
|
/* Reception is not complete */
|
||
|
|
huart->RxXferCount = nb_remaining_rx_data;
|
||
|
|
80021ac: 687b ldr r3, [r7, #4]
|
||
|
|
80021ae: 220a movs r2, #10
|
||
|
|
80021b0: 18ba adds r2, r7, r2
|
||
|
|
80021b2: 215a movs r1, #90 ; 0x5a
|
||
|
|
80021b4: 8812 ldrh r2, [r2, #0]
|
||
|
|
80021b6: 525a strh r2, [r3, r1]
|
||
|
|
|
||
|
|
/* In Normal mode, end DMA xfer and HAL UART Rx process*/
|
||
|
|
if (HAL_IS_BIT_CLR(huart->hdmarx->Instance->CCR, DMA_CCR_CIRC))
|
||
|
|
80021b8: 687b ldr r3, [r7, #4]
|
||
|
|
80021ba: 6f1b ldr r3, [r3, #112] ; 0x70
|
||
|
|
80021bc: 681b ldr r3, [r3, #0]
|
||
|
|
80021be: 681b ldr r3, [r3, #0]
|
||
|
|
80021c0: 2220 movs r2, #32
|
||
|
|
80021c2: 4013 ands r3, r2
|
||
|
|
80021c4: d12a bne.n 800221c <HAL_UART_IRQHandler+0x2e0>
|
||
|
|
{
|
||
|
|
/* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */
|
||
|
|
CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE);
|
||
|
|
80021c6: 687b ldr r3, [r7, #4]
|
||
|
|
80021c8: 681b ldr r3, [r3, #0]
|
||
|
|
80021ca: 687a ldr r2, [r7, #4]
|
||
|
|
80021cc: 6812 ldr r2, [r2, #0]
|
||
|
|
80021ce: 6812 ldr r2, [r2, #0]
|
||
|
|
80021d0: 491d ldr r1, [pc, #116] ; (8002248 <HAL_UART_IRQHandler+0x30c>)
|
||
|
|
80021d2: 400a ands r2, r1
|
||
|
|
80021d4: 601a str r2, [r3, #0]
|
||
|
|
CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
|
||
|
|
80021d6: 687b ldr r3, [r7, #4]
|
||
|
|
80021d8: 681b ldr r3, [r3, #0]
|
||
|
|
80021da: 687a ldr r2, [r7, #4]
|
||
|
|
80021dc: 6812 ldr r2, [r2, #0]
|
||
|
|
80021de: 6892 ldr r2, [r2, #8]
|
||
|
|
80021e0: 2101 movs r1, #1
|
||
|
|
80021e2: 438a bics r2, r1
|
||
|
|
80021e4: 609a str r2, [r3, #8]
|
||
|
|
|
||
|
|
/* Disable the DMA transfer for the receiver request by resetting the DMAR bit
|
||
|
|
in the UART CR3 register */
|
||
|
|
CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
|
||
|
|
80021e6: 687b ldr r3, [r7, #4]
|
||
|
|
80021e8: 681b ldr r3, [r3, #0]
|
||
|
|
80021ea: 687a ldr r2, [r7, #4]
|
||
|
|
80021ec: 6812 ldr r2, [r2, #0]
|
||
|
|
80021ee: 6892 ldr r2, [r2, #8]
|
||
|
|
80021f0: 2140 movs r1, #64 ; 0x40
|
||
|
|
80021f2: 438a bics r2, r1
|
||
|
|
80021f4: 609a str r2, [r3, #8]
|
||
|
|
|
||
|
|
/* At end of Rx process, restore huart->RxState to Ready */
|
||
|
|
huart->RxState = HAL_UART_STATE_READY;
|
||
|
|
80021f6: 687b ldr r3, [r7, #4]
|
||
|
|
80021f8: 2220 movs r2, #32
|
||
|
|
80021fa: 67da str r2, [r3, #124] ; 0x7c
|
||
|
|
huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
|
||
|
|
80021fc: 687b ldr r3, [r7, #4]
|
||
|
|
80021fe: 2200 movs r2, #0
|
||
|
|
8002200: 661a str r2, [r3, #96] ; 0x60
|
||
|
|
|
||
|
|
CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
|
||
|
|
8002202: 687b ldr r3, [r7, #4]
|
||
|
|
8002204: 681b ldr r3, [r3, #0]
|
||
|
|
8002206: 687a ldr r2, [r7, #4]
|
||
|
|
8002208: 6812 ldr r2, [r2, #0]
|
||
|
|
800220a: 6812 ldr r2, [r2, #0]
|
||
|
|
800220c: 2110 movs r1, #16
|
||
|
|
800220e: 438a bics r2, r1
|
||
|
|
8002210: 601a str r2, [r3, #0]
|
||
|
|
|
||
|
|
/* Last bytes received, so no need as the abort is immediate */
|
||
|
|
(void)HAL_DMA_Abort(huart->hdmarx);
|
||
|
|
8002212: 687b ldr r3, [r7, #4]
|
||
|
|
8002214: 6f1b ldr r3, [r3, #112] ; 0x70
|
||
|
|
8002216: 0018 movs r0, r3
|
||
|
|
8002218: f7fe fcad bl 8000b76 <HAL_DMA_Abort>
|
||
|
|
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
|
||
|
|
/*Call registered Rx Event callback*/
|
||
|
|
huart->RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount));
|
||
|
|
#else
|
||
|
|
/*Call legacy weak Rx Event callback*/
|
||
|
|
HAL_UARTEx_RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount));
|
||
|
|
800221c: 687b ldr r3, [r7, #4]
|
||
|
|
800221e: 2258 movs r2, #88 ; 0x58
|
||
|
|
8002220: 5a9a ldrh r2, [r3, r2]
|
||
|
|
8002222: 687b ldr r3, [r7, #4]
|
||
|
|
8002224: 215a movs r1, #90 ; 0x5a
|
||
|
|
8002226: 5a5b ldrh r3, [r3, r1]
|
||
|
|
8002228: b29b uxth r3, r3
|
||
|
|
800222a: 1ad3 subs r3, r2, r3
|
||
|
|
800222c: b29a uxth r2, r3
|
||
|
|
800222e: 687b ldr r3, [r7, #4]
|
||
|
|
8002230: 0011 movs r1, r2
|
||
|
|
8002232: 0018 movs r0, r3
|
||
|
|
8002234: f000 f89e bl 8002374 <HAL_UARTEx_RxEventCallback>
|
||
|
|
#endif
|
||
|
|
}
|
||
|
|
return;
|
||
|
|
8002238: e081 b.n 800233e <HAL_UART_IRQHandler+0x402>
|
||
|
|
800223a: 46c0 nop ; (mov r8, r8)
|
||
|
|
800223c: 0000080f .word 0x0000080f
|
||
|
|
8002240: 04000120 .word 0x04000120
|
||
|
|
8002244: 08002c59 .word 0x08002c59
|
||
|
|
8002248: fffffeff .word 0xfffffeff
|
||
|
|
else
|
||
|
|
{
|
||
|
|
/* DMA mode not enabled */
|
||
|
|
/* Check received length : If all expected data are received, do nothing.
|
||
|
|
Otherwise, if at least one data has already been received, IDLE event is to be notified to user */
|
||
|
|
uint16_t nb_rx_data = huart->RxXferSize - huart->RxXferCount;
|
||
|
|
800224c: 687b ldr r3, [r7, #4]
|
||
|
|
800224e: 2258 movs r2, #88 ; 0x58
|
||
|
|
8002250: 5a99 ldrh r1, [r3, r2]
|
||
|
|
8002252: 687b ldr r3, [r7, #4]
|
||
|
|
8002254: 225a movs r2, #90 ; 0x5a
|
||
|
|
8002256: 5a9b ldrh r3, [r3, r2]
|
||
|
|
8002258: b29a uxth r2, r3
|
||
|
|
800225a: 2308 movs r3, #8
|
||
|
|
800225c: 18fb adds r3, r7, r3
|
||
|
|
800225e: 1a8a subs r2, r1, r2
|
||
|
|
8002260: 801a strh r2, [r3, #0]
|
||
|
|
if ( (huart->RxXferCount > 0U)
|
||
|
|
8002262: 687b ldr r3, [r7, #4]
|
||
|
|
8002264: 225a movs r2, #90 ; 0x5a
|
||
|
|
8002266: 5a9b ldrh r3, [r3, r2]
|
||
|
|
8002268: b29b uxth r3, r3
|
||
|
|
800226a: 2b00 cmp r3, #0
|
||
|
|
800226c: d100 bne.n 8002270 <HAL_UART_IRQHandler+0x334>
|
||
|
|
800226e: e068 b.n 8002342 <HAL_UART_IRQHandler+0x406>
|
||
|
|
&&(nb_rx_data > 0U) )
|
||
|
|
8002270: 2308 movs r3, #8
|
||
|
|
8002272: 18fb adds r3, r7, r3
|
||
|
|
8002274: 881b ldrh r3, [r3, #0]
|
||
|
|
8002276: 2b00 cmp r3, #0
|
||
|
|
8002278: d063 beq.n 8002342 <HAL_UART_IRQHandler+0x406>
|
||
|
|
{
|
||
|
|
/* Disable the UART Parity Error Interrupt and RXNE interrupts */
|
||
|
|
CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
|
||
|
|
800227a: 687b ldr r3, [r7, #4]
|
||
|
|
800227c: 681b ldr r3, [r3, #0]
|
||
|
|
800227e: 687a ldr r2, [r7, #4]
|
||
|
|
8002280: 6812 ldr r2, [r2, #0]
|
||
|
|
8002282: 6812 ldr r2, [r2, #0]
|
||
|
|
8002284: 4932 ldr r1, [pc, #200] ; (8002350 <HAL_UART_IRQHandler+0x414>)
|
||
|
|
8002286: 400a ands r2, r1
|
||
|
|
8002288: 601a str r2, [r3, #0]
|
||
|
|
|
||
|
|
/* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */
|
||
|
|
CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
|
||
|
|
800228a: 687b ldr r3, [r7, #4]
|
||
|
|
800228c: 681b ldr r3, [r3, #0]
|
||
|
|
800228e: 687a ldr r2, [r7, #4]
|
||
|
|
8002290: 6812 ldr r2, [r2, #0]
|
||
|
|
8002292: 6892 ldr r2, [r2, #8]
|
||
|
|
8002294: 2101 movs r1, #1
|
||
|
|
8002296: 438a bics r2, r1
|
||
|
|
8002298: 609a str r2, [r3, #8]
|
||
|
|
|
||
|
|
/* Rx process is completed, restore huart->RxState to Ready */
|
||
|
|
huart->RxState = HAL_UART_STATE_READY;
|
||
|
|
800229a: 687b ldr r3, [r7, #4]
|
||
|
|
800229c: 2220 movs r2, #32
|
||
|
|
800229e: 67da str r2, [r3, #124] ; 0x7c
|
||
|
|
huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
|
||
|
|
80022a0: 687b ldr r3, [r7, #4]
|
||
|
|
80022a2: 2200 movs r2, #0
|
||
|
|
80022a4: 661a str r2, [r3, #96] ; 0x60
|
||
|
|
|
||
|
|
/* Clear RxISR function pointer */
|
||
|
|
huart->RxISR = NULL;
|
||
|
|
80022a6: 687b ldr r3, [r7, #4]
|
||
|
|
80022a8: 2200 movs r2, #0
|
||
|
|
80022aa: 665a str r2, [r3, #100] ; 0x64
|
||
|
|
|
||
|
|
CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
|
||
|
|
80022ac: 687b ldr r3, [r7, #4]
|
||
|
|
80022ae: 681b ldr r3, [r3, #0]
|
||
|
|
80022b0: 687a ldr r2, [r7, #4]
|
||
|
|
80022b2: 6812 ldr r2, [r2, #0]
|
||
|
|
80022b4: 6812 ldr r2, [r2, #0]
|
||
|
|
80022b6: 2110 movs r1, #16
|
||
|
|
80022b8: 438a bics r2, r1
|
||
|
|
80022ba: 601a str r2, [r3, #0]
|
||
|
|
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
|
||
|
|
/*Call registered Rx complete callback*/
|
||
|
|
huart->RxEventCallback(huart, nb_rx_data);
|
||
|
|
#else
|
||
|
|
/*Call legacy weak Rx Event callback*/
|
||
|
|
HAL_UARTEx_RxEventCallback(huart, nb_rx_data);
|
||
|
|
80022bc: 2308 movs r3, #8
|
||
|
|
80022be: 18fb adds r3, r7, r3
|
||
|
|
80022c0: 881a ldrh r2, [r3, #0]
|
||
|
|
80022c2: 687b ldr r3, [r7, #4]
|
||
|
|
80022c4: 0011 movs r1, r2
|
||
|
|
80022c6: 0018 movs r0, r3
|
||
|
|
80022c8: f000 f854 bl 8002374 <HAL_UARTEx_RxEventCallback>
|
||
|
|
#endif
|
||
|
|
}
|
||
|
|
return;
|
||
|
|
80022cc: e039 b.n 8002342 <HAL_UART_IRQHandler+0x406>
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
/* UART wakeup from Stop mode interrupt occurred ---------------------------*/
|
||
|
|
if (((isrflags & USART_ISR_WUF) != 0U) && ((cr3its & USART_CR3_WUFIE) != 0U))
|
||
|
|
80022ce: 69fa ldr r2, [r7, #28]
|
||
|
|
80022d0: 2380 movs r3, #128 ; 0x80
|
||
|
|
80022d2: 035b lsls r3, r3, #13
|
||
|
|
80022d4: 4013 ands r3, r2
|
||
|
|
80022d6: d00e beq.n 80022f6 <HAL_UART_IRQHandler+0x3ba>
|
||
|
|
80022d8: 697a ldr r2, [r7, #20]
|
||
|
|
80022da: 2380 movs r3, #128 ; 0x80
|
||
|
|
80022dc: 03db lsls r3, r3, #15
|
||
|
|
80022de: 4013 ands r3, r2
|
||
|
|
80022e0: d009 beq.n 80022f6 <HAL_UART_IRQHandler+0x3ba>
|
||
|
|
{
|
||
|
|
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_WUF);
|
||
|
|
80022e2: 687b ldr r3, [r7, #4]
|
||
|
|
80022e4: 681b ldr r3, [r3, #0]
|
||
|
|
80022e6: 2280 movs r2, #128 ; 0x80
|
||
|
|
80022e8: 0352 lsls r2, r2, #13
|
||
|
|
80022ea: 621a str r2, [r3, #32]
|
||
|
|
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
|
||
|
|
/* Call registered Wakeup Callback */
|
||
|
|
huart->WakeupCallback(huart);
|
||
|
|
#else
|
||
|
|
/* Call legacy weak Wakeup Callback */
|
||
|
|
HAL_UARTEx_WakeupCallback(huart);
|
||
|
|
80022ec: 687b ldr r3, [r7, #4]
|
||
|
|
80022ee: 0018 movs r0, r3
|
||
|
|
80022f0: f000 fce3 bl 8002cba <HAL_UARTEx_WakeupCallback>
|
||
|
|
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
|
||
|
|
return;
|
||
|
|
80022f4: e028 b.n 8002348 <HAL_UART_IRQHandler+0x40c>
|
||
|
|
}
|
||
|
|
|
||
|
|
/* UART in mode Transmitter ------------------------------------------------*/
|
||
|
|
if (((isrflags & USART_ISR_TXE) != 0U)
|
||
|
|
80022f6: 69fb ldr r3, [r7, #28]
|
||
|
|
80022f8: 2280 movs r2, #128 ; 0x80
|
||
|
|
80022fa: 4013 ands r3, r2
|
||
|
|
80022fc: d00d beq.n 800231a <HAL_UART_IRQHandler+0x3de>
|
||
|
|
&& ((cr1its & USART_CR1_TXEIE) != 0U))
|
||
|
|
80022fe: 69bb ldr r3, [r7, #24]
|
||
|
|
8002300: 2280 movs r2, #128 ; 0x80
|
||
|
|
8002302: 4013 ands r3, r2
|
||
|
|
8002304: d009 beq.n 800231a <HAL_UART_IRQHandler+0x3de>
|
||
|
|
{
|
||
|
|
if (huart->TxISR != NULL)
|
||
|
|
8002306: 687b ldr r3, [r7, #4]
|
||
|
|
8002308: 6e9b ldr r3, [r3, #104] ; 0x68
|
||
|
|
800230a: 2b00 cmp r3, #0
|
||
|
|
800230c: d01b beq.n 8002346 <HAL_UART_IRQHandler+0x40a>
|
||
|
|
{
|
||
|
|
huart->TxISR(huart);
|
||
|
|
800230e: 687b ldr r3, [r7, #4]
|
||
|
|
8002310: 6e9b ldr r3, [r3, #104] ; 0x68
|
||
|
|
8002312: 687a ldr r2, [r7, #4]
|
||
|
|
8002314: 0010 movs r0, r2
|
||
|
|
8002316: 4798 blx r3
|
||
|
|
}
|
||
|
|
return;
|
||
|
|
8002318: e015 b.n 8002346 <HAL_UART_IRQHandler+0x40a>
|
||
|
|
}
|
||
|
|
|
||
|
|
/* UART in mode Transmitter (transmission end) -----------------------------*/
|
||
|
|
if (((isrflags & USART_ISR_TC) != 0U) && ((cr1its & USART_CR1_TCIE) != 0U))
|
||
|
|
800231a: 69fb ldr r3, [r7, #28]
|
||
|
|
800231c: 2240 movs r2, #64 ; 0x40
|
||
|
|
800231e: 4013 ands r3, r2
|
||
|
|
8002320: d012 beq.n 8002348 <HAL_UART_IRQHandler+0x40c>
|
||
|
|
8002322: 69bb ldr r3, [r7, #24]
|
||
|
|
8002324: 2240 movs r2, #64 ; 0x40
|
||
|
|
8002326: 4013 ands r3, r2
|
||
|
|
8002328: d00e beq.n 8002348 <HAL_UART_IRQHandler+0x40c>
|
||
|
|
{
|
||
|
|
UART_EndTransmit_IT(huart);
|
||
|
|
800232a: 687b ldr r3, [r7, #4]
|
||
|
|
800232c: 0018 movs r0, r3
|
||
|
|
800232e: f000 fcaa bl 8002c86 <UART_EndTransmit_IT>
|
||
|
|
return;
|
||
|
|
8002332: 46c0 nop ; (mov r8, r8)
|
||
|
|
8002334: e008 b.n 8002348 <HAL_UART_IRQHandler+0x40c>
|
||
|
|
return;
|
||
|
|
8002336: 46c0 nop ; (mov r8, r8)
|
||
|
|
8002338: e006 b.n 8002348 <HAL_UART_IRQHandler+0x40c>
|
||
|
|
return;
|
||
|
|
800233a: 46c0 nop ; (mov r8, r8)
|
||
|
|
800233c: e004 b.n 8002348 <HAL_UART_IRQHandler+0x40c>
|
||
|
|
return;
|
||
|
|
800233e: 46c0 nop ; (mov r8, r8)
|
||
|
|
8002340: e002 b.n 8002348 <HAL_UART_IRQHandler+0x40c>
|
||
|
|
return;
|
||
|
|
8002342: 46c0 nop ; (mov r8, r8)
|
||
|
|
8002344: e000 b.n 8002348 <HAL_UART_IRQHandler+0x40c>
|
||
|
|
return;
|
||
|
|
8002346: 46c0 nop ; (mov r8, r8)
|
||
|
|
}
|
||
|
|
|
||
|
|
}
|
||
|
|
8002348: 46bd mov sp, r7
|
||
|
|
800234a: b008 add sp, #32
|
||
|
|
800234c: bd80 pop {r7, pc}
|
||
|
|
800234e: 46c0 nop ; (mov r8, r8)
|
||
|
|
8002350: fffffedf .word 0xfffffedf
|
||
|
|
|
||
|
|
08002354 <HAL_UART_TxCpltCallback>:
|
||
|
|
* @brief Tx Transfer completed callback.
|
||
|
|
* @param huart UART handle.
|
||
|
|
* @retval None
|
||
|
|
*/
|
||
|
|
__weak void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart)
|
||
|
|
{
|
||
|
|
8002354: b580 push {r7, lr}
|
||
|
|
8002356: b082 sub sp, #8
|
||
|
|
8002358: af00 add r7, sp, #0
|
||
|
|
800235a: 6078 str r0, [r7, #4]
|
||
|
|
UNUSED(huart);
|
||
|
|
|
||
|
|
/* NOTE : This function should not be modified, when the callback is needed,
|
||
|
|
the HAL_UART_TxCpltCallback can be implemented in the user file.
|
||
|
|
*/
|
||
|
|
}
|
||
|
|
800235c: 46c0 nop ; (mov r8, r8)
|
||
|
|
800235e: 46bd mov sp, r7
|
||
|
|
8002360: b002 add sp, #8
|
||
|
|
8002362: bd80 pop {r7, pc}
|
||
|
|
|
||
|
|
08002364 <HAL_UART_ErrorCallback>:
|
||
|
|
* @brief UART error callback.
|
||
|
|
* @param huart UART handle.
|
||
|
|
* @retval None
|
||
|
|
*/
|
||
|
|
__weak void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart)
|
||
|
|
{
|
||
|
|
8002364: b580 push {r7, lr}
|
||
|
|
8002366: b082 sub sp, #8
|
||
|
|
8002368: af00 add r7, sp, #0
|
||
|
|
800236a: 6078 str r0, [r7, #4]
|
||
|
|
UNUSED(huart);
|
||
|
|
|
||
|
|
/* NOTE : This function should not be modified, when the callback is needed,
|
||
|
|
the HAL_UART_ErrorCallback can be implemented in the user file.
|
||
|
|
*/
|
||
|
|
}
|
||
|
|
800236c: 46c0 nop ; (mov r8, r8)
|
||
|
|
800236e: 46bd mov sp, r7
|
||
|
|
8002370: b002 add sp, #8
|
||
|
|
8002372: bd80 pop {r7, pc}
|
||
|
|
|
||
|
|
08002374 <HAL_UARTEx_RxEventCallback>:
|
||
|
|
* @param Size Number of data available in application reception buffer (indicates a position in
|
||
|
|
* reception buffer until which, data are available)
|
||
|
|
* @retval None
|
||
|
|
*/
|
||
|
|
__weak void HAL_UARTEx_RxEventCallback(UART_HandleTypeDef *huart, uint16_t Size)
|
||
|
|
{
|
||
|
|
8002374: b580 push {r7, lr}
|
||
|
|
8002376: b082 sub sp, #8
|
||
|
|
8002378: af00 add r7, sp, #0
|
||
|
|
800237a: 6078 str r0, [r7, #4]
|
||
|
|
800237c: 000a movs r2, r1
|
||
|
|
800237e: 1cbb adds r3, r7, #2
|
||
|
|
8002380: 801a strh r2, [r3, #0]
|
||
|
|
UNUSED(Size);
|
||
|
|
|
||
|
|
/* NOTE : This function should not be modified, when the callback is needed,
|
||
|
|
the HAL_UARTEx_RxEventCallback can be implemented in the user file.
|
||
|
|
*/
|
||
|
|
}
|
||
|
|
8002382: 46c0 nop ; (mov r8, r8)
|
||
|
|
8002384: 46bd mov sp, r7
|
||
|
|
8002386: b002 add sp, #8
|
||
|
|
8002388: bd80 pop {r7, pc}
|
||
|
|
...
|
||
|
|
|
||
|
|
0800238c <UART_SetConfig>:
|
||
|
|
* @brief Configure the UART peripheral.
|
||
|
|
* @param huart UART handle.
|
||
|
|
* @retval HAL status
|
||
|
|
*/
|
||
|
|
HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart)
|
||
|
|
{
|
||
|
|
800238c: b5b0 push {r4, r5, r7, lr}
|
||
|
|
800238e: b08e sub sp, #56 ; 0x38
|
||
|
|
8002390: af00 add r7, sp, #0
|
||
|
|
8002392: 61f8 str r0, [r7, #28]
|
||
|
|
uint32_t tmpreg;
|
||
|
|
uint16_t brrtemp;
|
||
|
|
UART_ClockSourceTypeDef clocksource;
|
||
|
|
uint32_t usartdiv;
|
||
|
|
HAL_StatusTypeDef ret = HAL_OK;
|
||
|
|
8002394: 231a movs r3, #26
|
||
|
|
8002396: 2218 movs r2, #24
|
||
|
|
8002398: 4694 mov ip, r2
|
||
|
|
800239a: 44bc add ip, r7
|
||
|
|
800239c: 4463 add r3, ip
|
||
|
|
800239e: 2200 movs r2, #0
|
||
|
|
80023a0: 701a strb r2, [r3, #0]
|
||
|
|
* the UART Word Length, Parity, Mode and oversampling:
|
||
|
|
* set the M bits according to huart->Init.WordLength value
|
||
|
|
* set PCE and PS bits according to huart->Init.Parity value
|
||
|
|
* set TE and RE bits according to huart->Init.Mode value
|
||
|
|
* set OVER8 bit according to huart->Init.OverSampling value */
|
||
|
|
tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.OverSampling ;
|
||
|
|
80023a2: 69fb ldr r3, [r7, #28]
|
||
|
|
80023a4: 689a ldr r2, [r3, #8]
|
||
|
|
80023a6: 69fb ldr r3, [r7, #28]
|
||
|
|
80023a8: 691b ldr r3, [r3, #16]
|
||
|
|
80023aa: 431a orrs r2, r3
|
||
|
|
80023ac: 69fb ldr r3, [r7, #28]
|
||
|
|
80023ae: 695b ldr r3, [r3, #20]
|
||
|
|
80023b0: 431a orrs r2, r3
|
||
|
|
80023b2: 69fb ldr r3, [r7, #28]
|
||
|
|
80023b4: 69db ldr r3, [r3, #28]
|
||
|
|
80023b6: 4313 orrs r3, r2
|
||
|
|
80023b8: 637b str r3, [r7, #52] ; 0x34
|
||
|
|
MODIFY_REG(huart->Instance->CR1, USART_CR1_FIELDS, tmpreg);
|
||
|
|
80023ba: 69fb ldr r3, [r7, #28]
|
||
|
|
80023bc: 681b ldr r3, [r3, #0]
|
||
|
|
80023be: 69fa ldr r2, [r7, #28]
|
||
|
|
80023c0: 6812 ldr r2, [r2, #0]
|
||
|
|
80023c2: 6812 ldr r2, [r2, #0]
|
||
|
|
80023c4: 49c8 ldr r1, [pc, #800] ; (80026e8 <UART_SetConfig+0x35c>)
|
||
|
|
80023c6: 4011 ands r1, r2
|
||
|
|
80023c8: 6b7a ldr r2, [r7, #52] ; 0x34
|
||
|
|
80023ca: 430a orrs r2, r1
|
||
|
|
80023cc: 601a str r2, [r3, #0]
|
||
|
|
|
||
|
|
/*-------------------------- USART CR2 Configuration -----------------------*/
|
||
|
|
/* Configure the UART Stop Bits: Set STOP[13:12] bits according
|
||
|
|
* to huart->Init.StopBits value */
|
||
|
|
MODIFY_REG(huart->Instance->CR2, USART_CR2_STOP, huart->Init.StopBits);
|
||
|
|
80023ce: 69fb ldr r3, [r7, #28]
|
||
|
|
80023d0: 681b ldr r3, [r3, #0]
|
||
|
|
80023d2: 69fa ldr r2, [r7, #28]
|
||
|
|
80023d4: 6812 ldr r2, [r2, #0]
|
||
|
|
80023d6: 6852 ldr r2, [r2, #4]
|
||
|
|
80023d8: 49c4 ldr r1, [pc, #784] ; (80026ec <UART_SetConfig+0x360>)
|
||
|
|
80023da: 4011 ands r1, r2
|
||
|
|
80023dc: 69fa ldr r2, [r7, #28]
|
||
|
|
80023de: 68d2 ldr r2, [r2, #12]
|
||
|
|
80023e0: 430a orrs r2, r1
|
||
|
|
80023e2: 605a str r2, [r3, #4]
|
||
|
|
/* Configure
|
||
|
|
* - UART HardWare Flow Control: set CTSE and RTSE bits according
|
||
|
|
* to huart->Init.HwFlowCtl value
|
||
|
|
* - one-bit sampling method versus three samples' majority rule according
|
||
|
|
* to huart->Init.OneBitSampling (not applicable to LPUART) */
|
||
|
|
tmpreg = (uint32_t)huart->Init.HwFlowCtl;
|
||
|
|
80023e4: 69fb ldr r3, [r7, #28]
|
||
|
|
80023e6: 699b ldr r3, [r3, #24]
|
||
|
|
80023e8: 637b str r3, [r7, #52] ; 0x34
|
||
|
|
|
||
|
|
if (!(UART_INSTANCE_LOWPOWER(huart)))
|
||
|
|
80023ea: 69fb ldr r3, [r7, #28]
|
||
|
|
80023ec: 681b ldr r3, [r3, #0]
|
||
|
|
80023ee: 4ac0 ldr r2, [pc, #768] ; (80026f0 <UART_SetConfig+0x364>)
|
||
|
|
80023f0: 4293 cmp r3, r2
|
||
|
|
80023f2: d004 beq.n 80023fe <UART_SetConfig+0x72>
|
||
|
|
{
|
||
|
|
tmpreg |= huart->Init.OneBitSampling;
|
||
|
|
80023f4: 69fb ldr r3, [r7, #28]
|
||
|
|
80023f6: 6a1b ldr r3, [r3, #32]
|
||
|
|
80023f8: 6b7a ldr r2, [r7, #52] ; 0x34
|
||
|
|
80023fa: 4313 orrs r3, r2
|
||
|
|
80023fc: 637b str r3, [r7, #52] ; 0x34
|
||
|
|
}
|
||
|
|
MODIFY_REG(huart->Instance->CR3, USART_CR3_FIELDS, tmpreg);
|
||
|
|
80023fe: 69fb ldr r3, [r7, #28]
|
||
|
|
8002400: 681b ldr r3, [r3, #0]
|
||
|
|
8002402: 69fa ldr r2, [r7, #28]
|
||
|
|
8002404: 6812 ldr r2, [r2, #0]
|
||
|
|
8002406: 6892 ldr r2, [r2, #8]
|
||
|
|
8002408: 49ba ldr r1, [pc, #744] ; (80026f4 <UART_SetConfig+0x368>)
|
||
|
|
800240a: 4011 ands r1, r2
|
||
|
|
800240c: 6b7a ldr r2, [r7, #52] ; 0x34
|
||
|
|
800240e: 430a orrs r2, r1
|
||
|
|
8002410: 609a str r2, [r3, #8]
|
||
|
|
|
||
|
|
|
||
|
|
/*-------------------------- USART BRR Configuration -----------------------*/
|
||
|
|
UART_GETCLOCKSOURCE(huart, clocksource);
|
||
|
|
8002412: 69fb ldr r3, [r7, #28]
|
||
|
|
8002414: 681b ldr r3, [r3, #0]
|
||
|
|
8002416: 4ab8 ldr r2, [pc, #736] ; (80026f8 <UART_SetConfig+0x36c>)
|
||
|
|
8002418: 4293 cmp r3, r2
|
||
|
|
800241a: d134 bne.n 8002486 <UART_SetConfig+0xfa>
|
||
|
|
800241c: 4bb7 ldr r3, [pc, #732] ; (80026fc <UART_SetConfig+0x370>)
|
||
|
|
800241e: 6cdb ldr r3, [r3, #76] ; 0x4c
|
||
|
|
8002420: 2203 movs r2, #3
|
||
|
|
8002422: 4013 ands r3, r2
|
||
|
|
8002424: 2b01 cmp r3, #1
|
||
|
|
8002426: d015 beq.n 8002454 <UART_SetConfig+0xc8>
|
||
|
|
8002428: d304 bcc.n 8002434 <UART_SetConfig+0xa8>
|
||
|
|
800242a: 2b02 cmp r3, #2
|
||
|
|
800242c: d00a beq.n 8002444 <UART_SetConfig+0xb8>
|
||
|
|
800242e: 2b03 cmp r3, #3
|
||
|
|
8002430: d018 beq.n 8002464 <UART_SetConfig+0xd8>
|
||
|
|
8002432: e01f b.n 8002474 <UART_SetConfig+0xe8>
|
||
|
|
8002434: 231b movs r3, #27
|
||
|
|
8002436: 2218 movs r2, #24
|
||
|
|
8002438: 4694 mov ip, r2
|
||
|
|
800243a: 44bc add ip, r7
|
||
|
|
800243c: 4463 add r3, ip
|
||
|
|
800243e: 2201 movs r2, #1
|
||
|
|
8002440: 701a strb r2, [r3, #0]
|
||
|
|
8002442: e0c5 b.n 80025d0 <UART_SetConfig+0x244>
|
||
|
|
8002444: 231b movs r3, #27
|
||
|
|
8002446: 2218 movs r2, #24
|
||
|
|
8002448: 4694 mov ip, r2
|
||
|
|
800244a: 44bc add ip, r7
|
||
|
|
800244c: 4463 add r3, ip
|
||
|
|
800244e: 2202 movs r2, #2
|
||
|
|
8002450: 701a strb r2, [r3, #0]
|
||
|
|
8002452: e0bd b.n 80025d0 <UART_SetConfig+0x244>
|
||
|
|
8002454: 231b movs r3, #27
|
||
|
|
8002456: 2218 movs r2, #24
|
||
|
|
8002458: 4694 mov ip, r2
|
||
|
|
800245a: 44bc add ip, r7
|
||
|
|
800245c: 4463 add r3, ip
|
||
|
|
800245e: 2204 movs r2, #4
|
||
|
|
8002460: 701a strb r2, [r3, #0]
|
||
|
|
8002462: e0b5 b.n 80025d0 <UART_SetConfig+0x244>
|
||
|
|
8002464: 231b movs r3, #27
|
||
|
|
8002466: 2218 movs r2, #24
|
||
|
|
8002468: 4694 mov ip, r2
|
||
|
|
800246a: 44bc add ip, r7
|
||
|
|
800246c: 4463 add r3, ip
|
||
|
|
800246e: 2208 movs r2, #8
|
||
|
|
8002470: 701a strb r2, [r3, #0]
|
||
|
|
8002472: e0ad b.n 80025d0 <UART_SetConfig+0x244>
|
||
|
|
8002474: 231b movs r3, #27
|
||
|
|
8002476: 2218 movs r2, #24
|
||
|
|
8002478: 4694 mov ip, r2
|
||
|
|
800247a: 44bc add ip, r7
|
||
|
|
800247c: 4463 add r3, ip
|
||
|
|
800247e: 2210 movs r2, #16
|
||
|
|
8002480: 701a strb r2, [r3, #0]
|
||
|
|
8002482: 46c0 nop ; (mov r8, r8)
|
||
|
|
8002484: e0a4 b.n 80025d0 <UART_SetConfig+0x244>
|
||
|
|
8002486: 69fb ldr r3, [r7, #28]
|
||
|
|
8002488: 681b ldr r3, [r3, #0]
|
||
|
|
800248a: 4a9d ldr r2, [pc, #628] ; (8002700 <UART_SetConfig+0x374>)
|
||
|
|
800248c: 4293 cmp r3, r2
|
||
|
|
800248e: d137 bne.n 8002500 <UART_SetConfig+0x174>
|
||
|
|
8002490: 4b9a ldr r3, [pc, #616] ; (80026fc <UART_SetConfig+0x370>)
|
||
|
|
8002492: 6cdb ldr r3, [r3, #76] ; 0x4c
|
||
|
|
8002494: 220c movs r2, #12
|
||
|
|
8002496: 4013 ands r3, r2
|
||
|
|
8002498: 2b04 cmp r3, #4
|
||
|
|
800249a: d018 beq.n 80024ce <UART_SetConfig+0x142>
|
||
|
|
800249c: d802 bhi.n 80024a4 <UART_SetConfig+0x118>
|
||
|
|
800249e: 2b00 cmp r3, #0
|
||
|
|
80024a0: d005 beq.n 80024ae <UART_SetConfig+0x122>
|
||
|
|
80024a2: e024 b.n 80024ee <UART_SetConfig+0x162>
|
||
|
|
80024a4: 2b08 cmp r3, #8
|
||
|
|
80024a6: d00a beq.n 80024be <UART_SetConfig+0x132>
|
||
|
|
80024a8: 2b0c cmp r3, #12
|
||
|
|
80024aa: d018 beq.n 80024de <UART_SetConfig+0x152>
|
||
|
|
80024ac: e01f b.n 80024ee <UART_SetConfig+0x162>
|
||
|
|
80024ae: 231b movs r3, #27
|
||
|
|
80024b0: 2218 movs r2, #24
|
||
|
|
80024b2: 4694 mov ip, r2
|
||
|
|
80024b4: 44bc add ip, r7
|
||
|
|
80024b6: 4463 add r3, ip
|
||
|
|
80024b8: 2200 movs r2, #0
|
||
|
|
80024ba: 701a strb r2, [r3, #0]
|
||
|
|
80024bc: e088 b.n 80025d0 <UART_SetConfig+0x244>
|
||
|
|
80024be: 231b movs r3, #27
|
||
|
|
80024c0: 2218 movs r2, #24
|
||
|
|
80024c2: 4694 mov ip, r2
|
||
|
|
80024c4: 44bc add ip, r7
|
||
|
|
80024c6: 4463 add r3, ip
|
||
|
|
80024c8: 2202 movs r2, #2
|
||
|
|
80024ca: 701a strb r2, [r3, #0]
|
||
|
|
80024cc: e080 b.n 80025d0 <UART_SetConfig+0x244>
|
||
|
|
80024ce: 231b movs r3, #27
|
||
|
|
80024d0: 2218 movs r2, #24
|
||
|
|
80024d2: 4694 mov ip, r2
|
||
|
|
80024d4: 44bc add ip, r7
|
||
|
|
80024d6: 4463 add r3, ip
|
||
|
|
80024d8: 2204 movs r2, #4
|
||
|
|
80024da: 701a strb r2, [r3, #0]
|
||
|
|
80024dc: e078 b.n 80025d0 <UART_SetConfig+0x244>
|
||
|
|
80024de: 231b movs r3, #27
|
||
|
|
80024e0: 2218 movs r2, #24
|
||
|
|
80024e2: 4694 mov ip, r2
|
||
|
|
80024e4: 44bc add ip, r7
|
||
|
|
80024e6: 4463 add r3, ip
|
||
|
|
80024e8: 2208 movs r2, #8
|
||
|
|
80024ea: 701a strb r2, [r3, #0]
|
||
|
|
80024ec: e070 b.n 80025d0 <UART_SetConfig+0x244>
|
||
|
|
80024ee: 231b movs r3, #27
|
||
|
|
80024f0: 2218 movs r2, #24
|
||
|
|
80024f2: 4694 mov ip, r2
|
||
|
|
80024f4: 44bc add ip, r7
|
||
|
|
80024f6: 4463 add r3, ip
|
||
|
|
80024f8: 2210 movs r2, #16
|
||
|
|
80024fa: 701a strb r2, [r3, #0]
|
||
|
|
80024fc: 46c0 nop ; (mov r8, r8)
|
||
|
|
80024fe: e067 b.n 80025d0 <UART_SetConfig+0x244>
|
||
|
|
8002500: 69fb ldr r3, [r7, #28]
|
||
|
|
8002502: 681b ldr r3, [r3, #0]
|
||
|
|
8002504: 4a7f ldr r2, [pc, #508] ; (8002704 <UART_SetConfig+0x378>)
|
||
|
|
8002506: 4293 cmp r3, r2
|
||
|
|
8002508: d107 bne.n 800251a <UART_SetConfig+0x18e>
|
||
|
|
800250a: 231b movs r3, #27
|
||
|
|
800250c: 2218 movs r2, #24
|
||
|
|
800250e: 4694 mov ip, r2
|
||
|
|
8002510: 44bc add ip, r7
|
||
|
|
8002512: 4463 add r3, ip
|
||
|
|
8002514: 2200 movs r2, #0
|
||
|
|
8002516: 701a strb r2, [r3, #0]
|
||
|
|
8002518: e05a b.n 80025d0 <UART_SetConfig+0x244>
|
||
|
|
800251a: 69fb ldr r3, [r7, #28]
|
||
|
|
800251c: 681b ldr r3, [r3, #0]
|
||
|
|
800251e: 4a7a ldr r2, [pc, #488] ; (8002708 <UART_SetConfig+0x37c>)
|
||
|
|
8002520: 4293 cmp r3, r2
|
||
|
|
8002522: d107 bne.n 8002534 <UART_SetConfig+0x1a8>
|
||
|
|
8002524: 231b movs r3, #27
|
||
|
|
8002526: 2218 movs r2, #24
|
||
|
|
8002528: 4694 mov ip, r2
|
||
|
|
800252a: 44bc add ip, r7
|
||
|
|
800252c: 4463 add r3, ip
|
||
|
|
800252e: 2200 movs r2, #0
|
||
|
|
8002530: 701a strb r2, [r3, #0]
|
||
|
|
8002532: e04d b.n 80025d0 <UART_SetConfig+0x244>
|
||
|
|
8002534: 69fb ldr r3, [r7, #28]
|
||
|
|
8002536: 681b ldr r3, [r3, #0]
|
||
|
|
8002538: 4a6d ldr r2, [pc, #436] ; (80026f0 <UART_SetConfig+0x364>)
|
||
|
|
800253a: 4293 cmp r3, r2
|
||
|
|
800253c: d141 bne.n 80025c2 <UART_SetConfig+0x236>
|
||
|
|
800253e: 4b6f ldr r3, [pc, #444] ; (80026fc <UART_SetConfig+0x370>)
|
||
|
|
8002540: 6cda ldr r2, [r3, #76] ; 0x4c
|
||
|
|
8002542: 23c0 movs r3, #192 ; 0xc0
|
||
|
|
8002544: 011b lsls r3, r3, #4
|
||
|
|
8002546: 4013 ands r3, r2
|
||
|
|
8002548: 2280 movs r2, #128 ; 0x80
|
||
|
|
800254a: 00d2 lsls r2, r2, #3
|
||
|
|
800254c: 4293 cmp r3, r2
|
||
|
|
800254e: d01f beq.n 8002590 <UART_SetConfig+0x204>
|
||
|
|
8002550: 2280 movs r2, #128 ; 0x80
|
||
|
|
8002552: 00d2 lsls r2, r2, #3
|
||
|
|
8002554: 4293 cmp r3, r2
|
||
|
|
8002556: d802 bhi.n 800255e <UART_SetConfig+0x1d2>
|
||
|
|
8002558: 2b00 cmp r3, #0
|
||
|
|
800255a: d009 beq.n 8002570 <UART_SetConfig+0x1e4>
|
||
|
|
800255c: e028 b.n 80025b0 <UART_SetConfig+0x224>
|
||
|
|
800255e: 2280 movs r2, #128 ; 0x80
|
||
|
|
8002560: 0112 lsls r2, r2, #4
|
||
|
|
8002562: 4293 cmp r3, r2
|
||
|
|
8002564: d00c beq.n 8002580 <UART_SetConfig+0x1f4>
|
||
|
|
8002566: 22c0 movs r2, #192 ; 0xc0
|
||
|
|
8002568: 0112 lsls r2, r2, #4
|
||
|
|
800256a: 4293 cmp r3, r2
|
||
|
|
800256c: d018 beq.n 80025a0 <UART_SetConfig+0x214>
|
||
|
|
800256e: e01f b.n 80025b0 <UART_SetConfig+0x224>
|
||
|
|
8002570: 231b movs r3, #27
|
||
|
|
8002572: 2218 movs r2, #24
|
||
|
|
8002574: 4694 mov ip, r2
|
||
|
|
8002576: 44bc add ip, r7
|
||
|
|
8002578: 4463 add r3, ip
|
||
|
|
800257a: 2200 movs r2, #0
|
||
|
|
800257c: 701a strb r2, [r3, #0]
|
||
|
|
800257e: e027 b.n 80025d0 <UART_SetConfig+0x244>
|
||
|
|
8002580: 231b movs r3, #27
|
||
|
|
8002582: 2218 movs r2, #24
|
||
|
|
8002584: 4694 mov ip, r2
|
||
|
|
8002586: 44bc add ip, r7
|
||
|
|
8002588: 4463 add r3, ip
|
||
|
|
800258a: 2202 movs r2, #2
|
||
|
|
800258c: 701a strb r2, [r3, #0]
|
||
|
|
800258e: e01f b.n 80025d0 <UART_SetConfig+0x244>
|
||
|
|
8002590: 231b movs r3, #27
|
||
|
|
8002592: 2218 movs r2, #24
|
||
|
|
8002594: 4694 mov ip, r2
|
||
|
|
8002596: 44bc add ip, r7
|
||
|
|
8002598: 4463 add r3, ip
|
||
|
|
800259a: 2204 movs r2, #4
|
||
|
|
800259c: 701a strb r2, [r3, #0]
|
||
|
|
800259e: e017 b.n 80025d0 <UART_SetConfig+0x244>
|
||
|
|
80025a0: 231b movs r3, #27
|
||
|
|
80025a2: 2218 movs r2, #24
|
||
|
|
80025a4: 4694 mov ip, r2
|
||
|
|
80025a6: 44bc add ip, r7
|
||
|
|
80025a8: 4463 add r3, ip
|
||
|
|
80025aa: 2208 movs r2, #8
|
||
|
|
80025ac: 701a strb r2, [r3, #0]
|
||
|
|
80025ae: e00f b.n 80025d0 <UART_SetConfig+0x244>
|
||
|
|
80025b0: 231b movs r3, #27
|
||
|
|
80025b2: 2218 movs r2, #24
|
||
|
|
80025b4: 4694 mov ip, r2
|
||
|
|
80025b6: 44bc add ip, r7
|
||
|
|
80025b8: 4463 add r3, ip
|
||
|
|
80025ba: 2210 movs r2, #16
|
||
|
|
80025bc: 701a strb r2, [r3, #0]
|
||
|
|
80025be: 46c0 nop ; (mov r8, r8)
|
||
|
|
80025c0: e006 b.n 80025d0 <UART_SetConfig+0x244>
|
||
|
|
80025c2: 231b movs r3, #27
|
||
|
|
80025c4: 2218 movs r2, #24
|
||
|
|
80025c6: 4694 mov ip, r2
|
||
|
|
80025c8: 44bc add ip, r7
|
||
|
|
80025ca: 4463 add r3, ip
|
||
|
|
80025cc: 2210 movs r2, #16
|
||
|
|
80025ce: 701a strb r2, [r3, #0]
|
||
|
|
|
||
|
|
/* Check LPUART instance */
|
||
|
|
if (UART_INSTANCE_LOWPOWER(huart))
|
||
|
|
80025d0: 69fb ldr r3, [r7, #28]
|
||
|
|
80025d2: 681b ldr r3, [r3, #0]
|
||
|
|
80025d4: 4a46 ldr r2, [pc, #280] ; (80026f0 <UART_SetConfig+0x364>)
|
||
|
|
80025d6: 4293 cmp r3, r2
|
||
|
|
80025d8: d000 beq.n 80025dc <UART_SetConfig+0x250>
|
||
|
|
80025da: e09f b.n 800271c <UART_SetConfig+0x390>
|
||
|
|
{
|
||
|
|
/* Retrieve frequency clock */
|
||
|
|
switch (clocksource)
|
||
|
|
80025dc: 231b movs r3, #27
|
||
|
|
80025de: 2218 movs r2, #24
|
||
|
|
80025e0: 4694 mov ip, r2
|
||
|
|
80025e2: 44bc add ip, r7
|
||
|
|
80025e4: 4463 add r3, ip
|
||
|
|
80025e6: 781b ldrb r3, [r3, #0]
|
||
|
|
80025e8: 2b02 cmp r3, #2
|
||
|
|
80025ea: d00d beq.n 8002608 <UART_SetConfig+0x27c>
|
||
|
|
80025ec: dc02 bgt.n 80025f4 <UART_SetConfig+0x268>
|
||
|
|
80025ee: 2b00 cmp r3, #0
|
||
|
|
80025f0: d005 beq.n 80025fe <UART_SetConfig+0x272>
|
||
|
|
80025f2: e01d b.n 8002630 <UART_SetConfig+0x2a4>
|
||
|
|
80025f4: 2b04 cmp r3, #4
|
||
|
|
80025f6: d012 beq.n 800261e <UART_SetConfig+0x292>
|
||
|
|
80025f8: 2b08 cmp r3, #8
|
||
|
|
80025fa: d015 beq.n 8002628 <UART_SetConfig+0x29c>
|
||
|
|
80025fc: e018 b.n 8002630 <UART_SetConfig+0x2a4>
|
||
|
|
{
|
||
|
|
case UART_CLOCKSOURCE_PCLK1:
|
||
|
|
pclk = HAL_RCC_GetPCLK1Freq();
|
||
|
|
80025fe: f7ff facb bl 8001b98 <HAL_RCC_GetPCLK1Freq>
|
||
|
|
8002602: 0003 movs r3, r0
|
||
|
|
8002604: 62fb str r3, [r7, #44] ; 0x2c
|
||
|
|
break;
|
||
|
|
8002606: e01d b.n 8002644 <UART_SetConfig+0x2b8>
|
||
|
|
case UART_CLOCKSOURCE_HSI:
|
||
|
|
if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U)
|
||
|
|
8002608: 4b3c ldr r3, [pc, #240] ; (80026fc <UART_SetConfig+0x370>)
|
||
|
|
800260a: 681b ldr r3, [r3, #0]
|
||
|
|
800260c: 2210 movs r2, #16
|
||
|
|
800260e: 4013 ands r3, r2
|
||
|
|
8002610: d002 beq.n 8002618 <UART_SetConfig+0x28c>
|
||
|
|
{
|
||
|
|
pclk = (uint32_t)(HSI_VALUE >> 2U);
|
||
|
|
8002612: 4b3e ldr r3, [pc, #248] ; (800270c <UART_SetConfig+0x380>)
|
||
|
|
8002614: 62fb str r3, [r7, #44] ; 0x2c
|
||
|
|
}
|
||
|
|
else
|
||
|
|
{
|
||
|
|
pclk = (uint32_t) HSI_VALUE;
|
||
|
|
}
|
||
|
|
break;
|
||
|
|
8002616: e015 b.n 8002644 <UART_SetConfig+0x2b8>
|
||
|
|
pclk = (uint32_t) HSI_VALUE;
|
||
|
|
8002618: 4b3d ldr r3, [pc, #244] ; (8002710 <UART_SetConfig+0x384>)
|
||
|
|
800261a: 62fb str r3, [r7, #44] ; 0x2c
|
||
|
|
break;
|
||
|
|
800261c: e012 b.n 8002644 <UART_SetConfig+0x2b8>
|
||
|
|
case UART_CLOCKSOURCE_SYSCLK:
|
||
|
|
pclk = HAL_RCC_GetSysClockFreq();
|
||
|
|
800261e: f7ff fa0f bl 8001a40 <HAL_RCC_GetSysClockFreq>
|
||
|
|
8002622: 0003 movs r3, r0
|
||
|
|
8002624: 62fb str r3, [r7, #44] ; 0x2c
|
||
|
|
break;
|
||
|
|
8002626: e00d b.n 8002644 <UART_SetConfig+0x2b8>
|
||
|
|
case UART_CLOCKSOURCE_LSE:
|
||
|
|
pclk = (uint32_t) LSE_VALUE;
|
||
|
|
8002628: 2380 movs r3, #128 ; 0x80
|
||
|
|
800262a: 021b lsls r3, r3, #8
|
||
|
|
800262c: 62fb str r3, [r7, #44] ; 0x2c
|
||
|
|
break;
|
||
|
|
800262e: e009 b.n 8002644 <UART_SetConfig+0x2b8>
|
||
|
|
default:
|
||
|
|
pclk = 0U;
|
||
|
|
8002630: 2300 movs r3, #0
|
||
|
|
8002632: 62fb str r3, [r7, #44] ; 0x2c
|
||
|
|
ret = HAL_ERROR;
|
||
|
|
8002634: 231a movs r3, #26
|
||
|
|
8002636: 2218 movs r2, #24
|
||
|
|
8002638: 4694 mov ip, r2
|
||
|
|
800263a: 44bc add ip, r7
|
||
|
|
800263c: 4463 add r3, ip
|
||
|
|
800263e: 2201 movs r2, #1
|
||
|
|
8002640: 701a strb r2, [r3, #0]
|
||
|
|
break;
|
||
|
|
8002642: 46c0 nop ; (mov r8, r8)
|
||
|
|
}
|
||
|
|
|
||
|
|
/* If proper clock source reported */
|
||
|
|
if (pclk != 0U)
|
||
|
|
8002644: 6afb ldr r3, [r7, #44] ; 0x2c
|
||
|
|
8002646: 2b00 cmp r3, #0
|
||
|
|
8002648: d100 bne.n 800264c <UART_SetConfig+0x2c0>
|
||
|
|
800264a: e145 b.n 80028d8 <UART_SetConfig+0x54c>
|
||
|
|
{
|
||
|
|
/* No Prescaler applicable */
|
||
|
|
/* Ensure that Frequency clock is in the range [3 * baudrate, 4096 * baudrate] */
|
||
|
|
if ((pclk < (3U * huart->Init.BaudRate)) ||
|
||
|
|
800264c: 69fb ldr r3, [r7, #28]
|
||
|
|
800264e: 685a ldr r2, [r3, #4]
|
||
|
|
8002650: 0013 movs r3, r2
|
||
|
|
8002652: 005b lsls r3, r3, #1
|
||
|
|
8002654: 189a adds r2, r3, r2
|
||
|
|
8002656: 6afb ldr r3, [r7, #44] ; 0x2c
|
||
|
|
8002658: 429a cmp r2, r3
|
||
|
|
800265a: d805 bhi.n 8002668 <UART_SetConfig+0x2dc>
|
||
|
|
(pclk > (4096U * huart->Init.BaudRate)))
|
||
|
|
800265c: 69fb ldr r3, [r7, #28]
|
||
|
|
800265e: 685b ldr r3, [r3, #4]
|
||
|
|
8002660: 031a lsls r2, r3, #12
|
||
|
|
if ((pclk < (3U * huart->Init.BaudRate)) ||
|
||
|
|
8002662: 6afb ldr r3, [r7, #44] ; 0x2c
|
||
|
|
8002664: 429a cmp r2, r3
|
||
|
|
8002666: d207 bcs.n 8002678 <UART_SetConfig+0x2ec>
|
||
|
|
{
|
||
|
|
ret = HAL_ERROR;
|
||
|
|
8002668: 231a movs r3, #26
|
||
|
|
800266a: 2218 movs r2, #24
|
||
|
|
800266c: 4694 mov ip, r2
|
||
|
|
800266e: 44bc add ip, r7
|
||
|
|
8002670: 4463 add r3, ip
|
||
|
|
8002672: 2201 movs r2, #1
|
||
|
|
8002674: 701a strb r2, [r3, #0]
|
||
|
|
8002676: e12f b.n 80028d8 <UART_SetConfig+0x54c>
|
||
|
|
}
|
||
|
|
else
|
||
|
|
{
|
||
|
|
usartdiv = (uint32_t)(UART_DIV_LPUART(pclk, huart->Init.BaudRate));
|
||
|
|
8002678: 6afb ldr r3, [r7, #44] ; 0x2c
|
||
|
|
800267a: 613b str r3, [r7, #16]
|
||
|
|
800267c: 2300 movs r3, #0
|
||
|
|
800267e: 617b str r3, [r7, #20]
|
||
|
|
8002680: 6939 ldr r1, [r7, #16]
|
||
|
|
8002682: 697a ldr r2, [r7, #20]
|
||
|
|
8002684: 000b movs r3, r1
|
||
|
|
8002686: 0e1b lsrs r3, r3, #24
|
||
|
|
8002688: 0010 movs r0, r2
|
||
|
|
800268a: 0205 lsls r5, r0, #8
|
||
|
|
800268c: 431d orrs r5, r3
|
||
|
|
800268e: 000b movs r3, r1
|
||
|
|
8002690: 021c lsls r4, r3, #8
|
||
|
|
8002692: 69fb ldr r3, [r7, #28]
|
||
|
|
8002694: 685b ldr r3, [r3, #4]
|
||
|
|
8002696: 085b lsrs r3, r3, #1
|
||
|
|
8002698: 60bb str r3, [r7, #8]
|
||
|
|
800269a: 2300 movs r3, #0
|
||
|
|
800269c: 60fb str r3, [r7, #12]
|
||
|
|
800269e: 68b8 ldr r0, [r7, #8]
|
||
|
|
80026a0: 68f9 ldr r1, [r7, #12]
|
||
|
|
80026a2: 1900 adds r0, r0, r4
|
||
|
|
80026a4: 4169 adcs r1, r5
|
||
|
|
80026a6: 69fb ldr r3, [r7, #28]
|
||
|
|
80026a8: 685b ldr r3, [r3, #4]
|
||
|
|
80026aa: 603b str r3, [r7, #0]
|
||
|
|
80026ac: 2300 movs r3, #0
|
||
|
|
80026ae: 607b str r3, [r7, #4]
|
||
|
|
80026b0: 683a ldr r2, [r7, #0]
|
||
|
|
80026b2: 687b ldr r3, [r7, #4]
|
||
|
|
80026b4: f7fd fdb4 bl 8000220 <__aeabi_uldivmod>
|
||
|
|
80026b8: 0003 movs r3, r0
|
||
|
|
80026ba: 000c movs r4, r1
|
||
|
|
80026bc: 62bb str r3, [r7, #40] ; 0x28
|
||
|
|
if ((usartdiv >= LPUART_BRR_MIN) && (usartdiv <= LPUART_BRR_MAX))
|
||
|
|
80026be: 6abb ldr r3, [r7, #40] ; 0x28
|
||
|
|
80026c0: 4a14 ldr r2, [pc, #80] ; (8002714 <UART_SetConfig+0x388>)
|
||
|
|
80026c2: 4293 cmp r3, r2
|
||
|
|
80026c4: d908 bls.n 80026d8 <UART_SetConfig+0x34c>
|
||
|
|
80026c6: 6abb ldr r3, [r7, #40] ; 0x28
|
||
|
|
80026c8: 4a13 ldr r2, [pc, #76] ; (8002718 <UART_SetConfig+0x38c>)
|
||
|
|
80026ca: 4293 cmp r3, r2
|
||
|
|
80026cc: d804 bhi.n 80026d8 <UART_SetConfig+0x34c>
|
||
|
|
{
|
||
|
|
huart->Instance->BRR = usartdiv;
|
||
|
|
80026ce: 69fb ldr r3, [r7, #28]
|
||
|
|
80026d0: 681b ldr r3, [r3, #0]
|
||
|
|
80026d2: 6aba ldr r2, [r7, #40] ; 0x28
|
||
|
|
80026d4: 60da str r2, [r3, #12]
|
||
|
|
80026d6: e0ff b.n 80028d8 <UART_SetConfig+0x54c>
|
||
|
|
}
|
||
|
|
else
|
||
|
|
{
|
||
|
|
ret = HAL_ERROR;
|
||
|
|
80026d8: 231a movs r3, #26
|
||
|
|
80026da: 2218 movs r2, #24
|
||
|
|
80026dc: 4694 mov ip, r2
|
||
|
|
80026de: 44bc add ip, r7
|
||
|
|
80026e0: 4463 add r3, ip
|
||
|
|
80026e2: 2201 movs r2, #1
|
||
|
|
80026e4: 701a strb r2, [r3, #0]
|
||
|
|
80026e6: e0f7 b.n 80028d8 <UART_SetConfig+0x54c>
|
||
|
|
80026e8: efff69f3 .word 0xefff69f3
|
||
|
|
80026ec: ffffcfff .word 0xffffcfff
|
||
|
|
80026f0: 40004800 .word 0x40004800
|
||
|
|
80026f4: fffff4ff .word 0xfffff4ff
|
||
|
|
80026f8: 40013800 .word 0x40013800
|
||
|
|
80026fc: 40021000 .word 0x40021000
|
||
|
|
8002700: 40004400 .word 0x40004400
|
||
|
|
8002704: 40004c00 .word 0x40004c00
|
||
|
|
8002708: 40005000 .word 0x40005000
|
||
|
|
800270c: 003d0900 .word 0x003d0900
|
||
|
|
8002710: 00f42400 .word 0x00f42400
|
||
|
|
8002714: 000002ff .word 0x000002ff
|
||
|
|
8002718: 000fffff .word 0x000fffff
|
||
|
|
}
|
||
|
|
} /* if ( (pclk < (3 * huart->Init.BaudRate) ) || (pclk > (4096 * huart->Init.BaudRate) )) */
|
||
|
|
} /* if (pclk != 0) */
|
||
|
|
}
|
||
|
|
/* Check UART Over Sampling to set Baud Rate Register */
|
||
|
|
else if (huart->Init.OverSampling == UART_OVERSAMPLING_8)
|
||
|
|
800271c: 69fb ldr r3, [r7, #28]
|
||
|
|
800271e: 69da ldr r2, [r3, #28]
|
||
|
|
8002720: 2380 movs r3, #128 ; 0x80
|
||
|
|
8002722: 021b lsls r3, r3, #8
|
||
|
|
8002724: 429a cmp r2, r3
|
||
|
|
8002726: d000 beq.n 800272a <UART_SetConfig+0x39e>
|
||
|
|
8002728: e07d b.n 8002826 <UART_SetConfig+0x49a>
|
||
|
|
{
|
||
|
|
switch (clocksource)
|
||
|
|
800272a: 231b movs r3, #27
|
||
|
|
800272c: 2218 movs r2, #24
|
||
|
|
800272e: 4694 mov ip, r2
|
||
|
|
8002730: 44bc add ip, r7
|
||
|
|
8002732: 4463 add r3, ip
|
||
|
|
8002734: 781b ldrb r3, [r3, #0]
|
||
|
|
8002736: 2b08 cmp r3, #8
|
||
|
|
8002738: d822 bhi.n 8002780 <UART_SetConfig+0x3f4>
|
||
|
|
800273a: 009a lsls r2, r3, #2
|
||
|
|
800273c: 4b6e ldr r3, [pc, #440] ; (80028f8 <UART_SetConfig+0x56c>)
|
||
|
|
800273e: 18d3 adds r3, r2, r3
|
||
|
|
8002740: 681b ldr r3, [r3, #0]
|
||
|
|
8002742: 469f mov pc, r3
|
||
|
|
{
|
||
|
|
case UART_CLOCKSOURCE_PCLK1:
|
||
|
|
pclk = HAL_RCC_GetPCLK1Freq();
|
||
|
|
8002744: f7ff fa28 bl 8001b98 <HAL_RCC_GetPCLK1Freq>
|
||
|
|
8002748: 0003 movs r3, r0
|
||
|
|
800274a: 62fb str r3, [r7, #44] ; 0x2c
|
||
|
|
break;
|
||
|
|
800274c: e022 b.n 8002794 <UART_SetConfig+0x408>
|
||
|
|
case UART_CLOCKSOURCE_PCLK2:
|
||
|
|
pclk = HAL_RCC_GetPCLK2Freq();
|
||
|
|
800274e: f7ff fa39 bl 8001bc4 <HAL_RCC_GetPCLK2Freq>
|
||
|
|
8002752: 0003 movs r3, r0
|
||
|
|
8002754: 62fb str r3, [r7, #44] ; 0x2c
|
||
|
|
break;
|
||
|
|
8002756: e01d b.n 8002794 <UART_SetConfig+0x408>
|
||
|
|
case UART_CLOCKSOURCE_HSI:
|
||
|
|
if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U)
|
||
|
|
8002758: 4b68 ldr r3, [pc, #416] ; (80028fc <UART_SetConfig+0x570>)
|
||
|
|
800275a: 681b ldr r3, [r3, #0]
|
||
|
|
800275c: 2210 movs r2, #16
|
||
|
|
800275e: 4013 ands r3, r2
|
||
|
|
8002760: d002 beq.n 8002768 <UART_SetConfig+0x3dc>
|
||
|
|
{
|
||
|
|
pclk = (uint32_t)(HSI_VALUE >> 2U);
|
||
|
|
8002762: 4b67 ldr r3, [pc, #412] ; (8002900 <UART_SetConfig+0x574>)
|
||
|
|
8002764: 62fb str r3, [r7, #44] ; 0x2c
|
||
|
|
}
|
||
|
|
else
|
||
|
|
{
|
||
|
|
pclk = (uint32_t) HSI_VALUE;
|
||
|
|
}
|
||
|
|
break;
|
||
|
|
8002766: e015 b.n 8002794 <UART_SetConfig+0x408>
|
||
|
|
pclk = (uint32_t) HSI_VALUE;
|
||
|
|
8002768: 4b66 ldr r3, [pc, #408] ; (8002904 <UART_SetConfig+0x578>)
|
||
|
|
800276a: 62fb str r3, [r7, #44] ; 0x2c
|
||
|
|
break;
|
||
|
|
800276c: e012 b.n 8002794 <UART_SetConfig+0x408>
|
||
|
|
case UART_CLOCKSOURCE_SYSCLK:
|
||
|
|
pclk = HAL_RCC_GetSysClockFreq();
|
||
|
|
800276e: f7ff f967 bl 8001a40 <HAL_RCC_GetSysClockFreq>
|
||
|
|
8002772: 0003 movs r3, r0
|
||
|
|
8002774: 62fb str r3, [r7, #44] ; 0x2c
|
||
|
|
break;
|
||
|
|
8002776: e00d b.n 8002794 <UART_SetConfig+0x408>
|
||
|
|
case UART_CLOCKSOURCE_LSE:
|
||
|
|
pclk = (uint32_t) LSE_VALUE;
|
||
|
|
8002778: 2380 movs r3, #128 ; 0x80
|
||
|
|
800277a: 021b lsls r3, r3, #8
|
||
|
|
800277c: 62fb str r3, [r7, #44] ; 0x2c
|
||
|
|
break;
|
||
|
|
800277e: e009 b.n 8002794 <UART_SetConfig+0x408>
|
||
|
|
default:
|
||
|
|
pclk = 0U;
|
||
|
|
8002780: 2300 movs r3, #0
|
||
|
|
8002782: 62fb str r3, [r7, #44] ; 0x2c
|
||
|
|
ret = HAL_ERROR;
|
||
|
|
8002784: 231a movs r3, #26
|
||
|
|
8002786: 2218 movs r2, #24
|
||
|
|
8002788: 4694 mov ip, r2
|
||
|
|
800278a: 44bc add ip, r7
|
||
|
|
800278c: 4463 add r3, ip
|
||
|
|
800278e: 2201 movs r2, #1
|
||
|
|
8002790: 701a strb r2, [r3, #0]
|
||
|
|
break;
|
||
|
|
8002792: 46c0 nop ; (mov r8, r8)
|
||
|
|
}
|
||
|
|
|
||
|
|
/* USARTDIV must be greater than or equal to 0d16 */
|
||
|
|
if (pclk != 0U)
|
||
|
|
8002794: 6afb ldr r3, [r7, #44] ; 0x2c
|
||
|
|
8002796: 2b00 cmp r3, #0
|
||
|
|
8002798: d100 bne.n 800279c <UART_SetConfig+0x410>
|
||
|
|
800279a: e09d b.n 80028d8 <UART_SetConfig+0x54c>
|
||
|
|
{
|
||
|
|
usartdiv = (uint16_t)(UART_DIV_SAMPLING8(pclk, huart->Init.BaudRate));
|
||
|
|
800279c: 6afb ldr r3, [r7, #44] ; 0x2c
|
||
|
|
800279e: 005a lsls r2, r3, #1
|
||
|
|
80027a0: 69fb ldr r3, [r7, #28]
|
||
|
|
80027a2: 685b ldr r3, [r3, #4]
|
||
|
|
80027a4: 085b lsrs r3, r3, #1
|
||
|
|
80027a6: 18d2 adds r2, r2, r3
|
||
|
|
80027a8: 69fb ldr r3, [r7, #28]
|
||
|
|
80027aa: 685b ldr r3, [r3, #4]
|
||
|
|
80027ac: 0019 movs r1, r3
|
||
|
|
80027ae: 0010 movs r0, r2
|
||
|
|
80027b0: f7fd fcaa bl 8000108 <__udivsi3>
|
||
|
|
80027b4: 0003 movs r3, r0
|
||
|
|
80027b6: b29b uxth r3, r3
|
||
|
|
80027b8: 62bb str r3, [r7, #40] ; 0x28
|
||
|
|
if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX))
|
||
|
|
80027ba: 6abb ldr r3, [r7, #40] ; 0x28
|
||
|
|
80027bc: 2b0f cmp r3, #15
|
||
|
|
80027be: d92a bls.n 8002816 <UART_SetConfig+0x48a>
|
||
|
|
80027c0: 6abb ldr r3, [r7, #40] ; 0x28
|
||
|
|
80027c2: 4a51 ldr r2, [pc, #324] ; (8002908 <UART_SetConfig+0x57c>)
|
||
|
|
80027c4: 4293 cmp r3, r2
|
||
|
|
80027c6: d826 bhi.n 8002816 <UART_SetConfig+0x48a>
|
||
|
|
{
|
||
|
|
brrtemp = (uint16_t)(usartdiv & 0xFFF0U);
|
||
|
|
80027c8: 6abb ldr r3, [r7, #40] ; 0x28
|
||
|
|
80027ca: b29a uxth r2, r3
|
||
|
|
80027cc: 230e movs r3, #14
|
||
|
|
80027ce: 2118 movs r1, #24
|
||
|
|
80027d0: 468c mov ip, r1
|
||
|
|
80027d2: 44bc add ip, r7
|
||
|
|
80027d4: 4463 add r3, ip
|
||
|
|
80027d6: 210f movs r1, #15
|
||
|
|
80027d8: 438a bics r2, r1
|
||
|
|
80027da: 801a strh r2, [r3, #0]
|
||
|
|
brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000FU) >> 1U);
|
||
|
|
80027dc: 6abb ldr r3, [r7, #40] ; 0x28
|
||
|
|
80027de: 085b lsrs r3, r3, #1
|
||
|
|
80027e0: b29b uxth r3, r3
|
||
|
|
80027e2: 2207 movs r2, #7
|
||
|
|
80027e4: 4013 ands r3, r2
|
||
|
|
80027e6: b299 uxth r1, r3
|
||
|
|
80027e8: 230e movs r3, #14
|
||
|
|
80027ea: 2218 movs r2, #24
|
||
|
|
80027ec: 4694 mov ip, r2
|
||
|
|
80027ee: 44bc add ip, r7
|
||
|
|
80027f0: 4463 add r3, ip
|
||
|
|
80027f2: 220e movs r2, #14
|
||
|
|
80027f4: 2018 movs r0, #24
|
||
|
|
80027f6: 4684 mov ip, r0
|
||
|
|
80027f8: 44bc add ip, r7
|
||
|
|
80027fa: 4462 add r2, ip
|
||
|
|
80027fc: 8812 ldrh r2, [r2, #0]
|
||
|
|
80027fe: 430a orrs r2, r1
|
||
|
|
8002800: 801a strh r2, [r3, #0]
|
||
|
|
huart->Instance->BRR = brrtemp;
|
||
|
|
8002802: 69fb ldr r3, [r7, #28]
|
||
|
|
8002804: 681b ldr r3, [r3, #0]
|
||
|
|
8002806: 220e movs r2, #14
|
||
|
|
8002808: 2118 movs r1, #24
|
||
|
|
800280a: 468c mov ip, r1
|
||
|
|
800280c: 44bc add ip, r7
|
||
|
|
800280e: 4462 add r2, ip
|
||
|
|
8002810: 8812 ldrh r2, [r2, #0]
|
||
|
|
8002812: 60da str r2, [r3, #12]
|
||
|
|
8002814: e060 b.n 80028d8 <UART_SetConfig+0x54c>
|
||
|
|
}
|
||
|
|
else
|
||
|
|
{
|
||
|
|
ret = HAL_ERROR;
|
||
|
|
8002816: 231a movs r3, #26
|
||
|
|
8002818: 2218 movs r2, #24
|
||
|
|
800281a: 4694 mov ip, r2
|
||
|
|
800281c: 44bc add ip, r7
|
||
|
|
800281e: 4463 add r3, ip
|
||
|
|
8002820: 2201 movs r2, #1
|
||
|
|
8002822: 701a strb r2, [r3, #0]
|
||
|
|
8002824: e058 b.n 80028d8 <UART_SetConfig+0x54c>
|
||
|
|
}
|
||
|
|
}
|
||
|
|
}
|
||
|
|
else
|
||
|
|
{
|
||
|
|
switch (clocksource)
|
||
|
|
8002826: 231b movs r3, #27
|
||
|
|
8002828: 2218 movs r2, #24
|
||
|
|
800282a: 4694 mov ip, r2
|
||
|
|
800282c: 44bc add ip, r7
|
||
|
|
800282e: 4463 add r3, ip
|
||
|
|
8002830: 781b ldrb r3, [r3, #0]
|
||
|
|
8002832: 2b08 cmp r3, #8
|
||
|
|
8002834: d822 bhi.n 800287c <UART_SetConfig+0x4f0>
|
||
|
|
8002836: 009a lsls r2, r3, #2
|
||
|
|
8002838: 4b34 ldr r3, [pc, #208] ; (800290c <UART_SetConfig+0x580>)
|
||
|
|
800283a: 18d3 adds r3, r2, r3
|
||
|
|
800283c: 681b ldr r3, [r3, #0]
|
||
|
|
800283e: 469f mov pc, r3
|
||
|
|
{
|
||
|
|
case UART_CLOCKSOURCE_PCLK1:
|
||
|
|
pclk = HAL_RCC_GetPCLK1Freq();
|
||
|
|
8002840: f7ff f9aa bl 8001b98 <HAL_RCC_GetPCLK1Freq>
|
||
|
|
8002844: 0003 movs r3, r0
|
||
|
|
8002846: 62fb str r3, [r7, #44] ; 0x2c
|
||
|
|
break;
|
||
|
|
8002848: e022 b.n 8002890 <UART_SetConfig+0x504>
|
||
|
|
case UART_CLOCKSOURCE_PCLK2:
|
||
|
|
pclk = HAL_RCC_GetPCLK2Freq();
|
||
|
|
800284a: f7ff f9bb bl 8001bc4 <HAL_RCC_GetPCLK2Freq>
|
||
|
|
800284e: 0003 movs r3, r0
|
||
|
|
8002850: 62fb str r3, [r7, #44] ; 0x2c
|
||
|
|
break;
|
||
|
|
8002852: e01d b.n 8002890 <UART_SetConfig+0x504>
|
||
|
|
case UART_CLOCKSOURCE_HSI:
|
||
|
|
if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U)
|
||
|
|
8002854: 4b29 ldr r3, [pc, #164] ; (80028fc <UART_SetConfig+0x570>)
|
||
|
|
8002856: 681b ldr r3, [r3, #0]
|
||
|
|
8002858: 2210 movs r2, #16
|
||
|
|
800285a: 4013 ands r3, r2
|
||
|
|
800285c: d002 beq.n 8002864 <UART_SetConfig+0x4d8>
|
||
|
|
{
|
||
|
|
pclk = (uint32_t)(HSI_VALUE >> 2U);
|
||
|
|
800285e: 4b28 ldr r3, [pc, #160] ; (8002900 <UART_SetConfig+0x574>)
|
||
|
|
8002860: 62fb str r3, [r7, #44] ; 0x2c
|
||
|
|
}
|
||
|
|
else
|
||
|
|
{
|
||
|
|
pclk = (uint32_t) HSI_VALUE;
|
||
|
|
}
|
||
|
|
break;
|
||
|
|
8002862: e015 b.n 8002890 <UART_SetConfig+0x504>
|
||
|
|
pclk = (uint32_t) HSI_VALUE;
|
||
|
|
8002864: 4b27 ldr r3, [pc, #156] ; (8002904 <UART_SetConfig+0x578>)
|
||
|
|
8002866: 62fb str r3, [r7, #44] ; 0x2c
|
||
|
|
break;
|
||
|
|
8002868: e012 b.n 8002890 <UART_SetConfig+0x504>
|
||
|
|
case UART_CLOCKSOURCE_SYSCLK:
|
||
|
|
pclk = HAL_RCC_GetSysClockFreq();
|
||
|
|
800286a: f7ff f8e9 bl 8001a40 <HAL_RCC_GetSysClockFreq>
|
||
|
|
800286e: 0003 movs r3, r0
|
||
|
|
8002870: 62fb str r3, [r7, #44] ; 0x2c
|
||
|
|
break;
|
||
|
|
8002872: e00d b.n 8002890 <UART_SetConfig+0x504>
|
||
|
|
case UART_CLOCKSOURCE_LSE:
|
||
|
|
pclk = (uint32_t) LSE_VALUE;
|
||
|
|
8002874: 2380 movs r3, #128 ; 0x80
|
||
|
|
8002876: 021b lsls r3, r3, #8
|
||
|
|
8002878: 62fb str r3, [r7, #44] ; 0x2c
|
||
|
|
break;
|
||
|
|
800287a: e009 b.n 8002890 <UART_SetConfig+0x504>
|
||
|
|
default:
|
||
|
|
pclk = 0U;
|
||
|
|
800287c: 2300 movs r3, #0
|
||
|
|
800287e: 62fb str r3, [r7, #44] ; 0x2c
|
||
|
|
ret = HAL_ERROR;
|
||
|
|
8002880: 231a movs r3, #26
|
||
|
|
8002882: 2218 movs r2, #24
|
||
|
|
8002884: 4694 mov ip, r2
|
||
|
|
8002886: 44bc add ip, r7
|
||
|
|
8002888: 4463 add r3, ip
|
||
|
|
800288a: 2201 movs r2, #1
|
||
|
|
800288c: 701a strb r2, [r3, #0]
|
||
|
|
break;
|
||
|
|
800288e: 46c0 nop ; (mov r8, r8)
|
||
|
|
}
|
||
|
|
|
||
|
|
if (pclk != 0U)
|
||
|
|
8002890: 6afb ldr r3, [r7, #44] ; 0x2c
|
||
|
|
8002892: 2b00 cmp r3, #0
|
||
|
|
8002894: d020 beq.n 80028d8 <UART_SetConfig+0x54c>
|
||
|
|
{
|
||
|
|
/* USARTDIV must be greater than or equal to 0d16 */
|
||
|
|
usartdiv = (uint16_t)(UART_DIV_SAMPLING16(pclk, huart->Init.BaudRate));
|
||
|
|
8002896: 69fb ldr r3, [r7, #28]
|
||
|
|
8002898: 685b ldr r3, [r3, #4]
|
||
|
|
800289a: 085a lsrs r2, r3, #1
|
||
|
|
800289c: 6afb ldr r3, [r7, #44] ; 0x2c
|
||
|
|
800289e: 18d2 adds r2, r2, r3
|
||
|
|
80028a0: 69fb ldr r3, [r7, #28]
|
||
|
|
80028a2: 685b ldr r3, [r3, #4]
|
||
|
|
80028a4: 0019 movs r1, r3
|
||
|
|
80028a6: 0010 movs r0, r2
|
||
|
|
80028a8: f7fd fc2e bl 8000108 <__udivsi3>
|
||
|
|
80028ac: 0003 movs r3, r0
|
||
|
|
80028ae: b29b uxth r3, r3
|
||
|
|
80028b0: 62bb str r3, [r7, #40] ; 0x28
|
||
|
|
if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX))
|
||
|
|
80028b2: 6abb ldr r3, [r7, #40] ; 0x28
|
||
|
|
80028b4: 2b0f cmp r3, #15
|
||
|
|
80028b6: d908 bls.n 80028ca <UART_SetConfig+0x53e>
|
||
|
|
80028b8: 6abb ldr r3, [r7, #40] ; 0x28
|
||
|
|
80028ba: 4a13 ldr r2, [pc, #76] ; (8002908 <UART_SetConfig+0x57c>)
|
||
|
|
80028bc: 4293 cmp r3, r2
|
||
|
|
80028be: d804 bhi.n 80028ca <UART_SetConfig+0x53e>
|
||
|
|
{
|
||
|
|
huart->Instance->BRR = usartdiv;
|
||
|
|
80028c0: 69fb ldr r3, [r7, #28]
|
||
|
|
80028c2: 681b ldr r3, [r3, #0]
|
||
|
|
80028c4: 6aba ldr r2, [r7, #40] ; 0x28
|
||
|
|
80028c6: 60da str r2, [r3, #12]
|
||
|
|
80028c8: e006 b.n 80028d8 <UART_SetConfig+0x54c>
|
||
|
|
}
|
||
|
|
else
|
||
|
|
{
|
||
|
|
ret = HAL_ERROR;
|
||
|
|
80028ca: 231a movs r3, #26
|
||
|
|
80028cc: 2218 movs r2, #24
|
||
|
|
80028ce: 4694 mov ip, r2
|
||
|
|
80028d0: 44bc add ip, r7
|
||
|
|
80028d2: 4463 add r3, ip
|
||
|
|
80028d4: 2201 movs r2, #1
|
||
|
|
80028d6: 701a strb r2, [r3, #0]
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
|
||
|
|
/* Clear ISR function pointers */
|
||
|
|
huart->RxISR = NULL;
|
||
|
|
80028d8: 69fb ldr r3, [r7, #28]
|
||
|
|
80028da: 2200 movs r2, #0
|
||
|
|
80028dc: 665a str r2, [r3, #100] ; 0x64
|
||
|
|
huart->TxISR = NULL;
|
||
|
|
80028de: 69fb ldr r3, [r7, #28]
|
||
|
|
80028e0: 2200 movs r2, #0
|
||
|
|
80028e2: 669a str r2, [r3, #104] ; 0x68
|
||
|
|
|
||
|
|
return ret;
|
||
|
|
80028e4: 231a movs r3, #26
|
||
|
|
80028e6: 2218 movs r2, #24
|
||
|
|
80028e8: 4694 mov ip, r2
|
||
|
|
80028ea: 44bc add ip, r7
|
||
|
|
80028ec: 4463 add r3, ip
|
||
|
|
80028ee: 781b ldrb r3, [r3, #0]
|
||
|
|
}
|
||
|
|
80028f0: 0018 movs r0, r3
|
||
|
|
80028f2: 46bd mov sp, r7
|
||
|
|
80028f4: b00e add sp, #56 ; 0x38
|
||
|
|
80028f6: bdb0 pop {r4, r5, r7, pc}
|
||
|
|
80028f8: 08002db4 .word 0x08002db4
|
||
|
|
80028fc: 40021000 .word 0x40021000
|
||
|
|
8002900: 003d0900 .word 0x003d0900
|
||
|
|
8002904: 00f42400 .word 0x00f42400
|
||
|
|
8002908: 0000ffff .word 0x0000ffff
|
||
|
|
800290c: 08002dd8 .word 0x08002dd8
|
||
|
|
|
||
|
|
08002910 <UART_AdvFeatureConfig>:
|
||
|
|
* @brief Configure the UART peripheral advanced features.
|
||
|
|
* @param huart UART handle.
|
||
|
|
* @retval None
|
||
|
|
*/
|
||
|
|
void UART_AdvFeatureConfig(UART_HandleTypeDef *huart)
|
||
|
|
{
|
||
|
|
8002910: b580 push {r7, lr}
|
||
|
|
8002912: b082 sub sp, #8
|
||
|
|
8002914: af00 add r7, sp, #0
|
||
|
|
8002916: 6078 str r0, [r7, #4]
|
||
|
|
/* Check whether the set of advanced features to configure is properly set */
|
||
|
|
assert_param(IS_UART_ADVFEATURE_INIT(huart->AdvancedInit.AdvFeatureInit));
|
||
|
|
|
||
|
|
/* if required, configure TX pin active level inversion */
|
||
|
|
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_TXINVERT_INIT))
|
||
|
|
8002918: 687b ldr r3, [r7, #4]
|
||
|
|
800291a: 6a5b ldr r3, [r3, #36] ; 0x24
|
||
|
|
800291c: 2201 movs r2, #1
|
||
|
|
800291e: 4013 ands r3, r2
|
||
|
|
8002920: d00a beq.n 8002938 <UART_AdvFeatureConfig+0x28>
|
||
|
|
{
|
||
|
|
assert_param(IS_UART_ADVFEATURE_TXINV(huart->AdvancedInit.TxPinLevelInvert));
|
||
|
|
MODIFY_REG(huart->Instance->CR2, USART_CR2_TXINV, huart->AdvancedInit.TxPinLevelInvert);
|
||
|
|
8002922: 687b ldr r3, [r7, #4]
|
||
|
|
8002924: 681b ldr r3, [r3, #0]
|
||
|
|
8002926: 687a ldr r2, [r7, #4]
|
||
|
|
8002928: 6812 ldr r2, [r2, #0]
|
||
|
|
800292a: 6852 ldr r2, [r2, #4]
|
||
|
|
800292c: 4945 ldr r1, [pc, #276] ; (8002a44 <UART_AdvFeatureConfig+0x134>)
|
||
|
|
800292e: 4011 ands r1, r2
|
||
|
|
8002930: 687a ldr r2, [r7, #4]
|
||
|
|
8002932: 6a92 ldr r2, [r2, #40] ; 0x28
|
||
|
|
8002934: 430a orrs r2, r1
|
||
|
|
8002936: 605a str r2, [r3, #4]
|
||
|
|
}
|
||
|
|
|
||
|
|
/* if required, configure RX pin active level inversion */
|
||
|
|
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXINVERT_INIT))
|
||
|
|
8002938: 687b ldr r3, [r7, #4]
|
||
|
|
800293a: 6a5b ldr r3, [r3, #36] ; 0x24
|
||
|
|
800293c: 2202 movs r2, #2
|
||
|
|
800293e: 4013 ands r3, r2
|
||
|
|
8002940: d00a beq.n 8002958 <UART_AdvFeatureConfig+0x48>
|
||
|
|
{
|
||
|
|
assert_param(IS_UART_ADVFEATURE_RXINV(huart->AdvancedInit.RxPinLevelInvert));
|
||
|
|
MODIFY_REG(huart->Instance->CR2, USART_CR2_RXINV, huart->AdvancedInit.RxPinLevelInvert);
|
||
|
|
8002942: 687b ldr r3, [r7, #4]
|
||
|
|
8002944: 681b ldr r3, [r3, #0]
|
||
|
|
8002946: 687a ldr r2, [r7, #4]
|
||
|
|
8002948: 6812 ldr r2, [r2, #0]
|
||
|
|
800294a: 6852 ldr r2, [r2, #4]
|
||
|
|
800294c: 493e ldr r1, [pc, #248] ; (8002a48 <UART_AdvFeatureConfig+0x138>)
|
||
|
|
800294e: 4011 ands r1, r2
|
||
|
|
8002950: 687a ldr r2, [r7, #4]
|
||
|
|
8002952: 6ad2 ldr r2, [r2, #44] ; 0x2c
|
||
|
|
8002954: 430a orrs r2, r1
|
||
|
|
8002956: 605a str r2, [r3, #4]
|
||
|
|
}
|
||
|
|
|
||
|
|
/* if required, configure data inversion */
|
||
|
|
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DATAINVERT_INIT))
|
||
|
|
8002958: 687b ldr r3, [r7, #4]
|
||
|
|
800295a: 6a5b ldr r3, [r3, #36] ; 0x24
|
||
|
|
800295c: 2204 movs r2, #4
|
||
|
|
800295e: 4013 ands r3, r2
|
||
|
|
8002960: d00a beq.n 8002978 <UART_AdvFeatureConfig+0x68>
|
||
|
|
{
|
||
|
|
assert_param(IS_UART_ADVFEATURE_DATAINV(huart->AdvancedInit.DataInvert));
|
||
|
|
MODIFY_REG(huart->Instance->CR2, USART_CR2_DATAINV, huart->AdvancedInit.DataInvert);
|
||
|
|
8002962: 687b ldr r3, [r7, #4]
|
||
|
|
8002964: 681b ldr r3, [r3, #0]
|
||
|
|
8002966: 687a ldr r2, [r7, #4]
|
||
|
|
8002968: 6812 ldr r2, [r2, #0]
|
||
|
|
800296a: 6852 ldr r2, [r2, #4]
|
||
|
|
800296c: 4937 ldr r1, [pc, #220] ; (8002a4c <UART_AdvFeatureConfig+0x13c>)
|
||
|
|
800296e: 4011 ands r1, r2
|
||
|
|
8002970: 687a ldr r2, [r7, #4]
|
||
|
|
8002972: 6b12 ldr r2, [r2, #48] ; 0x30
|
||
|
|
8002974: 430a orrs r2, r1
|
||
|
|
8002976: 605a str r2, [r3, #4]
|
||
|
|
}
|
||
|
|
|
||
|
|
/* if required, configure RX/TX pins swap */
|
||
|
|
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_SWAP_INIT))
|
||
|
|
8002978: 687b ldr r3, [r7, #4]
|
||
|
|
800297a: 6a5b ldr r3, [r3, #36] ; 0x24
|
||
|
|
800297c: 2208 movs r2, #8
|
||
|
|
800297e: 4013 ands r3, r2
|
||
|
|
8002980: d00a beq.n 8002998 <UART_AdvFeatureConfig+0x88>
|
||
|
|
{
|
||
|
|
assert_param(IS_UART_ADVFEATURE_SWAP(huart->AdvancedInit.Swap));
|
||
|
|
MODIFY_REG(huart->Instance->CR2, USART_CR2_SWAP, huart->AdvancedInit.Swap);
|
||
|
|
8002982: 687b ldr r3, [r7, #4]
|
||
|
|
8002984: 681b ldr r3, [r3, #0]
|
||
|
|
8002986: 687a ldr r2, [r7, #4]
|
||
|
|
8002988: 6812 ldr r2, [r2, #0]
|
||
|
|
800298a: 6852 ldr r2, [r2, #4]
|
||
|
|
800298c: 4930 ldr r1, [pc, #192] ; (8002a50 <UART_AdvFeatureConfig+0x140>)
|
||
|
|
800298e: 4011 ands r1, r2
|
||
|
|
8002990: 687a ldr r2, [r7, #4]
|
||
|
|
8002992: 6b52 ldr r2, [r2, #52] ; 0x34
|
||
|
|
8002994: 430a orrs r2, r1
|
||
|
|
8002996: 605a str r2, [r3, #4]
|
||
|
|
}
|
||
|
|
|
||
|
|
/* if required, configure RX overrun detection disabling */
|
||
|
|
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXOVERRUNDISABLE_INIT))
|
||
|
|
8002998: 687b ldr r3, [r7, #4]
|
||
|
|
800299a: 6a5b ldr r3, [r3, #36] ; 0x24
|
||
|
|
800299c: 2210 movs r2, #16
|
||
|
|
800299e: 4013 ands r3, r2
|
||
|
|
80029a0: d00a beq.n 80029b8 <UART_AdvFeatureConfig+0xa8>
|
||
|
|
{
|
||
|
|
assert_param(IS_UART_OVERRUN(huart->AdvancedInit.OverrunDisable));
|
||
|
|
MODIFY_REG(huart->Instance->CR3, USART_CR3_OVRDIS, huart->AdvancedInit.OverrunDisable);
|
||
|
|
80029a2: 687b ldr r3, [r7, #4]
|
||
|
|
80029a4: 681b ldr r3, [r3, #0]
|
||
|
|
80029a6: 687a ldr r2, [r7, #4]
|
||
|
|
80029a8: 6812 ldr r2, [r2, #0]
|
||
|
|
80029aa: 6892 ldr r2, [r2, #8]
|
||
|
|
80029ac: 4929 ldr r1, [pc, #164] ; (8002a54 <UART_AdvFeatureConfig+0x144>)
|
||
|
|
80029ae: 4011 ands r1, r2
|
||
|
|
80029b0: 687a ldr r2, [r7, #4]
|
||
|
|
80029b2: 6b92 ldr r2, [r2, #56] ; 0x38
|
||
|
|
80029b4: 430a orrs r2, r1
|
||
|
|
80029b6: 609a str r2, [r3, #8]
|
||
|
|
}
|
||
|
|
|
||
|
|
/* if required, configure DMA disabling on reception error */
|
||
|
|
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DMADISABLEONERROR_INIT))
|
||
|
|
80029b8: 687b ldr r3, [r7, #4]
|
||
|
|
80029ba: 6a5b ldr r3, [r3, #36] ; 0x24
|
||
|
|
80029bc: 2220 movs r2, #32
|
||
|
|
80029be: 4013 ands r3, r2
|
||
|
|
80029c0: d00a beq.n 80029d8 <UART_AdvFeatureConfig+0xc8>
|
||
|
|
{
|
||
|
|
assert_param(IS_UART_ADVFEATURE_DMAONRXERROR(huart->AdvancedInit.DMADisableonRxError));
|
||
|
|
MODIFY_REG(huart->Instance->CR3, USART_CR3_DDRE, huart->AdvancedInit.DMADisableonRxError);
|
||
|
|
80029c2: 687b ldr r3, [r7, #4]
|
||
|
|
80029c4: 681b ldr r3, [r3, #0]
|
||
|
|
80029c6: 687a ldr r2, [r7, #4]
|
||
|
|
80029c8: 6812 ldr r2, [r2, #0]
|
||
|
|
80029ca: 6892 ldr r2, [r2, #8]
|
||
|
|
80029cc: 4922 ldr r1, [pc, #136] ; (8002a58 <UART_AdvFeatureConfig+0x148>)
|
||
|
|
80029ce: 4011 ands r1, r2
|
||
|
|
80029d0: 687a ldr r2, [r7, #4]
|
||
|
|
80029d2: 6bd2 ldr r2, [r2, #60] ; 0x3c
|
||
|
|
80029d4: 430a orrs r2, r1
|
||
|
|
80029d6: 609a str r2, [r3, #8]
|
||
|
|
}
|
||
|
|
|
||
|
|
/* if required, configure auto Baud rate detection scheme */
|
||
|
|
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_AUTOBAUDRATE_INIT))
|
||
|
|
80029d8: 687b ldr r3, [r7, #4]
|
||
|
|
80029da: 6a5b ldr r3, [r3, #36] ; 0x24
|
||
|
|
80029dc: 2240 movs r2, #64 ; 0x40
|
||
|
|
80029de: 4013 ands r3, r2
|
||
|
|
80029e0: d01b beq.n 8002a1a <UART_AdvFeatureConfig+0x10a>
|
||
|
|
{
|
||
|
|
assert_param(IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(huart->Instance));
|
||
|
|
assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATE(huart->AdvancedInit.AutoBaudRateEnable));
|
||
|
|
MODIFY_REG(huart->Instance->CR2, USART_CR2_ABREN, huart->AdvancedInit.AutoBaudRateEnable);
|
||
|
|
80029e2: 687b ldr r3, [r7, #4]
|
||
|
|
80029e4: 681b ldr r3, [r3, #0]
|
||
|
|
80029e6: 687a ldr r2, [r7, #4]
|
||
|
|
80029e8: 6812 ldr r2, [r2, #0]
|
||
|
|
80029ea: 6852 ldr r2, [r2, #4]
|
||
|
|
80029ec: 491b ldr r1, [pc, #108] ; (8002a5c <UART_AdvFeatureConfig+0x14c>)
|
||
|
|
80029ee: 4011 ands r1, r2
|
||
|
|
80029f0: 687a ldr r2, [r7, #4]
|
||
|
|
80029f2: 6c12 ldr r2, [r2, #64] ; 0x40
|
||
|
|
80029f4: 430a orrs r2, r1
|
||
|
|
80029f6: 605a str r2, [r3, #4]
|
||
|
|
/* set auto Baudrate detection parameters if detection is enabled */
|
||
|
|
if (huart->AdvancedInit.AutoBaudRateEnable == UART_ADVFEATURE_AUTOBAUDRATE_ENABLE)
|
||
|
|
80029f8: 687b ldr r3, [r7, #4]
|
||
|
|
80029fa: 6c1a ldr r2, [r3, #64] ; 0x40
|
||
|
|
80029fc: 2380 movs r3, #128 ; 0x80
|
||
|
|
80029fe: 035b lsls r3, r3, #13
|
||
|
|
8002a00: 429a cmp r2, r3
|
||
|
|
8002a02: d10a bne.n 8002a1a <UART_AdvFeatureConfig+0x10a>
|
||
|
|
{
|
||
|
|
assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATEMODE(huart->AdvancedInit.AutoBaudRateMode));
|
||
|
|
MODIFY_REG(huart->Instance->CR2, USART_CR2_ABRMODE, huart->AdvancedInit.AutoBaudRateMode);
|
||
|
|
8002a04: 687b ldr r3, [r7, #4]
|
||
|
|
8002a06: 681b ldr r3, [r3, #0]
|
||
|
|
8002a08: 687a ldr r2, [r7, #4]
|
||
|
|
8002a0a: 6812 ldr r2, [r2, #0]
|
||
|
|
8002a0c: 6852 ldr r2, [r2, #4]
|
||
|
|
8002a0e: 4914 ldr r1, [pc, #80] ; (8002a60 <UART_AdvFeatureConfig+0x150>)
|
||
|
|
8002a10: 4011 ands r1, r2
|
||
|
|
8002a12: 687a ldr r2, [r7, #4]
|
||
|
|
8002a14: 6c52 ldr r2, [r2, #68] ; 0x44
|
||
|
|
8002a16: 430a orrs r2, r1
|
||
|
|
8002a18: 605a str r2, [r3, #4]
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
/* if required, configure MSB first on communication line */
|
||
|
|
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_MSBFIRST_INIT))
|
||
|
|
8002a1a: 687b ldr r3, [r7, #4]
|
||
|
|
8002a1c: 6a5b ldr r3, [r3, #36] ; 0x24
|
||
|
|
8002a1e: 2280 movs r2, #128 ; 0x80
|
||
|
|
8002a20: 4013 ands r3, r2
|
||
|
|
8002a22: d00a beq.n 8002a3a <UART_AdvFeatureConfig+0x12a>
|
||
|
|
{
|
||
|
|
assert_param(IS_UART_ADVFEATURE_MSBFIRST(huart->AdvancedInit.MSBFirst));
|
||
|
|
MODIFY_REG(huart->Instance->CR2, USART_CR2_MSBFIRST, huart->AdvancedInit.MSBFirst);
|
||
|
|
8002a24: 687b ldr r3, [r7, #4]
|
||
|
|
8002a26: 681b ldr r3, [r3, #0]
|
||
|
|
8002a28: 687a ldr r2, [r7, #4]
|
||
|
|
8002a2a: 6812 ldr r2, [r2, #0]
|
||
|
|
8002a2c: 6852 ldr r2, [r2, #4]
|
||
|
|
8002a2e: 490d ldr r1, [pc, #52] ; (8002a64 <UART_AdvFeatureConfig+0x154>)
|
||
|
|
8002a30: 4011 ands r1, r2
|
||
|
|
8002a32: 687a ldr r2, [r7, #4]
|
||
|
|
8002a34: 6c92 ldr r2, [r2, #72] ; 0x48
|
||
|
|
8002a36: 430a orrs r2, r1
|
||
|
|
8002a38: 605a str r2, [r3, #4]
|
||
|
|
}
|
||
|
|
}
|
||
|
|
8002a3a: 46c0 nop ; (mov r8, r8)
|
||
|
|
8002a3c: 46bd mov sp, r7
|
||
|
|
8002a3e: b002 add sp, #8
|
||
|
|
8002a40: bd80 pop {r7, pc}
|
||
|
|
8002a42: 46c0 nop ; (mov r8, r8)
|
||
|
|
8002a44: fffdffff .word 0xfffdffff
|
||
|
|
8002a48: fffeffff .word 0xfffeffff
|
||
|
|
8002a4c: fffbffff .word 0xfffbffff
|
||
|
|
8002a50: ffff7fff .word 0xffff7fff
|
||
|
|
8002a54: ffffefff .word 0xffffefff
|
||
|
|
8002a58: ffffdfff .word 0xffffdfff
|
||
|
|
8002a5c: ffefffff .word 0xffefffff
|
||
|
|
8002a60: ff9fffff .word 0xff9fffff
|
||
|
|
8002a64: fff7ffff .word 0xfff7ffff
|
||
|
|
|
||
|
|
08002a68 <UART_CheckIdleState>:
|
||
|
|
* @brief Check the UART Idle State.
|
||
|
|
* @param huart UART handle.
|
||
|
|
* @retval HAL status
|
||
|
|
*/
|
||
|
|
HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart)
|
||
|
|
{
|
||
|
|
8002a68: b580 push {r7, lr}
|
||
|
|
8002a6a: b086 sub sp, #24
|
||
|
|
8002a6c: af02 add r7, sp, #8
|
||
|
|
8002a6e: 6078 str r0, [r7, #4]
|
||
|
|
uint32_t tickstart;
|
||
|
|
|
||
|
|
/* Initialize the UART ErrorCode */
|
||
|
|
huart->ErrorCode = HAL_UART_ERROR_NONE;
|
||
|
|
8002a70: 687b ldr r3, [r7, #4]
|
||
|
|
8002a72: 2280 movs r2, #128 ; 0x80
|
||
|
|
8002a74: 2100 movs r1, #0
|
||
|
|
8002a76: 5099 str r1, [r3, r2]
|
||
|
|
|
||
|
|
/* Init tickstart for timeout management */
|
||
|
|
tickstart = HAL_GetTick();
|
||
|
|
8002a78: f7fd ff94 bl 80009a4 <HAL_GetTick>
|
||
|
|
8002a7c: 0003 movs r3, r0
|
||
|
|
8002a7e: 60fb str r3, [r7, #12]
|
||
|
|
|
||
|
|
/* Check if the Transmitter is enabled */
|
||
|
|
if ((huart->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE)
|
||
|
|
8002a80: 687b ldr r3, [r7, #4]
|
||
|
|
8002a82: 681b ldr r3, [r3, #0]
|
||
|
|
8002a84: 681b ldr r3, [r3, #0]
|
||
|
|
8002a86: 2208 movs r2, #8
|
||
|
|
8002a88: 4013 ands r3, r2
|
||
|
|
8002a8a: 2b08 cmp r3, #8
|
||
|
|
8002a8c: d10d bne.n 8002aaa <UART_CheckIdleState+0x42>
|
||
|
|
{
|
||
|
|
/* Wait until TEACK flag is set */
|
||
|
|
if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_TEACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK)
|
||
|
|
8002a8e: 68fa ldr r2, [r7, #12]
|
||
|
|
8002a90: 2380 movs r3, #128 ; 0x80
|
||
|
|
8002a92: 0399 lsls r1, r3, #14
|
||
|
|
8002a94: 6878 ldr r0, [r7, #4]
|
||
|
|
8002a96: 4b18 ldr r3, [pc, #96] ; (8002af8 <UART_CheckIdleState+0x90>)
|
||
|
|
8002a98: 9300 str r3, [sp, #0]
|
||
|
|
8002a9a: 0013 movs r3, r2
|
||
|
|
8002a9c: 2200 movs r2, #0
|
||
|
|
8002a9e: f000 f82d bl 8002afc <UART_WaitOnFlagUntilTimeout>
|
||
|
|
8002aa2: 1e03 subs r3, r0, #0
|
||
|
|
8002aa4: d001 beq.n 8002aaa <UART_CheckIdleState+0x42>
|
||
|
|
{
|
||
|
|
/* Timeout occurred */
|
||
|
|
return HAL_TIMEOUT;
|
||
|
|
8002aa6: 2303 movs r3, #3
|
||
|
|
8002aa8: e022 b.n 8002af0 <UART_CheckIdleState+0x88>
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
/* Check if the Receiver is enabled */
|
||
|
|
if ((huart->Instance->CR1 & USART_CR1_RE) == USART_CR1_RE)
|
||
|
|
8002aaa: 687b ldr r3, [r7, #4]
|
||
|
|
8002aac: 681b ldr r3, [r3, #0]
|
||
|
|
8002aae: 681b ldr r3, [r3, #0]
|
||
|
|
8002ab0: 2204 movs r2, #4
|
||
|
|
8002ab2: 4013 ands r3, r2
|
||
|
|
8002ab4: 2b04 cmp r3, #4
|
||
|
|
8002ab6: d10d bne.n 8002ad4 <UART_CheckIdleState+0x6c>
|
||
|
|
{
|
||
|
|
/* Wait until REACK flag is set */
|
||
|
|
if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_REACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK)
|
||
|
|
8002ab8: 68fa ldr r2, [r7, #12]
|
||
|
|
8002aba: 2380 movs r3, #128 ; 0x80
|
||
|
|
8002abc: 03d9 lsls r1, r3, #15
|
||
|
|
8002abe: 6878 ldr r0, [r7, #4]
|
||
|
|
8002ac0: 4b0d ldr r3, [pc, #52] ; (8002af8 <UART_CheckIdleState+0x90>)
|
||
|
|
8002ac2: 9300 str r3, [sp, #0]
|
||
|
|
8002ac4: 0013 movs r3, r2
|
||
|
|
8002ac6: 2200 movs r2, #0
|
||
|
|
8002ac8: f000 f818 bl 8002afc <UART_WaitOnFlagUntilTimeout>
|
||
|
|
8002acc: 1e03 subs r3, r0, #0
|
||
|
|
8002ace: d001 beq.n 8002ad4 <UART_CheckIdleState+0x6c>
|
||
|
|
{
|
||
|
|
/* Timeout occurred */
|
||
|
|
return HAL_TIMEOUT;
|
||
|
|
8002ad0: 2303 movs r3, #3
|
||
|
|
8002ad2: e00d b.n 8002af0 <UART_CheckIdleState+0x88>
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
/* Initialize the UART State */
|
||
|
|
huart->gState = HAL_UART_STATE_READY;
|
||
|
|
8002ad4: 687b ldr r3, [r7, #4]
|
||
|
|
8002ad6: 2220 movs r2, #32
|
||
|
|
8002ad8: 679a str r2, [r3, #120] ; 0x78
|
||
|
|
huart->RxState = HAL_UART_STATE_READY;
|
||
|
|
8002ada: 687b ldr r3, [r7, #4]
|
||
|
|
8002adc: 2220 movs r2, #32
|
||
|
|
8002ade: 67da str r2, [r3, #124] ; 0x7c
|
||
|
|
huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
|
||
|
|
8002ae0: 687b ldr r3, [r7, #4]
|
||
|
|
8002ae2: 2200 movs r2, #0
|
||
|
|
8002ae4: 661a str r2, [r3, #96] ; 0x60
|
||
|
|
|
||
|
|
__HAL_UNLOCK(huart);
|
||
|
|
8002ae6: 687b ldr r3, [r7, #4]
|
||
|
|
8002ae8: 2274 movs r2, #116 ; 0x74
|
||
|
|
8002aea: 2100 movs r1, #0
|
||
|
|
8002aec: 5499 strb r1, [r3, r2]
|
||
|
|
|
||
|
|
return HAL_OK;
|
||
|
|
8002aee: 2300 movs r3, #0
|
||
|
|
}
|
||
|
|
8002af0: 0018 movs r0, r3
|
||
|
|
8002af2: 46bd mov sp, r7
|
||
|
|
8002af4: b004 add sp, #16
|
||
|
|
8002af6: bd80 pop {r7, pc}
|
||
|
|
8002af8: 01ffffff .word 0x01ffffff
|
||
|
|
|
||
|
|
08002afc <UART_WaitOnFlagUntilTimeout>:
|
||
|
|
* @param Timeout Timeout duration
|
||
|
|
* @retval HAL status
|
||
|
|
*/
|
||
|
|
HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status,
|
||
|
|
uint32_t Tickstart, uint32_t Timeout)
|
||
|
|
{
|
||
|
|
8002afc: b580 push {r7, lr}
|
||
|
|
8002afe: b084 sub sp, #16
|
||
|
|
8002b00: af00 add r7, sp, #0
|
||
|
|
8002b02: 60f8 str r0, [r7, #12]
|
||
|
|
8002b04: 60b9 str r1, [r7, #8]
|
||
|
|
8002b06: 603b str r3, [r7, #0]
|
||
|
|
8002b08: 1dfb adds r3, r7, #7
|
||
|
|
8002b0a: 701a strb r2, [r3, #0]
|
||
|
|
/* Wait until flag is set */
|
||
|
|
while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status)
|
||
|
|
8002b0c: e05e b.n 8002bcc <UART_WaitOnFlagUntilTimeout+0xd0>
|
||
|
|
{
|
||
|
|
/* Check for the Timeout */
|
||
|
|
if (Timeout != HAL_MAX_DELAY)
|
||
|
|
8002b0e: 69bb ldr r3, [r7, #24]
|
||
|
|
8002b10: 3301 adds r3, #1
|
||
|
|
8002b12: d05b beq.n 8002bcc <UART_WaitOnFlagUntilTimeout+0xd0>
|
||
|
|
{
|
||
|
|
if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
|
||
|
|
8002b14: f7fd ff46 bl 80009a4 <HAL_GetTick>
|
||
|
|
8002b18: 0002 movs r2, r0
|
||
|
|
8002b1a: 683b ldr r3, [r7, #0]
|
||
|
|
8002b1c: 1ad2 subs r2, r2, r3
|
||
|
|
8002b1e: 69bb ldr r3, [r7, #24]
|
||
|
|
8002b20: 429a cmp r2, r3
|
||
|
|
8002b22: d802 bhi.n 8002b2a <UART_WaitOnFlagUntilTimeout+0x2e>
|
||
|
|
8002b24: 69bb ldr r3, [r7, #24]
|
||
|
|
8002b26: 2b00 cmp r3, #0
|
||
|
|
8002b28: d11b bne.n 8002b62 <UART_WaitOnFlagUntilTimeout+0x66>
|
||
|
|
{
|
||
|
|
/* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error)
|
||
|
|
interrupts for the interrupt process */
|
||
|
|
CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE));
|
||
|
|
8002b2a: 68fb ldr r3, [r7, #12]
|
||
|
|
8002b2c: 681b ldr r3, [r3, #0]
|
||
|
|
8002b2e: 68fa ldr r2, [r7, #12]
|
||
|
|
8002b30: 6812 ldr r2, [r2, #0]
|
||
|
|
8002b32: 6812 ldr r2, [r2, #0]
|
||
|
|
8002b34: 492f ldr r1, [pc, #188] ; (8002bf4 <UART_WaitOnFlagUntilTimeout+0xf8>)
|
||
|
|
8002b36: 400a ands r2, r1
|
||
|
|
8002b38: 601a str r2, [r3, #0]
|
||
|
|
CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
|
||
|
|
8002b3a: 68fb ldr r3, [r7, #12]
|
||
|
|
8002b3c: 681b ldr r3, [r3, #0]
|
||
|
|
8002b3e: 68fa ldr r2, [r7, #12]
|
||
|
|
8002b40: 6812 ldr r2, [r2, #0]
|
||
|
|
8002b42: 6892 ldr r2, [r2, #8]
|
||
|
|
8002b44: 2101 movs r1, #1
|
||
|
|
8002b46: 438a bics r2, r1
|
||
|
|
8002b48: 609a str r2, [r3, #8]
|
||
|
|
|
||
|
|
huart->gState = HAL_UART_STATE_READY;
|
||
|
|
8002b4a: 68fb ldr r3, [r7, #12]
|
||
|
|
8002b4c: 2220 movs r2, #32
|
||
|
|
8002b4e: 679a str r2, [r3, #120] ; 0x78
|
||
|
|
huart->RxState = HAL_UART_STATE_READY;
|
||
|
|
8002b50: 68fb ldr r3, [r7, #12]
|
||
|
|
8002b52: 2220 movs r2, #32
|
||
|
|
8002b54: 67da str r2, [r3, #124] ; 0x7c
|
||
|
|
|
||
|
|
__HAL_UNLOCK(huart);
|
||
|
|
8002b56: 68fb ldr r3, [r7, #12]
|
||
|
|
8002b58: 2274 movs r2, #116 ; 0x74
|
||
|
|
8002b5a: 2100 movs r1, #0
|
||
|
|
8002b5c: 5499 strb r1, [r3, r2]
|
||
|
|
|
||
|
|
return HAL_TIMEOUT;
|
||
|
|
8002b5e: 2303 movs r3, #3
|
||
|
|
8002b60: e044 b.n 8002bec <UART_WaitOnFlagUntilTimeout+0xf0>
|
||
|
|
}
|
||
|
|
|
||
|
|
if (READ_BIT(huart->Instance->CR1, USART_CR1_RE) != 0U)
|
||
|
|
8002b62: 68fb ldr r3, [r7, #12]
|
||
|
|
8002b64: 681b ldr r3, [r3, #0]
|
||
|
|
8002b66: 681b ldr r3, [r3, #0]
|
||
|
|
8002b68: 2204 movs r2, #4
|
||
|
|
8002b6a: 4013 ands r3, r2
|
||
|
|
8002b6c: d02e beq.n 8002bcc <UART_WaitOnFlagUntilTimeout+0xd0>
|
||
|
|
{
|
||
|
|
if (__HAL_UART_GET_FLAG(huart, UART_FLAG_RTOF) == SET)
|
||
|
|
8002b6e: 68fb ldr r3, [r7, #12]
|
||
|
|
8002b70: 681b ldr r3, [r3, #0]
|
||
|
|
8002b72: 69da ldr r2, [r3, #28]
|
||
|
|
8002b74: 2380 movs r3, #128 ; 0x80
|
||
|
|
8002b76: 011b lsls r3, r3, #4
|
||
|
|
8002b78: 401a ands r2, r3
|
||
|
|
8002b7a: 2380 movs r3, #128 ; 0x80
|
||
|
|
8002b7c: 011b lsls r3, r3, #4
|
||
|
|
8002b7e: 429a cmp r2, r3
|
||
|
|
8002b80: d124 bne.n 8002bcc <UART_WaitOnFlagUntilTimeout+0xd0>
|
||
|
|
{
|
||
|
|
/* Clear Receiver Timeout flag*/
|
||
|
|
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_RTOF);
|
||
|
|
8002b82: 68fb ldr r3, [r7, #12]
|
||
|
|
8002b84: 681b ldr r3, [r3, #0]
|
||
|
|
8002b86: 2280 movs r2, #128 ; 0x80
|
||
|
|
8002b88: 0112 lsls r2, r2, #4
|
||
|
|
8002b8a: 621a str r2, [r3, #32]
|
||
|
|
|
||
|
|
/* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error)
|
||
|
|
interrupts for the interrupt process */
|
||
|
|
CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE));
|
||
|
|
8002b8c: 68fb ldr r3, [r7, #12]
|
||
|
|
8002b8e: 681b ldr r3, [r3, #0]
|
||
|
|
8002b90: 68fa ldr r2, [r7, #12]
|
||
|
|
8002b92: 6812 ldr r2, [r2, #0]
|
||
|
|
8002b94: 6812 ldr r2, [r2, #0]
|
||
|
|
8002b96: 4917 ldr r1, [pc, #92] ; (8002bf4 <UART_WaitOnFlagUntilTimeout+0xf8>)
|
||
|
|
8002b98: 400a ands r2, r1
|
||
|
|
8002b9a: 601a str r2, [r3, #0]
|
||
|
|
CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
|
||
|
|
8002b9c: 68fb ldr r3, [r7, #12]
|
||
|
|
8002b9e: 681b ldr r3, [r3, #0]
|
||
|
|
8002ba0: 68fa ldr r2, [r7, #12]
|
||
|
|
8002ba2: 6812 ldr r2, [r2, #0]
|
||
|
|
8002ba4: 6892 ldr r2, [r2, #8]
|
||
|
|
8002ba6: 2101 movs r1, #1
|
||
|
|
8002ba8: 438a bics r2, r1
|
||
|
|
8002baa: 609a str r2, [r3, #8]
|
||
|
|
|
||
|
|
huart->gState = HAL_UART_STATE_READY;
|
||
|
|
8002bac: 68fb ldr r3, [r7, #12]
|
||
|
|
8002bae: 2220 movs r2, #32
|
||
|
|
8002bb0: 679a str r2, [r3, #120] ; 0x78
|
||
|
|
huart->RxState = HAL_UART_STATE_READY;
|
||
|
|
8002bb2: 68fb ldr r3, [r7, #12]
|
||
|
|
8002bb4: 2220 movs r2, #32
|
||
|
|
8002bb6: 67da str r2, [r3, #124] ; 0x7c
|
||
|
|
huart->ErrorCode = HAL_UART_ERROR_RTO;
|
||
|
|
8002bb8: 68fb ldr r3, [r7, #12]
|
||
|
|
8002bba: 2280 movs r2, #128 ; 0x80
|
||
|
|
8002bbc: 2120 movs r1, #32
|
||
|
|
8002bbe: 5099 str r1, [r3, r2]
|
||
|
|
|
||
|
|
/* Process Unlocked */
|
||
|
|
__HAL_UNLOCK(huart);
|
||
|
|
8002bc0: 68fb ldr r3, [r7, #12]
|
||
|
|
8002bc2: 2274 movs r2, #116 ; 0x74
|
||
|
|
8002bc4: 2100 movs r1, #0
|
||
|
|
8002bc6: 5499 strb r1, [r3, r2]
|
||
|
|
|
||
|
|
return HAL_TIMEOUT;
|
||
|
|
8002bc8: 2303 movs r3, #3
|
||
|
|
8002bca: e00f b.n 8002bec <UART_WaitOnFlagUntilTimeout+0xf0>
|
||
|
|
while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status)
|
||
|
|
8002bcc: 68fb ldr r3, [r7, #12]
|
||
|
|
8002bce: 681b ldr r3, [r3, #0]
|
||
|
|
8002bd0: 69db ldr r3, [r3, #28]
|
||
|
|
8002bd2: 68ba ldr r2, [r7, #8]
|
||
|
|
8002bd4: 401a ands r2, r3
|
||
|
|
8002bd6: 68bb ldr r3, [r7, #8]
|
||
|
|
8002bd8: 1ad3 subs r3, r2, r3
|
||
|
|
8002bda: 425a negs r2, r3
|
||
|
|
8002bdc: 4153 adcs r3, r2
|
||
|
|
8002bde: b2db uxtb r3, r3
|
||
|
|
8002be0: 001a movs r2, r3
|
||
|
|
8002be2: 1dfb adds r3, r7, #7
|
||
|
|
8002be4: 781b ldrb r3, [r3, #0]
|
||
|
|
8002be6: 429a cmp r2, r3
|
||
|
|
8002be8: d091 beq.n 8002b0e <UART_WaitOnFlagUntilTimeout+0x12>
|
||
|
|
}
|
||
|
|
}
|
||
|
|
}
|
||
|
|
}
|
||
|
|
return HAL_OK;
|
||
|
|
8002bea: 2300 movs r3, #0
|
||
|
|
}
|
||
|
|
8002bec: 0018 movs r0, r3
|
||
|
|
8002bee: 46bd mov sp, r7
|
||
|
|
8002bf0: b004 add sp, #16
|
||
|
|
8002bf2: bd80 pop {r7, pc}
|
||
|
|
8002bf4: fffffe5f .word 0xfffffe5f
|
||
|
|
|
||
|
|
08002bf8 <UART_EndRxTransfer>:
|
||
|
|
* @brief End ongoing Rx transfer on UART peripheral (following error detection or Reception completion).
|
||
|
|
* @param huart UART handle.
|
||
|
|
* @retval None
|
||
|
|
*/
|
||
|
|
static void UART_EndRxTransfer(UART_HandleTypeDef *huart)
|
||
|
|
{
|
||
|
|
8002bf8: b580 push {r7, lr}
|
||
|
|
8002bfa: b082 sub sp, #8
|
||
|
|
8002bfc: af00 add r7, sp, #0
|
||
|
|
8002bfe: 6078 str r0, [r7, #4]
|
||
|
|
/* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
|
||
|
|
CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
|
||
|
|
8002c00: 687b ldr r3, [r7, #4]
|
||
|
|
8002c02: 681b ldr r3, [r3, #0]
|
||
|
|
8002c04: 687a ldr r2, [r7, #4]
|
||
|
|
8002c06: 6812 ldr r2, [r2, #0]
|
||
|
|
8002c08: 6812 ldr r2, [r2, #0]
|
||
|
|
8002c0a: 4912 ldr r1, [pc, #72] ; (8002c54 <UART_EndRxTransfer+0x5c>)
|
||
|
|
8002c0c: 400a ands r2, r1
|
||
|
|
8002c0e: 601a str r2, [r3, #0]
|
||
|
|
CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
|
||
|
|
8002c10: 687b ldr r3, [r7, #4]
|
||
|
|
8002c12: 681b ldr r3, [r3, #0]
|
||
|
|
8002c14: 687a ldr r2, [r7, #4]
|
||
|
|
8002c16: 6812 ldr r2, [r2, #0]
|
||
|
|
8002c18: 6892 ldr r2, [r2, #8]
|
||
|
|
8002c1a: 2101 movs r1, #1
|
||
|
|
8002c1c: 438a bics r2, r1
|
||
|
|
8002c1e: 609a str r2, [r3, #8]
|
||
|
|
|
||
|
|
/* In case of reception waiting for IDLE event, disable also the IDLE IE interrupt source */
|
||
|
|
if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
|
||
|
|
8002c20: 687b ldr r3, [r7, #4]
|
||
|
|
8002c22: 6e1b ldr r3, [r3, #96] ; 0x60
|
||
|
|
8002c24: 2b01 cmp r3, #1
|
||
|
|
8002c26: d107 bne.n 8002c38 <UART_EndRxTransfer+0x40>
|
||
|
|
{
|
||
|
|
CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
|
||
|
|
8002c28: 687b ldr r3, [r7, #4]
|
||
|
|
8002c2a: 681b ldr r3, [r3, #0]
|
||
|
|
8002c2c: 687a ldr r2, [r7, #4]
|
||
|
|
8002c2e: 6812 ldr r2, [r2, #0]
|
||
|
|
8002c30: 6812 ldr r2, [r2, #0]
|
||
|
|
8002c32: 2110 movs r1, #16
|
||
|
|
8002c34: 438a bics r2, r1
|
||
|
|
8002c36: 601a str r2, [r3, #0]
|
||
|
|
}
|
||
|
|
|
||
|
|
/* At end of Rx process, restore huart->RxState to Ready */
|
||
|
|
huart->RxState = HAL_UART_STATE_READY;
|
||
|
|
8002c38: 687b ldr r3, [r7, #4]
|
||
|
|
8002c3a: 2220 movs r2, #32
|
||
|
|
8002c3c: 67da str r2, [r3, #124] ; 0x7c
|
||
|
|
huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
|
||
|
|
8002c3e: 687b ldr r3, [r7, #4]
|
||
|
|
8002c40: 2200 movs r2, #0
|
||
|
|
8002c42: 661a str r2, [r3, #96] ; 0x60
|
||
|
|
|
||
|
|
/* Reset RxIsr function pointer */
|
||
|
|
huart->RxISR = NULL;
|
||
|
|
8002c44: 687b ldr r3, [r7, #4]
|
||
|
|
8002c46: 2200 movs r2, #0
|
||
|
|
8002c48: 665a str r2, [r3, #100] ; 0x64
|
||
|
|
}
|
||
|
|
8002c4a: 46c0 nop ; (mov r8, r8)
|
||
|
|
8002c4c: 46bd mov sp, r7
|
||
|
|
8002c4e: b002 add sp, #8
|
||
|
|
8002c50: bd80 pop {r7, pc}
|
||
|
|
8002c52: 46c0 nop ; (mov r8, r8)
|
||
|
|
8002c54: fffffedf .word 0xfffffedf
|
||
|
|
|
||
|
|
08002c58 <UART_DMAAbortOnError>:
|
||
|
|
* (To be called at end of DMA Abort procedure following error occurrence).
|
||
|
|
* @param hdma DMA handle.
|
||
|
|
* @retval None
|
||
|
|
*/
|
||
|
|
static void UART_DMAAbortOnError(DMA_HandleTypeDef *hdma)
|
||
|
|
{
|
||
|
|
8002c58: b580 push {r7, lr}
|
||
|
|
8002c5a: b084 sub sp, #16
|
||
|
|
8002c5c: af00 add r7, sp, #0
|
||
|
|
8002c5e: 6078 str r0, [r7, #4]
|
||
|
|
UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent);
|
||
|
|
8002c60: 687b ldr r3, [r7, #4]
|
||
|
|
8002c62: 6a9b ldr r3, [r3, #40] ; 0x28
|
||
|
|
8002c64: 60fb str r3, [r7, #12]
|
||
|
|
huart->RxXferCount = 0U;
|
||
|
|
8002c66: 68fb ldr r3, [r7, #12]
|
||
|
|
8002c68: 225a movs r2, #90 ; 0x5a
|
||
|
|
8002c6a: 2100 movs r1, #0
|
||
|
|
8002c6c: 5299 strh r1, [r3, r2]
|
||
|
|
huart->TxXferCount = 0U;
|
||
|
|
8002c6e: 68fb ldr r3, [r7, #12]
|
||
|
|
8002c70: 2252 movs r2, #82 ; 0x52
|
||
|
|
8002c72: 2100 movs r1, #0
|
||
|
|
8002c74: 5299 strh r1, [r3, r2]
|
||
|
|
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
|
||
|
|
/*Call registered error callback*/
|
||
|
|
huart->ErrorCallback(huart);
|
||
|
|
#else
|
||
|
|
/*Call legacy weak error callback*/
|
||
|
|
HAL_UART_ErrorCallback(huart);
|
||
|
|
8002c76: 68fb ldr r3, [r7, #12]
|
||
|
|
8002c78: 0018 movs r0, r3
|
||
|
|
8002c7a: f7ff fb73 bl 8002364 <HAL_UART_ErrorCallback>
|
||
|
|
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
|
||
|
|
}
|
||
|
|
8002c7e: 46c0 nop ; (mov r8, r8)
|
||
|
|
8002c80: 46bd mov sp, r7
|
||
|
|
8002c82: b004 add sp, #16
|
||
|
|
8002c84: bd80 pop {r7, pc}
|
||
|
|
|
||
|
|
08002c86 <UART_EndTransmit_IT>:
|
||
|
|
* @param huart pointer to a UART_HandleTypeDef structure that contains
|
||
|
|
* the configuration information for the specified UART module.
|
||
|
|
* @retval None
|
||
|
|
*/
|
||
|
|
static void UART_EndTransmit_IT(UART_HandleTypeDef *huart)
|
||
|
|
{
|
||
|
|
8002c86: b580 push {r7, lr}
|
||
|
|
8002c88: b082 sub sp, #8
|
||
|
|
8002c8a: af00 add r7, sp, #0
|
||
|
|
8002c8c: 6078 str r0, [r7, #4]
|
||
|
|
/* Disable the UART Transmit Complete Interrupt */
|
||
|
|
CLEAR_BIT(huart->Instance->CR1, USART_CR1_TCIE);
|
||
|
|
8002c8e: 687b ldr r3, [r7, #4]
|
||
|
|
8002c90: 681b ldr r3, [r3, #0]
|
||
|
|
8002c92: 687a ldr r2, [r7, #4]
|
||
|
|
8002c94: 6812 ldr r2, [r2, #0]
|
||
|
|
8002c96: 6812 ldr r2, [r2, #0]
|
||
|
|
8002c98: 2140 movs r1, #64 ; 0x40
|
||
|
|
8002c9a: 438a bics r2, r1
|
||
|
|
8002c9c: 601a str r2, [r3, #0]
|
||
|
|
|
||
|
|
/* Tx process is ended, restore huart->gState to Ready */
|
||
|
|
huart->gState = HAL_UART_STATE_READY;
|
||
|
|
8002c9e: 687b ldr r3, [r7, #4]
|
||
|
|
8002ca0: 2220 movs r2, #32
|
||
|
|
8002ca2: 679a str r2, [r3, #120] ; 0x78
|
||
|
|
|
||
|
|
/* Cleat TxISR function pointer */
|
||
|
|
huart->TxISR = NULL;
|
||
|
|
8002ca4: 687b ldr r3, [r7, #4]
|
||
|
|
8002ca6: 2200 movs r2, #0
|
||
|
|
8002ca8: 669a str r2, [r3, #104] ; 0x68
|
||
|
|
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
|
||
|
|
/*Call registered Tx complete callback*/
|
||
|
|
huart->TxCpltCallback(huart);
|
||
|
|
#else
|
||
|
|
/*Call legacy weak Tx complete callback*/
|
||
|
|
HAL_UART_TxCpltCallback(huart);
|
||
|
|
8002caa: 687b ldr r3, [r7, #4]
|
||
|
|
8002cac: 0018 movs r0, r3
|
||
|
|
8002cae: f7ff fb51 bl 8002354 <HAL_UART_TxCpltCallback>
|
||
|
|
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
|
||
|
|
}
|
||
|
|
8002cb2: 46c0 nop ; (mov r8, r8)
|
||
|
|
8002cb4: 46bd mov sp, r7
|
||
|
|
8002cb6: b002 add sp, #8
|
||
|
|
8002cb8: bd80 pop {r7, pc}
|
||
|
|
|
||
|
|
08002cba <HAL_UARTEx_WakeupCallback>:
|
||
|
|
* @brief UART wakeup from Stop mode callback.
|
||
|
|
* @param huart UART handle.
|
||
|
|
* @retval None
|
||
|
|
*/
|
||
|
|
__weak void HAL_UARTEx_WakeupCallback(UART_HandleTypeDef *huart)
|
||
|
|
{
|
||
|
|
8002cba: b580 push {r7, lr}
|
||
|
|
8002cbc: b082 sub sp, #8
|
||
|
|
8002cbe: af00 add r7, sp, #0
|
||
|
|
8002cc0: 6078 str r0, [r7, #4]
|
||
|
|
UNUSED(huart);
|
||
|
|
|
||
|
|
/* NOTE : This function should not be modified, when the callback is needed,
|
||
|
|
the HAL_UARTEx_WakeupCallback can be implemented in the user file.
|
||
|
|
*/
|
||
|
|
}
|
||
|
|
8002cc2: 46c0 nop ; (mov r8, r8)
|
||
|
|
8002cc4: 46bd mov sp, r7
|
||
|
|
8002cc6: b002 add sp, #8
|
||
|
|
8002cc8: bd80 pop {r7, pc}
|
||
|
|
...
|
||
|
|
|
||
|
|
08002ccc <Reset_Handler>:
|
||
|
|
|
||
|
|
.section .text.Reset_Handler
|
||
|
|
.weak Reset_Handler
|
||
|
|
.type Reset_Handler, %function
|
||
|
|
Reset_Handler:
|
||
|
|
ldr r0, =_estack
|
||
|
|
8002ccc: 480d ldr r0, [pc, #52] ; (8002d04 <LoopForever+0x2>)
|
||
|
|
mov sp, r0 /* set stack pointer */
|
||
|
|
8002cce: 4685 mov sp, r0
|
||
|
|
|
||
|
|
/* Copy the data segment initializers from flash to SRAM */
|
||
|
|
ldr r0, =_sdata
|
||
|
|
8002cd0: 480d ldr r0, [pc, #52] ; (8002d08 <LoopForever+0x6>)
|
||
|
|
ldr r1, =_edata
|
||
|
|
8002cd2: 490e ldr r1, [pc, #56] ; (8002d0c <LoopForever+0xa>)
|
||
|
|
ldr r2, =_sidata
|
||
|
|
8002cd4: 4a0e ldr r2, [pc, #56] ; (8002d10 <LoopForever+0xe>)
|
||
|
|
movs r3, #0
|
||
|
|
8002cd6: 2300 movs r3, #0
|
||
|
|
b LoopCopyDataInit
|
||
|
|
8002cd8: e002 b.n 8002ce0 <LoopCopyDataInit>
|
||
|
|
|
||
|
|
08002cda <CopyDataInit>:
|
||
|
|
|
||
|
|
CopyDataInit:
|
||
|
|
ldr r4, [r2, r3]
|
||
|
|
8002cda: 58d4 ldr r4, [r2, r3]
|
||
|
|
str r4, [r0, r3]
|
||
|
|
8002cdc: 50c4 str r4, [r0, r3]
|
||
|
|
adds r3, r3, #4
|
||
|
|
8002cde: 3304 adds r3, #4
|
||
|
|
|
||
|
|
08002ce0 <LoopCopyDataInit>:
|
||
|
|
|
||
|
|
LoopCopyDataInit:
|
||
|
|
adds r4, r0, r3
|
||
|
|
8002ce0: 18c4 adds r4, r0, r3
|
||
|
|
cmp r4, r1
|
||
|
|
8002ce2: 428c cmp r4, r1
|
||
|
|
bcc CopyDataInit
|
||
|
|
8002ce4: d3f9 bcc.n 8002cda <CopyDataInit>
|
||
|
|
|
||
|
|
/* Zero fill the bss segment. */
|
||
|
|
ldr r2, =_sbss
|
||
|
|
8002ce6: 4a0b ldr r2, [pc, #44] ; (8002d14 <LoopForever+0x12>)
|
||
|
|
ldr r4, =_ebss
|
||
|
|
8002ce8: 4c0b ldr r4, [pc, #44] ; (8002d18 <LoopForever+0x16>)
|
||
|
|
movs r3, #0
|
||
|
|
8002cea: 2300 movs r3, #0
|
||
|
|
b LoopFillZerobss
|
||
|
|
8002cec: e001 b.n 8002cf2 <LoopFillZerobss>
|
||
|
|
|
||
|
|
08002cee <FillZerobss>:
|
||
|
|
|
||
|
|
FillZerobss:
|
||
|
|
str r3, [r2]
|
||
|
|
8002cee: 6013 str r3, [r2, #0]
|
||
|
|
adds r2, r2, #4
|
||
|
|
8002cf0: 3204 adds r2, #4
|
||
|
|
|
||
|
|
08002cf2 <LoopFillZerobss>:
|
||
|
|
|
||
|
|
LoopFillZerobss:
|
||
|
|
cmp r2, r4
|
||
|
|
8002cf2: 42a2 cmp r2, r4
|
||
|
|
bcc FillZerobss
|
||
|
|
8002cf4: d3fb bcc.n 8002cee <FillZerobss>
|
||
|
|
|
||
|
|
/* Call the clock system intitialization function.*/
|
||
|
|
bl SystemInit
|
||
|
|
8002cf6: f7fd fd67 bl 80007c8 <SystemInit>
|
||
|
|
/* Call static constructors */
|
||
|
|
bl __libc_init_array
|
||
|
|
8002cfa: f000 f811 bl 8002d20 <__libc_init_array>
|
||
|
|
/* Call the application's entry point.*/
|
||
|
|
bl main
|
||
|
|
8002cfe: f7fd fc8b bl 8000618 <main>
|
||
|
|
|
||
|
|
08002d02 <LoopForever>:
|
||
|
|
|
||
|
|
LoopForever:
|
||
|
|
b LoopForever
|
||
|
|
8002d02: e7fe b.n 8002d02 <LoopForever>
|
||
|
|
ldr r0, =_estack
|
||
|
|
8002d04: 20005000 .word 0x20005000
|
||
|
|
ldr r0, =_sdata
|
||
|
|
8002d08: 20000000 .word 0x20000000
|
||
|
|
ldr r1, =_edata
|
||
|
|
8002d0c: 2000000c .word 0x2000000c
|
||
|
|
ldr r2, =_sidata
|
||
|
|
8002d10: 08002e0c .word 0x08002e0c
|
||
|
|
ldr r2, =_sbss
|
||
|
|
8002d14: 2000000c .word 0x2000000c
|
||
|
|
ldr r4, =_ebss
|
||
|
|
8002d18: 200000b0 .word 0x200000b0
|
||
|
|
|
||
|
|
08002d1c <ADC1_COMP_IRQHandler>:
|
||
|
|
* @retval : None
|
||
|
|
*/
|
||
|
|
.section .text.Default_Handler,"ax",%progbits
|
||
|
|
Default_Handler:
|
||
|
|
Infinite_Loop:
|
||
|
|
b Infinite_Loop
|
||
|
|
8002d1c: e7fe b.n 8002d1c <ADC1_COMP_IRQHandler>
|
||
|
|
...
|
||
|
|
|
||
|
|
08002d20 <__libc_init_array>:
|
||
|
|
8002d20: b570 push {r4, r5, r6, lr}
|
||
|
|
8002d22: 2600 movs r6, #0
|
||
|
|
8002d24: 4d0c ldr r5, [pc, #48] ; (8002d58 <__libc_init_array+0x38>)
|
||
|
|
8002d26: 4c0d ldr r4, [pc, #52] ; (8002d5c <__libc_init_array+0x3c>)
|
||
|
|
8002d28: 1b64 subs r4, r4, r5
|
||
|
|
8002d2a: 10a4 asrs r4, r4, #2
|
||
|
|
8002d2c: 42a6 cmp r6, r4
|
||
|
|
8002d2e: d109 bne.n 8002d44 <__libc_init_array+0x24>
|
||
|
|
8002d30: 2600 movs r6, #0
|
||
|
|
8002d32: f000 f821 bl 8002d78 <_init>
|
||
|
|
8002d36: 4d0a ldr r5, [pc, #40] ; (8002d60 <__libc_init_array+0x40>)
|
||
|
|
8002d38: 4c0a ldr r4, [pc, #40] ; (8002d64 <__libc_init_array+0x44>)
|
||
|
|
8002d3a: 1b64 subs r4, r4, r5
|
||
|
|
8002d3c: 10a4 asrs r4, r4, #2
|
||
|
|
8002d3e: 42a6 cmp r6, r4
|
||
|
|
8002d40: d105 bne.n 8002d4e <__libc_init_array+0x2e>
|
||
|
|
8002d42: bd70 pop {r4, r5, r6, pc}
|
||
|
|
8002d44: 00b3 lsls r3, r6, #2
|
||
|
|
8002d46: 58eb ldr r3, [r5, r3]
|
||
|
|
8002d48: 4798 blx r3
|
||
|
|
8002d4a: 3601 adds r6, #1
|
||
|
|
8002d4c: e7ee b.n 8002d2c <__libc_init_array+0xc>
|
||
|
|
8002d4e: 00b3 lsls r3, r6, #2
|
||
|
|
8002d50: 58eb ldr r3, [r5, r3]
|
||
|
|
8002d52: 4798 blx r3
|
||
|
|
8002d54: 3601 adds r6, #1
|
||
|
|
8002d56: e7f2 b.n 8002d3e <__libc_init_array+0x1e>
|
||
|
|
8002d58: 08002e04 .word 0x08002e04
|
||
|
|
8002d5c: 08002e04 .word 0x08002e04
|
||
|
|
8002d60: 08002e04 .word 0x08002e04
|
||
|
|
8002d64: 08002e08 .word 0x08002e08
|
||
|
|
|
||
|
|
08002d68 <memset>:
|
||
|
|
8002d68: 0003 movs r3, r0
|
||
|
|
8002d6a: 1882 adds r2, r0, r2
|
||
|
|
8002d6c: 4293 cmp r3, r2
|
||
|
|
8002d6e: d100 bne.n 8002d72 <memset+0xa>
|
||
|
|
8002d70: 4770 bx lr
|
||
|
|
8002d72: 7019 strb r1, [r3, #0]
|
||
|
|
8002d74: 3301 adds r3, #1
|
||
|
|
8002d76: e7f9 b.n 8002d6c <memset+0x4>
|
||
|
|
|
||
|
|
08002d78 <_init>:
|
||
|
|
8002d78: b5f8 push {r3, r4, r5, r6, r7, lr}
|
||
|
|
8002d7a: 46c0 nop ; (mov r8, r8)
|
||
|
|
8002d7c: bcf8 pop {r3, r4, r5, r6, r7}
|
||
|
|
8002d7e: bc08 pop {r3}
|
||
|
|
8002d80: 469e mov lr, r3
|
||
|
|
8002d82: 4770 bx lr
|
||
|
|
|
||
|
|
08002d84 <_fini>:
|
||
|
|
8002d84: b5f8 push {r3, r4, r5, r6, r7, lr}
|
||
|
|
8002d86: 46c0 nop ; (mov r8, r8)
|
||
|
|
8002d88: bcf8 pop {r3, r4, r5, r6, r7}
|
||
|
|
8002d8a: bc08 pop {r3}
|
||
|
|
8002d8c: 469e mov lr, r3
|
||
|
|
8002d8e: 4770 bx lr
|